SPIXR SPIXR peripheral. 0x4003A000 0x00 0x1000 registers DATA32 Register for reading and writing the FIFO. 0x00 32 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 32 2 2 DATA16[%s] Register for reading and writing the FIFO. DATA32 0x00 16 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 16 4 1 DATA8[%s] Register for reading and writing the FIFO. DATA32 0x00 8 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 8 ctrl1 Register for controlling SPI peripheral. 0x04 read-write ENABLE SPI Enable. 0 1 dis SPI is disabled. 0 en SPI is enabled. 1 MASTER Master Mode Enable. 1 1 dis SPI is Slave mode. 0 en SPI is Master mode. 1 SS_IO Slave Select 0, IO direction, to support Multi-Master mode, Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 4 1 output Slave select 0 is output. 0 input Slave Select 0 is input, only valid if MMEN=1. 1 START Start Transmit. 5 1 start Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction completes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. 1 SS_CTRL Slave Select Control. 8 1 deassert SPI de-asserts Slave Select at the end of a transaction. 0 assert SPI leaves Slave Select asserted at the end of a transaction. 1 SS Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 16 1 ctrl2 Register for controlling SPI peripheral. 0x08 read-write TX_NUM_CHAR Nubmer of Characters to transmit. 0 16 RX_NUM_CHAR Nubmer of Characters to receive. 16 16 ctrl3 Register for controlling SPI peripheral. 0x0C read-write CPHA Clock Phase. 0 1 risingEdge Data sampled on rising edge. 0 fallingEdge Data sample on falling edge. 1 CPOL Clock Polarity. 1 1 normal Normal clock. 0 inverted Inverted clock. 1 SCLK_INV Invert SCLK Feedback in Master Mode. 4 1 Normal SCLK is not inverted to Line Receiver. 0 NUMBITS Number of Bits per character. 8 4 16BITS 16 bits per character. 0 1BITS 1 bits per character. 1 2BITS 2 bits per character. 2 3BITS 3 bits per character. 3 4BITS 4 bits per character. 4 5BITS 5 bits per character. 5 6BITS 6 bits per character. 6 7BITS 7 bits per character. 7 8BITS 8 bits per character. 8 9BITS 9 bits per character. 9 10BITS 10 bits per character. 10 11BITS 11 bits per character. 11 12BITS 12 bits per character. 12 13BITS 13 bits per character. 13 14BITS 14 bits per character. 14 15BITS 15 bits per character. 15 DATA_WIDTH SPI Data width. 12 2 Mono 1 data pin. 0 Dual 2 data pins. 1 Quad 4 data pins. 2 THREE_WIRE Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 15 1 4wire Use four wire mode (Mono only). 0 3wire Use three wire mode. 1 SSPOL Slave Select Polarity 16 1 activeLow Slave select is active low. 0 activeHigh Slave select is active high. 1 SS_TIME Register for controlling SPI peripheral. 0x10 read-write SSACT1 Slave Select Action delay 1. 0 8 SSACT2 Slave Select Action delay 2. 8 8 SSINACT Slave Select Inactive delay. 16 8 BRG_CTRL Register for controlling SPI clock rate. 0x14 read-write LO Low duty cycle control. In timer mode, reload[7:0]. 0 8 HI High duty cycle control. In timer mode, reload[15:8]. 8 8 SCALE System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. 16 4 div1 clk_freq = f_pclk/1. 0 div2 clk_freq = f_pclk/2. 1 div4 clk_freq = f_pclk/4. 2 div8 clk_freq = f_pclk/8. 3 div16 clk_freq = f_pclk/16. 4 div32 clk_freq = f_pclk/32. 5 div64 clk_freq = f_pclk/64. 6 div128 clk_freq = f_pclk/128. 7 div256 clk_freq = f_pclk/256. 8 DMA Register for controlling DMA. 0x1C read-write TX_FIFO_LEVEL Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. 0 5 TX_FIFO_EN Transmit FIFO enabled for SPI transactions. 6 1 dis Transmit FIFO is not enabled. 0 en Transmit FIFO is enabled. 1 TX_FIFO_CLEAR Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 7 1 clear Clear the Transmit FIFO, clears any pending TX FIFO status. 1 TX_FIFO_CNT Count of entries in TX FIFO. 8 6 TX_DMA_EN TX DMA Enable. 15 1 dis TX DMA requests are disabled, andy pending DMA requests are cleared. 0 en TX DMA requests are enabled. 1 RX_FIFO_LEVEL Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. 16 5 RX_FIFO_EN Receive FIFO enabled for SPI transactions. 22 1 dis Receive FIFO is not enabled. 0 en Receive FIFO is enabled. 1 RX_FIFO_CLEAR Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 23 1 clear Clear the Receive FIFIO, clears any pending RX FIFO status. 1 RX_FIFO_CNT Count of entries in RX FIFO. 24 6 RX_DMA_EN RX DMA Enable. 31 1 dis RX DMA requests are disabled, any pending DMA requests are cleared. 0 en RX DMA requests are enabled. 1 int_fl Register for reading and clearing interrupt flags. All bits are write 1 to clear. 0x20 read-write TX_LEVEL TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EMPTY TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_LEVEL RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL RX FIFO FULL. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSA Slave Select Asserted. 4 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSD Slave Select Deasserted. 5 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 FAULT Multi-Master Mode Fault. 8 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 ABORT Slave Abort Detected. 9 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 M_DONE Master Done, set when SPI Master has completed any transactions. 11 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_OVR Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 12 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_UND Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. 13 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_OVR Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. 14 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_UND Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. 15 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 int_en Register for enabling interrupts. 0x24 read-write TX_LEVEL TX FIFO Threshold interrupt enable. 0 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_EMPTY TX FIFO Empty interrupt enable. 1 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_LEVEL RX FIFO Threshold Crossed interrupt enable. 2 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_FULL RX FIFO FULL interrupt enable. 3 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSA Slave Select Asserted interrupt enable. 4 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSD Slave Select Deasserted interrupt enable. 5 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 FAULT Multi-Master Mode Fault interrupt enable. 8 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 ABORT Slave Abort Detected interrupt enable. 9 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 M_DONE Master Done interrupt enable. 11 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_OVR Transmit FIFO Overrun interrupt enable. 12 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_UND Transmit FIFO Underrun interrupt enable. 13 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_OVR Receive FIFO Overrun interrupt enable. 14 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_UND Receive FIFO Underrun interrupt enable. 15 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 WAKE_FL Register for wake up flags. All bits in this register are write 1 to clear. 0x28 read-write TX_LEVEL Wake on TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EMPTY Wake on TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_LEVEL Wake on RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL Wake on RX FIFO Full. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 WAKE_EN Register for wake up enable. 0x2C read-write TX_LEVEL Wake on TX FIFO Threshold Crossed Enable. 0 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 TX_EMPTY Wake on TX FIFO Empty Enable. 1 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_LEVEL Wake on RX FIFO Threshold Crossed Enable. 2 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_FULL Wake on RX FIFO Full Enable. 3 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 STAT SPI Status register. 0x30 read-only BUSY SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 0 1 notActive SPI not active. 0 active SPI active. 1 XMEM_CTRL Register to control external memory. 0x34 read-write XMEM_RD_CMD Read command. 0 8 XMEM_WR_CMD Write command. 8 8 XMEM_DCLKS Dummy clocks. 16 8 XMEM_EN XMEM enable. 31 1 dis External memory disabled. 0 en External memory enabled. 1