1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPIXFM</name> 5 <description>SPIXF Master</description> 6 <baseAddress>0x40026000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>CFG</name> 15 <description>SPIX Configuration Register.</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>MODE</name> 20 <description>Defines SPI Mode, Only valid values are 0 and 3.</description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>2</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>SCLK_HI_SAMPLE_RISING</name> 26 <description>Description not available.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>SCLK_LO_SAMPLE_FAILLING</name> 31 <description>Description not available.</description> 32 <value>3</value> 33 </enumeratedValue> 34 </enumeratedValues> 35 </field> 36 <field> 37 <name>SSPOL</name> 38 <description>Slave Select Polarity.</description> 39 <bitOffset>2</bitOffset> 40 <bitWidth>1</bitWidth> 41 <enumeratedValues> 42 <enumeratedValue> 43 <name>ACTIVE_HIGH</name> 44 <description>Slave Select is Active High.</description> 45 <value>0</value> 46 </enumeratedValue> 47 <enumeratedValue> 48 <name>ACTIVE_LOW</name> 49 <description>Slave Select is Active Low.</description> 50 <value>1</value> 51 </enumeratedValue> 52 </enumeratedValues> 53 </field> 54 <field> 55 <name>SSEL</name> 56 <description>Slave Select. Only valid value is zero.</description> 57 <bitOffset>4</bitOffset> 58 <bitWidth>3</bitWidth> 59 </field> 60 <field> 61 <name>LO_CLK</name> 62 <description>Number of system clocks that SCLK will be low when SCLK pulses are generated.</description> 63 <bitOffset>8</bitOffset> 64 <bitWidth>4</bitWidth> 65 </field> 66 <field> 67 <name>HI_CLK</name> 68 <description>Number of system clocks that SCLK will be high when SCLK pulses are generated.</description> 69 <bitOffset>12</bitOffset> 70 <bitWidth>4</bitWidth> 71 </field> 72 <field> 73 <name>SSACT</name> 74 <description>Slave Select Active Timing.</description> 75 <bitOffset>16</bitOffset> 76 <bitWidth>2</bitWidth> 77 <enumeratedValues> 78 <enumeratedValue> 79 <name>off</name> 80 <description>0 system clocks.</description> 81 <value>0</value> 82 </enumeratedValue> 83 <enumeratedValue> 84 <name>for_2_mod_clk</name> 85 <description>2 System clocks.</description> 86 <value>1</value> 87 </enumeratedValue> 88 <enumeratedValue> 89 <name>for_4_mod_clk</name> 90 <description>4 System clocks.</description> 91 <value>2</value> 92 </enumeratedValue> 93 <enumeratedValue> 94 <name>for_8_mod_clk</name> 95 <description>8 System clocks.</description> 96 <value>3</value> 97 </enumeratedValue> 98 </enumeratedValues> 99 </field> 100 <field> 101 <name>SSIACT</name> 102 <description>Slave Select Inactive Timing.</description> 103 <bitOffset>18</bitOffset> 104 <bitWidth>2</bitWidth> 105 <enumeratedValues> 106 <enumeratedValue> 107 <name>for_1_mod_clk</name> 108 <description>1 system clocks.</description> 109 <value>0</value> 110 </enumeratedValue> 111 <enumeratedValue> 112 <name>for_3_mod_clk</name> 113 <description>3 System clocks.</description> 114 <value>1</value> 115 </enumeratedValue> 116 <enumeratedValue> 117 <name>for_5_mod_clk</name> 118 <description>5 System clocks.</description> 119 <value>2</value> 120 </enumeratedValue> 121 <enumeratedValue> 122 <name>for_9_mod_clk</name> 123 <description>9 System clocks.</description> 124 <value>3</value> 125 </enumeratedValue> 126 </enumeratedValues> 127 </field> 128 </fields> 129 </register> 130 <register> 131 <name>FETCH_CTRL</name> 132 <description>SPIX Fetch Control Register.</description> 133 <addressOffset>0x04</addressOffset> 134 <fields> 135 <field> 136 <name>CMDVAL</name> 137 <description>Command Value sent to target to initiate fetching from SPI flash.</description> 138 <bitOffset>0</bitOffset> 139 <bitWidth>8</bitWidth> 140 </field> 141 <field> 142 <name>CMD_WIDTH</name> 143 <description>Command Width. Number of data I/O used to send commands.</description> 144 <bitOffset>8</bitOffset> 145 <bitWidth>2</bitWidth> 146 <enumeratedValues> 147 <enumeratedValue> 148 <name>Single</name> 149 <description>Single SDIO.</description> 150 <value>0</value> 151 </enumeratedValue> 152 <enumeratedValue> 153 <name>Dual_IO</name> 154 <description>Dual SDIO.</description> 155 <value>1</value> 156 </enumeratedValue> 157 <enumeratedValue> 158 <name>Quad_IO</name> 159 <description>Quad SDIO.</description> 160 <value>2</value> 161 </enumeratedValue> 162 <enumeratedValue> 163 <name>Invalid</name> 164 <description>Invalid.</description> 165 <value>3</value> 166 </enumeratedValue> 167 </enumeratedValues> 168 </field> 169 <field> 170 <name>ADDR_WIDTH</name> 171 <description>Address Width. Number of data I/O used to send address, and mode/dummy clocks.</description> 172 <bitOffset>10</bitOffset> 173 <bitWidth>2</bitWidth> 174 <enumeratedValues> 175 <enumeratedValue> 176 <name>Single</name> 177 <description>Single SDIO.</description> 178 <value>0</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>Dual_IO</name> 182 <description>Dual SDIO.</description> 183 <value>1</value> 184 </enumeratedValue> 185 <enumeratedValue> 186 <name>Quad_IO</name> 187 <description>Quad SDIO.</description> 188 <value>2</value> 189 </enumeratedValue> 190 <enumeratedValue> 191 <name>Invalid</name> 192 <description>Invalid.</description> 193 <value>3</value> 194 </enumeratedValue> 195 </enumeratedValues> 196 </field> 197 <field> 198 <name>DATA_WIDTH</name> 199 <description>Data Width. Number of data I/O used to receive data.</description> 200 <bitOffset>12</bitOffset> 201 <bitWidth>2</bitWidth> 202 <enumeratedValues> 203 <enumeratedValue> 204 <name>Single</name> 205 <description>Single SDIO.</description> 206 <value>0</value> 207 </enumeratedValue> 208 <enumeratedValue> 209 <name>Dual_IO</name> 210 <description>Dual SDIO.</description> 211 <value>1</value> 212 </enumeratedValue> 213 <enumeratedValue> 214 <name>Quad_IO</name> 215 <description>Quad SDIO.</description> 216 <value>2</value> 217 </enumeratedValue> 218 <enumeratedValue> 219 <name>Invalid</name> 220 <description>Invalid.</description> 221 <value>3</value> 222 </enumeratedValue> 223 </enumeratedValues> 224 </field> 225 <field> 226 <name>FOUR_BYTE_ADDR</name> 227 <description>Four Byte Address Mode. Enables 4-byte Flash Address Mode.</description> 228 <bitOffset>16</bitOffset> 229 <bitWidth>1</bitWidth> 230 <enumeratedValues> 231 <enumeratedValue> 232 <name>3</name> 233 <description>3 Byte Address Mode.</description> 234 <value>0</value> 235 </enumeratedValue> 236 <enumeratedValue> 237 <name>4</name> 238 <description>4 Byte Address Mode.</description> 239 <value>1</value> 240 </enumeratedValue> 241 </enumeratedValues> 242 </field> 243 </fields> 244 </register> 245 <register> 246 <name>MODE_CTRL</name> 247 <description>SPIX Mode Control Register.</description> 248 <addressOffset>0x08</addressOffset> 249 <fields> 250 <field> 251 <name>MDCLK</name> 252 <description>Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch.</description> 253 <bitOffset>0</bitOffset> 254 <bitWidth>4</bitWidth> 255 </field> 256 <field> 257 <name>NO_CMD_MODE</name> 258 <description>No Command Mode.</description> 259 <bitOffset>8</bitOffset> 260 <bitWidth>1</bitWidth> 261 <enumeratedValues> 262 <enumeratedValue> 263 <name>always</name> 264 <description>Send read command every time SPI transaction is initiated.</description> 265 <value>0</value> 266 </enumeratedValue> 267 <enumeratedValue> 268 <name>once</name> 269 <description>Send read command only once. NO read command in subsequent SPI transactions.</description> 270 <value>1</value> 271 </enumeratedValue> 272 </enumeratedValues> 273 </field> 274 <field> 275 <name>EXIT_NO_CMD_MODE</name> 276 <description>Exit no command mode.</description> 277 <bitOffset>9</bitOffset> 278 <bitWidth>1</bitWidth> 279 </field> 280 </fields> 281 </register> 282 <register> 283 <name>MODE_DATA</name> 284 <description>SPIX Mode Data Register.</description> 285 <addressOffset>0x0C</addressOffset> 286 <fields> 287 <field> 288 <name>DATA</name> 289 <description>Mode Data. Specifies the data to send with the Dummy/Mode clocks.</description> 290 <bitOffset>0</bitOffset> 291 <bitWidth>16</bitWidth> 292 </field> 293 <field> 294 <name>OUT_EN</name> 295 <description>Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA.</description> 296 <bitOffset>16</bitOffset> 297 <bitWidth>16</bitWidth> 298 </field> 299 </fields> 300 </register> 301 <register> 302 <name>SCLK_FB_CTRL</name> 303 <description>SPIX Feedback Control Register.</description> 304 <addressOffset>0x10</addressOffset> 305 <fields> 306 <field> 307 <name>FB_EN</name> 308 <description>Enable SCLK feedback mode.</description> 309 <bitOffset>0</bitOffset> 310 <bitWidth>1</bitWidth> 311 <enumeratedValues> 312 <enumeratedValue> 313 <name>dis</name> 314 <description>Disable SCLK feedback mode.</description> 315 <value>0</value> 316 </enumeratedValue> 317 <enumeratedValue> 318 <name>en</name> 319 <description>Enable SCLK feedback mode.</description> 320 <value>1</value> 321 </enumeratedValue> 322 </enumeratedValues> 323 </field> 324 <field> 325 <name>INVERT_EN</name> 326 <description>Invert SCLK in feedback mode.</description> 327 <bitOffset>1</bitOffset> 328 <bitWidth>1</bitWidth> 329 <enumeratedValues> 330 <enumeratedValue> 331 <name>dis</name> 332 <description>Disable Invert SCLK feedback mode.</description> 333 <value>0</value> 334 </enumeratedValue> 335 <enumeratedValue> 336 <name>en</name> 337 <description>Enable Invert SCLK feedback mode.</description> 338 <value>1</value> 339 </enumeratedValue> 340 </enumeratedValues> 341 </field> 342 </fields> 343 </register> 344 <register> 345 <name>IO_CTRL</name> 346 <description>SPIX IO Control Register.</description> 347 <addressOffset>0x1C</addressOffset> 348 <fields> 349 <field> 350 <name>SCLK_DS</name> 351 <description>SCLK drive Strength. This bit controls the drive strength on the SCLK pin.</description> 352 <bitOffset>0</bitOffset> 353 <bitWidth>1</bitWidth> 354 <enumeratedValues> 355 <enumeratedValue> 356 <name>Low</name> 357 <description>Low drive strength.</description> 358 <value>0</value> 359 </enumeratedValue> 360 <enumeratedValue> 361 <name>High</name> 362 <description>High drive strength.</description> 363 <value>1</value> 364 </enumeratedValue> 365 </enumeratedValues> 366 </field> 367 <field> 368 <name>SS_DS</name> 369 <description>Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin.</description> 370 <bitOffset>1</bitOffset> 371 <bitWidth>1</bitWidth> 372 <enumeratedValues> 373 <enumeratedValue> 374 <name>Low</name> 375 <description>Low drive strength.</description> 376 <value>0</value> 377 </enumeratedValue> 378 <enumeratedValue> 379 <name>High</name> 380 <description>High drive strength.</description> 381 <value>1</value> 382 </enumeratedValue> 383 </enumeratedValues> 384 </field> 385 <field> 386 <name>SDIO_DS</name> 387 <description>SDIO Drive Strength. This bit controls the drive strength of all SDIO pins.</description> 388 <bitOffset>2</bitOffset> 389 <bitWidth>1</bitWidth> 390 <enumeratedValues> 391 <enumeratedValue> 392 <name>Low</name> 393 <description>Low drive strength.</description> 394 <value>0</value> 395 </enumeratedValue> 396 <enumeratedValue> 397 <name>High</name> 398 <description>High drive strength.</description> 399 <value>1</value> 400 </enumeratedValue> 401 </enumeratedValues> 402 </field> 403 <field> 404 <name>PU_PD_CTRL</name> 405 <description>IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins.</description> 406 <bitOffset>3</bitOffset> 407 <bitWidth>2</bitWidth> 408 <enumeratedValues> 409 <enumeratedValue> 410 <name>tri_state</name> 411 <description>Tristate.</description> 412 <value>0</value> 413 </enumeratedValue> 414 <enumeratedValue> 415 <name>Pull_Up</name> 416 <description>Pull-Up.</description> 417 <value>1</value> 418 </enumeratedValue> 419 <enumeratedValue> 420 <name>Pull_down</name> 421 <description>Pull-Down.</description> 422 <value>2</value> 423 </enumeratedValue> 424 </enumeratedValues> 425 </field> 426 </fields> 427 </register> 428 <register> 429 <name>MEMSECCN</name> 430 <description>SPIX Memory Security Control Register.</description> 431 <addressOffset>0x20</addressOffset> 432 <fields> 433 <field> 434 <name>DECEN</name> 435 <description>Decryption Enable.</description> 436 <bitOffset>0</bitOffset> 437 <bitWidth>1</bitWidth> 438 <enumeratedValues> 439 <enumeratedValue> 440 <name>dis</name> 441 <description>Disable decryption of SPIX data.</description> 442 <value>0</value> 443 </enumeratedValue> 444 <enumeratedValue> 445 <name>en</name> 446 <description>Enable decryption of SPIX data.</description> 447 <value>1</value> 448 </enumeratedValue> 449 </enumeratedValues> 450 </field> 451 <field> 452 <name>AUTH_DISABLE</name> 453 <description>Integrity Enable.</description> 454 <bitOffset>1</bitOffset> 455 <bitWidth>1</bitWidth> 456 <enumeratedValues> 457 <enumeratedValue> 458 <name>dis</name> 459 <description>Integrity checking disabled.</description> 460 <value>0</value> 461 </enumeratedValue> 462 <enumeratedValue> 463 <name>en</name> 464 <description>Integrity checking enabled.</description> 465 <value>1</value> 466 </enumeratedValue> 467 </enumeratedValues> 468 </field> 469 <field> 470 <name>CNTOPTIEN</name> 471 <description>Enable counters optimization (when authentication is enabled)</description> 472 <bitOffset>2</bitOffset> 473 <bitWidth>1</bitWidth> 474 <enumeratedValues> 475 <enumeratedValue> 476 <name>dis</name> 477 <description>disable</description> 478 <value>0</value> 479 </enumeratedValue> 480 <enumeratedValue> 481 <name>en</name> 482 <description>enable</description> 483 <value>1</value> 484 </enumeratedValue> 485 </enumeratedValues> 486 </field> 487 <field> 488 <name>INTERLDIS</name> 489 <description>Disable authenticity interleaving (when authentication is enabled)</description> 490 <bitOffset>3</bitOffset> 491 <bitWidth>1</bitWidth> 492 <enumeratedValues> 493 <enumeratedValue> 494 <name>dis</name> 495 <description>disable</description> 496 <value>1</value> 497 </enumeratedValue> 498 <enumeratedValue> 499 <name>en</name> 500 <description>enable</description> 501 <value>0</value> 502 </enumeratedValue> 503 </enumeratedValues> 504 </field> 505 <field> 506 <name>AUTHERR</name> 507 <description>Authentication Error Flah Bit.</description> 508 <bitOffset>4</bitOffset> 509 <bitWidth>1</bitWidth> 510 </field> 511 </fields> 512 </register> 513 <register> 514 <name>BUS_IDLE</name> 515 <description>SPIXF Bus Idle Detection.</description> 516 <addressOffset>0x24</addressOffset> 517 <fields> 518 <field> 519 <name>BUSIDLE</name> 520 <description>Bus Idle Timer Limit.</description> 521 <bitOffset>0</bitOffset> 522 <bitWidth>16</bitWidth> 523 </field> 524 </fields> 525 </register> 526 </registers> 527 </peripheral> 528 <!-- SPIXF: SPI XiP Master --> 529</device>
