SPIXFM SPIXF Master 0x40026000 0x00 0x1000 registers CFG SPIX Configuration Register. 0x00 MODE Defines SPI Mode, Only valid values are 0 and 3. 0 2 SCLK_HI_SAMPLE_RISING Description not available. 0 SCLK_LO_SAMPLE_FAILLING Description not available. 3 SSPOL Slave Select Polarity. 2 1 ACTIVE_HIGH Slave Select is Active High. 0 ACTIVE_LOW Slave Select is Active Low. 1 SSEL Slave Select. Only valid value is zero. 4 3 LO_CLK Number of system clocks that SCLK will be low when SCLK pulses are generated. 8 4 HI_CLK Number of system clocks that SCLK will be high when SCLK pulses are generated. 12 4 SSACT Slave Select Active Timing. 16 2 off 0 system clocks. 0 for_2_mod_clk 2 System clocks. 1 for_4_mod_clk 4 System clocks. 2 for_8_mod_clk 8 System clocks. 3 SSIACT Slave Select Inactive Timing. 18 2 for_1_mod_clk 1 system clocks. 0 for_3_mod_clk 3 System clocks. 1 for_5_mod_clk 5 System clocks. 2 for_9_mod_clk 9 System clocks. 3 FETCH_CTRL SPIX Fetch Control Register. 0x04 CMDVAL Command Value sent to target to initiate fetching from SPI flash. 0 8 CMD_WIDTH Command Width. Number of data I/O used to send commands. 8 2 Single Single SDIO. 0 Dual_IO Dual SDIO. 1 Quad_IO Quad SDIO. 2 Invalid Invalid. 3 ADDR_WIDTH Address Width. Number of data I/O used to send address, and mode/dummy clocks. 10 2 Single Single SDIO. 0 Dual_IO Dual SDIO. 1 Quad_IO Quad SDIO. 2 Invalid Invalid. 3 DATA_WIDTH Data Width. Number of data I/O used to receive data. 12 2 Single Single SDIO. 0 Dual_IO Dual SDIO. 1 Quad_IO Quad SDIO. 2 Invalid Invalid. 3 FOUR_BYTE_ADDR Four Byte Address Mode. Enables 4-byte Flash Address Mode. 16 1 3 3 Byte Address Mode. 0 4 4 Byte Address Mode. 1 MODE_CTRL SPIX Mode Control Register. 0x08 MDCLK Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch. 0 4 NO_CMD_MODE No Command Mode. 8 1 always Send read command every time SPI transaction is initiated. 0 once Send read command only once. NO read command in subsequent SPI transactions. 1 EXIT_NO_CMD_MODE Exit no command mode. 9 1 MODE_DATA SPIX Mode Data Register. 0x0C DATA Mode Data. Specifies the data to send with the Dummy/Mode clocks. 0 16 OUT_EN Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA. 16 16 SCLK_FB_CTRL SPIX Feedback Control Register. 0x10 FB_EN Enable SCLK feedback mode. 0 1 dis Disable SCLK feedback mode. 0 en Enable SCLK feedback mode. 1 INVERT_EN Invert SCLK in feedback mode. 1 1 dis Disable Invert SCLK feedback mode. 0 en Enable Invert SCLK feedback mode. 1 IO_CTRL SPIX IO Control Register. 0x1C SCLK_DS SCLK drive Strength. This bit controls the drive strength on the SCLK pin. 0 1 Low Low drive strength. 0 High High drive strength. 1 SS_DS Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin. 1 1 Low Low drive strength. 0 High High drive strength. 1 SDIO_DS SDIO Drive Strength. This bit controls the drive strength of all SDIO pins. 2 1 Low Low drive strength. 0 High High drive strength. 1 PU_PD_CTRL IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins. 3 2 tri_state Tristate. 0 Pull_Up Pull-Up. 1 Pull_down Pull-Down. 2 MEMSECCN SPIX Memory Security Control Register. 0x20 DECEN Decryption Enable. 0 1 dis Disable decryption of SPIX data. 0 en Enable decryption of SPIX data. 1 AUTH_DISABLE Integrity Enable. 1 1 dis Integrity checking disabled. 0 en Integrity checking enabled. 1 CNTOPTIEN Enable counters optimization (when authentication is enabled) 2 1 dis disable 0 en enable 1 INTERLDIS Disable authenticity interleaving (when authentication is enabled) 3 1 dis disable 1 en enable 0 AUTHERR Authentication Error Flah Bit. 4 1 BUS_IDLE SPIXF Bus Idle Detection. 0x24 BUSIDLE Bus Idle Timer Limit. 0 16