1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>SPI0</name> 5 <description>SPI peripheral.</description> 6 <baseAddress>0x40046000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>SPI0</name> 14 <value>16</value> 15 </interrupt> 16 <registers> 17 <register> 18 <name>FIFO32</name> 19 <description>Register for reading and writing the FIFO.</description> 20 <addressOffset>0x00</addressOffset> 21 <size>32</size> 22 <access>read-write</access> 23 <fields> 24 <field> 25 <name>DATA</name> 26 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <dim>2</dim> 34 <dimIncrement>2</dimIncrement> 35 <name>FIFO16[%s]</name> 36 <description>Register for reading and writing the FIFO.</description> 37 <alternateRegister>FIFO32</alternateRegister> 38 <addressOffset>0x00</addressOffset> 39 <size>16</size> 40 <access>read-write</access> 41 <fields> 42 <field> 43 <name>DATA</name> 44 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 45 <bitOffset>0</bitOffset> 46 <bitWidth>16</bitWidth> 47 </field> 48 </fields> 49 </register> 50 <register> 51 <dim>4</dim> 52 <dimIncrement>1</dimIncrement> 53 <name>FIFO8[%s]</name> 54 <description>Register for reading and writing the FIFO.</description> 55 <alternateRegister>FIFO32</alternateRegister> 56 <addressOffset>0x00</addressOffset> 57 <size>8</size> 58 <access>read-write</access> 59 <fields> 60 <field> 61 <name>DATA</name> 62 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 63 <bitOffset>0</bitOffset> 64 <bitWidth>8</bitWidth> 65 </field> 66 </fields> 67 </register> 68 <register> 69 <name>CTRL0</name> 70 <description>Register for controlling SPI peripheral.</description> 71 <addressOffset>0x04</addressOffset> 72 <access>read-write</access> 73 <fields> 74 <field> 75 <name>EN</name> 76 <description>SPI Enable.</description> 77 <bitOffset>0</bitOffset> 78 <bitWidth>1</bitWidth> 79 <enumeratedValues> 80 <enumeratedValue> 81 <name>dis</name> 82 <description>SPI is disabled.</description> 83 <value>0</value> 84 </enumeratedValue> 85 <enumeratedValue> 86 <name>en</name> 87 <description>SPI is enabled.</description> 88 <value>1</value> 89 </enumeratedValue> 90 </enumeratedValues> 91 </field> 92 <field> 93 <name>MST_MODE</name> 94 <description>Master Mode Enable.</description> 95 <bitOffset>1</bitOffset> 96 <bitWidth>1</bitWidth> 97 <enumeratedValues> 98 <enumeratedValue> 99 <name>dis</name> 100 <description>SPI is Slave mode.</description> 101 <value>0</value> 102 </enumeratedValue> 103 <enumeratedValue> 104 <name>en</name> 105 <description>SPI is Master mode.</description> 106 <value>1</value> 107 </enumeratedValue> 108 </enumeratedValues> 109 </field> 110 <field> 111 <name>SS_IO</name> 112 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 113 <bitOffset>4</bitOffset> 114 <bitWidth>1</bitWidth> 115 <enumeratedValues> 116 <enumeratedValue> 117 <name>output</name> 118 <description>Slave select 0 is output.</description> 119 <value>0</value> 120 </enumeratedValue> 121 <enumeratedValue> 122 <name>input</name> 123 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 124 <value>1</value> 125 </enumeratedValue> 126 </enumeratedValues> 127 </field> 128 <field> 129 <name>START</name> 130 <description>Start Transmit.</description> 131 <bitOffset>5</bitOffset> 132 <bitWidth>1</bitWidth> 133 <enumeratedValues> 134 <enumeratedValue> 135 <name>start</name> 136 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 137 <value>1</value> 138 </enumeratedValue> 139 </enumeratedValues> 140 </field> 141 <field> 142 <name>SS_CTRL</name> 143 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 144 <bitOffset>8</bitOffset> 145 <bitWidth>1</bitWidth> 146 <enumeratedValues> 147 <enumeratedValue> 148 <name>DEASSERT</name> 149 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 150 <value>0</value> 151 </enumeratedValue> 152 <enumeratedValue> 153 <name>ASSERT</name> 154 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 155 <value>1</value> 156 </enumeratedValue> 157 </enumeratedValues> 158 </field> 159 <field> 160 <name>SS_ACTIVE</name> 161 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 162 <bitOffset>16</bitOffset> 163 <bitWidth>4</bitWidth> 164 <enumeratedValues> 165 <enumeratedValue> 166 <name>SS0</name> 167 <description>SS0 is selected.</description> 168 <value>0x1</value> 169 </enumeratedValue> 170 <enumeratedValue> 171 <name>SS1</name> 172 <description>SS1 is selected.</description> 173 <value>0x2</value> 174 </enumeratedValue> 175 <enumeratedValue> 176 <name>SS2</name> 177 <description>SS2 is selected.</description> 178 <value>0x4</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>SS3</name> 182 <description>SS3 is selected.</description> 183 <value>0x8</value> 184 </enumeratedValue> 185 </enumeratedValues> 186 </field> 187 </fields> 188 </register> 189 <register> 190 <name>CTRL1</name> 191 <description>Register for controlling SPI peripheral.</description> 192 <addressOffset>0x08</addressOffset> 193 <access>read-write</access> 194 <fields> 195 <field> 196 <name>TX_NUM_CHAR</name> 197 <description>Nubmer of Characters to transmit.</description> 198 <bitOffset>0</bitOffset> 199 <bitWidth>16</bitWidth> 200 </field> 201 <field> 202 <name>RX_NUM_CHAR</name> 203 <description>Nubmer of Characters to receive.</description> 204 <bitOffset>16</bitOffset> 205 <bitWidth>16</bitWidth> 206 </field> 207 </fields> 208 </register> 209 <register> 210 <name>CTRL2</name> 211 <description>Register for controlling SPI peripheral.</description> 212 <addressOffset>0x0C</addressOffset> 213 <access>read-write</access> 214 <fields> 215 <field> 216 <name>CLKPHA</name> 217 <description>Clock Phase.</description> 218 <bitOffset>0</bitOffset> 219 <bitWidth>1</bitWidth> 220 <enumeratedValues> 221 <enumeratedValue> 222 <name>Rising_Edge</name> 223 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 224 <value>0</value> 225 </enumeratedValue> 226 <enumeratedValue> 227 <name>Falling_Edge</name> 228 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 229 <value>1</value> 230 </enumeratedValue> 231 </enumeratedValues> 232 </field> 233 <field> 234 <name>CLKPOL</name> 235 <description>Clock Polarity.</description> 236 <bitOffset>1</bitOffset> 237 <bitWidth>1</bitWidth> 238 <enumeratedValues> 239 <enumeratedValue> 240 <name>Normal</name> 241 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 242 <value>0</value> 243 </enumeratedValue> 244 <enumeratedValue> 245 <name>Inverted</name> 246 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 247 <value>1</value> 248 </enumeratedValue> 249 </enumeratedValues> 250 </field> 251 <field> 252 <name>SCLK_FB_INV</name> 253 <description>Clock Polarity.</description> 254 <bitOffset>4</bitOffset> 255 <bitWidth>1</bitWidth> 256 <enumeratedValues> 257 <enumeratedValue> 258 <name>Normal</name> 259 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 260 <value>0</value> 261 </enumeratedValue> 262 <enumeratedValue> 263 <name>Inverted</name> 264 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 265 <value>1</value> 266 </enumeratedValue> 267 </enumeratedValues> 268 </field> 269 <field> 270 <name>NUMBITS</name> 271 <description>Number of Bits per character.</description> 272 <bitOffset>8</bitOffset> 273 <bitWidth>4</bitWidth> 274 <enumeratedValues> 275 <enumeratedValue> 276 <name>16</name> 277 <description>16 bits per character.</description> 278 <value>0</value> 279 </enumeratedValue> 280 <enumeratedValue> 281 <name>1</name> 282 <description>1 bits per character.</description> 283 <value>1</value> 284 </enumeratedValue> 285 <enumeratedValue> 286 <name>2</name> 287 <description>2 bits per character.</description> 288 <value>2</value> 289 </enumeratedValue> 290 <enumeratedValue> 291 <name>3</name> 292 <description>3 bits per character.</description> 293 <value>3</value> 294 </enumeratedValue> 295 <enumeratedValue> 296 <name>4</name> 297 <description>4 bits per character.</description> 298 <value>4</value> 299 </enumeratedValue> 300 <enumeratedValue> 301 <name>5</name> 302 <description>5 bits per character.</description> 303 <value>5</value> 304 </enumeratedValue> 305 <enumeratedValue> 306 <name>6</name> 307 <description>6 bits per character.</description> 308 <value>6</value> 309 </enumeratedValue> 310 <enumeratedValue> 311 <name>7</name> 312 <description>7 bits per character.</description> 313 <value>7</value> 314 </enumeratedValue> 315 <enumeratedValue> 316 <name>8</name> 317 <description>8 bits per character.</description> 318 <value>8</value> 319 </enumeratedValue> 320 <enumeratedValue> 321 <name>9</name> 322 <description>9 bits per character.</description> 323 <value>9</value> 324 </enumeratedValue> 325 <enumeratedValue> 326 <name>10</name> 327 <description>10 bits per character.</description> 328 <value>10</value> 329 </enumeratedValue> 330 <enumeratedValue> 331 <name>11</name> 332 <description>11 bits per character.</description> 333 <value>11</value> 334 </enumeratedValue> 335 <enumeratedValue> 336 <name>12</name> 337 <description>12 bits per character.</description> 338 <value>12</value> 339 </enumeratedValue> 340 <enumeratedValue> 341 <name>13</name> 342 <description>13 bits per character.</description> 343 <value>13</value> 344 </enumeratedValue> 345 <enumeratedValue> 346 <name>14</name> 347 <description>14 bits per character.</description> 348 <value>14</value> 349 </enumeratedValue> 350 <enumeratedValue> 351 <name>15</name> 352 <description>15 bits per character.</description> 353 <value>15</value> 354 </enumeratedValue> 355 </enumeratedValues> 356 </field> 357 <field> 358 <name>DATA_WIDTH</name> 359 <description>SPI Data width.</description> 360 <bitOffset>12</bitOffset> 361 <bitWidth>2</bitWidth> 362 <enumeratedValues> 363 <enumeratedValue> 364 <name>Mono</name> 365 <description>1 data pin.</description> 366 <value>0</value> 367 </enumeratedValue> 368 <enumeratedValue> 369 <name>Dual</name> 370 <description>2 data pins.</description> 371 <value>1</value> 372 </enumeratedValue> 373 <enumeratedValue> 374 <name>Quad</name> 375 <description>4 data pins.</description> 376 <value>2</value> 377 </enumeratedValue> 378 </enumeratedValues> 379 </field> 380 <field> 381 <name>THREE_WIRE</name> 382 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 383 <bitOffset>15</bitOffset> 384 <bitWidth>1</bitWidth> 385 <enumeratedValues> 386 <enumeratedValue> 387 <name>dis</name> 388 <description>Use four wire mode (Mono only).</description> 389 <value>0</value> 390 </enumeratedValue> 391 <enumeratedValue> 392 <name>en</name> 393 <description>Use three wire mode.</description> 394 <value>1</value> 395 </enumeratedValue> 396 </enumeratedValues> 397 </field> 398 <field> 399 <name>SS_POL</name> 400 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 401 <bitOffset>16</bitOffset> 402 <bitWidth>8</bitWidth> 403 <enumeratedValues> 404 <enumeratedValue> 405 <name>SS0_high</name> 406 <description>SS0 active high.</description> 407 <value>0x1</value> 408 </enumeratedValue> 409 <enumeratedValue> 410 <name>SS1_high</name> 411 <description>SS1 active high.</description> 412 <value>0x2</value> 413 </enumeratedValue> 414 <enumeratedValue> 415 <name>SS2_high</name> 416 <description>SS2 active high.</description> 417 <value>0x4</value> 418 </enumeratedValue> 419 <enumeratedValue> 420 <name>SS3_high</name> 421 <description>SS3 active high.</description> 422 <value>0x8</value> 423 </enumeratedValue> 424 </enumeratedValues> 425 </field> 426 </fields> 427 </register> 428 <register> 429 <name>SSTIME</name> 430 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 431 <addressOffset>0x10</addressOffset> 432 <access>read-write</access> 433 <fields> 434 <field> 435 <name>PRE</name> 436 <description>Slave Select Pre delay 1.</description> 437 <bitOffset>0</bitOffset> 438 <bitWidth>8</bitWidth> 439 <enumeratedValues> 440 <enumeratedValue> 441 <name>256</name> 442 <description>256 system clocks between SS active and first serial clock edge.</description> 443 <value>0</value> 444 </enumeratedValue> 445 </enumeratedValues> 446 </field> 447 <field> 448 <name>POST</name> 449 <description>Slave Select Post delay 2.</description> 450 <bitOffset>8</bitOffset> 451 <bitWidth>8</bitWidth> 452 <enumeratedValues> 453 <enumeratedValue> 454 <name>256</name> 455 <description>256 system clocks between last serial clock edge and SS inactive.</description> 456 <value>0</value> 457 </enumeratedValue> 458 </enumeratedValues> 459 </field> 460 <field> 461 <name>INACT</name> 462 <description>Slave Select Inactive delay.</description> 463 <bitOffset>16</bitOffset> 464 <bitWidth>8</bitWidth> 465 <enumeratedValues> 466 <enumeratedValue> 467 <name>256</name> 468 <description>256 system clocks between transactions.</description> 469 <value>0</value> 470 </enumeratedValue> 471 </enumeratedValues> 472 </field> 473 </fields> 474 </register> 475 <register> 476 <name>CLKCTRL</name> 477 <description>Register for controlling SPI clock rate.</description> 478 <addressOffset>0x14</addressOffset> 479 <access>read-write</access> 480 <fields> 481 <field> 482 <name>LO</name> 483 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 484 <bitOffset>0</bitOffset> 485 <bitWidth>8</bitWidth> 486 <enumeratedValues> 487 <enumeratedValue> 488 <name>Dis</name> 489 <description>Duty cycle control of serial clock generation is disabled.</description> 490 <value>0</value> 491 </enumeratedValue> 492 </enumeratedValues> 493 </field> 494 <field> 495 <name>HI</name> 496 <description>High duty cycle control. In timer mode, reload[15:8].</description> 497 <bitOffset>8</bitOffset> 498 <bitWidth>8</bitWidth> 499 <enumeratedValues> 500 <enumeratedValue> 501 <name>Dis</name> 502 <description>Duty cycle control of serial clock generation is disabled.</description> 503 <value>0</value> 504 </enumeratedValue> 505 </enumeratedValues> 506 </field> 507 <field> 508 <name>CLKDIV</name> 509 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 510 <bitOffset>16</bitOffset> 511 <bitWidth>4</bitWidth> 512 </field> 513 <field> 514 <name>AFP_FCD</name> 515 <description>AFP FCD.</description> 516 <bitOffset>24</bitOffset> 517 <bitWidth>3</bitWidth> 518 </field> 519 </fields> 520 </register> 521 <register> 522 <name>DMA</name> 523 <description>Register for controlling DMA.</description> 524 <addressOffset>0x1C</addressOffset> 525 <access>read-write</access> 526 <fields> 527 <field> 528 <name>TX_THD_VAL</name> 529 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 530 <bitOffset>0</bitOffset> 531 <bitWidth>5</bitWidth> 532 </field> 533 <field> 534 <name>TX_FIFO_EN</name> 535 <description>Transmit FIFO enabled for SPI transactions.</description> 536 <bitOffset>6</bitOffset> 537 <bitWidth>1</bitWidth> 538 <enumeratedValues> 539 <enumeratedValue> 540 <name>dis</name> 541 <description>Transmit FIFO is not enabled.</description> 542 <value>0</value> 543 </enumeratedValue> 544 <enumeratedValue> 545 <name>en</name> 546 <description>Transmit FIFO is enabled.</description> 547 <value>1</value> 548 </enumeratedValue> 549 </enumeratedValues> 550 </field> 551 <field> 552 <name>TX_FLUSH</name> 553 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 554 <bitOffset>7</bitOffset> 555 <bitWidth>1</bitWidth> 556 <enumeratedValues> 557 <enumeratedValue> 558 <name>CLEAR</name> 559 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 560 <value>1</value> 561 </enumeratedValue> 562 </enumeratedValues> 563 </field> 564 <field> 565 <name>TX_LVL</name> 566 <description>Count of entries in TX FIFO.</description> 567 <bitOffset>8</bitOffset> 568 <bitWidth>6</bitWidth> 569 <access>read-only</access> 570 </field> 571 <field> 572 <name>DMA_TX_EN</name> 573 <description>TX DMA Enable.</description> 574 <bitOffset>15</bitOffset> 575 <bitWidth>1</bitWidth> 576 <enumeratedValues> 577 <enumeratedValue> 578 <name>DIS</name> 579 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 580 <value>0</value> 581 </enumeratedValue> 582 <enumeratedValue> 583 <name>en</name> 584 <description>TX DMA requests are enabled.</description> 585 <value>1</value> 586 </enumeratedValue> 587 </enumeratedValues> 588 </field> 589 <field> 590 <name>RX_THD_VAL</name> 591 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 592 <bitOffset>16</bitOffset> 593 <bitWidth>5</bitWidth> 594 </field> 595 <field> 596 <name>RX_FIFO_EN</name> 597 <description>Receive FIFO enabled for SPI transactions.</description> 598 <bitOffset>22</bitOffset> 599 <bitWidth>1</bitWidth> 600 <enumeratedValues> 601 <enumeratedValue> 602 <name>DIS</name> 603 <description>Receive FIFO is not enabled.</description> 604 <value>0</value> 605 </enumeratedValue> 606 <enumeratedValue> 607 <name>en</name> 608 <description>Receive FIFO is enabled.</description> 609 <value>1</value> 610 </enumeratedValue> 611 </enumeratedValues> 612 </field> 613 <field> 614 <name>RX_FLUSH</name> 615 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 616 <bitOffset>23</bitOffset> 617 <bitWidth>1</bitWidth> 618 <enumeratedValues> 619 <enumeratedValue> 620 <name>CLEAR</name> 621 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 622 <value>1</value> 623 </enumeratedValue> 624 </enumeratedValues> 625 </field> 626 <field> 627 <name>RX_LVL</name> 628 <description>Count of entries in RX FIFO.</description> 629 <bitOffset>24</bitOffset> 630 <bitWidth>6</bitWidth> 631 <access>read-only</access> 632 </field> 633 <field> 634 <name>DMA_RX_EN</name> 635 <description>RX DMA Enable.</description> 636 <bitOffset>31</bitOffset> 637 <bitWidth>1</bitWidth> 638 <enumeratedValues> 639 <enumeratedValue> 640 <name>dis</name> 641 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 642 <value>0</value> 643 </enumeratedValue> 644 <enumeratedValue> 645 <name>en</name> 646 <description>RX DMA requests are enabled.</description> 647 <value>1</value> 648 </enumeratedValue> 649 </enumeratedValues> 650 </field> 651 </fields> 652 </register> 653 <register> 654 <name>INTFL</name> 655 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 656 <addressOffset>0x20</addressOffset> 657 <access>read-write</access> 658 <fields> 659 <field> 660 <name>TX_THD</name> 661 <description>TX FIFO Threshold Crossed.</description> 662 <bitOffset>0</bitOffset> 663 <bitWidth>1</bitWidth> 664 <enumeratedValues> 665 <enumeratedValue> 666 <name>clear</name> 667 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 668 <value>1</value> 669 </enumeratedValue> 670 </enumeratedValues> 671 </field> 672 <field> 673 <name>TX_EM</name> 674 <description>TX FIFO Empty.</description> 675 <bitOffset>1</bitOffset> 676 <bitWidth>1</bitWidth> 677 <enumeratedValues> 678 <enumeratedValue> 679 <name>clear</name> 680 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 681 <value>1</value> 682 </enumeratedValue> 683 </enumeratedValues> 684 </field> 685 <field> 686 <name>RX_THD</name> 687 <description>RX FIFO Threshold Crossed.</description> 688 <bitOffset>2</bitOffset> 689 <bitWidth>1</bitWidth> 690 <enumeratedValues> 691 <enumeratedValue> 692 <name>clear</name> 693 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 694 <value>1</value> 695 </enumeratedValue> 696 </enumeratedValues> 697 </field> 698 <field> 699 <name>RX_FULL</name> 700 <description>RX FIFO FULL.</description> 701 <bitOffset>3</bitOffset> 702 <bitWidth>1</bitWidth> 703 <enumeratedValues> 704 <enumeratedValue> 705 <name>clear</name> 706 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 707 <value>1</value> 708 </enumeratedValue> 709 </enumeratedValues> 710 </field> 711 <field> 712 <name>SSA</name> 713 <description>Slave Select Asserted.</description> 714 <bitOffset>4</bitOffset> 715 <bitWidth>1</bitWidth> 716 <enumeratedValues> 717 <enumeratedValue> 718 <name>clear</name> 719 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 720 <value>1</value> 721 </enumeratedValue> 722 </enumeratedValues> 723 </field> 724 <field> 725 <name>SSD</name> 726 <description>Slave Select Deasserted.</description> 727 <bitOffset>5</bitOffset> 728 <bitWidth>1</bitWidth> 729 <enumeratedValues> 730 <enumeratedValue> 731 <name>clear</name> 732 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 733 <value>1</value> 734 </enumeratedValue> 735 </enumeratedValues> 736 </field> 737 <field> 738 <name>FAULT</name> 739 <description>Multi-Master Mode Fault.</description> 740 <bitOffset>8</bitOffset> 741 <bitWidth>1</bitWidth> 742 <enumeratedValues> 743 <enumeratedValue> 744 <name>clear</name> 745 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 746 <value>1</value> 747 </enumeratedValue> 748 </enumeratedValues> 749 </field> 750 <field> 751 <name>ABORT</name> 752 <description>Slave Abort Detected.</description> 753 <bitOffset>9</bitOffset> 754 <bitWidth>1</bitWidth> 755 <enumeratedValues> 756 <enumeratedValue> 757 <name>clear</name> 758 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 759 <value>1</value> 760 </enumeratedValue> 761 </enumeratedValues> 762 </field> 763 <field> 764 <name>MST_DONE</name> 765 <description>Master Done, set when SPI Master has completed any transactions.</description> 766 <bitOffset>11</bitOffset> 767 <bitWidth>1</bitWidth> 768 <enumeratedValues> 769 <enumeratedValue> 770 <name>clear</name> 771 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 772 <value>1</value> 773 </enumeratedValue> 774 </enumeratedValues> 775 </field> 776 <field> 777 <name>TX_OV</name> 778 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 779 <bitOffset>12</bitOffset> 780 <bitWidth>1</bitWidth> 781 <enumeratedValues> 782 <enumeratedValue> 783 <name>clear</name> 784 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 785 <value>1</value> 786 </enumeratedValue> 787 </enumeratedValues> 788 </field> 789 <field> 790 <name>TX_UN</name> 791 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 792 <bitOffset>13</bitOffset> 793 <bitWidth>1</bitWidth> 794 <enumeratedValues> 795 <enumeratedValue> 796 <name>clear</name> 797 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 798 <value>1</value> 799 </enumeratedValue> 800 </enumeratedValues> 801 </field> 802 <field> 803 <name>RX_OV</name> 804 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 805 <bitOffset>14</bitOffset> 806 <bitWidth>1</bitWidth> 807 <enumeratedValues> 808 <enumeratedValue> 809 <name>clear</name> 810 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 811 <value>1</value> 812 </enumeratedValue> 813 </enumeratedValues> 814 </field> 815 <field> 816 <name>RX_UN</name> 817 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 818 <bitOffset>15</bitOffset> 819 <bitWidth>1</bitWidth> 820 <enumeratedValues> 821 <enumeratedValue> 822 <name>clear</name> 823 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 824 <value>1</value> 825 </enumeratedValue> 826 </enumeratedValues> 827 </field> 828 </fields> 829 </register> 830 <register> 831 <name>INTEN</name> 832 <description>Register for enabling interrupts.</description> 833 <addressOffset>0x24</addressOffset> 834 <access>read-write</access> 835 <fields> 836 <field> 837 <name>TX_THD</name> 838 <description>TX FIFO Threshold interrupt enable.</description> 839 <bitOffset>0</bitOffset> 840 <bitWidth>1</bitWidth> 841 <enumeratedValues> 842 <enumeratedValue> 843 <name>dis</name> 844 <description>Interrupt is disabled.</description> 845 <value>0</value> 846 </enumeratedValue> 847 <enumeratedValue> 848 <name>en</name> 849 <description>Interrupt is enabled.</description> 850 <value>1</value> 851 </enumeratedValue> 852 </enumeratedValues> 853 </field> 854 <field> 855 <name>TX_EM</name> 856 <description>TX FIFO Empty interrupt enable.</description> 857 <bitOffset>1</bitOffset> 858 <bitWidth>1</bitWidth> 859 <enumeratedValues> 860 <enumeratedValue> 861 <name>dis</name> 862 <description>Interrupt is disabled.</description> 863 <value>0</value> 864 </enumeratedValue> 865 <enumeratedValue> 866 <name>en</name> 867 <description>Interrupt is enabled.</description> 868 <value>1</value> 869 </enumeratedValue> 870 </enumeratedValues> 871 </field> 872 <field> 873 <name>RX_THD</name> 874 <description>RX FIFO Threshold Crossed interrupt enable.</description> 875 <bitOffset>2</bitOffset> 876 <bitWidth>1</bitWidth> 877 <enumeratedValues> 878 <enumeratedValue> 879 <name>dis</name> 880 <description>Interrupt is disabled.</description> 881 <value>0</value> 882 </enumeratedValue> 883 <enumeratedValue> 884 <name>en</name> 885 <description>Interrupt is enabled.</description> 886 <value>1</value> 887 </enumeratedValue> 888 </enumeratedValues> 889 </field> 890 <field> 891 <name>RX_FULL</name> 892 <description>RX FIFO FULL interrupt enable.</description> 893 <bitOffset>3</bitOffset> 894 <bitWidth>1</bitWidth> 895 <enumeratedValues> 896 <enumeratedValue> 897 <name>dis</name> 898 <description>Interrupt is disabled.</description> 899 <value>0</value> 900 </enumeratedValue> 901 <enumeratedValue> 902 <name>en</name> 903 <description>Interrupt is enabled.</description> 904 <value>1</value> 905 </enumeratedValue> 906 </enumeratedValues> 907 </field> 908 <field> 909 <name>SSA</name> 910 <description>Slave Select Asserted interrupt enable.</description> 911 <bitOffset>4</bitOffset> 912 <bitWidth>1</bitWidth> 913 <enumeratedValues> 914 <enumeratedValue> 915 <name>dis</name> 916 <description>Interrupt is disabled.</description> 917 <value>0</value> 918 </enumeratedValue> 919 <enumeratedValue> 920 <name>en</name> 921 <description>Interrupt is enabled.</description> 922 <value>1</value> 923 </enumeratedValue> 924 </enumeratedValues> 925 </field> 926 <field> 927 <name>SSD</name> 928 <description>Slave Select Deasserted interrupt enable.</description> 929 <bitOffset>5</bitOffset> 930 <bitWidth>1</bitWidth> 931 <enumeratedValues> 932 <enumeratedValue> 933 <name>dis</name> 934 <description>Interrupt is disabled.</description> 935 <value>0</value> 936 </enumeratedValue> 937 <enumeratedValue> 938 <name>en</name> 939 <description>Interrupt is enabled.</description> 940 <value>1</value> 941 </enumeratedValue> 942 </enumeratedValues> 943 </field> 944 <field> 945 <name>FAULT</name> 946 <description>Multi-Master Mode Fault interrupt enable.</description> 947 <bitOffset>8</bitOffset> 948 <bitWidth>1</bitWidth> 949 <enumeratedValues> 950 <enumeratedValue> 951 <name>dis</name> 952 <description>Interrupt is disabled.</description> 953 <value>0</value> 954 </enumeratedValue> 955 <enumeratedValue> 956 <name>en</name> 957 <description>Interrupt is enabled.</description> 958 <value>1</value> 959 </enumeratedValue> 960 </enumeratedValues> 961 </field> 962 <field> 963 <name>ABORT</name> 964 <description>Slave Abort Detected interrupt enable.</description> 965 <bitOffset>9</bitOffset> 966 <bitWidth>1</bitWidth> 967 <enumeratedValues> 968 <enumeratedValue> 969 <name>dis</name> 970 <description>Interrupt is disabled.</description> 971 <value>0</value> 972 </enumeratedValue> 973 <enumeratedValue> 974 <name>en</name> 975 <description>Interrupt is enabled.</description> 976 <value>1</value> 977 </enumeratedValue> 978 </enumeratedValues> 979 </field> 980 <field> 981 <name>MST_DONE</name> 982 <description>Master Done interrupt enable.</description> 983 <bitOffset>11</bitOffset> 984 <bitWidth>1</bitWidth> 985 <enumeratedValues> 986 <enumeratedValue> 987 <name>dis</name> 988 <description>Interrupt is disabled.</description> 989 <value>0</value> 990 </enumeratedValue> 991 <enumeratedValue> 992 <name>en</name> 993 <description>Interrupt is enabled.</description> 994 <value>1</value> 995 </enumeratedValue> 996 </enumeratedValues> 997 </field> 998 <field> 999 <name>TX_OV</name> 1000 <description>Transmit FIFO Overrun interrupt enable.</description> 1001 <bitOffset>12</bitOffset> 1002 <bitWidth>1</bitWidth> 1003 <enumeratedValues> 1004 <enumeratedValue> 1005 <name>dis</name> 1006 <description>Interrupt is disabled.</description> 1007 <value>0</value> 1008 </enumeratedValue> 1009 <enumeratedValue> 1010 <name>en</name> 1011 <description>Interrupt is enabled.</description> 1012 <value>1</value> 1013 </enumeratedValue> 1014 </enumeratedValues> 1015 </field> 1016 <field> 1017 <name>TX_UN</name> 1018 <description>Transmit FIFO Underrun interrupt enable.</description> 1019 <bitOffset>13</bitOffset> 1020 <bitWidth>1</bitWidth> 1021 <enumeratedValues> 1022 <enumeratedValue> 1023 <name>dis</name> 1024 <description>Interrupt is disabled.</description> 1025 <value>0</value> 1026 </enumeratedValue> 1027 <enumeratedValue> 1028 <name>en</name> 1029 <description>Interrupt is enabled.</description> 1030 <value>1</value> 1031 </enumeratedValue> 1032 </enumeratedValues> 1033 </field> 1034 <field> 1035 <name>RX_OV</name> 1036 <description>Receive FIFO Overrun interrupt enable.</description> 1037 <bitOffset>14</bitOffset> 1038 <bitWidth>1</bitWidth> 1039 <enumeratedValues> 1040 <enumeratedValue> 1041 <name>dis</name> 1042 <description>Interrupt is disabled.</description> 1043 <value>0</value> 1044 </enumeratedValue> 1045 <enumeratedValue> 1046 <name>en</name> 1047 <description>Interrupt is enabled.</description> 1048 <value>1</value> 1049 </enumeratedValue> 1050 </enumeratedValues> 1051 </field> 1052 <field> 1053 <name>RX_UN</name> 1054 <description>Receive FIFO Underrun interrupt enable.</description> 1055 <bitOffset>15</bitOffset> 1056 <bitWidth>1</bitWidth> 1057 <enumeratedValues> 1058 <enumeratedValue> 1059 <name>dis</name> 1060 <description>Interrupt is disabled.</description> 1061 <value>0</value> 1062 </enumeratedValue> 1063 <enumeratedValue> 1064 <name>en</name> 1065 <description>Interrupt is enabled.</description> 1066 <value>1</value> 1067 </enumeratedValue> 1068 </enumeratedValues> 1069 </field> 1070 </fields> 1071 </register> 1072 <register> 1073 <name>WKFL</name> 1074 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 1075 <addressOffset>0x28</addressOffset> 1076 <access>read-write</access> 1077 <fields> 1078 <field> 1079 <name>TX_THD</name> 1080 <description>Wake on TX FIFO Threshold Crossed.</description> 1081 <bitOffset>0</bitOffset> 1082 <bitWidth>1</bitWidth> 1083 <enumeratedValues> 1084 <enumeratedValue> 1085 <name>clear</name> 1086 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1087 <value>1</value> 1088 </enumeratedValue> 1089 </enumeratedValues> 1090 </field> 1091 <field> 1092 <name>TX_EM</name> 1093 <description>Wake on TX FIFO Empty.</description> 1094 <bitOffset>1</bitOffset> 1095 <bitWidth>1</bitWidth> 1096 <enumeratedValues> 1097 <enumeratedValue> 1098 <name>clear</name> 1099 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1100 <value>1</value> 1101 </enumeratedValue> 1102 </enumeratedValues> 1103 </field> 1104 <field> 1105 <name>RX_THD</name> 1106 <description>Wake on RX FIFO Threshold Crossed.</description> 1107 <bitOffset>2</bitOffset> 1108 <bitWidth>1</bitWidth> 1109 <enumeratedValues> 1110 <enumeratedValue> 1111 <name>clear</name> 1112 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1113 <value>1</value> 1114 </enumeratedValue> 1115 </enumeratedValues> 1116 </field> 1117 <field> 1118 <name>RX_FULL</name> 1119 <description>Wake on RX FIFO Full.</description> 1120 <bitOffset>3</bitOffset> 1121 <bitWidth>1</bitWidth> 1122 <enumeratedValues> 1123 <enumeratedValue> 1124 <name>clear</name> 1125 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 1126 <value>1</value> 1127 </enumeratedValue> 1128 </enumeratedValues> 1129 </field> 1130 </fields> 1131 </register> 1132 <register> 1133 <name>WKEN</name> 1134 <description>Register for wake up enable.</description> 1135 <addressOffset>0x2C</addressOffset> 1136 <access>read-write</access> 1137 <fields> 1138 <field> 1139 <name>TX_THD</name> 1140 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 1141 <bitOffset>0</bitOffset> 1142 <bitWidth>1</bitWidth> 1143 <enumeratedValues> 1144 <enumeratedValue> 1145 <name>dis</name> 1146 <description>Wakeup source disabled.</description> 1147 <value>0</value> 1148 </enumeratedValue> 1149 <enumeratedValue> 1150 <name>en</name> 1151 <description>Wakeup source enabled.</description> 1152 <value>1</value> 1153 </enumeratedValue> 1154 </enumeratedValues> 1155 </field> 1156 <field> 1157 <name>TX_EM</name> 1158 <description>Wake on TX FIFO Empty Enable.</description> 1159 <bitOffset>1</bitOffset> 1160 <bitWidth>1</bitWidth> 1161 <enumeratedValues> 1162 <enumeratedValue> 1163 <name>dis</name> 1164 <description>Wakeup source disabled.</description> 1165 <value>0</value> 1166 </enumeratedValue> 1167 <enumeratedValue> 1168 <name>en</name> 1169 <description>Wakeup source enabled.</description> 1170 <value>1</value> 1171 </enumeratedValue> 1172 </enumeratedValues> 1173 </field> 1174 <field> 1175 <name>RX_THD</name> 1176 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 1177 <bitOffset>2</bitOffset> 1178 <bitWidth>1</bitWidth> 1179 <enumeratedValues> 1180 <enumeratedValue> 1181 <name>dis</name> 1182 <description>Wakeup source disabled.</description> 1183 <value>0</value> 1184 </enumeratedValue> 1185 <enumeratedValue> 1186 <name>en</name> 1187 <description>Wakeup source enabled.</description> 1188 <value>1</value> 1189 </enumeratedValue> 1190 </enumeratedValues> 1191 </field> 1192 <field> 1193 <name>RX_FULL</name> 1194 <description>Wake on RX FIFO Full Enable.</description> 1195 <bitOffset>3</bitOffset> 1196 <bitWidth>1</bitWidth> 1197 <enumeratedValues> 1198 <enumeratedValue> 1199 <name>dis</name> 1200 <description>Wakeup source disabled.</description> 1201 <value>0</value> 1202 </enumeratedValue> 1203 <enumeratedValue> 1204 <name>en</name> 1205 <description>Wakeup source enabled.</description> 1206 <value>1</value> 1207 </enumeratedValue> 1208 </enumeratedValues> 1209 </field> 1210 </fields> 1211 </register> 1212 <register> 1213 <name>STAT</name> 1214 <description>SPI Status register.</description> 1215 <addressOffset>0x30</addressOffset> 1216 <access>read-only</access> 1217 <fields> 1218 <field> 1219 <name>BUSY</name> 1220 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 1221 <bitOffset>0</bitOffset> 1222 <bitWidth>1</bitWidth> 1223 <enumeratedValues> 1224 <enumeratedValue> 1225 <name>not</name> 1226 <description>SPI not active.</description> 1227 <value>0</value> 1228 </enumeratedValue> 1229 <enumeratedValue> 1230 <name>active</name> 1231 <description>SPI active.</description> 1232 <value>1</value> 1233 </enumeratedValue> 1234 </enumeratedValues> 1235 </field> 1236 </fields> 1237 </register> 1238 </registers> 1239 </peripheral> 1240 <!-- SPI: Serial Peripheral Interface --> 1241</device>
