SPI0 SPI peripheral. 0x40046000 0x00 0x1000 registers SPI0 16 FIFO32 Register for reading and writing the FIFO. 0x00 32 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 32 2 2 FIFO16[%s] Register for reading and writing the FIFO. FIFO32 0x00 16 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 16 4 1 FIFO8[%s] Register for reading and writing the FIFO. FIFO32 0x00 8 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 8 CTRL0 Register for controlling SPI peripheral. 0x04 read-write EN SPI Enable. 0 1 dis SPI is disabled. 0 en SPI is enabled. 1 MST_MODE Master Mode Enable. 1 1 dis SPI is Slave mode. 0 en SPI is Master mode. 1 SS_IO Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 4 1 output Slave select 0 is output. 0 input Slave Select 0 is input, only valid if MMEN=1. 1 START Start Transmit. 5 1 start Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. 1 SS_CTRL Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. 8 1 DEASSERT SPI De-asserts Slave Select at the end of a transaction. 0 ASSERT SPI leaves Slave Select asserted at the end of a transaction. 1 SS_ACTIVE Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 16 4 SS0 SS0 is selected. 0x1 SS1 SS1 is selected. 0x2 SS2 SS2 is selected. 0x4 SS3 SS3 is selected. 0x8 CTRL1 Register for controlling SPI peripheral. 0x08 read-write TX_NUM_CHAR Nubmer of Characters to transmit. 0 16 RX_NUM_CHAR Nubmer of Characters to receive. 16 16 CTRL2 Register for controlling SPI peripheral. 0x0C read-write CLKPHA Clock Phase. 0 1 Rising_Edge Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 0 Falling_Edge Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 1 CLKPOL Clock Polarity. 1 1 Normal Normal Clock. Use when in SPI Mode 0 and Mode 1 0 Inverted Inverted Clock. Use when in SPI Mode 2 and Mode 3 1 SCLK_FB_INV Clock Polarity. 4 1 Normal Normal Clock. Use when in SPI Mode 0 and Mode 1 0 Inverted Inverted Clock. Use when in SPI Mode 2 and Mode 3 1 NUMBITS Number of Bits per character. 8 4 16 16 bits per character. 0 1 1 bits per character. 1 2 2 bits per character. 2 3 3 bits per character. 3 4 4 bits per character. 4 5 5 bits per character. 5 6 6 bits per character. 6 7 7 bits per character. 7 8 8 bits per character. 8 9 9 bits per character. 9 10 10 bits per character. 10 11 11 bits per character. 11 12 12 bits per character. 12 13 13 bits per character. 13 14 14 bits per character. 14 15 15 bits per character. 15 DATA_WIDTH SPI Data width. 12 2 Mono 1 data pin. 0 Dual 2 data pins. 1 Quad 4 data pins. 2 THREE_WIRE Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 15 1 dis Use four wire mode (Mono only). 0 en Use three wire mode. 1 SS_POL Slave Select Polarity, each Slave Select can have unique polarity. 16 8 SS0_high SS0 active high. 0x1 SS1_high SS1 active high. 0x2 SS2_high SS2 active high. 0x4 SS3_high SS3 active high. 0x8 SSTIME Register for controlling SPI peripheral/Slave Select Timing. 0x10 read-write PRE Slave Select Pre delay 1. 0 8 256 256 system clocks between SS active and first serial clock edge. 0 POST Slave Select Post delay 2. 8 8 256 256 system clocks between last serial clock edge and SS inactive. 0 INACT Slave Select Inactive delay. 16 8 256 256 system clocks between transactions. 0 CLKCTRL Register for controlling SPI clock rate. 0x14 read-write LO Low duty cycle control. In timer mode, reload[7:0]. 0 8 Dis Duty cycle control of serial clock generation is disabled. 0 HI High duty cycle control. In timer mode, reload[15:8]. 8 8 Dis Duty cycle control of serial clock generation is disabled. 0 CLKDIV System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. 16 4 AFP_FCD AFP FCD. 24 3 DMA Register for controlling DMA. 0x1C read-write TX_THD_VAL Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. 0 5 TX_FIFO_EN Transmit FIFO enabled for SPI transactions. 6 1 dis Transmit FIFO is not enabled. 0 en Transmit FIFO is enabled. 1 TX_FLUSH Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 7 1 CLEAR Clear the Transmit FIFO, clears any pending TX FIFO status. 1 TX_LVL Count of entries in TX FIFO. 8 6 read-only DMA_TX_EN TX DMA Enable. 15 1 DIS TX DMA requests are disabled, andy pending DMA requests are cleared. 0 en TX DMA requests are enabled. 1 RX_THD_VAL Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. 16 5 RX_FIFO_EN Receive FIFO enabled for SPI transactions. 22 1 DIS Receive FIFO is not enabled. 0 en Receive FIFO is enabled. 1 RX_FLUSH Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 23 1 CLEAR Clear the Receive FIFO, clears any pending RX FIFO status. 1 RX_LVL Count of entries in RX FIFO. 24 6 read-only DMA_RX_EN RX DMA Enable. 31 1 dis RX DMA requests are disabled, any pending DMA requests are cleared. 0 en RX DMA requests are enabled. 1 INTFL Register for reading and clearing interrupt flags. All bits are write 1 to clear. 0x20 read-write TX_THD TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL RX FIFO FULL. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSA Slave Select Asserted. 4 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSD Slave Select Deasserted. 5 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 FAULT Multi-Master Mode Fault. 8 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 ABORT Slave Abort Detected. 9 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 MST_DONE Master Done, set when SPI Master has completed any transactions. 11 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_OV Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 12 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_UN Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. 13 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_OV Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. 14 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_UN Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. 15 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 INTEN Register for enabling interrupts. 0x24 read-write TX_THD TX FIFO Threshold interrupt enable. 0 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_EM TX FIFO Empty interrupt enable. 1 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_THD RX FIFO Threshold Crossed interrupt enable. 2 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_FULL RX FIFO FULL interrupt enable. 3 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSA Slave Select Asserted interrupt enable. 4 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSD Slave Select Deasserted interrupt enable. 5 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 FAULT Multi-Master Mode Fault interrupt enable. 8 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 ABORT Slave Abort Detected interrupt enable. 9 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 MST_DONE Master Done interrupt enable. 11 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_OV Transmit FIFO Overrun interrupt enable. 12 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_UN Transmit FIFO Underrun interrupt enable. 13 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_OV Receive FIFO Overrun interrupt enable. 14 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_UN Receive FIFO Underrun interrupt enable. 15 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 WKFL Register for wake up flags. All bits in this register are write 1 to clear. 0x28 read-write TX_THD Wake on TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM Wake on TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD Wake on RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL Wake on RX FIFO Full. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 WKEN Register for wake up enable. 0x2C read-write TX_THD Wake on TX FIFO Threshold Crossed Enable. 0 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 TX_EM Wake on TX FIFO Empty Enable. 1 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_THD Wake on RX FIFO Threshold Crossed Enable. 2 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_FULL Wake on RX FIFO Full Enable. 3 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 STAT SPI Status register. 0x30 read-only BUSY SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 0 1 not SPI not active. 0 active SPI active. 1