1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>RTC</name> 5 <description>Real Time Clock and Alarm.</description> 6 <baseAddress>0x40006000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>RTC</name> 14 <description>RTC interrupt.</description> 15 <value>3</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>SEC</name> 20 <description>RTC Second Counter. This register contains the 32-bit second counter.</description> 21 <addressOffset>0x00</addressOffset> 22 <resetMask>0x00000000</resetMask> 23 <fields> 24 <field> 25 <name>RTS</name> 26 <description>Seconds Counter.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <name>SSEC</name> 34 <description>RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.</description> 35 <addressOffset>0x04</addressOffset> 36 <resetMask>0x00000000</resetMask> 37 <fields> 38 <field> 39 <name>RTSS</name> 40 <description>Sub-Seconds Counter (8-bit).</description> 41 <bitOffset>0</bitOffset> 42 <bitWidth>8</bitWidth> 43 </field> 44 </fields> 45 </register> 46 <register> 47 <name>RAS</name> 48 <description>Time-of-day Alarm.</description> 49 <addressOffset>0x08</addressOffset> 50 <resetMask>0x00000000</resetMask> 51 <fields> 52 <field> 53 <name>RAS</name> 54 <description>Time-of-day Alarm.</description> 55 <bitOffset>0</bitOffset> 56 <bitWidth>20</bitWidth> 57 </field> 58 </fields> 59 </register> 60 <register> 61 <name>RSSA</name> 62 <description>RTC sub-second alarm. This register contains the reload value for the sub-second alarm.</description> 63 <addressOffset>0x0C</addressOffset> 64 <resetMask>0x00000000</resetMask> 65 <fields> 66 <field> 67 <name>RSSA</name> 68 <description>This register contains the reload value for the sub-second alarm.</description> 69 <bitOffset>0</bitOffset> 70 <bitWidth>32</bitWidth> 71 </field> 72 </fields> 73 </register> 74 <register> 75 <name>CTRL</name> 76 <description>RTC Control Register.</description> 77 <addressOffset>0x10</addressOffset> 78 <resetValue>0x00000008</resetValue> 79 <resetMask>0xFFFFFF38</resetMask> 80 <fields> 81 <field> 82 <name>ENABLE</name> 83 <description>Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 84 <bitOffset>0</bitOffset> 85 <bitWidth>1</bitWidth> 86 <enumeratedValues> 87 <enumeratedValue> 88 <name>dis</name> 89 <description>Disable.</description> 90 <value>0</value> 91 </enumeratedValue> 92 <enumeratedValue> 93 <name>en</name> 94 <description>Enable.</description> 95 <value>1</value> 96 </enumeratedValue> 97 </enumeratedValues> 98 </field> 99 <field> 100 <name>ALARM_TOD_EN</name> 101 <description>Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 102 <bitOffset>1</bitOffset> 103 <bitWidth>1</bitWidth> 104 <enumeratedValues> 105 <enumeratedValue> 106 <name>dis</name> 107 <description>Disable.</description> 108 <value>0</value> 109 </enumeratedValue> 110 <enumeratedValue> 111 <name>en</name> 112 <description>Enable.</description> 113 <value>1</value> 114 </enumeratedValue> 115 </enumeratedValues> 116 </field> 117 <field> 118 <name>ALARM_SS_EN</name> 119 <description>Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 120 <bitOffset>2</bitOffset> 121 <bitWidth>1</bitWidth> 122 <enumeratedValues> 123 <enumeratedValue> 124 <name>dis</name> 125 <description>Disable.</description> 126 <value>0</value> 127 </enumeratedValue> 128 <enumeratedValue> 129 <name>en</name> 130 <description>Enable.</description> 131 <value>1</value> 132 </enumeratedValue> 133 </enumeratedValues> 134 </field> 135 <field> 136 <name>BUSY</name> 137 <description>RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.</description> 138 <bitOffset>3</bitOffset> 139 <bitWidth>1</bitWidth> 140 <access>read-only</access> 141 <enumeratedValues> 142 <enumeratedValue> 143 <name>idle</name> 144 <description>Idle.</description> 145 <value>0</value> 146 </enumeratedValue> 147 <enumeratedValue> 148 <name>busy</name> 149 <description>Busy.</description> 150 <value>1</value> 151 </enumeratedValue> 152 </enumeratedValues> 153 </field> 154 <field> 155 <name>READY</name> 156 <description>RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.</description> 157 <bitOffset>4</bitOffset> 158 <bitWidth>1</bitWidth> 159 <enumeratedValues> 160 <enumeratedValue> 161 <name>busy</name> 162 <description>Register has not updated.</description> 163 <value>0</value> 164 </enumeratedValue> 165 <enumeratedValue> 166 <name>ready</name> 167 <description>Ready.</description> 168 <value>1</value> 169 </enumeratedValue> 170 </enumeratedValues> 171 </field> 172 <field> 173 <name>READY_INT_EN</name> 174 <description>RTC Ready Interrupt Enable.</description> 175 <bitOffset>5</bitOffset> 176 <bitWidth>1</bitWidth> 177 <enumeratedValues> 178 <enumeratedValue> 179 <name>dis</name> 180 <description>Disable.</description> 181 <value>0</value> 182 </enumeratedValue> 183 <enumeratedValue> 184 <name>en</name> 185 <description>Enable.</description> 186 <value>1</value> 187 </enumeratedValue> 188 </enumeratedValues> 189 </field> 190 <field> 191 <name>ALARM_TOD_FL</name> 192 <description>Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 193 <bitOffset>6</bitOffset> 194 <bitWidth>1</bitWidth> 195 <access>read-only</access> 196 <enumeratedValues> 197 <enumeratedValue> 198 <name>inactive</name> 199 <description>Not active</description> 200 <value>0</value> 201 </enumeratedValue> 202 <enumeratedValue> 203 <name>Pending</name> 204 <description>Active</description> 205 <value>1</value> 206 </enumeratedValue> 207 </enumeratedValues> 208 </field> 209 <field> 210 <name>ALARM_SS_FL</name> 211 <description>Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 212 <bitOffset>7</bitOffset> 213 <bitWidth>1</bitWidth> 214 <access>read-only</access> 215 <enumeratedValues> 216 <enumeratedValue> 217 <name>inactive</name> 218 <description>Not active</description> 219 <value>0</value> 220 </enumeratedValue> 221 <enumeratedValue> 222 <name>Pending</name> 223 <description>Active</description> 224 <value>1</value> 225 </enumeratedValue> 226 </enumeratedValues> 227 </field> 228 <field> 229 <name>32KOUT_EN</name> 230 <description>Square Wave Output Enable.</description> 231 <bitOffset>8</bitOffset> 232 <bitWidth>1</bitWidth> 233 <enumeratedValues> 234 <enumeratedValue> 235 <name>inactive</name> 236 <description>Not active</description> 237 <value>0</value> 238 </enumeratedValue> 239 <enumeratedValue> 240 <name>Pending</name> 241 <description>Active</description> 242 <value>1</value> 243 </enumeratedValue> 244 </enumeratedValues> 245 </field> 246 <field> 247 <name>FREQ_SEL</name> 248 <description>Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.</description> 249 <bitOffset>9</bitOffset> 250 <bitWidth>2</bitWidth> 251 <enumeratedValues> 252 <enumeratedValue> 253 <name>freq1Hz</name> 254 <description>1 Hz (Compensated).</description> 255 <value>0</value> 256 </enumeratedValue> 257 <enumeratedValue> 258 <name>freq512Hz</name> 259 <description>512 Hz (Compensated).</description> 260 <value>1</value> 261 </enumeratedValue> 262 <enumeratedValue> 263 <name>freq4KHz</name> 264 <description>4 KHz.</description> 265 <value>2</value> 266 </enumeratedValue> 267 <enumeratedValue> 268 <name>freq4KHz</name> 269 <description>4 KHz.</description> 270 <value>3</value> 271 </enumeratedValue> 272 </enumeratedValues> 273 </field> 274 <field> 275 <name>X32K_MODE</name> 276 <description>32kHz Oscillator Mode Select</description> 277 <bitOffset>11</bitOffset> 278 <bitWidth>2</bitWidth> 279 <enumeratedValues> 280 <enumeratedValue> 281 <name>noise_immunity</name> 282 <description>Operates in noise immunity mode.</description> 283 <value>0</value> 284 </enumeratedValue> 285 <enumeratedValue> 286 <name>quiet</name> 287 <description>Operates in quiet mode. Oscillator warm-up is not required.</description> 288 <value>1</value> 289 </enumeratedValue> 290 <enumeratedValue> 291 <name>quiet_deep_sleep</name> 292 <description>Operates in noise immunity mode when the processor is in active modes and 293switches to quiet mode when the processor enters DEEPSLEEP. The system waits 294for the 32kHz oscillator to warm-up prior to the processor exiting stop mode.</description> 295 <value>2</value> 296 </enumeratedValue> 297 <enumeratedValue> 298 <name>quiet_stop</name> 299 <description>Operates in noise immunity mode when the processor is in active modes and 300switches to quiet mode when the processor enters stop mode. The system does 301not wait for the 32kHz oscillator to warm-up prior to the processor exiting stop 302mode and beginning code execution. 303</description> 304 <value>3</value> 305 </enumeratedValue> 306 </enumeratedValues> 307 </field> 308 <field> 309 <name>WRITE_EN</name> 310 <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.</description> 311 <bitOffset>15</bitOffset> 312 <bitWidth>1</bitWidth> 313 <enumeratedValues> 314 <enumeratedValue> 315 <name>inactive</name> 316 <description>Not active</description> 317 <value>0</value> 318 </enumeratedValue> 319 <enumeratedValue> 320 <name>Pending</name> 321 <description>Active</description> 322 <value>1</value> 323 </enumeratedValue> 324 </enumeratedValues> 325 </field> 326 </fields> 327 </register> 328 <register> 329 <name>TRIM</name> 330 <description>RTC Trim Register.</description> 331 <addressOffset>0x14</addressOffset> 332 <resetMask>0x00000000</resetMask> 333 <fields> 334 <field> 335 <name>TRIM</name> 336 <description>RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.</description> 337 <bitOffset>0</bitOffset> 338 <bitWidth>8</bitWidth> 339 </field> 340 <field> 341 <name>VRTC_TMR</name> 342 <description>VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.</description> 343 <bitOffset>8</bitOffset> 344 <bitWidth>24</bitWidth> 345 </field> 346 </fields> 347 </register> 348 <register> 349 <name>OSCCTRL</name> 350 <description>RTC Oscillator Control Register.</description> 351 <addressOffset>0x18</addressOffset> 352 <resetMask>0x00000000</resetMask> 353 <fields> 354 <field> 355 <name>FILTER_EN</name> 356 <description>RTC Oscillator Filter Enable</description> 357 <bitOffset>0</bitOffset> 358 <bitWidth>1</bitWidth> 359 </field> 360 <field> 361 <name>IBIAS_SEL</name> 362 <description>RTC Oscillator 4x Bias Current Select. 0: 2x bias current. 1: 4x bias current.</description> 363 <bitOffset>1</bitOffset> 364 <bitWidth>1</bitWidth> 365 </field> 366 <field> 367 <name>HYST_EN</name> 368 <description>RTC Oscillator Hysteresis Buffer Enable</description> 369 <bitOffset>2</bitOffset> 370 <bitWidth>1</bitWidth> 371 </field> 372 <field> 373 <name>IBIAS_EN</name> 374 <description>RTC Oscillator Bias Current</description> 375 <bitOffset>3</bitOffset> 376 <bitWidth>1</bitWidth> 377 </field> 378 <field> 379 <name>BYPASS</name> 380 <description>RTC Crystal Bypass</description> 381 <bitOffset>4</bitOffset> 382 <bitWidth>1</bitWidth> 383 </field> 384 <field> 385 <name>32KOUT</name> 386 <description>RTC 32kHz Square Wave Output</description> 387 <bitOffset>5</bitOffset> 388 <bitWidth>1</bitWidth> 389 </field> 390 </fields> 391 </register> 392 </registers> 393 </peripheral> 394 <!-- RTC : Real Time Clock & Alarm --> 395</device>
