RTC Real Time Clock and Alarm. 0x40006000 0x00 0x400 registers RTC RTC interrupt. 3 SEC RTC Second Counter. This register contains the 32-bit second counter. 0x00 0x00000000 RTS Seconds Counter. 0 32 SSEC RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 RTSS Sub-Seconds Counter (8-bit). 0 8 RAS Time-of-day Alarm. 0x08 0x00000000 RAS Time-of-day Alarm. 0 20 RSSA RTC sub-second alarm. This register contains the reload value for the sub-second alarm. 0x0C 0x00000000 RSSA This register contains the reload value for the sub-second alarm. 0 32 CTRL RTC Control Register. 0x10 0x00000008 0xFFFFFF38 ENABLE Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 ALARM_TOD_EN Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 ALARM_SS_EN Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 READY RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 4 1 busy Register has not updated. 0 ready Ready. 1 READY_INT_EN RTC Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 ALARM_TOD_FL Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active 0 Pending Active 1 ALARM_SS_FL Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active 0 Pending Active 1 32KOUT_EN Square Wave Output Enable. 8 1 inactive Not active 0 Pending Active 1 FREQ_SEL Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 9 2 freq1Hz 1 Hz (Compensated). 0 freq512Hz 512 Hz (Compensated). 1 freq4KHz 4 KHz. 2 freq4KHz 4 KHz. 3 X32K_MODE 32kHz Oscillator Mode Select 11 2 noise_immunity Operates in noise immunity mode. 0 quiet Operates in quiet mode. Oscillator warm-up is not required. 1 quiet_deep_sleep Operates in noise immunity mode when the processor is in active modes and switches to quiet mode when the processor enters DEEPSLEEP. The system waits for the 32kHz oscillator to warm-up prior to the processor exiting stop mode. 2 quiet_stop Operates in noise immunity mode when the processor is in active modes and switches to quiet mode when the processor enters stop mode. The system does not wait for the 32kHz oscillator to warm-up prior to the processor exiting stop mode and beginning code execution. 3 WRITE_EN Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 15 1 inactive Not active 0 Pending Active 1 TRIM RTC Trim Register. 0x14 0x00000000 TRIM RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. 0 8 VRTC_TMR VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. 8 24 OSCCTRL RTC Oscillator Control Register. 0x18 0x00000000 FILTER_EN RTC Oscillator Filter Enable 0 1 IBIAS_SEL RTC Oscillator 4x Bias Current Select. 0: 2x bias current. 1: 4x bias current. 1 1 HYST_EN RTC Oscillator Hysteresis Buffer Enable 2 1 IBIAS_EN RTC Oscillator Bias Current 3 1 BYPASS RTC Crystal Bypass 4 1 32KOUT RTC 32kHz Square Wave Output 5 1