1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>RTC</name> 5 <description>Real Time Clock and Alarm.</description> 6 <baseAddress>0x40006000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>RTC</name> 14 <description>RTC interrupt.</description> 15 <value>3</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>SEC</name> 20 <description>RTC Second Counter. This register contains the 32-bit second counter.</description> 21 <addressOffset>0x00</addressOffset> 22 <resetMask>0x00000000</resetMask> 23 <fields> 24 <field> 25 <name>SEC</name> 26 <description>RTC Seconds Counter.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <name>SSEC</name> 34 <description>RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.</description> 35 <addressOffset>0x04</addressOffset> 36 <resetMask>0x00000000</resetMask> 37 <fields> 38 <field> 39 <name>SSEC</name> 40 <description>RTC Sub-second Counter.</description> 41 <bitOffset>0</bitOffset> 42 <bitWidth>8</bitWidth> 43 </field> 44 </fields> 45 </register> 46 <register> 47 <name>TODA</name> 48 <description>Time-of-day Alarm.</description> 49 <addressOffset>0x08</addressOffset> 50 <resetMask>0x00000000</resetMask> 51 <fields> 52 <field> 53 <name>TOD_ALARM</name> 54 <description>Time-of-day Alarm.</description> 55 <bitOffset>0</bitOffset> 56 <bitWidth>20</bitWidth> 57 </field> 58 </fields> 59 </register> 60 <register> 61 <name>SSECA</name> 62 <description>RTC sub-second alarm. This register contains the reload value for the sub-second alarm.</description> 63 <addressOffset>0x0C</addressOffset> 64 <resetMask>0x00000000</resetMask> 65 <fields> 66 <field> 67 <name>SSEC_ALARM</name> 68 <description>This register contains the reload value for the sub-second alarm.</description> 69 <bitOffset>0</bitOffset> 70 <bitWidth>32</bitWidth> 71 </field> 72 </fields> 73 </register> 74 <register> 75 <name>CTRL</name> 76 <description>RTC Control Register.</description> 77 <addressOffset>0x10</addressOffset> 78 <resetValue>0x00000008</resetValue> 79 <resetMask>0xFFFFFF38</resetMask> 80 <fields> 81 <field> 82 <name>ENABLE</name> 83 <description>Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 84 <bitOffset>0</bitOffset> 85 <bitWidth>1</bitWidth> 86 <enumeratedValues> 87 <enumeratedValue> 88 <name>dis</name> 89 <description>Disable.</description> 90 <value>0</value> 91 </enumeratedValue> 92 <enumeratedValue> 93 <name>en</name> 94 <description>Enable.</description> 95 <value>1</value> 96 </enumeratedValue> 97 </enumeratedValues> 98 </field> 99 <field> 100 <name>TOD_ALARM_EN</name> 101 <description>Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 102 <bitOffset>1</bitOffset> 103 <bitWidth>1</bitWidth> 104 <enumeratedValues> 105 <enumeratedValue> 106 <name>dis</name> 107 <description>Disable.</description> 108 <value>0</value> 109 </enumeratedValue> 110 <enumeratedValue> 111 <name>en</name> 112 <description>Enable.</description> 113 <value>1</value> 114 </enumeratedValue> 115 </enumeratedValues> 116 </field> 117 <field> 118 <name>SSEC_ALARM_EN</name> 119 <description>Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 120 <bitOffset>2</bitOffset> 121 <bitWidth>1</bitWidth> 122 <enumeratedValues> 123 <enumeratedValue> 124 <name>dis</name> 125 <description>Disable.</description> 126 <value>0</value> 127 </enumeratedValue> 128 <enumeratedValue> 129 <name>en</name> 130 <description>Enable.</description> 131 <value>1</value> 132 </enumeratedValue> 133 </enumeratedValues> 134 </field> 135 <field> 136 <name>BUSY</name> 137 <description>RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.</description> 138 <bitOffset>3</bitOffset> 139 <bitWidth>1</bitWidth> 140 <access>read-only</access> 141 <enumeratedValues> 142 <enumeratedValue> 143 <name>idle</name> 144 <description>Idle.</description> 145 <value>0</value> 146 </enumeratedValue> 147 <enumeratedValue> 148 <name>busy</name> 149 <description>Busy.</description> 150 <value>1</value> 151 </enumeratedValue> 152 </enumeratedValues> 153 </field> 154 <field> 155 <name>READY</name> 156 <description>RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.</description> 157 <bitOffset>4</bitOffset> 158 <bitWidth>1</bitWidth> 159 <enumeratedValues> 160 <enumeratedValue> 161 <name>not_ready</name> 162 <description>Register has not updated.</description> 163 <value>0</value> 164 </enumeratedValue> 165 <enumeratedValue> 166 <name>ready</name> 167 <description>Ready.</description> 168 <value>1</value> 169 </enumeratedValue> 170 </enumeratedValues> 171 </field> 172 <field> 173 <name>READY_INT_EN</name> 174 <description>RTC Ready Interrupt Enable.</description> 175 <bitOffset>5</bitOffset> 176 <bitWidth>1</bitWidth> 177 <enumeratedValues> 178 <enumeratedValue> 179 <name>dis</name> 180 <description>Disable.</description> 181 <value>0</value> 182 </enumeratedValue> 183 <enumeratedValue> 184 <name>en</name> 185 <description>Enable.</description> 186 <value>1</value> 187 </enumeratedValue> 188 </enumeratedValues> 189 </field> 190 <field> 191 <name>TOD_ALARM_FL</name> 192 <description>Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 193 <bitOffset>6</bitOffset> 194 <bitWidth>1</bitWidth> 195 <access>read-only</access> 196 <enumeratedValues> 197 <enumeratedValue> 198 <name>inactive</name> 199 <description>Not active</description> 200 <value>0</value> 201 </enumeratedValue> 202 <enumeratedValue> 203 <name>Pending</name> 204 <description>Active</description> 205 <value>1</value> 206 </enumeratedValue> 207 </enumeratedValues> 208 </field> 209 <field> 210 <name>SSEC_ALARM_FL</name> 211 <description>Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 212 <bitOffset>7</bitOffset> 213 <bitWidth>1</bitWidth> 214 <access>read-only</access> 215 <enumeratedValues> 216 <enumeratedValue> 217 <name>inactive</name> 218 <description>Not active</description> 219 <value>0</value> 220 </enumeratedValue> 221 <enumeratedValue> 222 <name>Pending</name> 223 <description>Active</description> 224 <value>1</value> 225 </enumeratedValue> 226 </enumeratedValues> 227 </field> 228 <field> 229 <name>SQWOUT_EN</name> 230 <description>Square Wave Output Enable.</description> 231 <bitOffset>8</bitOffset> 232 <bitWidth>1</bitWidth> 233 <enumeratedValues> 234 <enumeratedValue> 235 <name>dis</name> 236 <description>Disabled.</description> 237 <value>0</value> 238 </enumeratedValue> 239 <enumeratedValue> 240 <name>en</name> 241 <description>Enabled.</description> 242 <value>1</value> 243 </enumeratedValue> 244 </enumeratedValues> 245 </field> 246 <field> 247 <name>FREQ_SEL</name> 248 <description>Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.</description> 249 <bitOffset>9</bitOffset> 250 <bitWidth>2</bitWidth> 251 <enumeratedValues> 252 <enumeratedValue> 253 <name>freq1Hz</name> 254 <description>1 Hz (Compensated).</description> 255 <value>0</value> 256 </enumeratedValue> 257 <enumeratedValue> 258 <name>freq512Hz</name> 259 <description>512 Hz (Compensated).</description> 260 <value>1</value> 261 </enumeratedValue> 262 <enumeratedValue> 263 <name>freq4KHz</name> 264 <description>4 KHz.</description> 265 <value>2</value> 266 </enumeratedValue> 267 </enumeratedValues> 268 </field> 269 <field> 270 <name>ACRE</name> 271 <description>Asynchronous Counter Read Enable.</description> 272 <bitOffset>14</bitOffset> 273 <bitWidth>1</bitWidth> 274 <enumeratedValues> 275 <enumeratedValue> 276 <name>sync</name> 277 <description>SEC and SSEC registers synchronized and should only be accessed while CTRL.rdy = 1.</description> 278 <value>0</value> 279 </enumeratedValue> 280 <enumeratedValue> 281 <name>async</name> 282 <description>SEC and SSEC registers are asynchronous and will require software interaction to ensure data accuracy.</description> 283 <value>1</value> 284 </enumeratedValue> 285 </enumeratedValues> 286 </field> 287 <field> 288 <name>WRITE_EN</name> 289 <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.</description> 290 <bitOffset>15</bitOffset> 291 <bitWidth>1</bitWidth> 292 <enumeratedValues> 293 <enumeratedValue> 294 <name>dis</name> 295 <description>Writes to RTC_CTRL.enable are ignored.</description> 296 <value>0</value> 297 </enumeratedValue> 298 <enumeratedValue> 299 <name>en</name> 300 <description>Writes to RTC_CTRL.enable are allowed.</description> 301 <value>1</value> 302 </enumeratedValue> 303 </enumeratedValues> 304 </field> 305 </fields> 306 </register> 307 <register> 308 <name>OSCCTRL</name> 309 <description>RTC Oscillator Control Register.</description> 310 <addressOffset>0x18</addressOffset> 311 <resetMask>0x00000000</resetMask> 312 <fields> 313 <field> 314 <name>FILTER_EN</name> 315 <description>Enables analog deglitch filter.</description> 316 <bitOffset>0</bitOffset> 317 <bitWidth>1</bitWidth> 318 </field> 319 <field> 320 <name>IBIAS_SEL</name> 321 <description>If IBIAS_EN is 1, selects 4x,2x mode.</description> 322 <bitOffset>1</bitOffset> 323 <bitWidth>1</bitWidth> 324 </field> 325 <field> 326 <name>HYST_EN</name> 327 <description>Enables high current hysteresis buffer.</description> 328 <bitOffset>2</bitOffset> 329 <bitWidth>1</bitWidth> 330 </field> 331 <field> 332 <name>IBIAS_EN</name> 333 <description>Enables higher 4x,2x current modes.</description> 334 <bitOffset>3</bitOffset> 335 <bitWidth>1</bitWidth> 336 </field> 337 <field> 338 <name>BYPASS</name> 339 <description>RTC Crystal Bypass</description> 340 <bitOffset>4</bitOffset> 341 <bitWidth>1</bitWidth> 342 </field> 343 <field> 344 <name>32KOUT</name> 345 <description>RTC 32kHz Square Wave Output</description> 346 <bitOffset>5</bitOffset> 347 <bitWidth>1</bitWidth> 348 </field> 349 </fields> 350 </register> 351 </registers> 352 </peripheral> 353 <!-- RTC :Real Time Clock & Alarm --> 354</device>
