RTC Real Time Clock and Alarm. 0x40006000 0x00 0x400 registers RTC RTC interrupt. 3 SEC RTC Second Counter. This register contains the 32-bit second counter. 0x00 0x00000000 SEC RTC Seconds Counter. 0 32 SSEC RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 SSEC RTC Sub-second Counter. 0 8 TODA Time-of-day Alarm. 0x08 0x00000000 TOD_ALARM Time-of-day Alarm. 0 20 SSECA RTC sub-second alarm. This register contains the reload value for the sub-second alarm. 0x0C 0x00000000 SSEC_ALARM This register contains the reload value for the sub-second alarm. 0 32 CTRL RTC Control Register. 0x10 0x00000008 0xFFFFFF38 ENABLE Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 TOD_ALARM_EN Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 SSEC_ALARM_EN Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 READY RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 4 1 not_ready Register has not updated. 0 ready Ready. 1 READY_INT_EN RTC Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 TOD_ALARM_FL Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active 0 Pending Active 1 SSEC_ALARM_FL Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active 0 Pending Active 1 SQWOUT_EN Square Wave Output Enable. 8 1 dis Disabled. 0 en Enabled. 1 FREQ_SEL Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 9 2 freq1Hz 1 Hz (Compensated). 0 freq512Hz 512 Hz (Compensated). 1 freq4KHz 4 KHz. 2 ACRE Asynchronous Counter Read Enable. 14 1 sync SEC and SSEC registers synchronized and should only be accessed while CTRL.rdy = 1. 0 async SEC and SSEC registers are asynchronous and will require software interaction to ensure data accuracy. 1 WRITE_EN Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 15 1 dis Writes to RTC_CTRL.enable are ignored. 0 en Writes to RTC_CTRL.enable are allowed. 1 OSCCTRL RTC Oscillator Control Register. 0x18 0x00000000 FILTER_EN Enables analog deglitch filter. 0 1 IBIAS_SEL If IBIAS_EN is 1, selects 4x,2x mode. 1 1 HYST_EN Enables high current hysteresis buffer. 2 1 IBIAS_EN Enables higher 4x,2x current modes. 3 1 BYPASS RTC Crystal Bypass 4 1 32KOUT RTC 32kHz Square Wave Output 5 1