1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3  <peripheral>
4    <name>OTP</name>
5    <description>One-Time Programmable (OTP) Memory Controller.</description>
6    <groupName>OTP</groupName>
7    <baseAddress>0x40041000</baseAddress>
8    <addressBlock>
9      <offset>0x00</offset>
10      <size>0x1000</size>
11      <usage>registers</usage>
12    </addressBlock>
13    <registers>
14      <register>
15        <name>CTRL</name>
16        <description>OTP Control Register.</description>
17        <addressOffset>0x00</addressOffset>
18        <fields>
19          <field>
20            <name>ADDR</name>
21            <description>Address of the OTP 32 bit value.</description>
22            <bitOffset>0</bitOffset>
23            <bitWidth>16</bitWidth>
24          </field>
25          <field>
26            <name>READ</name>
27            <description>Read Operation. Setting this bit starts a read operation from the OTP.</description>
28            <bitOffset>24</bitOffset>
29            <bitWidth>1</bitWidth>
30            <enumeratedValues>
31              <enumeratedValue>
32                <name>no_op</name>
33                <description>No operation.</description>
34                <value>0</value>
35              </enumeratedValue>
36              <enumeratedValue>
37                <name>start</name>
38                <description>Initiate program operation.</description>
39                <value>1</value>
40              </enumeratedValue>
41            </enumeratedValues>
42          </field>
43          <field>
44            <name>WRITE</name>
45            <description>Program Operation. Setting this bit starts a write operation from the OTP location specified in the ADDR field.</description>
46            <bitOffset>25</bitOffset>
47            <bitWidth>1</bitWidth>
48          </field>
49        </fields>
50      </register>
51      <register>
52        <name>CLKDIV</name>
53        <description>OTP Clock Divide Register.</description>
54        <addressOffset>0x04</addressOffset>
55        <fields>
56          <field>
57            <name>PCLKDIV</name>
58            <description>Clock Divider. The input clock, PCLK, is divided for generating OTP timing signals.</description>
59            <bitOffset>0</bitOffset>
60            <bitWidth>6</bitWidth>
61            <enumeratedValues>
62              <enumeratedValue>
63                <name>DIV2</name>
64                <description>Divide by 2</description>
65                <value>1</value>
66              </enumeratedValue>
67              <enumeratedValue>
68                <name>DIV4</name>
69                <description>Divide by 4</description>
70                <value>3</value>
71              </enumeratedValue>
72              <enumeratedValue>
73                <name>DIV8</name>
74                <description>Divide by 8</description>
75                <value>7</value>
76              </enumeratedValue>
77              <enumeratedValue>
78                <name>DIV16</name>
79                <description>Divide by 16</description>
80                <value>15</value>
81              </enumeratedValue>
82              <enumeratedValue>
83                <name>DIV32</name>
84                <description>Divide by 32</description>
85                <value>31</value>
86              </enumeratedValue>
87            </enumeratedValues>
88          </field>
89          <field>
90            <name>SPWE</name>
91            <description>Smart PWE. If programmed value is 1, don't assert PWE.</description>
92            <bitOffset>8</bitOffset>
93            <bitWidth>1</bitWidth>
94          </field>
95          <field>
96            <name>PD</name>
97            <description>Power Down OTP. OTP controller will generate power up and down signals for control pins.</description>
98            <bitOffset>9</bitOffset>
99            <bitWidth>1</bitWidth>
100          </field>
101          <field>
102            <name>HCLKDIV</name>
103            <description>Clock Divider. The input clock, HCLK, is divided for generating OTP pwr on and down timing signals.</description>
104            <bitOffset>16</bitOffset>
105            <bitWidth>6</bitWidth>
106          </field>
107        </fields>
108      </register>
109      <register>
110        <name>RDATA</name>
111        <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description>
112        <addressOffset>0x08</addressOffset>
113        <fields>
114          <field>
115            <name>DATA</name>
116            <description>OTP Read Data.</description>
117            <bitOffset>0</bitOffset>
118            <bitWidth>32</bitWidth>
119          </field>
120        </fields>
121      </register>
122      <register>
123        <name>STATUS</name>
124        <description>OTP Status Register.</description>
125        <addressOffset>0x0C</addressOffset>
126        <fields>
127          <field>
128            <name>BUSY</name>
129            <description>OTP Busy Flag. This bit indicates whether the OTP controller is working a read or write operation.</description>
130            <bitOffset>0</bitOffset>
131            <bitWidth>1</bitWidth>
132          </field>
133          <field>
134            <name>FAIL</name>
135            <description>OTP Failed Flag. This bit indicates whether OTP programming has failed. OTP programming fails if the controller accesses a 32 bit location that has not been previously programmed.</description>
136            <bitOffset>1</bitOffset>
137            <bitWidth>1</bitWidth>
138          </field>
139          <field>
140            <name>UNLOCK1</name>
141            <description>Unlock1 Flag. This bit indicates that 1st password was entered, and the user block is enabled for OTP programming.</description>
142            <bitOffset>8</bitOffset>
143            <bitWidth>1</bitWidth>
144          </field>
145          <field>
146            <name>UNLOCK3</name>
147            <description>Unlock3 Flag. This bit indicates that 3 words unlock process is complete.</description>
148            <bitOffset>9</bitOffset>
149            <bitWidth>1</bitWidth>
150          </field>
151          <field>
152            <name>PWR_RDY</name>
153            <description>OTP Power On Status.</description>
154            <bitOffset>16</bitOffset>
155            <bitWidth>1</bitWidth>
156          </field>
157        </fields>
158      </register>
159      <register>
160        <name>WDATA</name>
161        <description>OTP Write Data Register.</description>
162        <addressOffset>0x30</addressOffset>
163        <fields>
164          <field>
165            <name>DATA</name>
166            <description>Write Data.</description>
167            <bitOffset>0</bitOffset>
168            <bitWidth>32</bitWidth>
169          </field>
170        </fields>
171      </register>
172      <register>
173        <name>ACTRL0</name>
174        <description>Access Control for user block.</description>
175        <addressOffset>0x3C</addressOffset>
176        <fields>
177          <field>
178            <name>ADATA</name>
179            <description>User Block Access Control.</description>
180            <bitOffset>0</bitOffset>
181            <bitWidth>32</bitWidth>
182          </field>
183        </fields>
184      </register>
185      <register>
186        <name>ACTRL1</name>
187        <description>Access Control for sys and user block.</description>
188        <addressOffset>0x40</addressOffset>
189        <fields>
190          <field>
191            <name>ADATA</name>
192            <description>System Info Block Access Data.</description>
193            <bitOffset>0</bitOffset>
194            <bitWidth>32</bitWidth>
195          </field>
196        </fields>
197      </register>
198    </registers>
199  </peripheral>
200  <!--OTP: One-Time Programmable Memory -->
201</device>