OTP One-Time Programmable (OTP) Memory Controller. OTP 0x40041000 0x00 0x1000 registers CTRL OTP Control Register. 0x00 ADDR Address of the OTP 32 bit value. 0 16 READ Read Operation. Setting this bit starts a read operation from the OTP. 24 1 no_op No operation. 0 start Initiate program operation. 1 WRITE Program Operation. Setting this bit starts a write operation from the OTP location specified in the ADDR field. 25 1 CLKDIV OTP Clock Divide Register. 0x04 PCLKDIV Clock Divider. The input clock, PCLK, is divided for generating OTP timing signals. 0 6 DIV2 Divide by 2 1 DIV4 Divide by 4 3 DIV8 Divide by 8 7 DIV16 Divide by 16 15 DIV32 Divide by 32 31 SPWE Smart PWE. If programmed value is 1, don't assert PWE. 8 1 PD Power Down OTP. OTP controller will generate power up and down signals for control pins. 9 1 HCLKDIV Clock Divider. The input clock, HCLK, is divided for generating OTP pwr on and down timing signals. 16 6 RDATA GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. 0x08 DATA OTP Read Data. 0 32 STATUS OTP Status Register. 0x0C BUSY OTP Busy Flag. This bit indicates whether the OTP controller is working a read or write operation. 0 1 FAIL OTP Failed Flag. This bit indicates whether OTP programming has failed. OTP programming fails if the controller accesses a 32 bit location that has not been previously programmed. 1 1 UNLOCK1 Unlock1 Flag. This bit indicates that 1st password was entered, and the user block is enabled for OTP programming. 8 1 UNLOCK3 Unlock3 Flag. This bit indicates that 3 words unlock process is complete. 9 1 PWR_RDY OTP Power On Status. 16 1 WDATA OTP Write Data Register. 0x30 DATA Write Data. 0 32 ACTRL0 Access Control for user block. 0x3C ADATA User Block Access Control. 0 32 ACTRL1 Access Control for sys and user block. 0x40 ADATA System Info Block Access Data. 0 32