1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>PWRSEQ</name> 5 <description>Power Sequencer / Low Power Control Register.</description> 6 <baseAddress>0x40006800</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>LPCN</name> 15 <description>Low Power Control Register.</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAMRET0</name> 20 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>1</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>dis</name> 26 <description>Disable Ram Retention.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>en</name> 31 <description>Enable System RAM 0 retention.</description> 32 <value>1</value> 33 </enumeratedValue> 34 </enumeratedValues> 35 </field> 36 <field> 37 <name>RAMRET1</name> 38 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 39 <bitOffset>1</bitOffset> 40 <bitWidth>1</bitWidth> 41 <enumeratedValues> 42 <enumeratedValue> 43 <name>dis</name> 44 <description>Disable Ram Retention.</description> 45 <value>0</value> 46 </enumeratedValue> 47 <enumeratedValue> 48 <name>en</name> 49 <description>Enable System RAM 1 retention.</description> 50 <value>1</value> 51 </enumeratedValue> 52 </enumeratedValues> 53 </field> 54 <field> 55 <name>RAMRET2</name> 56 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 57 <bitOffset>2</bitOffset> 58 <bitWidth>1</bitWidth> 59 <enumeratedValues> 60 <enumeratedValue> 61 <name>dis</name> 62 <description>Disable Ram Retention.</description> 63 <value>0</value> 64 </enumeratedValue> 65 <enumeratedValue> 66 <name>en</name> 67 <description>Enable System RAM 2 retention.</description> 68 <value>1</value> 69 </enumeratedValue> 70 </enumeratedValues> 71 </field> 72 <field> 73 <name>RAMRET3</name> 74 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 75 <bitOffset>3</bitOffset> 76 <bitWidth>1</bitWidth> 77 <enumeratedValues> 78 <enumeratedValue> 79 <name>dis</name> 80 <description>Disable Ram Retention.</description> 81 <value>0</value> 82 </enumeratedValue> 83 <enumeratedValue> 84 <name>en</name> 85 <description>Enable System RAM 3 retention.</description> 86 <value>1</value> 87 </enumeratedValue> 88 </enumeratedValues> 89 </field> 90 <field> 91 <name>RAMRET4</name> 92 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 93 <bitOffset>4</bitOffset> 94 <bitWidth>1</bitWidth> 95 <enumeratedValues> 96 <enumeratedValue> 97 <name>dis</name> 98 <description>Disable Ram Retention.</description> 99 <value>0</value> 100 </enumeratedValue> 101 <enumeratedValue> 102 <name>en</name> 103 <description>Enable System RAM 3 retention.</description> 104 <value>1</value> 105 </enumeratedValue> 106 </enumeratedValues> 107 </field> 108 <field> 109 <name>RAMRET5</name> 110 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 111 <bitOffset>5</bitOffset> 112 <bitWidth>1</bitWidth> 113 <enumeratedValues> 114 <enumeratedValue> 115 <name>dis</name> 116 <description>Disable Ram Retention.</description> 117 <value>0</value> 118 </enumeratedValue> 119 <enumeratedValue> 120 <name>en</name> 121 <description>Enable System RAM 3 retention.</description> 122 <value>1</value> 123 </enumeratedValue> 124 </enumeratedValues> 125 </field> 126 <field> 127 <name>RAMRET6</name> 128 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 129 <bitOffset>6</bitOffset> 130 <bitWidth>1</bitWidth> 131 <enumeratedValues> 132 <enumeratedValue> 133 <name>dis</name> 134 <description>Disable Ram Retention.</description> 135 <value>0</value> 136 </enumeratedValue> 137 <enumeratedValue> 138 <name>en</name> 139 <description>Enable System RAM 3 retention.</description> 140 <value>1</value> 141 </enumeratedValue> 142 </enumeratedValues> 143 </field> 144 <field> 145 <name>RAMRET8</name> 146 <description>System RAM retention in BACKUP mode. RAM7 is retained if any of RAM0 to RAM6 is retained.</description> 147 <bitOffset>7</bitOffset> 148 <bitWidth>1</bitWidth> 149 <enumeratedValues> 150 <enumeratedValue> 151 <name>dis</name> 152 <description>Disable Ram Retention.</description> 153 <value>0</value> 154 </enumeratedValue> 155 <enumeratedValue> 156 <name>en</name> 157 <description>Enable System RAM 3 retention.</description> 158 <value>1</value> 159 </enumeratedValue> 160 </enumeratedValues> 161 </field> 162 <field> 163 <name>ISOCLK_SELECT</name> 164 <description>0 = PCLK 1= ISO CLK use for RISV in Low power mode </description> 165 <bitOffset>8</bitOffset> 166 <bitWidth>1</bitWidth> 167 </field> 168 <field> 169 <name>FAST_ENTRY_DIS</name> 170 <description>Fast Low Power mode entry disable</description> 171 <bitOffset>9</bitOffset> 172 <bitWidth>1</bitWidth> 173 </field> 174 <field> 175 <name>BGOFF</name> 176 <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description> 177 <bitOffset>11</bitOffset> 178 <bitWidth>1</bitWidth> 179 <enumeratedValues> 180 <enumeratedValue> 181 <name>on</name> 182 <description>Bandgap is always ON.</description> 183 <value>0</value> 184 </enumeratedValue> 185 <enumeratedValue> 186 <name>off</name> 187 <description>Bandgap is OFF in DeepSleep mode (default).</description> 188 <value>1</value> 189 </enumeratedValue> 190 </enumeratedValues> 191 </field> 192 <field> 193 <name>WKRST</name> 194 <description>Reset wakeup status registers</description> 195 <bitOffset>31</bitOffset> 196 <bitWidth>1</bitWidth> 197 </field> 198 </fields> 199 </register> 200 <register> 201 <name>LPWKST0</name> 202 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 203 <addressOffset>0x04</addressOffset> 204 <fields> 205 <field> 206 <name>WAKEST</name> 207 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 208 <bitOffset>0</bitOffset> 209 <bitWidth>1</bitWidth> 210 </field> 211 </fields> 212 </register> 213 <register> 214 <name>LPWKEN0</name> 215 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 216 <addressOffset>0x08</addressOffset> 217 <fields> 218 <field> 219 <name>WAKEEN</name> 220 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 221 <bitOffset>0</bitOffset> 222 <bitWidth>31</bitWidth> 223 </field> 224 </fields> 225 </register> 226 <register> 227 <name>LPWKST1</name> 228 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 229 <addressOffset>0x0C</addressOffset> 230 <fields> 231 <field> 232 <name>WAKEST</name> 233 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 234 <bitOffset>0</bitOffset> 235 <bitWidth>10</bitWidth> 236 </field> 237 </fields> 238 </register> 239 <register> 240 <name>LPWKEN1</name> 241 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 242 <addressOffset>0x10</addressOffset> 243 <fields> 244 <field> 245 <name>WAKEEN</name> 246 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 247 <bitOffset>0</bitOffset> 248 <bitWidth>10</bitWidth> 249 </field> 250 </fields> 251 </register> 252 <register> 253 <name>LPWKST2</name> 254 <description>Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.</description> 255 <addressOffset>0x14</addressOffset> 256 <fields> 257 <field> 258 <name>WAKEST</name> 259 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 260 <bitOffset>0</bitOffset> 261 <bitWidth>8</bitWidth> 262 </field> 263 </fields> 264 </register> 265 <register> 266 <name>LPWKEN2</name> 267 <description>Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.</description> 268 <addressOffset>0x18</addressOffset> 269 <fields> 270 <field> 271 <name>WAKEEN</name> 272 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 273 <bitOffset>0</bitOffset> 274 <bitWidth>8</bitWidth> 275 </field> 276 </fields> 277 </register> 278 <register> 279 <name>LPWKST3</name> 280 <description>Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.</description> 281 <addressOffset>0x1C</addressOffset> 282 <fields> 283 <field> 284 <name>WAKEST</name> 285 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 286 <bitOffset>0</bitOffset> 287 <bitWidth>2</bitWidth> 288 </field> 289 </fields> 290 </register> 291 <register> 292 <name>LPWKEN3</name> 293 <description>Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.</description> 294 <addressOffset>0x20</addressOffset> 295 <fields> 296 <field> 297 <name>WAKEEN</name> 298 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 299 <bitOffset>0</bitOffset> 300 <bitWidth>2</bitWidth> 301 </field> 302 </fields> 303 </register> 304 <register> 305 <name>LPWKST4</name> 306 <description>Low Power I/O Wakeup Status Register 4. This register indicates the low power wakeup status for GPIO4.</description> 307 <addressOffset>0x24</addressOffset> 308 <fields> 309 <field> 310 <name>WAKEST</name> 311 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 312 <bitOffset>0</bitOffset> 313 <bitWidth>2</bitWidth> 314 </field> 315 </fields> 316 </register> 317 <register> 318 <name>LPWKEN4</name> 319 <description>Low Power I/O Wakeup Enable Register 4. This register enables low power wakeup functionality for GPIO4.</description> 320 <addressOffset>0x28</addressOffset> 321 <fields> 322 <field> 323 <name>WAKEEN</name> 324 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 325 <bitOffset>0</bitOffset> 326 <bitWidth>2</bitWidth> 327 </field> 328 </fields> 329 </register> 330 <register> 331 <name>LPPWST</name> 332 <description>Low Power Peripheral Wakeup Status Register.</description> 333 <addressOffset>0x30</addressOffset> 334 <fields> 335 <field> 336 <name>AINCOMP0</name> 337 <description>Analog Input Comparator Wakeup Flag.</description> 338 <bitOffset>4</bitOffset> 339 <bitWidth>1</bitWidth> 340 </field> 341 <field> 342 <name>BACKUP</name> 343 <description>Backup Mode Wakeup Flag.</description> 344 <bitOffset>16</bitOffset> 345 <bitWidth>1</bitWidth> 346 </field> 347 <field> 348 <name>RESET</name> 349 <description>Reset Detected Wakeup Flag.</description> 350 <bitOffset>17</bitOffset> 351 <bitWidth>1</bitWidth> 352 </field> 353 </fields> 354 </register> 355 <register> 356 <name>LPPWEN</name> 357 <description>Low Power Peripheral Wakeup Enable Register.</description> 358 <addressOffset>0x34</addressOffset> 359 <fields> 360 <field> 361 <name>USBLS</name> 362 <description> USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate 363signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set.</description> 364 <bitOffset>0</bitOffset> 365 <bitWidth>2</bitWidth> 366 </field> 367 <field> 368 <name>USBVBUS</name> 369 <description> USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status.</description> 370 <bitOffset>2</bitOffset> 371 <bitWidth>1</bitWidth> 372 </field> 373 <field> 374 <name>AINCOMP0</name> 375 <description> AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0.</description> 376 <bitOffset>4</bitOffset> 377 <bitWidth>1</bitWidth> 378 </field> 379 <field> 380 <name>WDT0</name> 381 <description> WDT0 Wakeup Enable. This bit allows wakeup from the WDT0.</description> 382 <bitOffset>8</bitOffset> 383 <bitWidth>1</bitWidth> 384 </field> 385 <field> 386 <name>WDT1</name> 387 <description> WDT1 Wakeup Enable. This bit allows wakeup from the WDT1.</description> 388 <bitOffset>9</bitOffset> 389 <bitWidth>1</bitWidth> 390 </field> 391 <field> 392 <name>CPU1</name> 393 <description> CPU1 Wakeup Enable. This bit allows wakeup from the CPU1.</description> 394 <bitOffset>10</bitOffset> 395 <bitWidth>1</bitWidth> 396 </field> 397 <field> 398 <name>TMR0</name> 399 <description> TMR0 Wakeup Enable. This bit allows wakeup from the TMR0.</description> 400 <bitOffset>11</bitOffset> 401 <bitWidth>1</bitWidth> 402 </field> 403 <field> 404 <name>TMR1</name> 405 <description> TMR1 Wakeup Enable. This bit allows wakeup from the TMR1.</description> 406 <bitOffset>12</bitOffset> 407 <bitWidth>1</bitWidth> 408 </field> 409 <field> 410 <name>TMR2</name> 411 <description> TMR2 Wakeup Enable. This bit allows wakeup from the TMR2.</description> 412 <bitOffset>13</bitOffset> 413 <bitWidth>1</bitWidth> 414 </field> 415 <field> 416 <name>TMR3</name> 417 <description> TMR3 Wakeup Enable. This bit allows wakeup from the TMR3.</description> 418 <bitOffset>14</bitOffset> 419 <bitWidth>1</bitWidth> 420 </field> 421 <field> 422 <name>TMR4</name> 423 <description> TMR4 Wakeup Enable. This bit allows wakeup from the TMR4.</description> 424 <bitOffset>15</bitOffset> 425 <bitWidth>1</bitWidth> 426 </field> 427 <field> 428 <name>TMR5</name> 429 <description> TMR5 Wakeup Enable. This bit allows wakeup from the TMR5.</description> 430 <bitOffset>16</bitOffset> 431 <bitWidth>1</bitWidth> 432 </field> 433 <field> 434 <name>UART0</name> 435 <description> UART0 Wakeup Enable. This bit allows wakeup from the UART0.</description> 436 <bitOffset>17</bitOffset> 437 <bitWidth>1</bitWidth> 438 </field> 439 <field> 440 <name>UART1</name> 441 <description> UART1 Wakeup Enable. This bit allows wakeup from the UART1.</description> 442 <bitOffset>18</bitOffset> 443 <bitWidth>1</bitWidth> 444 </field> 445 <field> 446 <name>UART2</name> 447 <description> UART2 Wakeup Enable. This bit allows wakeup from the UART2.</description> 448 <bitOffset>19</bitOffset> 449 <bitWidth>1</bitWidth> 450 </field> 451 <field> 452 <name>UART3</name> 453 <description> UART3 Wakeup Enable. This bit allows wakeup from the UART3.</description> 454 <bitOffset>20</bitOffset> 455 <bitWidth>1</bitWidth> 456 </field> 457 <field> 458 <name>I2C0</name> 459 <description> I2C0 Wakeup Enable. This bit allows wakeup from the I2C0.</description> 460 <bitOffset>21</bitOffset> 461 <bitWidth>1</bitWidth> 462 </field> 463 <field> 464 <name>I2C1</name> 465 <description> I2C1 Wakeup Enable. This bit allows wakeup from the I2C1.</description> 466 <bitOffset>22</bitOffset> 467 <bitWidth>1</bitWidth> 468 </field> 469 <field> 470 <name>I2C2</name> 471 <description> I2C2 Wakeup Enable. This bit allows wakeup from the I2C2.</description> 472 <bitOffset>23</bitOffset> 473 <bitWidth>1</bitWidth> 474 </field> 475 <field> 476 <name>I2S</name> 477 <description> I2S Wakeup Enable. This bit allows wakeup from the I2S.</description> 478 <bitOffset>24</bitOffset> 479 <bitWidth>1</bitWidth> 480 </field> 481 <field> 482 <name>SPI0</name> 483 <description> SPI0 Wakeup Enable. This bit allows wakeup from the SPI0.</description> 484 <bitOffset>25</bitOffset> 485 <bitWidth>1</bitWidth> 486 </field> 487 <field> 488 <name>LPCMP</name> 489 <description> LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP.</description> 490 <bitOffset>26</bitOffset> 491 <bitWidth>1</bitWidth> 492 </field> 493 <field> 494 <name>BTLE</name> 495 <description>BTLE Wakeup Enable. This bit allows wakeup from the BTLE.</description> 496 <bitOffset>27</bitOffset> 497 <bitWidth>1</bitWidth> 498 </field> 499 <field> 500 <name>SPI1</name> 501 <description> SPI1 Wakeup Enable. This bit allows wakeup from the SPI1.</description> 502 <bitOffset>28</bitOffset> 503 <bitWidth>1</bitWidth> 504 </field> 505 <field> 506 <name>SPI2</name> 507 <description> SPI2 Wakeup Enable. This bit allows wakeup from the SPI2.</description> 508 <bitOffset>29</bitOffset> 509 <bitWidth>1</bitWidth> 510 </field> 511 <field> 512 <name>CAN0</name> 513 <description>CAN0 Wakeup Enable. This bit allows wakeup from the CAN0.</description> 514 <bitOffset>30</bitOffset> 515 <bitWidth>1</bitWidth> 516 </field> 517 <field> 518 <name>CAN1</name> 519 <description>CAN1 Wakeup Enable. This bit allows wakeup from the CAN1.</description> 520 <bitOffset>31</bitOffset> 521 <bitWidth>1</bitWidth> 522 </field> 523 </fields> 524 </register> 525 <register> 526 <name>GP0</name> 527 <description>General Purpose Register 0</description> 528 <addressOffset>0x48</addressOffset> 529 </register> 530 <register> 531 <name>GP1</name> 532 <description>General Purpose Register 1</description> 533 <addressOffset>0x4C</addressOffset> 534 </register> 535 </registers> 536 </peripheral> 537 <!-- PWRSEQ: Power sequencer --> 538</device>
