PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers LPCN Low Power Control Register. 0x00 RAMRET0 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 1 dis Disable Ram Retention. 0 en Enable System RAM 0 retention. 1 RAMRET1 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 1 1 dis Disable Ram Retention. 0 en Enable System RAM 1 retention. 1 RAMRET2 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 2 1 dis Disable Ram Retention. 0 en Enable System RAM 2 retention. 1 RAMRET3 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 3 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 RAMRET4 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 4 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 RAMRET5 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 5 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 RAMRET6 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 6 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 RAMRET8 System RAM retention in BACKUP mode. RAM7 is retained if any of RAM0 to RAM6 is retained. 7 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 ISOCLK_SELECT 0 = PCLK 1= ISO CLK use for RISV in Low power mode 8 1 FAST_ENTRY_DIS Fast Low Power mode entry disable 9 1 BGOFF Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode (default). 1 WKRST Reset wakeup status registers 31 1 LPWKST0 Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 1 LPWKEN0 Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 LPWKST1 Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 10 LPWKEN1 Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 10 LPWKST2 Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2. 0x14 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 8 LPWKEN2 Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2. 0x18 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 8 LPWKST3 Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3. 0x1C WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 2 LPWKEN3 Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3. 0x20 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 2 LPWKST4 Low Power I/O Wakeup Status Register 4. This register indicates the low power wakeup status for GPIO4. 0x24 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 2 LPWKEN4 Low Power I/O Wakeup Enable Register 4. This register enables low power wakeup functionality for GPIO4. 0x28 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 2 LPPWST Low Power Peripheral Wakeup Status Register. 0x30 AINCOMP0 Analog Input Comparator Wakeup Flag. 4 1 BACKUP Backup Mode Wakeup Flag. 16 1 RESET Reset Detected Wakeup Flag. 17 1 LPPWEN Low Power Peripheral Wakeup Enable Register. 0x34 USBLS USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set. 0 2 USBVBUS USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. 2 1 AINCOMP0 AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. 4 1 WDT0 WDT0 Wakeup Enable. This bit allows wakeup from the WDT0. 8 1 WDT1 WDT1 Wakeup Enable. This bit allows wakeup from the WDT1. 9 1 CPU1 CPU1 Wakeup Enable. This bit allows wakeup from the CPU1. 10 1 TMR0 TMR0 Wakeup Enable. This bit allows wakeup from the TMR0. 11 1 TMR1 TMR1 Wakeup Enable. This bit allows wakeup from the TMR1. 12 1 TMR2 TMR2 Wakeup Enable. This bit allows wakeup from the TMR2. 13 1 TMR3 TMR3 Wakeup Enable. This bit allows wakeup from the TMR3. 14 1 TMR4 TMR4 Wakeup Enable. This bit allows wakeup from the TMR4. 15 1 TMR5 TMR5 Wakeup Enable. This bit allows wakeup from the TMR5. 16 1 UART0 UART0 Wakeup Enable. This bit allows wakeup from the UART0. 17 1 UART1 UART1 Wakeup Enable. This bit allows wakeup from the UART1. 18 1 UART2 UART2 Wakeup Enable. This bit allows wakeup from the UART2. 19 1 UART3 UART3 Wakeup Enable. This bit allows wakeup from the UART3. 20 1 I2C0 I2C0 Wakeup Enable. This bit allows wakeup from the I2C0. 21 1 I2C1 I2C1 Wakeup Enable. This bit allows wakeup from the I2C1. 22 1 I2C2 I2C2 Wakeup Enable. This bit allows wakeup from the I2C2. 23 1 I2S I2S Wakeup Enable. This bit allows wakeup from the I2S. 24 1 SPI0 SPI0 Wakeup Enable. This bit allows wakeup from the SPI0. 25 1 LPCMP LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP. 26 1 BTLE BTLE Wakeup Enable. This bit allows wakeup from the BTLE. 27 1 SPI1 SPI1 Wakeup Enable. This bit allows wakeup from the SPI1. 28 1 SPI2 SPI2 Wakeup Enable. This bit allows wakeup from the SPI2. 29 1 CAN0 CAN0 Wakeup Enable. This bit allows wakeup from the CAN0. 30 1 CAN1 CAN1 Wakeup Enable. This bit allows wakeup from the CAN1. 31 1 GP0 General Purpose Register 0 0x48 GP1 General Purpose Register 1 0x4C