1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>PWRSEQ</name> 5 <description>Power Sequencer / Low Power Control Register.</description> 6 <baseAddress>0x40006800</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>LPCN</name> 15 <description>Low Power Control Register.</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAMRET</name> 20 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>2</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>dis</name> 26 <description>Disable Ram Retention.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>en1</name> 31 <description>Enable System RAM 0 retention.</description> 32 <value>1</value> 33 </enumeratedValue> 34 <enumeratedValue> 35 <name>en2</name> 36 <description>Enable System RAM 0 and 1 retention.</description> 37 <value>2</value> 38 </enumeratedValue> 39 <enumeratedValue> 40 <name>en3</name> 41 <description>Enable System RAM 0 and 1 retention, if RREGEN=0, Enable all System RAM retention.</description> 42 <value>3</value> 43 </enumeratedValue> 44 </enumeratedValues> 45 </field> 46 <field> 47 <name>BCKGRND</name> 48 <description>Background Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep.</description> 49 <bitOffset>9</bitOffset> 50 <bitWidth>1</bitWidth> 51 <enumeratedValues> 52 <enumeratedValue> 53 <name>dis</name> 54 <description>Disabled.</description> 55 <value>0</value> 56 </enumeratedValue> 57 <enumeratedValue> 58 <name>en</name> 59 <description>Enabled.</description> 60 <value>1</value> 61 </enumeratedValue> 62 </enumeratedValues> 63 </field> 64 <field> 65 <name>FWKM</name> 66 <description>Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). </description> 67 <bitOffset>10</bitOffset> 68 <bitWidth>1</bitWidth> 69 <enumeratedValues> 70 <enumeratedValue> 71 <name>dis</name> 72 <description>Disabled.</description> 73 <value>0</value> 74 </enumeratedValue> 75 <enumeratedValue> 76 <name>en</name> 77 <description>Enabled.</description> 78 <value>1</value> 79 </enumeratedValue> 80 </enumeratedValues> 81 </field> 82 <field> 83 <name>BGOFF</name> 84 <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description> 85 <bitOffset>11</bitOffset> 86 <bitWidth>1</bitWidth> 87 <enumeratedValues> 88 <enumeratedValue> 89 <name>on</name> 90 <description>Bandgap is always ON.</description> 91 <value>0</value> 92 </enumeratedValue> 93 <enumeratedValue> 94 <name>off</name> 95 <description>Bandgap is OFF in DeepSleep mode(default).</description> 96 <value>1</value> 97 </enumeratedValue> 98 </enumeratedValues> 99 </field> 100 <field> 101 <name>VCOREMD</name> 102 <description>VDDC(Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.</description> 103 <bitOffset>20</bitOffset> 104 <bitWidth>1</bitWidth> 105 <enumeratedValues> 106 <enumeratedValue> 107 <name>en</name> 108 <description>Enable if Bandgap is ON(default)</description> 109 <value>0</value> 110 </enumeratedValue> 111 <enumeratedValue> 112 <name>dis</name> 113 <description>Disabled.</description> 114 <value>1</value> 115 </enumeratedValue> 116 </enumeratedValues> 117 </field> 118 <field> 119 <name>VREGIMD</name> 120 <description>VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes.</description> 121 <bitOffset>21</bitOffset> 122 <bitWidth>1</bitWidth> 123 <enumeratedValues> 124 <enumeratedValue> 125 <name>en</name> 126 <description>Enable if Bandgap is ON(default)</description> 127 <value>0</value> 128 </enumeratedValue> 129 <enumeratedValue> 130 <name>dis</name> 131 <description>Disabled.</description> 132 <value>1</value> 133 </enumeratedValue> 134 </enumeratedValues> 135 </field> 136 <field> 137 <name>VDDAMD</name> 138 <description>VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 139 <bitOffset>22</bitOffset> 140 <bitWidth>1</bitWidth> 141 <enumeratedValues> 142 <enumeratedValue> 143 <name>en</name> 144 <description>Enable if Bandgap is ON(default)</description> 145 <value>0</value> 146 </enumeratedValue> 147 <enumeratedValue> 148 <name>dis</name> 149 <description>Disabled.</description> 150 <value>1</value> 151 </enumeratedValue> 152 </enumeratedValues> 153 </field> 154 <field> 155 <name>VDDIOMD</name> 156 <description>VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 157 <bitOffset>23</bitOffset> 158 <bitWidth>1</bitWidth> 159 <enumeratedValues> 160 <enumeratedValue> 161 <name>en</name> 162 <description>Enable if Bandgap is ON(default)</description> 163 <value>0</value> 164 </enumeratedValue> 165 <enumeratedValue> 166 <name>dis</name> 167 <description>Disabled.</description> 168 <value>1</value> 169 </enumeratedValue> 170 </enumeratedValues> 171 </field> 172 <field> 173 <name>VDDIOHMD</name> 174 <description>VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 175 <bitOffset>24</bitOffset> 176 <bitWidth>1</bitWidth> 177 <enumeratedValues> 178 <enumeratedValue> 179 <name>en</name> 180 <description>Enable if Bandgap is ON(default)</description> 181 <value>0</value> 182 </enumeratedValue> 183 <enumeratedValue> 184 <name>dis</name> 185 <description>Disabled.</description> 186 <value>1</value> 187 </enumeratedValue> 188 </enumeratedValues> 189 </field> 190 <field> 191 <name>PORVDDIOMD</name> 192 <description>VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.</description> 193 <bitOffset>25</bitOffset> 194 <bitWidth>1</bitWidth> 195 <enumeratedValues> 196 <enumeratedValue> 197 <name>dis</name> 198 <description>Disabled.</description> 199 <value>0</value> 200 </enumeratedValue> 201 <enumeratedValue> 202 <name>en</name> 203 <description>Enabled.</description> 204 <value>1</value> 205 </enumeratedValue> 206 </enumeratedValues> 207 </field> 208 <field> 209 <name>PORVDDIOHMD</name> 210 <description>VDDIOH Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIOH supply in all operating mods.</description> 211 <bitOffset>26</bitOffset> 212 <bitWidth>1</bitWidth> 213 <enumeratedValues> 214 <enumeratedValue> 215 <name>dis</name> 216 <description>Disabled.</description> 217 <value>0</value> 218 </enumeratedValue> 219 <enumeratedValue> 220 <name>en</name> 221 <description>Enabled.</description> 222 <value>1</value> 223 </enumeratedValue> 224 </enumeratedValues> 225 </field> 226 <field> 227 <name>VDDBMD</name> 228 <description>VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods.</description> 229 <bitOffset>27</bitOffset> 230 <bitWidth>1</bitWidth> 231 <enumeratedValues> 232 <enumeratedValue> 233 <name>dis</name> 234 <description>Disabled.</description> 235 <value>0</value> 236 </enumeratedValue> 237 <enumeratedValue> 238 <name>en</name> 239 <description>Enabled.</description> 240 <value>1</value> 241 </enumeratedValue> 242 </enumeratedValues> 243 </field> 244 <field> 245 <name>VRXOUTMD</name> 246 <description>VRXOUT Bluetooth Receiver Supply Power Monitor Disable .</description> 247 <bitOffset>28</bitOffset> 248 <bitWidth>1</bitWidth> 249 </field> 250 <field> 251 <name>VTXOUTMD</name> 252 <description>VTXOUT Bluetooth Transmitter Supply Power Monitor Disable .</description> 253 <bitOffset>29</bitOffset> 254 <bitWidth>1</bitWidth> 255 </field> 256 <field> 257 <name>PDOWNDSLEN</name> 258 <description>PDOWN DEEPSLEEP Output Enable .</description> 259 <bitOffset>30</bitOffset> 260 <bitWidth>1</bitWidth> 261 </field> 262 </fields> 263 </register> 264 <register> 265 <name>LPWKST0</name> 266 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 267 <addressOffset>0x04</addressOffset> 268 <fields> 269 <field> 270 <name>WAKEST</name> 271 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 272 <bitOffset>0</bitOffset> 273 <bitWidth>32</bitWidth> 274 </field> 275 </fields> 276 </register> 277 <register> 278 <name>LPWKEN0</name> 279 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 280 <addressOffset>0x08</addressOffset> 281 <fields> 282 <field> 283 <name>WAKEEN</name> 284 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 285 <bitOffset>0</bitOffset> 286 <bitWidth>31</bitWidth> 287 </field> 288 </fields> 289 </register> 290 <register> 291 <name>LPWKST1</name> 292 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 293 <addressOffset>0x0C</addressOffset> 294 <fields> 295 <field> 296 <name>WAKEST</name> 297 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 298 <bitOffset>0</bitOffset> 299 <bitWidth>18</bitWidth> 300 </field> 301 </fields> 302 </register> 303 <register> 304 <name>LPWKEN1</name> 305 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 306 <addressOffset>0x10</addressOffset> 307 <fields> 308 <field> 309 <name>WAKEEN</name> 310 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 311 <bitOffset>0</bitOffset> 312 <bitWidth>31</bitWidth> 313 </field> 314 </fields> 315 </register> 316 <register> 317 <name>LPPWST</name> 318 <description>Low Power Peripheral Wakeup Status Register.</description> 319 <addressOffset>0x30</addressOffset> 320 <fields> 321 <field> 322 <name>USBLSWKST</name> 323 <description>USB UTMI Linestate Detect Wakeup Flag(write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN.</description> 324 <bitOffset>0</bitOffset> 325 <bitWidth>2</bitWidth> 326 </field> 327 <field> 328 <name>USBVBUSWKST</name> 329 <description>USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off.</description> 330 <bitOffset>2</bitOffset> 331 <bitWidth>1</bitWidth> 332 </field> 333 <field> 334 <name>SDMAWKST</name> 335 <description>SDMA Wakeup Status Flag.</description> 336 <bitOffset>3</bitOffset> 337 <bitWidth>1</bitWidth> 338 </field> 339 <field> 340 <name>AINCOMP0WKST</name> 341 <description>Analog Input Comparator 0 Wakeup Status Flag.</description> 342 <bitOffset>4</bitOffset> 343 <bitWidth>1</bitWidth> 344 </field> 345 <field> 346 <name>AINCOMP1WKST</name> 347 <description>Analog Input Comparator 1 Wakeup Status Flag.</description> 348 <bitOffset>5</bitOffset> 349 <bitWidth>1</bitWidth> 350 </field> 351 <field> 352 <name>AINCOMP2WKST</name> 353 <description>Analog Input Comparator 2 Wakeup Status Flag.</description> 354 <bitOffset>6</bitOffset> 355 <bitWidth>1</bitWidth> 356 </field> 357 <field> 358 <name>AINCOMP3WKST</name> 359 <description>Analog Input Comparator 3 Wakeup Status Flag.</description> 360 <bitOffset>7</bitOffset> 361 <bitWidth>1</bitWidth> 362 </field> 363 <field> 364 <name>AINCOMP0ST</name> 365 <description>Analog Input Comparator 0 Output Status Flag.</description> 366 <bitOffset>8</bitOffset> 367 <bitWidth>1</bitWidth> 368 </field> 369 <field> 370 <name>AINCOMP1ST</name> 371 <description>Analog Input Comparator 1 Output Status Flag.</description> 372 <bitOffset>9</bitOffset> 373 <bitWidth>1</bitWidth> 374 </field> 375 <field> 376 <name>AINCOMP2ST</name> 377 <description>Analog Input Comparator 2 Output Status Flag.</description> 378 <bitOffset>10</bitOffset> 379 <bitWidth>1</bitWidth> 380 </field> 381 <field> 382 <name>AINCOMP3ST</name> 383 <description>Analog Input Comparator 3 Output Status Flag.</description> 384 <bitOffset>11</bitOffset> 385 <bitWidth>1</bitWidth> 386 </field> 387 <field> 388 <name>BBMODEST</name> 389 <description>Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode.</description> 390 <bitOffset>16</bitOffset> 391 <bitWidth>1</bitWidth> 392 </field> 393 <field> 394 <name>RSTWKST</name> 395 <description>Reset Detect Wakeup Status Flag.</description> 396 <bitOffset>17</bitOffset> 397 <bitWidth>1</bitWidth> 398 </field> 399 </fields> 400 </register> 401 <register> 402 <name>LPPWEN</name> 403 <description>Low Power Peripheral Wakeup Enable Register.</description> 404 <addressOffset>0x34</addressOffset> 405 <fields> 406 <field> 407 <name>USBLSWKEN</name> 408 <description>USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set.</description> 409 <bitOffset>0</bitOffset> 410 <bitWidth>2</bitWidth> 411 </field> 412 <field> 413 <name>USBVBUSWKEN</name> 414 <description>USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status.</description> 415 <bitOffset>2</bitOffset> 416 <bitWidth>1</bitWidth> 417 </field> 418 <field> 419 <name>SDMAWKEN</name> 420 <description>SDMA Wakeup Enable.</description> 421 <bitOffset>3</bitOffset> 422 <bitWidth>1</bitWidth> 423 </field> 424 <field> 425 <name>AINCOMP0WKEN</name> 426 <description>Analog Input Comparator 0 Wakeup Enable.</description> 427 <bitOffset>4</bitOffset> 428 <bitWidth>1</bitWidth> 429 </field> 430 <field> 431 <name>AINCOMP1WKEN</name> 432 <description>Analog Input Comparator 1 Wakeup Enable.</description> 433 <bitOffset>5</bitOffset> 434 <bitWidth>1</bitWidth> 435 </field> 436 <field> 437 <name>AINCOMP2WKEN</name> 438 <description>Analog Input Comparator 2 Wakeup Enable.</description> 439 <bitOffset>6</bitOffset> 440 <bitWidth>1</bitWidth> 441 </field> 442 <field> 443 <name>AINCOMP3WKEN</name> 444 <description>Analog Input Comparator 3 Wakeup Enable.</description> 445 <bitOffset>7</bitOffset> 446 <bitWidth>1</bitWidth> 447 </field> 448 </fields> 449 </register> 450 <register> 451 <name>LPMEMSD</name> 452 <description>Low Power Memory Shutdown Control.</description> 453 <addressOffset>0x40</addressOffset> 454 <fields> 455 <field> 456 <name>SRAM0SD</name> 457 <description>System RAM block 0 Shut Down.</description> 458 <bitOffset>0</bitOffset> 459 <bitWidth>1</bitWidth> 460 <enumeratedValues> 461 <enumeratedValue> 462 <name>normal</name> 463 <description>Normal Operating Mode.</description> 464 <value>0</value> 465 </enumeratedValue> 466 <enumeratedValue> 467 <name>shutdown</name> 468 <description>Shutdown Mode.</description> 469 <value>1</value> 470 </enumeratedValue> 471 </enumeratedValues> 472 </field> 473 <field> 474 <name>SRAM1SD</name> 475 <description>System RAM block 1 Shut Down.</description> 476 <bitOffset>1</bitOffset> 477 <bitWidth>1</bitWidth> 478 <enumeratedValues> 479 <enumeratedValue> 480 <name>normal</name> 481 <description>Normal Operating Mode.</description> 482 <value>0</value> 483 </enumeratedValue> 484 <enumeratedValue> 485 <name>shutdown</name> 486 <description>Shutdown Mode.</description> 487 <value>1</value> 488 </enumeratedValue> 489 </enumeratedValues> 490 </field> 491 <field> 492 <name>SRAM2SD</name> 493 <description>System RAM block 2 Shut Down.</description> 494 <bitOffset>2</bitOffset> 495 <bitWidth>1</bitWidth> 496 <enumeratedValues> 497 <enumeratedValue> 498 <name>normal</name> 499 <description>Normal Operating Mode.</description> 500 <value>0</value> 501 </enumeratedValue> 502 <enumeratedValue> 503 <name>shutdown</name> 504 <description>Shutdown Mode.</description> 505 <value>1</value> 506 </enumeratedValue> 507 </enumeratedValues> 508 </field> 509 <field> 510 <name>SRAM3SD</name> 511 <description>System RAM block 3 Shut Down.</description> 512 <bitOffset>3</bitOffset> 513 <bitWidth>1</bitWidth> 514 <enumeratedValues> 515 <enumeratedValue> 516 <name>normal</name> 517 <description>Normal Operating Mode.</description> 518 <value>0</value> 519 </enumeratedValue> 520 <enumeratedValue> 521 <name>shutdown</name> 522 <description>Shutdown Mode.</description> 523 <value>1</value> 524 </enumeratedValue> 525 </enumeratedValues> 526 </field> 527 <field> 528 <name>SRAM4SD</name> 529 <description>System RAM block 4 Shut Down.</description> 530 <bitOffset>4</bitOffset> 531 <bitWidth>1</bitWidth> 532 <enumeratedValues> 533 <enumeratedValue> 534 <name>normal</name> 535 <description>Normal Operating Mode.</description> 536 <value>0</value> 537 </enumeratedValue> 538 <enumeratedValue> 539 <name>shutdown</name> 540 <description>Shutdown Mode.</description> 541 <value>1</value> 542 </enumeratedValue> 543 </enumeratedValues> 544 </field> 545 <field> 546 <name>SRAM5SD</name> 547 <description>System RAM block 5 Shut Down.</description> 548 <bitOffset>5</bitOffset> 549 <bitWidth>1</bitWidth> 550 <enumeratedValues> 551 <enumeratedValue> 552 <name>normal</name> 553 <description>Normal Operating Mode.</description> 554 <value>0</value> 555 </enumeratedValue> 556 <enumeratedValue> 557 <name>shutdown</name> 558 <description>Shutdown Mode.</description> 559 <value>1</value> 560 </enumeratedValue> 561 </enumeratedValues> 562 </field> 563 <field> 564 <name>ICACHESD</name> 565 <description>Instruction Cache RAM Shut Down.</description> 566 <bitOffset>7</bitOffset> 567 <bitWidth>1</bitWidth> 568 <enumeratedValues> 569 <enumeratedValue> 570 <name>normal</name> 571 <description>Normal Operating Mode.</description> 572 <value>0</value> 573 </enumeratedValue> 574 <enumeratedValue> 575 <name>shutdown</name> 576 <description>Shutdown Mode.</description> 577 <value>1</value> 578 </enumeratedValue> 579 </enumeratedValues> 580 </field> 581 <field> 582 <name>ICACHEXIPSD</name> 583 <description>XiP Instruction Cache RAM Shut Down.</description> 584 <bitOffset>8</bitOffset> 585 <bitWidth>1</bitWidth> 586 <enumeratedValues> 587 <enumeratedValue> 588 <name>normal</name> 589 <description>Normal Operating Mode.</description> 590 <value>0</value> 591 </enumeratedValue> 592 <enumeratedValue> 593 <name>shutdown</name> 594 <description>Shutdown Mode.</description> 595 <value>1</value> 596 </enumeratedValue> 597 </enumeratedValues> 598 </field> 599 <field> 600 <name>SRCCSD</name> 601 <description>System Cache RAM Shut Down.</description> 602 <bitOffset>9</bitOffset> 603 <bitWidth>1</bitWidth> 604 <enumeratedValues> 605 <enumeratedValue> 606 <name>normal</name> 607 <description>Normal Operating Mode.</description> 608 <value>0</value> 609 </enumeratedValue> 610 <enumeratedValue> 611 <name>shutdown</name> 612 <description>Shutdown Mode.</description> 613 <value>1</value> 614 </enumeratedValue> 615 </enumeratedValues> 616 </field> 617 <field> 618 <name>CRYPTOSD</name> 619 <description>Crypto MAA RAM Shut Down.</description> 620 <bitOffset>10</bitOffset> 621 <bitWidth>1</bitWidth> 622 <enumeratedValues> 623 <enumeratedValue> 624 <name>normal</name> 625 <description>Normal Operating Mode.</description> 626 <value>0</value> 627 </enumeratedValue> 628 <enumeratedValue> 629 <name>shutdown</name> 630 <description>Shutdown Mode.</description> 631 <value>1</value> 632 </enumeratedValue> 633 </enumeratedValues> 634 </field> 635 <field> 636 <name>USBFIFOSD</name> 637 <description>USB FIFO Shut Down.</description> 638 <bitOffset>11</bitOffset> 639 <bitWidth>1</bitWidth> 640 <enumeratedValues> 641 <enumeratedValue> 642 <name>normal</name> 643 <description>Normal Operating Mode.</description> 644 <value>0</value> 645 </enumeratedValue> 646 <enumeratedValue> 647 <name>shutdown</name> 648 <description>Shutdown Mode.</description> 649 <value>1</value> 650 </enumeratedValue> 651 </enumeratedValues> 652 </field> 653 <field> 654 <name>ROMSD</name> 655 <description>ROM Shut Down.</description> 656 <bitOffset>12</bitOffset> 657 <bitWidth>1</bitWidth> 658 <enumeratedValues> 659 <enumeratedValue> 660 <name>normal</name> 661 <description>Normal Operating Mode.</description> 662 <value>0</value> 663 </enumeratedValue> 664 <enumeratedValue> 665 <name>shutdown</name> 666 <description>Shutdown Mode.</description> 667 <value>1</value> 668 </enumeratedValue> 669 </enumeratedValues> 670 </field> 671 <field> 672 <name>ROM1SD</name> 673 <description>ROM1 Shut Down.</description> 674 <bitOffset>13</bitOffset> 675 <bitWidth>1</bitWidth> 676 <enumeratedValues> 677 <enumeratedValue> 678 <name>normal</name> 679 <description>Normal Operating Mode.</description> 680 <value>0</value> 681 </enumeratedValue> 682 <enumeratedValue> 683 <name>shutdown</name> 684 <description>Shutdown Mode.</description> 685 <value>1</value> 686 </enumeratedValue> 687 </enumeratedValues> 688 </field> 689 <field> 690 <name>IC1SD</name> 691 <description>ICache 1 Shut Down.</description> 692 <bitOffset>14</bitOffset> 693 <bitWidth>1</bitWidth> 694 <enumeratedValues> 695 <enumeratedValue> 696 <name>normal</name> 697 <description>Normal Operating Mode.</description> 698 <value>0</value> 699 </enumeratedValue> 700 <enumeratedValue> 701 <name>shutdown</name> 702 <description>Shutdown Mode.</description> 703 <value>1</value> 704 </enumeratedValue> 705 </enumeratedValues> 706 </field> 707 </fields> 708 </register> 709 <register> 710 <name>LPVDDPD</name> 711 <description>Low Power VDD Domain Power Down Control.</description> 712 <addressOffset>0x44</addressOffset> 713 <fields> 714 <field> 715 <name>VREGOBPD</name> 716 <description>Power down SIMO Vreg B (VCOREB+VDDC) in backup mode.</description> 717 <bitOffset>0</bitOffset> 718 <bitWidth>1</bitWidth> 719 <enumeratedValues> 720 <enumeratedValue> 721 <name>up</name> 722 <description>Enabled in backup mode.</description> 723 <value>0</value> 724 </enumeratedValue> 725 <enumeratedValue> 726 <name>down</name> 727 <description>Disabled in backup mode.</description> 728 <value>1</value> 729 </enumeratedValue> 730 </enumeratedValues> 731 </field> 732 <field> 733 <name>VREGODPD</name> 734 <description>Power down SIMO Vreg D (BTLE).</description> 735 <bitOffset>1</bitOffset> 736 <bitWidth>1</bitWidth> 737 <enumeratedValues> 738 <enumeratedValue> 739 <name>up</name> 740 <description>Enabled</description> 741 <value>0</value> 742 </enumeratedValue> 743 <enumeratedValue> 744 <name>down</name> 745 <description>Disabled</description> 746 <value>1</value> 747 </enumeratedValue> 748 </enumeratedValues> 749 </field> 750 <field> 751 <name>VDD2PD</name> 752 <description>Power down VDD2 (CPU0+peripherals).</description> 753 <bitOffset>8</bitOffset> 754 <bitWidth>1</bitWidth> 755 <enumeratedValues> 756 <enumeratedValue> 757 <name>up</name> 758 <description>Enabled</description> 759 <value>0</value> 760 </enumeratedValue> 761 <enumeratedValue> 762 <name>down</name> 763 <description>Disabled</description> 764 <value>1</value> 765 </enumeratedValue> 766 </enumeratedValues> 767 </field> 768 <field> 769 <name>VDD3PD</name> 770 <description>Power down VDD3 (CPU1+audio).</description> 771 <bitOffset>9</bitOffset> 772 <bitWidth>1</bitWidth> 773 <enumeratedValues> 774 <enumeratedValue> 775 <name>up</name> 776 <description>Enabled</description> 777 <value>0</value> 778 </enumeratedValue> 779 <enumeratedValue> 780 <name>down</name> 781 <description>Disabled</description> 782 <value>1</value> 783 </enumeratedValue> 784 </enumeratedValues> 785 </field> 786 <field> 787 <name>VDD4PD</name> 788 <description>Power down VDD4 (SDMA+peripherals).</description> 789 <bitOffset>10</bitOffset> 790 <bitWidth>1</bitWidth> 791 <enumeratedValues> 792 <enumeratedValue> 793 <name>up</name> 794 <description>Enabled</description> 795 <value>0</value> 796 </enumeratedValue> 797 <enumeratedValue> 798 <name>down</name> 799 <description>Disabled</description> 800 <value>1</value> 801 </enumeratedValue> 802 </enumeratedValues> 803 </field> 804 <field> 805 <name>VDD5PD</name> 806 <description>Power down VDD5 (BTLE digital).</description> 807 <bitOffset>11</bitOffset> 808 <bitWidth>1</bitWidth> 809 <enumeratedValues> 810 <enumeratedValue> 811 <name>up</name> 812 <description>Enabled</description> 813 <value>0</value> 814 </enumeratedValue> 815 <enumeratedValue> 816 <name>down</name> 817 <description>Disabled</description> 818 <value>1</value> 819 </enumeratedValue> 820 </enumeratedValues> 821 </field> 822 </fields> 823 </register> 824 <register> 825 <name>BURETVEC</name> 826 <description>BACKUP Return Vector Register</description> 827 <addressOffset>0x48</addressOffset> 828 <fields> 829 <field> 830 <name>GPR0</name> 831 <description>General Purpose Register 0.</description> 832 <bitOffset>0</bitOffset> 833 <bitWidth>32</bitWidth> 834 </field> 835 </fields> 836 </register> 837 <register> 838 <name>BUAOD</name> 839 <description>BACKUP AoD Register</description> 840 <addressOffset>0x4C</addressOffset> 841 <fields> 842 <field> 843 <name>GPR1</name> 844 <description>General Purpose Register 1.</description> 845 <bitOffset>0</bitOffset> 846 <bitWidth>32</bitWidth> 847 </field> 848 </fields> 849 </register> 850 </registers> 851 </peripheral> 852 <!-- PWRSEQ: Power sequencer --> 853</device>
