PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers LPCN Low Power Control Register. 0x00 RAMRET System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 2 dis Disable Ram Retention. 0 en1 Enable System RAM 0 retention. 1 en2 Enable System RAM 0 and 1 retention. 2 en3 Enable System RAM 0 and 1 retention, if RREGEN=0, Enable all System RAM retention. 3 BCKGRND Background Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep. 9 1 dis Disabled. 0 en Enabled. 1 FWKM Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). 10 1 dis Disabled. 0 en Enabled. 1 BGOFF Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode(default). 1 VCOREMD VDDC(Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. 20 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VREGIMD VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. 21 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDAMD VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 22 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDIOMD VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 23 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDIOHMD VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 24 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 PORVDDIOMD VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. 25 1 dis Disabled. 0 en Enabled. 1 PORVDDIOHMD VDDIOH Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIOH supply in all operating mods. 26 1 dis Disabled. 0 en Enabled. 1 VDDBMD VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. 27 1 dis Disabled. 0 en Enabled. 1 VRXOUTMD VRXOUT Bluetooth Receiver Supply Power Monitor Disable . 28 1 VTXOUTMD VTXOUT Bluetooth Transmitter Supply Power Monitor Disable . 29 1 PDOWNDSLEN PDOWN DEEPSLEEP Output Enable . 30 1 LPWKST0 Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 32 LPWKEN0 Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 LPWKST1 Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 18 LPWKEN1 Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 LPPWST Low Power Peripheral Wakeup Status Register. 0x30 USBLSWKST USB UTMI Linestate Detect Wakeup Flag(write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. 0 2 USBVBUSWKST USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. 2 1 SDMAWKST SDMA Wakeup Status Flag. 3 1 AINCOMP0WKST Analog Input Comparator 0 Wakeup Status Flag. 4 1 AINCOMP1WKST Analog Input Comparator 1 Wakeup Status Flag. 5 1 AINCOMP2WKST Analog Input Comparator 2 Wakeup Status Flag. 6 1 AINCOMP3WKST Analog Input Comparator 3 Wakeup Status Flag. 7 1 AINCOMP0ST Analog Input Comparator 0 Output Status Flag. 8 1 AINCOMP1ST Analog Input Comparator 1 Output Status Flag. 9 1 AINCOMP2ST Analog Input Comparator 2 Output Status Flag. 10 1 AINCOMP3ST Analog Input Comparator 3 Output Status Flag. 11 1 BBMODEST Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode. 16 1 RSTWKST Reset Detect Wakeup Status Flag. 17 1 LPPWEN Low Power Peripheral Wakeup Enable Register. 0x34 USBLSWKEN USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set. 0 2 USBVBUSWKEN USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. 2 1 SDMAWKEN SDMA Wakeup Enable. 3 1 AINCOMP0WKEN Analog Input Comparator 0 Wakeup Enable. 4 1 AINCOMP1WKEN Analog Input Comparator 1 Wakeup Enable. 5 1 AINCOMP2WKEN Analog Input Comparator 2 Wakeup Enable. 6 1 AINCOMP3WKEN Analog Input Comparator 3 Wakeup Enable. 7 1 LPMEMSD Low Power Memory Shutdown Control. 0x40 SRAM0SD System RAM block 0 Shut Down. 0 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM1SD System RAM block 1 Shut Down. 1 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM2SD System RAM block 2 Shut Down. 2 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM3SD System RAM block 3 Shut Down. 3 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM4SD System RAM block 4 Shut Down. 4 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM5SD System RAM block 5 Shut Down. 5 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ICACHESD Instruction Cache RAM Shut Down. 7 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ICACHEXIPSD XiP Instruction Cache RAM Shut Down. 8 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRCCSD System Cache RAM Shut Down. 9 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 CRYPTOSD Crypto MAA RAM Shut Down. 10 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 USBFIFOSD USB FIFO Shut Down. 11 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ROMSD ROM Shut Down. 12 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ROM1SD ROM1 Shut Down. 13 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 IC1SD ICache 1 Shut Down. 14 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 LPVDDPD Low Power VDD Domain Power Down Control. 0x44 VREGOBPD Power down SIMO Vreg B (VCOREB+VDDC) in backup mode. 0 1 up Enabled in backup mode. 0 down Disabled in backup mode. 1 VREGODPD Power down SIMO Vreg D (BTLE). 1 1 up Enabled 0 down Disabled 1 VDD2PD Power down VDD2 (CPU0+peripherals). 8 1 up Enabled 0 down Disabled 1 VDD3PD Power down VDD3 (CPU1+audio). 9 1 up Enabled 0 down Disabled 1 VDD4PD Power down VDD4 (SDMA+peripherals). 10 1 up Enabled 0 down Disabled 1 VDD5PD Power down VDD5 (BTLE digital). 11 1 up Enabled 0 down Disabled 1 BURETVEC BACKUP Return Vector Register 0x48 GPR0 General Purpose Register 0. 0 32 BUAOD BACKUP AoD Register 0x4C GPR1 General Purpose Register 1. 0 32