1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>PWRSEQ</name> 5 <description>Power Sequencer / Low Power Control Register.</description> 6 <baseAddress>0x40006800</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>LPCTRL</name> 15 <description>Low Power Control Register.</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAM0RET_EN</name> 20 <description>System RAM 0 retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>1</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>dis</name> 26 <description>Disable Ram Retention.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>en</name> 31 <description>Enable System RAM 0 retention.</description> 32 <value>1</value> 33 </enumeratedValue> 34 </enumeratedValues> 35 </field> 36 <field> 37 <name>RAM1RET_EN</name> 38 <description>System RAM 1 retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 39 <bitOffset>1</bitOffset> 40 <bitWidth>1</bitWidth> 41 <enumeratedValues> 42 <enumeratedValue> 43 <name>dis</name> 44 <description>Disable Ram Retention.</description> 45 <value>0</value> 46 </enumeratedValue> 47 <enumeratedValue> 48 <name>en</name> 49 <description>Enable System RAM 1 retention.</description> 50 <value>1</value> 51 </enumeratedValue> 52 </enumeratedValues> 53 </field> 54 <field> 55 <name>RAM2RET_EN</name> 56 <description>System RAM 2 retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 57 <bitOffset>2</bitOffset> 58 <bitWidth>1</bitWidth> 59 <enumeratedValues> 60 <enumeratedValue> 61 <name>dis</name> 62 <description>Disable Ram Retention.</description> 63 <value>0</value> 64 </enumeratedValue> 65 <enumeratedValue> 66 <name>en</name> 67 <description>Enable System RAM 2 retention.</description> 68 <value>1</value> 69 </enumeratedValue> 70 </enumeratedValues> 71 </field> 72 <field> 73 <name>RAM3RET_EN</name> 74 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 75 <bitOffset>3</bitOffset> 76 <bitWidth>1</bitWidth> 77 <enumeratedValues> 78 <enumeratedValue> 79 <name>dis</name> 80 <description>Disable Ram Retention.</description> 81 <value>0</value> 82 </enumeratedValue> 83 <enumeratedValue> 84 <name>en</name> 85 <description>Enable System RAM 3 retention.</description> 86 <value>1</value> 87 </enumeratedValue> 88 </enumeratedValues> 89 </field> 90 <field> 91 <name>OVR</name> 92 <description>Operating Voltage Range. The Operating Voltage Range 93bits (OVR) determine the operating range for VCORE 94domain.</description> 95 <bitOffset>4</bitOffset> 96 <bitWidth>2</bitWidth> 97 <enumeratedValues> 98 <enumeratedValue> 99 <name>0_9V</name> 100 <description>0.9V</description> 101 <value>0</value> 102 </enumeratedValue> 103 <enumeratedValue> 104 <name>1_0V</name> 105 <description>1.0V</description> 106 <value>1</value> 107 </enumeratedValue> 108 <enumeratedValue> 109 <name>1_1V</name> 110 <description>1.1V</description> 111 <value>2</value> 112 </enumeratedValue> 113 </enumeratedValues> 114 </field> 115 <field> 116 <name>VCORE_DET_BYPASS</name> 117 <description>Block Auto Detect. Prevent the power sequencer from taking time to detect whether an external power source exists on the VCORE pin. Should always be set to 1 if VCORE is not provided from an external source.</description> 118 <bitOffset>6</bitOffset> 119 <bitWidth>1</bitWidth> 120 <enumeratedValues> 121 <enumeratedValue> 122 <name>dis</name> 123 <description>Disable auto detection.</description> 124 <value>0</value> 125 </enumeratedValue> 126 <enumeratedValue> 127 <name>en</name> 128 <description>Enable auto detection.</description> 129 <value>1</value> 130 </enumeratedValue> 131 </enumeratedValues> 132 </field> 133 <field> 134 <name>FVDD_EN</name> 135 <description>Flash VDD Enable. FOrce the flash VDD to remain enabled during LP modes.</description> 136 <bitOffset>7</bitOffset> 137 <bitWidth>1</bitWidth> 138 <enumeratedValues> 139 <enumeratedValue> 140 <name>dis</name> 141 <description>Flash VDDIO Not Forced.</description> 142 <value>0</value> 143 </enumeratedValue> 144 <enumeratedValue> 145 <name>en</name> 146 <description>Flash VDDIO Force on.</description> 147 <value>1</value> 148 </enumeratedValue> 149 </enumeratedValues> 150 </field> 151 <field> 152 <name>RETREG_EN</name> 153 <description>Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. This bit should be 1 all the time if user wants to use retention regulator.</description> 154 <bitOffset>8</bitOffset> 155 <bitWidth>1</bitWidth> 156 <enumeratedValues> 157 <enumeratedValue> 158 <name>dis</name> 159 <description>Disable.</description> 160 <value>0</value> 161 </enumeratedValue> 162 <enumeratedValue> 163 <name>en</name> 164 <description>Enable.</description> 165 <value>1</value> 166 </enumeratedValue> 167 </enumeratedValues> 168 </field> 169 <field> 170 <name>STORAGE_EN</name> 171 <description>STORAGE mode enable.</description> 172 <bitOffset>9</bitOffset> 173 <bitWidth>1</bitWidth> 174 </field> 175 <field> 176 <name>FASTWK_EN</name> 177 <description>Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode.</description> 178 <bitOffset>10</bitOffset> 179 <bitWidth>1</bitWidth> 180 </field> 181 <field> 182 <name>BG_DIS</name> 183 <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description> 184 <bitOffset>11</bitOffset> 185 <bitWidth>1</bitWidth> 186 <enumeratedValues> 187 <enumeratedValue> 188 <name>on</name> 189 <description>Bandgap is always ON.</description> 190 <value>0</value> 191 </enumeratedValue> 192 <enumeratedValue> 193 <name>off</name> 194 <description>Bandgap is OFF in DeepSleep mode (default).</description> 195 <value>1</value> 196 </enumeratedValue> 197 </enumeratedValues> 198 </field> 199 <field> 200 <name>VCOREPOR_DIS</name> 201 <description>VCORE Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode.</description> 202 <bitOffset>12</bitOffset> 203 <bitWidth>1</bitWidth> 204 </field> 205 <field> 206 <name>LDO_DIS</name> 207 <description>Disable Main LDO. This bit initializes to 1 until the power sequencer determines that no external power source exists on the VCORE pin. At that time, this bit is automatically cleared to 0. If an external power source is detected on the VCORE pin, then this bit will remain at 1. </description> 208 <bitOffset>16</bitOffset> 209 <bitWidth>1</bitWidth> 210 </field> 211 <field> 212 <name>VCORE_EXT</name> 213 <description>Use external VCORE for 1V supply.</description> 214 <bitOffset>17</bitOffset> 215 <bitWidth>1</bitWidth> 216 </field> 217 <field> 218 <name>VCOREMON_DIS</name> 219 <description>VCORE Monitor Disable. This bit controls the power monitor on the VCORE supply in all operating modes.</description> 220 <bitOffset>20</bitOffset> 221 <bitWidth>1</bitWidth> 222 </field> 223 <field> 224 <name>VDDAMON_DIS</name> 225 <description>VDDA Monitor Disable. This bit controls the power monitor on the Analog supply in all operating modes.</description> 226 <bitOffset>22</bitOffset> 227 <bitWidth>1</bitWidth> 228 </field> 229 <field> 230 <name>PORVDDMON_DIS</name> 231 <description>VCORE Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VCORE supply in all operating modes.</description> 232 <bitOffset>25</bitOffset> 233 <bitWidth>1</bitWidth> 234 </field> 235 <field> 236 <name>VBBMON_DIS</name> 237 <description>VDDA Monitor Disable. This bit controls the power monitor on the Analog supply in all operating modes.</description> 238 <bitOffset>27</bitOffset> 239 <bitWidth>1</bitWidth> 240 </field> 241 <field> 242 <name>INRO_EN</name> 243 <description>Allow LIRC80K to remain on in all Power modes. If STORAGE is set, this bit has no effect.</description> 244 <bitOffset>28</bitOffset> 245 <bitWidth>1</bitWidth> 246 </field> 247 <field> 248 <name>ERTCO_EN</name> 249 <description>Allow LIRC32K to remain on in all Power modes. If STORAGE is set, this bit has no effect.</description> 250 <bitOffset>29</bitOffset> 251 <bitWidth>1</bitWidth> 252 </field> 253 </fields> 254 </register> 255 <register> 256 <name>LPWKFL0</name> 257 <description>Low Power I/O Wakeup Status Flag Register 0. This register indicates the low power wakeup status for GPIO0.</description> 258 <addressOffset>0x04</addressOffset> 259 <fields> 260 <field> 261 <name>WAKEFL</name> 262 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 263 <bitOffset>0</bitOffset> 264 <bitWidth>31</bitWidth> 265 </field> 266 </fields> 267 </register> 268 <register> 269 <name>LPWKEN0</name> 270 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 271 <addressOffset>0x08</addressOffset> 272 <fields> 273 <field> 274 <name>WAKEEN</name> 275 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 276 <bitOffset>0</bitOffset> 277 <bitWidth>31</bitWidth> 278 </field> 279 </fields> 280 </register> 281 <register> 282 <name>LPPWKFL</name> 283 <description>Low Power Peripheral Wakeup Status Flag Register.</description> 284 <addressOffset>0x30</addressOffset> 285 <fields> 286 <field> 287 <name>TMR3</name> 288 <description>TMR3 (LPTMR0) Wakeup Flag.</description> 289 <bitOffset>0</bitOffset> 290 <bitWidth>1</bitWidth> 291 </field> 292 <field> 293 <name>AINCOMP0</name> 294 <description>Analog Input Comparator 0 Wakeup Flag.</description> 295 <bitOffset>3</bitOffset> 296 <bitWidth>1</bitWidth> 297 </field> 298 <field> 299 <name>AINCOMP1</name> 300 <description>Analog Input Comparator 1 Wakeup Flag.</description> 301 <bitOffset>4</bitOffset> 302 <bitWidth>1</bitWidth> 303 </field> 304 <field> 305 <name>AINCOMP0_ST</name> 306 <description>Analog Input Comparator 0 Status.</description> 307 <bitOffset>5</bitOffset> 308 <bitWidth>1</bitWidth> 309 </field> 310 <field> 311 <name>AINCOMP1_ST</name> 312 <description>Analog Input Comparator 1 Status.</description> 313 <bitOffset>6</bitOffset> 314 <bitWidth>1</bitWidth> 315 </field> 316 <field> 317 <name>BACKUP</name> 318 <description>Backup Mode Wakeup Flag.</description> 319 <bitOffset>16</bitOffset> 320 <bitWidth>1</bitWidth> 321 </field> 322 </fields> 323 </register> 324 <register> 325 <name>LPPWKEN</name> 326 <description>Low Power Peripheral Wakeup Enable Register.</description> 327 <addressOffset>0x34</addressOffset> 328 <fields> 329 <field> 330 <name>LPTMR0</name> 331 <description>LPTMR0 Wakeup Enable. This bit allows wakeup from the LPTIMER0.</description> 332 <bitOffset>0</bitOffset> 333 <bitWidth>1</bitWidth> 334 </field> 335 <field> 336 <name>AINCOMP0</name> 337 <description> AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0.</description> 338 <bitOffset>3</bitOffset> 339 <bitWidth>1</bitWidth> 340 </field> 341 <field> 342 <name>AINCOMP1</name> 343 <description> AINCOMP1 Wakeup Enable. This bit allows wakeup from the AINCOMP1.</description> 344 <bitOffset>4</bitOffset> 345 <bitWidth>1</bitWidth> 346 </field> 347 </fields> 348 </register> 349 <register> 350 <name>LPMEMSD</name> 351 <description>Low Power Memory Shutdown Register.</description> 352 <addressOffset>0x40</addressOffset> 353 <fields> 354 <field> 355 <name>RAM0</name> 356 <description>System RAM block 0 Shut Down.</description> 357 <bitOffset>0</bitOffset> 358 <bitWidth>1</bitWidth> 359 </field> 360 <field> 361 <name>RAM1</name> 362 <description>Systen RAM block 1 Shut Down.</description> 363 <bitOffset>1</bitOffset> 364 <bitWidth>1</bitWidth> 365 </field> 366 <field> 367 <name>RAM2</name> 368 <description>System RAM block 2 Shut Down.</description> 369 <bitOffset>2</bitOffset> 370 <bitWidth>1</bitWidth> 371 </field> 372 <field> 373 <name>RAM3</name> 374 <description>System RAM block 2 Shut Down.</description> 375 <bitOffset>3</bitOffset> 376 <bitWidth>1</bitWidth> 377 </field> 378 </fields> 379 </register> 380 </registers> 381 </peripheral> 382 <!-- PWRSEQ: Power sequencer --> 383</device>
