PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers LPCTRL Low Power Control Register. 0x00 RAM0RET_EN System RAM 0 retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 1 dis Disable Ram Retention. 0 en Enable System RAM 0 retention. 1 RAM1RET_EN System RAM 1 retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 1 1 dis Disable Ram Retention. 0 en Enable System RAM 1 retention. 1 RAM2RET_EN System RAM 2 retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 2 1 dis Disable Ram Retention. 0 en Enable System RAM 2 retention. 1 RAM3RET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 3 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 OVR Operating Voltage Range. The Operating Voltage Range bits (OVR) determine the operating range for VCORE domain. 4 2 0_9V 0.9V 0 1_0V 1.0V 1 1_1V 1.1V 2 VCORE_DET_BYPASS Block Auto Detect. Prevent the power sequencer from taking time to detect whether an external power source exists on the VCORE pin. Should always be set to 1 if VCORE is not provided from an external source. 6 1 dis Disable auto detection. 0 en Enable auto detection. 1 FVDD_EN Flash VDD Enable. FOrce the flash VDD to remain enabled during LP modes. 7 1 dis Flash VDDIO Not Forced. 0 en Flash VDDIO Force on. 1 RETREG_EN Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. This bit should be 1 all the time if user wants to use retention regulator. 8 1 dis Disable. 0 en Enable. 1 STORAGE_EN STORAGE mode enable. 9 1 FASTWK_EN Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. 10 1 BG_DIS Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode (default). 1 VCOREPOR_DIS VCORE Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. 12 1 LDO_DIS Disable Main LDO. This bit initializes to 1 until the power sequencer determines that no external power source exists on the VCORE pin. At that time, this bit is automatically cleared to 0. If an external power source is detected on the VCORE pin, then this bit will remain at 1. 16 1 VCORE_EXT Use external VCORE for 1V supply. 17 1 VCOREMON_DIS VCORE Monitor Disable. This bit controls the power monitor on the VCORE supply in all operating modes. 20 1 VDDAMON_DIS VDDA Monitor Disable. This bit controls the power monitor on the Analog supply in all operating modes. 22 1 PORVDDMON_DIS VCORE Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VCORE supply in all operating modes. 25 1 VBBMON_DIS VDDA Monitor Disable. This bit controls the power monitor on the Analog supply in all operating modes. 27 1 INRO_EN Allow LIRC80K to remain on in all Power modes. If STORAGE is set, this bit has no effect. 28 1 ERTCO_EN Allow LIRC32K to remain on in all Power modes. If STORAGE is set, this bit has no effect. 29 1 LPWKFL0 Low Power I/O Wakeup Status Flag Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 WAKEFL Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 31 LPWKEN0 Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 LPPWKFL Low Power Peripheral Wakeup Status Flag Register. 0x30 TMR3 TMR3 (LPTMR0) Wakeup Flag. 0 1 AINCOMP0 Analog Input Comparator 0 Wakeup Flag. 3 1 AINCOMP1 Analog Input Comparator 1 Wakeup Flag. 4 1 AINCOMP0_ST Analog Input Comparator 0 Status. 5 1 AINCOMP1_ST Analog Input Comparator 1 Status. 6 1 BACKUP Backup Mode Wakeup Flag. 16 1 LPPWKEN Low Power Peripheral Wakeup Enable Register. 0x34 LPTMR0 LPTMR0 Wakeup Enable. This bit allows wakeup from the LPTIMER0. 0 1 AINCOMP0 AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. 3 1 AINCOMP1 AINCOMP1 Wakeup Enable. This bit allows wakeup from the AINCOMP1. 4 1 LPMEMSD Low Power Memory Shutdown Register. 0x40 RAM0 System RAM block 0 Shut Down. 0 1 RAM1 Systen RAM block 1 Shut Down. 1 1 RAM2 System RAM block 2 Shut Down. 2 1 RAM3 System RAM block 2 Shut Down. 3 1