1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>PWRSEQ</name> 5 <description>Power Sequencer / Low Power Control Register.</description> 6 <baseAddress>0x40006800</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x800</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>LP_CTRL</name> 15 <description>Low Power Control Register.</description> 16 <addressOffset>0x00</addressOffset> 17 <fields> 18 <field> 19 <name>RAMRET_SEL0</name> 20 <description>System RAM 0 Data retention in BACKUP mode. </description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>1</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>dis</name> 26 <description>Disabled.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>en</name> 31 <description>Enabled.</description> 32 <value>1</value> 33 </enumeratedValue> 34 </enumeratedValues> 35 </field> 36 <field> 37 <name>RAMRET_SEL1</name> 38 <description>System RAM 1 Data retention in BACKUP mode. </description> 39 <bitOffset>1</bitOffset> 40 <bitWidth>1</bitWidth> 41 <enumeratedValues> 42 <enumeratedValue> 43 <name>dis</name> 44 <description>Disabled.</description> 45 <value>0</value> 46 </enumeratedValue> 47 <enumeratedValue> 48 <name>en</name> 49 <description>Enabled.</description> 50 <value>1</value> 51 </enumeratedValue> 52 </enumeratedValues> 53 </field> 54 <field> 55 <name>RAMRET_SEL2</name> 56 <description>System RAM 2 Data retention in BACKUP mode. </description> 57 <bitOffset>2</bitOffset> 58 <bitWidth>1</bitWidth> 59 <enumeratedValues> 60 <enumeratedValue> 61 <name>dis</name> 62 <description>Disabled.</description> 63 <value>0</value> 64 </enumeratedValue> 65 <enumeratedValue> 66 <name>en</name> 67 <description>Enabled.</description> 68 <value>1</value> 69 </enumeratedValue> 70 </enumeratedValues> 71 </field> 72 <field> 73 <name>RAMRET_SEL3</name> 74 <description>System RAM 3 Data retention in BACKUP mode. </description> 75 <bitOffset>3</bitOffset> 76 <bitWidth>1</bitWidth> 77 <enumeratedValues> 78 <enumeratedValue> 79 <name>dis</name> 80 <description>Disabled.</description> 81 <value>0</value> 82 </enumeratedValue> 83 <enumeratedValue> 84 <name>en</name> 85 <description>Enabled.</description> 86 <value>1</value> 87 </enumeratedValue> 88 </enumeratedValues> 89 </field> 90 <field> 91 <name>OVR</name> 92 <description>Operating Voltage Range</description> 93 <bitOffset>4</bitOffset> 94 <bitWidth>2</bitWidth> 95 <enumeratedValues> 96 <enumeratedValue> 97 <name>0_9V</name> 98 <description>0.9V 24MHz</description> 99 <value>0</value> 100 </enumeratedValue> 101 <enumeratedValue> 102 <name>1_0V</name> 103 <description>1.0V 48MHz</description> 104 <value>1</value> 105 </enumeratedValue> 106 <enumeratedValue> 107 <name>1_1V</name> 108 <description>1.1V 96MHz</description> 109 <value>2</value> 110 </enumeratedValue> 111 </enumeratedValues> 112 </field> 113 <field> 114 <name>VCORE_DET_BYPASS</name> 115 <description>Bypass V CORE External Supply Detection</description> 116 <bitOffset>6</bitOffset> 117 <bitWidth>1</bitWidth> 118 <enumeratedValues> 119 <enumeratedValue> 120 <name>enabled</name> 121 <description>enable</description> 122 <value>0</value> 123 </enumeratedValue> 124 <enumeratedValue> 125 <name>Disable</name> 126 <description>disable</description> 127 <value>1</value> 128 </enumeratedValue> 129 </enumeratedValues> 130 </field> 131 <field> 132 <name>RETREG_EN</name> 133 <description>Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. </description> 134 <bitOffset>8</bitOffset> 135 <bitWidth>1</bitWidth> 136 <enumeratedValues> 137 <enumeratedValue> 138 <name>dis</name> 139 <description>Disabled.</description> 140 <value>0</value> 141 </enumeratedValue> 142 <enumeratedValue> 143 <name>en</name> 144 <description>Enabled.</description> 145 <value>1</value> 146 </enumeratedValue> 147 </enumeratedValues> 148 </field> 149 <field> 150 <name>FAST_WK_EN</name> 151 <description>Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. </description> 152 <bitOffset>10</bitOffset> 153 <bitWidth>1</bitWidth> 154 <enumeratedValues> 155 <enumeratedValue> 156 <name>dis</name> 157 <description>Disabled.</description> 158 <value>0</value> 159 </enumeratedValue> 160 <enumeratedValue> 161 <name>en</name> 162 <description>Enabled.</description> 163 <value>1</value> 164 </enumeratedValue> 165 </enumeratedValues> 166 </field> 167 <field> 168 <name>BG_OFF</name> 169 <description>Band Gap Disable for DEEPSLEEP and BACKUP Mode</description> 170 <bitOffset>11</bitOffset> 171 <bitWidth>1</bitWidth> 172 <enumeratedValues> 173 <enumeratedValue> 174 <name>on</name> 175 <description>Bandgap is always ON.</description> 176 <value>0</value> 177 </enumeratedValue> 178 <enumeratedValue> 179 <name>off</name> 180 <description>Bandgap is OFF in DeepSleep mode(default).</description> 181 <value>1</value> 182 </enumeratedValue> 183 </enumeratedValues> 184 </field> 185 <field> 186 <name>VCORE_POR_DIS</name> 187 <description>V CORE POR Disable for DEEPSLEEP and BACKUP Mode</description> 188 <bitOffset>12</bitOffset> 189 <bitWidth>1</bitWidth> 190 <enumeratedValues> 191 <enumeratedValue> 192 <name>dis</name> 193 <description>Disabled.</description> 194 <value>0</value> 195 </enumeratedValue> 196 <enumeratedValue> 197 <name>en</name> 198 <description>Enabled.</description> 199 <value>1</value> 200 </enumeratedValue> 201 </enumeratedValues> 202 </field> 203 <field> 204 <name>LDO_DIS</name> 205 <description>LDO Disable</description> 206 <bitOffset>16</bitOffset> 207 <bitWidth>1</bitWidth> 208 <enumeratedValues> 209 <enumeratedValue> 210 <name>en</name> 211 <description>Enable if Bandgap is ON(default)</description> 212 <value>0</value> 213 </enumeratedValue> 214 <enumeratedValue> 215 <name>dis</name> 216 <description>Disabled.</description> 217 <value>1</value> 218 </enumeratedValue> 219 </enumeratedValues> 220 </field> 221 <field> 222 <name>VCORE_SVM_DIS</name> 223 <description>V CORE Supply Voltage Monitor Disable</description> 224 <bitOffset>20</bitOffset> 225 <bitWidth>1</bitWidth> 226 <enumeratedValues> 227 <enumeratedValue> 228 <name>en</name> 229 <description>Enable if Bandgap is ON(default)</description> 230 <value>0</value> 231 </enumeratedValue> 232 <enumeratedValue> 233 <name>dis</name> 234 <description>Disabled.</description> 235 <value>1</value> 236 </enumeratedValue> 237 </enumeratedValues> 238 </field> 239 <field> 240 <name>VDDIO_POR_DIS</name> 241 <description>VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.</description> 242 <bitOffset>25</bitOffset> 243 <bitWidth>1</bitWidth> 244 <enumeratedValues> 245 <enumeratedValue> 246 <name>en</name> 247 <description>Enabled.</description> 248 <value>0</value> 249 </enumeratedValue> 250 <enumeratedValue> 251 <name>dis</name> 252 <description>Disabled.</description> 253 <value>1</value> 254 </enumeratedValue> 255 </enumeratedValues> 256 </field> 257 </fields> 258 </register> 259 <register> 260 <name>LP_WAKEFL</name> 261 <description>Low Power Mode Wakeup Flags for GPIO0</description> 262 <addressOffset>0x04</addressOffset> 263 <fields> 264 <field> 265 <name>WAKEST</name> 266 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 267 <bitOffset>0</bitOffset> 268 <bitWidth>14</bitWidth> 269 </field> 270 </fields> 271 </register> 272 <register> 273 <name>LPWK_EN</name> 274 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 275 <addressOffset>0x08</addressOffset> 276 <fields> 277 <field> 278 <name>WAKEEN</name> 279 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 280 <bitOffset>0</bitOffset> 281 <bitWidth>14</bitWidth> 282 </field> 283 </fields> 284 </register> 285 <register> 286 <name>LPMEMSD</name> 287 <description>Low Power Memory Shutdown Control.</description> 288 <addressOffset>0x40</addressOffset> 289 <fields> 290 <field> 291 <name>SRAM0_OFF</name> 292 <description>System RAM block 0 Shut Down.</description> 293 <bitOffset>0</bitOffset> 294 <bitWidth>1</bitWidth> 295 <enumeratedValues> 296 <enumeratedValue> 297 <name>normal</name> 298 <description>Normal Operating Mode.</description> 299 <value>0</value> 300 </enumeratedValue> 301 <enumeratedValue> 302 <name>shutdown</name> 303 <description>Shutdown Mode.</description> 304 <value>1</value> 305 </enumeratedValue> 306 </enumeratedValues> 307 </field> 308 <field> 309 <name>SRAM1_OFF</name> 310 <description>System RAM block 1 Shut Down.</description> 311 <bitOffset>1</bitOffset> 312 <bitWidth>1</bitWidth> 313 <enumeratedValues> 314 <enumeratedValue> 315 <name>normal</name> 316 <description>Normal Operating Mode.</description> 317 <value>0</value> 318 </enumeratedValue> 319 <enumeratedValue> 320 <name>shutdown</name> 321 <description>Shutdown Mode.</description> 322 <value>1</value> 323 </enumeratedValue> 324 </enumeratedValues> 325 </field> 326 <field> 327 <name>SRAM2_OFF</name> 328 <description>System RAM block 2 Shut Down.</description> 329 <bitOffset>2</bitOffset> 330 <bitWidth>1</bitWidth> 331 <enumeratedValues> 332 <enumeratedValue> 333 <name>normal</name> 334 <description>Normal Operating Mode.</description> 335 <value>0</value> 336 </enumeratedValue> 337 <enumeratedValue> 338 <name>shutdown</name> 339 <description>Shutdown Mode.</description> 340 <value>1</value> 341 </enumeratedValue> 342 </enumeratedValues> 343 </field> 344 <field> 345 <name>SRAM3_OFF</name> 346 <description>System RAM block 3 Shut Down.</description> 347 <bitOffset>3</bitOffset> 348 <bitWidth>1</bitWidth> 349 <enumeratedValues> 350 <enumeratedValue> 351 <name>normal</name> 352 <description>Normal Operating Mode.</description> 353 <value>0</value> 354 </enumeratedValue> 355 <enumeratedValue> 356 <name>shutdown</name> 357 <description>Shutdown Mode.</description> 358 <value>1</value> 359 </enumeratedValue> 360 </enumeratedValues> 361 </field> 362 </fields> 363 </register> 364 </registers> 365 </peripheral> 366 <!-- PWRSEQ: Power sequencer --> 367</device>
