PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x800 registers LP_CTRL Low Power Control Register. 0x00 RAMRET_SEL0 System RAM 0 Data retention in BACKUP mode. 0 1 dis Disabled. 0 en Enabled. 1 RAMRET_SEL1 System RAM 1 Data retention in BACKUP mode. 1 1 dis Disabled. 0 en Enabled. 1 RAMRET_SEL2 System RAM 2 Data retention in BACKUP mode. 2 1 dis Disabled. 0 en Enabled. 1 RAMRET_SEL3 System RAM 3 Data retention in BACKUP mode. 3 1 dis Disabled. 0 en Enabled. 1 OVR Operating Voltage Range 4 2 0_9V 0.9V 24MHz 0 1_0V 1.0V 48MHz 1 1_1V 1.1V 96MHz 2 VCORE_DET_BYPASS Bypass V CORE External Supply Detection 6 1 enabled enable 0 Disable disable 1 RETREG_EN Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. 8 1 dis Disabled. 0 en Enabled. 1 FAST_WK_EN Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. 10 1 dis Disabled. 0 en Enabled. 1 BG_OFF Band Gap Disable for DEEPSLEEP and BACKUP Mode 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode(default). 1 VCORE_POR_DIS V CORE POR Disable for DEEPSLEEP and BACKUP Mode 12 1 dis Disabled. 0 en Enabled. 1 LDO_DIS LDO Disable 16 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VCORE_SVM_DIS V CORE Supply Voltage Monitor Disable 20 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDIO_POR_DIS VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. 25 1 en Enabled. 0 dis Disabled. 1 LP_WAKEFL Low Power Mode Wakeup Flags for GPIO0 0x04 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 14 LPWK_EN Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 14 LPMEMSD Low Power Memory Shutdown Control. 0x40 SRAM0_OFF System RAM block 0 Shut Down. 0 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM1_OFF System RAM block 1 Shut Down. 1 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM2_OFF System RAM block 2 Shut Down. 2 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM3_OFF System RAM block 3 Shut Down. 3 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1