1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3  <peripheral>
4    <name>ICC0</name>
5    <description>Instruction Cache Controller Registers</description>
6    <baseAddress>0x4002A000</baseAddress>
7    <addressBlock>
8      <offset>0x00</offset>
9      <size>0x800</size>
10      <usage>registers</usage>
11    </addressBlock>
12    <registers>
13      <register>
14        <name>INFO</name>
15        <description>Cache ID Register.</description>
16        <addressOffset>0x0000</addressOffset>
17        <access>read-only</access>
18        <fields>
19          <field>
20            <name>RELNUM</name>
21            <description>Release Number. Identifies the RTL release version.</description>
22            <bitOffset>0</bitOffset>
23            <bitWidth>6</bitWidth>
24          </field>
25          <field>
26            <name>PARTNUM</name>
27            <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description>
28            <bitOffset>6</bitOffset>
29            <bitWidth>4</bitWidth>
30          </field>
31          <field>
32            <name>ID</name>
33            <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description>
34            <bitOffset>10</bitOffset>
35            <bitWidth>6</bitWidth>
36          </field>
37        </fields>
38      </register>
39      <register>
40        <name>SZ</name>
41        <description>Memory Configuration Register.</description>
42        <addressOffset>0x0004</addressOffset>
43        <access>read-only</access>
44        <resetValue>0x00080008</resetValue>
45        <fields>
46          <field>
47            <name>CCH</name>
48            <description>Cache Size. Indicates total size in Kbytes of cache.</description>
49            <bitOffset>0</bitOffset>
50            <bitWidth>16</bitWidth>
51          </field>
52          <field>
53            <name>MEM</name>
54            <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description>
55            <bitOffset>16</bitOffset>
56            <bitWidth>16</bitWidth>
57          </field>
58        </fields>
59      </register>
60      <register>
61        <name>CTRL</name>
62        <description>Cache Control and Status Register.</description>
63        <addressOffset>0x0100</addressOffset>
64        <fields>
65          <field>
66            <name>EN</name>
67            <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description>
68            <bitOffset>0</bitOffset>
69            <bitWidth>1</bitWidth>
70            <enumeratedValues>
71              <enumeratedValue>
72                <name>dis</name>
73                <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description>
74                <value>0</value>
75              </enumeratedValue>
76              <enumeratedValue>
77                <name>en</name>
78                <description>Cache Enabled.</description>
79                <value>1</value>
80              </enumeratedValue>
81            </enumeratedValues>
82          </field>
83          <field>
84            <name>RDY</name>
85            <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description>
86            <bitOffset>16</bitOffset>
87            <bitWidth>1</bitWidth>
88            <access>read-only</access>
89            <enumeratedValues>
90              <enumeratedValue>
91                <name>notReady</name>
92                <description>Not Ready.</description>
93                <value>0</value>
94              </enumeratedValue>
95              <enumeratedValue>
96                <name>ready</name>
97                <description>Ready.</description>
98                <value>1</value>
99              </enumeratedValue>
100            </enumeratedValues>
101          </field>
102        </fields>
103      </register>
104      <register>
105        <name>INVALIDATE</name>
106        <description>Invalidate All Registers.</description>
107        <addressOffset>0x0700</addressOffset>
108        <access>read-write</access>
109        <fields>
110          <field>
111            <name>INVALID</name>
112            <description>Invalidate.</description>
113            <bitOffset>0</bitOffset>
114            <bitWidth>32</bitWidth>
115          </field>
116        </fields>
117      </register>
118    </registers>
119  </peripheral>
120  <!-- ICC: Instruction Cache Controller Registers-->
121</device>