ICC0 Instruction Cache Controller Registers 0x4002A000 0x00 0x800 registers INFO Cache ID Register. 0x0000 read-only RELNUM Release Number. Identifies the RTL release version. 0 6 PARTNUM Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. 6 4 ID Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. 10 6 SZ Memory Configuration Register. 0x0004 read-only 0x00080008 CCH Cache Size. Indicates total size in Kbytes of cache. 0 16 MEM Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. 16 16 CTRL Cache Control and Status Register. 0x0100 EN Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. 0 1 dis Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. 0 en Cache Enabled. 1 RDY Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. 16 1 read-only notReady Not Ready. 0 ready Ready. 1 INVALIDATE Invalidate All Registers. 0x0700 read-write INVALID Invalidate. 0 32