1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3  <peripheral>
4    <name>I2S</name>
5    <description>Inter-IC Sound Interface.</description>
6    <groupName>I2S</groupName>
7    <baseAddress>0x40060000</baseAddress>
8    <size>32</size>
9    <addressBlock>
10      <offset>0x00</offset>
11      <size>0x1000</size>
12      <usage>registers</usage>
13    </addressBlock>
14    <interrupt>
15      <name>I2S</name>
16      <description>I2S IRQ</description>
17      <value>99</value>
18    </interrupt>
19    <registers>
20      <register>
21        <name>CTRL0CH0</name>
22        <description>Global mode channel.</description>
23        <addressOffset>0x00</addressOffset>
24        <fields>
25          <field>
26            <name>LSB_FIRST</name>
27            <description>LSB Transmit Receive First.</description>
28            <bitRange>[1:1]</bitRange>
29            <access>read-write</access>
30          </field>
31          <field>
32            <name>CH_MODE</name>
33            <description>SCK Select.</description>
34            <bitRange>[7:6]</bitRange>
35            <access>read-write</access>
36          </field>
37          <field>
38            <name>WS_POL</name>
39            <description>WS polarity select. </description>
40            <bitRange>[8:8]</bitRange>
41            <access>read-write</access>
42          </field>
43          <field>
44            <name>MSB_LOC</name>
45            <description>MSB location. </description>
46            <bitRange>[9:9]</bitRange>
47            <access>read-only</access>
48          </field>
49          <field>
50            <name>ALIGN</name>
51            <description>Align to MSB or LSB.</description>
52            <bitRange>[10:10]</bitRange>
53            <access>read-only</access>
54          </field>
55          <field>
56            <name>EXT_SEL</name>
57            <description>External SCK/WS selection.</description>
58            <bitRange>[11:11]</bitRange>
59            <access>read-write</access>
60          </field>
61          <field>
62            <name>STEREO</name>
63            <description>Stereo mode of I2S.</description>
64            <bitRange>[13:12]</bitRange>
65            <access>read-only</access>
66          </field>
67          <field>
68            <name>WSIZE</name>
69            <description>Data size when write to FIFO.</description>
70            <bitRange>[15:14]</bitRange>
71            <access>read-write</access>
72          </field>
73          <field>
74            <name>TX_EN</name>
75            <description>TX channel enable. </description>
76            <bitRange>[16:16]</bitRange>
77            <access>read-write</access>
78          </field>
79          <field>
80            <name>RX_EN</name>
81            <description>RX channel enable. </description>
82            <bitRange>[17:17]</bitRange>
83            <access>read-write</access>
84          </field>
85          <field>
86            <name>FLUSH</name>
87            <description>Flushes the TX/RX FIFO buffer. </description>
88            <bitRange>[18:18]</bitRange>
89            <access>read-write</access>
90          </field>
91          <field>
92            <name>RST</name>
93            <description>Write 1 to reset channel. </description>
94            <bitRange>[19:19]</bitRange>
95            <access>read-write</access>
96          </field>
97          <field>
98            <name>FIFO_LSB</name>
99            <description>Bit Field Control. </description>
100            <bitRange>[20:20]</bitRange>
101            <access>read-write</access>
102          </field>
103          <field>
104            <name>RX_THD_VAL</name>
105            <description>depth of receive FIFO for threshold interrupt generation. </description>
106            <bitRange>[31:24]</bitRange>
107            <access>read-write</access>
108          </field>
109        </fields>
110      </register>
111      <register>
112        <name>CTRL1CH0</name>
113        <description>Local channel Setup.</description>
114        <addressOffset>0x10</addressOffset>
115        <fields>
116          <field>
117            <name>BITS_WORD</name>
118            <description>I2S word length.</description>
119            <bitRange>[4:0]</bitRange>
120            <access>read-write</access>
121          </field>
122          <field>
123            <name>EN</name>
124            <description>I2S clock enable.</description>
125            <bitRange>[8:8]</bitRange>
126            <access>read-write</access>
127          </field>
128          <field>
129            <name>SMP_SIZE</name>
130            <description>I2S sample size length.</description>
131            <bitRange>[13:9]</bitRange>
132            <access>read-write</access>
133          </field>
134          <field>
135            <name>ADJST</name>
136            <description>LSB/MSB Justify.</description>
137            <bitRange>[15:15]</bitRange>
138            <access>read-write</access>
139          </field>
140          <field>
141            <name>CLKDIV</name>
142            <description>I2S clock frequency divisor.</description>
143            <bitRange>[31:16]</bitRange>
144            <access>read-write</access>
145          </field>
146        </fields>
147      </register>
148      <register>
149        <name>DMACH0</name>
150        <description>DMA Control.</description>
151        <addressOffset>0x30</addressOffset>
152        <fields>
153          <field>
154            <name>DMA_TX_THD_VAL</name>
155            <description>TX FIFO Level DMA Trigger.</description>
156            <bitRange>[6:0]</bitRange>
157            <access>read-write</access>
158          </field>
159          <field>
160            <name>DMA_TX_EN</name>
161            <description>TX DMA channel enable.</description>
162            <bitRange>[7:7]</bitRange>
163            <access>read-write</access>
164          </field>
165          <field>
166            <name>DMA_RX_THD_VAL</name>
167            <description>RX FIFO Level DMA Trigger.</description>
168            <bitRange>[14:8]</bitRange>
169            <access>read-write</access>
170          </field>
171          <field>
172            <name>DMA_RX_EN</name>
173            <description>RX DMA channel enable.</description>
174            <bitRange>[15:15]</bitRange>
175            <access>read-write</access>
176          </field>
177          <field>
178            <name>TX_LVL</name>
179            <description>Number of data word in the TX FIFO.</description>
180            <bitRange>[23:16]</bitRange>
181            <access>read-write</access>
182          </field>
183          <field>
184            <name>RX_LVL</name>
185            <description>Number of data word in the RX FIFO.</description>
186            <bitRange>[31:24]</bitRange>
187            <access>read-write</access>
188          </field>
189        </fields>
190      </register>
191      <register>
192        <name>FIFOCH0</name>
193        <description>I2S Fifo.</description>
194        <addressOffset>0x40</addressOffset>
195        <fields>
196          <field>
197            <name>DATA</name>
198            <description>Load/unload location for TX and RX FIFO buffers.</description>
199            <bitRange>[31:0]</bitRange>
200            <access>read-write</access>
201          </field>
202        </fields>
203      </register>
204      <register>
205        <name>INTFL</name>
206        <description>ISR Status.</description>
207        <addressOffset>0x50</addressOffset>
208        <fields>
209          <field>
210            <name>RX_OV_CH0</name>
211            <description>Status for RX FIFO Overrun interrupt.</description>
212            <bitRange>[0:0]</bitRange>
213            <access>read-write</access>
214          </field>
215          <field>
216            <name>RX_THD_CH0</name>
217            <description>Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
218            <bitRange>[1:1]</bitRange>
219            <access>read-write</access>
220          </field>
221          <field>
222            <name>TX_OB_CH0</name>
223            <description>Status for interrupt when TX FIFO has only one byte remaining.</description>
224            <bitRange>[2:2]</bitRange>
225            <access>read-write</access>
226          </field>
227          <field>
228            <name>TX_HE_CH0</name>
229            <description>Status for interrupt when TX FIFO is half empty.</description>
230            <bitRange>[3:3]</bitRange>
231            <access>read-write</access>
232          </field>
233        </fields>
234      </register>
235      <register>
236        <name>INTEN</name>
237        <description>Interrupt Enable.</description>
238        <addressOffset>0x54</addressOffset>
239        <fields>
240          <field>
241            <name>RX_OV_CH0</name>
242            <description>Enable for RX FIFO Overrun interrupt.</description>
243            <bitRange>[0:0]</bitRange>
244            <access>read-write</access>
245          </field>
246          <field>
247            <name>RX_THD_CH0</name>
248            <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
249            <bitRange>[1:1]</bitRange>
250            <access>read-write</access>
251          </field>
252          <field>
253            <name>TX_OB_CH0</name>
254            <description>Enable for interrupt when TX FIFO has only one byte remaining.</description>
255            <bitRange>[2:2]</bitRange>
256            <access>read-write</access>
257          </field>
258          <field>
259            <name>TX_HE_CH0</name>
260            <description>Enable for interrupt when TX FIFO is half empty.</description>
261            <bitRange>[3:3]</bitRange>
262            <access>read-write</access>
263          </field>
264        </fields>
265      </register>
266      <register>
267        <name>EXTSETUP</name>
268        <description>Ext Control.</description>
269        <addressOffset>0x58</addressOffset>
270        <fields>
271          <field>
272            <name>EXT_BITS_WORD</name>
273            <description>Word Length for ch_mode.</description>
274            <bitRange>[4:0]</bitRange>
275            <access>read-write</access>
276          </field>
277        </fields>
278      </register>
279    </registers>
280  </peripheral>
281  <!-- I2S: Inter-IC Sound Interface -->
282</device>