I2S Inter-IC Sound Interface. I2S 0x40060000 32 0x00 0x1000 registers I2S I2S IRQ 99 CTRL0CH0 Global mode channel. 0x00 LSB_FIRST LSB Transmit Receive First. [1:1] read-write CH_MODE SCK Select. [7:6] read-write WS_POL WS polarity select. [8:8] read-write MSB_LOC MSB location. [9:9] read-only ALIGN Align to MSB or LSB. [10:10] read-only EXT_SEL External SCK/WS selection. [11:11] read-write STEREO Stereo mode of I2S. [13:12] read-only WSIZE Data size when write to FIFO. [15:14] read-write TX_EN TX channel enable. [16:16] read-write RX_EN RX channel enable. [17:17] read-write FLUSH Flushes the TX/RX FIFO buffer. [18:18] read-write RST Write 1 to reset channel. [19:19] read-write FIFO_LSB Bit Field Control. [20:20] read-write RX_THD_VAL depth of receive FIFO for threshold interrupt generation. [31:24] read-write CTRL1CH0 Local channel Setup. 0x10 BITS_WORD I2S word length. [4:0] read-write EN I2S clock enable. [8:8] read-write SMP_SIZE I2S sample size length. [13:9] read-write ADJST LSB/MSB Justify. [15:15] read-write CLKDIV I2S clock frequency divisor. [31:16] read-write DMACH0 DMA Control. 0x30 DMA_TX_THD_VAL TX FIFO Level DMA Trigger. [6:0] read-write DMA_TX_EN TX DMA channel enable. [7:7] read-write DMA_RX_THD_VAL RX FIFO Level DMA Trigger. [14:8] read-write DMA_RX_EN RX DMA channel enable. [15:15] read-write TX_LVL Number of data word in the TX FIFO. [23:16] read-write RX_LVL Number of data word in the RX FIFO. [31:24] read-write FIFOCH0 I2S Fifo. 0x40 DATA Load/unload location for TX and RX FIFO buffers. [31:0] read-write INTFL ISR Status. 0x50 RX_OV_CH0 Status for RX FIFO Overrun interrupt. [0:0] read-write RX_THD_CH0 Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. [1:1] read-write TX_OB_CH0 Status for interrupt when TX FIFO has only one byte remaining. [2:2] read-write TX_HE_CH0 Status for interrupt when TX FIFO is half empty. [3:3] read-write INTEN Interrupt Enable. 0x54 RX_OV_CH0 Enable for RX FIFO Overrun interrupt. [0:0] read-write RX_THD_CH0 Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. [1:1] read-write TX_OB_CH0 Enable for interrupt when TX FIFO has only one byte remaining. [2:2] read-write TX_HE_CH0 Enable for interrupt when TX FIFO is half empty. [3:3] read-write EXTSETUP Ext Control. 0x58 EXT_BITS_WORD Word Length for ch_mode. [4:0] read-write