1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>HTMR</name> 5 <description>High Speed Timer Module.</description> 6 <baseAddress>0x4001B000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0xFFF</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>HTimer</name> 14 <description>HTimer interrupt.</description> 15 <value>93</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>LNICNT</name> 20 <description>HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter.</description> 21 <addressOffset>0x00</addressOffset> 22 <resetMask>0x00000000</resetMask> 23 <fields> 24 <field> 25 <name>CNT</name> 26 <description>HTimer Long Interval Counter.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 </field> 30 </fields> 31 </register> 32 <register> 33 <name>SHICNT</name> 34 <description>HTimer Short Interval Counter. This counter ticks every t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00.</description> 35 <addressOffset>0x04</addressOffset> 36 <resetMask>0x00000000</resetMask> 37 <fields> 38 <field> 39 <name>CNT</name> 40 <description>HTimer Short Interval Counter.</description> 41 <bitOffset>0</bitOffset> 42 <bitWidth>8</bitWidth> 43 </field> 44 </fields> 45 </register> 46 <register> 47 <name>LNIALM</name> 48 <description>HTimer Long Interval Alarm Value Register.</description> 49 <addressOffset>0x08</addressOffset> 50 <resetMask>0x00000000</resetMask> 51 <fields> 52 <field> 53 <name>ALM</name> 54 <description>HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0]</description> 55 <bitOffset>0</bitOffset> 56 <bitWidth>20</bitWidth> 57 </field> 58 </fields> 59 </register> 60 <register> 61 <name>SHIALM</name> 62 <description>HTimer Short Interval Alarm Value Register.</description> 63 <addressOffset>0x0C</addressOffset> 64 <resetMask>0x00000000</resetMask> 65 <fields> 66 <field> 67 <name>ALM</name> 68 <description>This register contains the reload value for the short interval alarm.</description> 69 <bitOffset>0</bitOffset> 70 <bitWidth>32</bitWidth> 71 </field> 72 </fields> 73 </register> 74 <register> 75 <name>CTRL</name> 76 <description>HTimer Control Register.</description> 77 <addressOffset>0x10</addressOffset> 78 <resetValue>0x00000008</resetValue> 79 <resetMask>0xFFFFFF38</resetMask> 80 <fields> 81 <field> 82 <name>EN</name> 83 <description>HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 84 <bitOffset>0</bitOffset> 85 <bitWidth>1</bitWidth> 86 <enumeratedValues> 87 <enumeratedValue> 88 <name>dis</name> 89 <description>Disable.</description> 90 <value>0</value> 91 </enumeratedValue> 92 <enumeratedValue> 93 <name>en</name> 94 <description>Enable.</description> 95 <value>1</value> 96 </enumeratedValue> 97 </enumeratedValues> 98 </field> 99 <field> 100 <name>LONG_ALM_IE</name> 101 <description>Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 102 <bitOffset>1</bitOffset> 103 <bitWidth>1</bitWidth> 104 <enumeratedValues> 105 <enumeratedValue> 106 <name>dis</name> 107 <description>Disable.</description> 108 <value>0</value> 109 </enumeratedValue> 110 <enumeratedValue> 111 <name>en</name> 112 <description>Enable.</description> 113 <value>1</value> 114 </enumeratedValue> 115 </enumeratedValues> 116 </field> 117 <field> 118 <name>SHORT_ALM_IE</name> 119 <description>Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 120 <bitOffset>2</bitOffset> 121 <bitWidth>1</bitWidth> 122 <enumeratedValues> 123 <enumeratedValue> 124 <name>dis</name> 125 <description>Disable.</description> 126 <value>0</value> 127 </enumeratedValue> 128 <enumeratedValue> 129 <name>en</name> 130 <description>Enable.</description> 131 <value>1</value> 132 </enumeratedValue> 133 </enumeratedValues> 134 </field> 135 <field> 136 <name>BUSY</name> 137 <description>HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.</description> 138 <bitOffset>3</bitOffset> 139 <bitWidth>1</bitWidth> 140 <access>read-only</access> 141 <enumeratedValues> 142 <enumeratedValue> 143 <name>idle</name> 144 <description>Idle.</description> 145 <value>0</value> 146 </enumeratedValue> 147 <enumeratedValue> 148 <name>busy</name> 149 <description>Busy.</description> 150 <value>1</value> 151 </enumeratedValue> 152 </enumeratedValues> 153 </field> 154 <field> 155 <name>RDY</name> 156 <description>HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register.</description> 157 <bitOffset>4</bitOffset> 158 <bitWidth>1</bitWidth> 159 <enumeratedValues> 160 <enumeratedValue> 161 <name>busy</name> 162 <description>Register has not updated.</description> 163 <value>0</value> 164 </enumeratedValue> 165 <enumeratedValue> 166 <name>ready</name> 167 <description>Ready.</description> 168 <value>1</value> 169 </enumeratedValue> 170 </enumeratedValues> 171 </field> 172 <field> 173 <name>RDY_IE</name> 174 <description>HTimer Ready Interrupt Enable.</description> 175 <bitOffset>5</bitOffset> 176 <bitWidth>1</bitWidth> 177 <enumeratedValues> 178 <enumeratedValue> 179 <name>dis</name> 180 <description>Disable.</description> 181 <value>0</value> 182 </enumeratedValue> 183 <enumeratedValue> 184 <name>en</name> 185 <description>Enable.</description> 186 <value>1</value> 187 </enumeratedValue> 188 </enumeratedValues> 189 </field> 190 <field> 191 <name>LONG_ALM_IF</name> 192 <description>Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 193 <bitOffset>6</bitOffset> 194 <bitWidth>1</bitWidth> 195 <access>read-only</access> 196 <enumeratedValues> 197 <enumeratedValue> 198 <name>inactive</name> 199 <description>Not active.</description> 200 <value>0</value> 201 </enumeratedValue> 202 <enumeratedValue> 203 <name>pending</name> 204 <description>Active.</description> 205 <value>1</value> 206 </enumeratedValue> 207 </enumeratedValues> 208 </field> 209 <field> 210 <name>SHORT_ALM_IF</name> 211 <description>Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 212 <bitOffset>7</bitOffset> 213 <bitWidth>1</bitWidth> 214 <access>read-only</access> 215 <enumeratedValues> 216 <enumeratedValue> 217 <name>inactive</name> 218 <description>Not active.</description> 219 <value>0</value> 220 </enumeratedValue> 221 <enumeratedValue> 222 <name>Pending</name> 223 <description>Active.</description> 224 <value>1</value> 225 </enumeratedValue> 226 </enumeratedValues> 227 </field> 228 <field> 229 <name>WR_EN</name> 230 <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits.</description> 231 <bitOffset>15</bitOffset> 232 <bitWidth>1</bitWidth> 233 <enumeratedValues> 234 <enumeratedValue> 235 <name>dis</name> 236 <description>Not active.</description> 237 <value>0</value> 238 </enumeratedValue> 239 <enumeratedValue> 240 <name>en</name> 241 <description>.</description> 242 <value>1</value> 243 </enumeratedValue> 244 </enumeratedValues> 245 </field> 246 </fields> 247 </register> 248 <register> 249 <name>TRIM</name> 250 <description>HTimer Trim Register.</description> 251 <addressOffset>0x14</addressOffset> 252 <resetMask>0x00000000</resetMask> 253 <fields> 254 <field> 255 <name>TRIM</name> 256 <description>HTimer Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.</description> 257 <bitOffset>0</bitOffset> 258 <bitWidth>8</bitWidth> 259 </field> 260 <field> 261 <name>VBAT_TMR</name> 262 <description>VBAT Timer Value. When HTimer is running off of VBAT, this field is incremented every 32 seconds.</description> 263 <bitOffset>8</bitOffset> 264 <bitWidth>24</bitWidth> 265 </field> 266 </fields> 267 </register> 268 <register> 269 <name>OSCCTRL</name> 270 <description>HTimer Oscillator Control Register.</description> 271 <addressOffset>0x18</addressOffset> 272 <resetMask>0x00000000</resetMask> 273 <fields> 274 <field> 275 <name>FILTER_EN</name> 276 <description>Enable Filter.</description> 277 <bitOffset>0</bitOffset> 278 <bitWidth>1</bitWidth> 279 </field> 280 <field> 281 <name>IBIAS_SEL</name> 282 <description>IBIAS Select.</description> 283 <bitOffset>1</bitOffset> 284 <bitWidth>1</bitWidth> 285 <enumeratedValues> 286 <enumeratedValue> 287 <name>2x</name> 288 <description>2x</description> 289 <value>0</value> 290 </enumeratedValue> 291 <enumeratedValue> 292 <name>4x</name> 293 <description>4x</description> 294 <value>1</value> 295 </enumeratedValue> 296 </enumeratedValues> 297 </field> 298 <field> 299 <name>HYST_EN</name> 300 <description>HTimer Hysteresis Enable.</description> 301 <bitOffset>2</bitOffset> 302 <bitWidth>1</bitWidth> 303 </field> 304 <field> 305 <name>IBIAS_EN</name> 306 <description>HTimer IBIAS Enable.</description> 307 <bitOffset>3</bitOffset> 308 <bitWidth>1</bitWidth> 309 </field> 310 <field> 311 <name>BYPASS</name> 312 <description>HTimer Crystal Bypass</description> 313 <bitOffset>4</bitOffset> 314 <bitWidth>1</bitWidth> 315 <enumeratedValues> 316 <enumeratedValue> 317 <name>dis</name> 318 <description>Disable.</description> 319 <value>0</value> 320 </enumeratedValue> 321 <enumeratedValue> 322 <name>en</name> 323 <description>Enable.</description> 324 <value>1</value> 325 </enumeratedValue> 326 </enumeratedValues> 327 </field> 328 <field> 329 <name>SQW_32K</name> 330 <description>HTimer 32kHz Square Wave Output</description> 331 <bitOffset>5</bitOffset> 332 <bitWidth>1</bitWidth> 333 <enumeratedValues> 334 <enumeratedValue> 335 <name>dis</name> 336 <description>Disable.</description> 337 <value>0</value> 338 </enumeratedValue> 339 <enumeratedValue> 340 <name>en</name> 341 <description>Enable.</description> 342 <value>1</value> 343 </enumeratedValue> 344 </enumeratedValues> 345 </field> 346 </fields> 347 </register> 348 </registers> 349 </peripheral> 350 <!-- HTIMER : 351 High Speed Timer and Alarm--> 352</device>
