HTMR High Speed Timer Module. 0x4001B000 0x00 0xFFF registers HTimer HTimer interrupt. 93 LNICNT HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter. 0x00 0x00000000 CNT HTimer Long Interval Counter. 0 32 SHICNT HTimer Short Interval Counter. This counter ticks every t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 CNT HTimer Short Interval Counter. 0 8 LNIALM HTimer Long Interval Alarm Value Register. 0x08 0x00000000 ALM HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0] 0 20 SHIALM HTimer Short Interval Alarm Value Register. 0x0C 0x00000000 ALM This register contains the reload value for the short interval alarm. 0 32 CTRL HTimer Control Register. 0x10 0x00000008 0xFFFFFF38 EN HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 LONG_ALM_IE Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 SHORT_ALM_IE Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 RDY HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register. 4 1 busy Register has not updated. 0 ready Ready. 1 RDY_IE HTimer Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 LONG_ALM_IF Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active. 0 pending Active. 1 SHORT_ALM_IF Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active. 0 Pending Active. 1 WR_EN Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits. 15 1 dis Not active. 0 en . 1 TRIM HTimer Trim Register. 0x14 0x00000000 TRIM HTimer Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. 0 8 VBAT_TMR VBAT Timer Value. When HTimer is running off of VBAT, this field is incremented every 32 seconds. 8 24 OSCCTRL HTimer Oscillator Control Register. 0x18 0x00000000 FILTER_EN Enable Filter. 0 1 IBIAS_SEL IBIAS Select. 1 1 2x 2x 0 4x 4x 1 HYST_EN HTimer Hysteresis Enable. 2 1 IBIAS_EN HTimer IBIAS Enable. 3 1 BYPASS HTimer Crystal Bypass 4 1 dis Disable. 0 en Enable. 1 SQW_32K HTimer 32kHz Square Wave Output 5 1 dis Disable. 0 en Enable. 1