1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>HPB</name> 5 <description>HyperBus Memory Controller</description> 6 <baseAddress>0x40039000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>HPB</name> 14 <description>HPB interrupt.</description> 15 <value>61</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>STATUS</name> 20 <description>HPB Status Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <resetMask>0x00000000</resetMask> 23 <fields> 24 <field> 25 <name>RACT</name> 26 <description>Read transaction in progress.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 <enumeratedValues> 30 <enumeratedValue> 31 <name>noRead</name> 32 <description>No read transaction in progress.</description> 33 <value>0</value> 34 </enumeratedValue> 35 <enumeratedValue> 36 <name>read</name> 37 <description>Read transaction in progress.</description> 38 <value>1</value> 39 </enumeratedValue> 40 </enumeratedValues> 41 </field> 42 <field> 43 <name>RDECERR</name> 44 <description>Read address error.</description> 45 <bitOffset>8</bitOffset> 46 <bitWidth>1</bitWidth> 47 <enumeratedValues> 48 <enumeratedValue> 49 <name>noErr</name> 50 <description>No error.</description> 51 <value>0</value> 52 </enumeratedValue> 53 <enumeratedValue> 54 <name>err</name> 55 <description>Error.</description> 56 <value>1</value> 57 </enumeratedValue> 58 </enumeratedValues> 59 </field> 60 <field> 61 <name>RRSTOERR</name> 62 <description>Reset during read error.</description> 63 <bitOffset>10</bitOffset> 64 <bitWidth>1</bitWidth> 65 <enumeratedValues> 66 <enumeratedValue> 67 <name>noErr</name> 68 <description>No error.</description> 69 <value>0</value> 70 </enumeratedValue> 71 <enumeratedValue> 72 <name>err</name> 73 <description>Error.</description> 74 <value>1</value> 75 </enumeratedValue> 76 </enumeratedValues> 77 </field> 78 <field> 79 <name>RDSSTALL</name> 80 <description>Read data stall.</description> 81 <bitOffset>11</bitOffset> 82 <bitWidth>1</bitWidth> 83 <enumeratedValues> 84 <enumeratedValue> 85 <name>normalop</name> 86 <description>Read operation normal.</description> 87 <value>0</value> 88 </enumeratedValue> 89 <enumeratedValue> 90 <name>stalled</name> 91 <description>Read stalled.</description> 92 <value>1</value> 93 </enumeratedValue> 94 </enumeratedValues> 95 </field> 96 <field> 97 <name>WACT</name> 98 <description>Write transaction in progress.</description> 99 <bitOffset>16</bitOffset> 100 <bitWidth>1</bitWidth> 101 <enumeratedValues> 102 <enumeratedValue> 103 <name>noWrite</name> 104 <description>No write transaction in progress.</description> 105 <value>0</value> 106 </enumeratedValue> 107 <enumeratedValue> 108 <name>write</name> 109 <description>Write transaction in progress.</description> 110 <value>1</value> 111 </enumeratedValue> 112 </enumeratedValues> 113 </field> 114 <field> 115 <name>WDECERR</name> 116 <description>Write address error.</description> 117 <bitOffset>24</bitOffset> 118 <bitWidth>1</bitWidth> 119 <enumeratedValues> 120 <enumeratedValue> 121 <name>noErr</name> 122 <description>No error.</description> 123 <value>0</value> 124 </enumeratedValue> 125 <enumeratedValue> 126 <name>err</name> 127 <description>Error.</description> 128 <value>1</value> 129 </enumeratedValue> 130 </enumeratedValues> 131 </field> 132 <field> 133 <name>WRSTOERR</name> 134 <description>Reset during write error.</description> 135 <bitOffset>26</bitOffset> 136 <bitWidth>1</bitWidth> 137 <enumeratedValues> 138 <enumeratedValue> 139 <name>noErr</name> 140 <description>No error.</description> 141 <value>0</value> 142 </enumeratedValue> 143 <enumeratedValue> 144 <name>err</name> 145 <description>Error.</description> 146 <value>1</value> 147 </enumeratedValue> 148 </enumeratedValues> 149 </field> 150 </fields> 151 </register> 152 <register> 153 <name>INTEN</name> 154 <description>HPB Interrupt Enable.</description> 155 <addressOffset>0x04</addressOffset> 156 <resetMask>0x00000000</resetMask> 157 <fields> 158 <field> 159 <name>ERRINTE</name> 160 <description>Error interrupt enable.</description> 161 <bitOffset>1</bitOffset> 162 <bitWidth>1</bitWidth> 163 <enumeratedValues> 164 <enumeratedValue> 165 <name>dis</name> 166 <description>Disable error interrupt.</description> 167 <value>0</value> 168 </enumeratedValue> 169 <enumeratedValue> 170 <name>en</name> 171 <description>Enable error interrupt.</description> 172 <value>1</value> 173 </enumeratedValue> 174 </enumeratedValues> 175 </field> 176 </fields> 177 </register> 178 <register> 179 <name>INTFL</name> 180 <description>HPB Interrupt Status Flags.</description> 181 <addressOffset>0x08</addressOffset> 182 <resetMask>0x00000000</resetMask> 183 <fields> 184 <field> 185 <name>ERRINT</name> 186 <description>Error interrupt status flags.</description> 187 <bitOffset>1</bitOffset> 188 <bitWidth>1</bitWidth> 189 <enumeratedValues> 190 <enumeratedValue> 191 <name>noInt</name> 192 <description>No interrupt pending.</description> 193 <value>0</value> 194 </enumeratedValue> 195 <enumeratedValue> 196 <name>pending</name> 197 <description>Error interrupt pending.</description> 198 <value>1</value> 199 </enumeratedValue> 200 </enumeratedValues> 201 </field> 202 </fields> 203 </register> 204 <register> 205 <dim>2</dim> 206 <dimIncrement>4</dimIncrement> 207 <name>MBR[%s]</name> 208 <description>HPB Memory Base Address.</description> 209 <addressOffset>0x10</addressOffset> 210 <resetMask>0x00000000</resetMask> 211 <fields> 212 <field> 213 <name>ADDR</name> 214 <description>Memory Base Address.</description> 215 <bitOffset>24</bitOffset> 216 <bitWidth>8</bitWidth> 217 </field> 218 </fields> 219 </register> 220 <register> 221 <dim>2</dim> 222 <dimIncrement>4</dimIncrement> 223 <name>MCR[%s]</name> 224 <description>HPB Memory Configuration Register.</description> 225 <addressOffset>0x20</addressOffset> 226 <resetMask>0x00000000</resetMask> 227 <fields> 228 <field> 229 <name>DEV_TYPE</name> 230 <description>Memory device type select.</description> 231 <bitOffset>3</bitOffset> 232 <bitWidth>2</bitWidth> 233 <enumeratedValues> 234 <enumeratedValue> 235 <name>hyperFlash</name> 236 <description>HyperFlash.</description> 237 <value>0</value> 238 </enumeratedValue> 239 <enumeratedValue> 240 <name>xccelaPSRAM</name> 241 <description>Xccela PSRAM.</description> 242 <value>1</value> 243 </enumeratedValue> 244 <enumeratedValue> 245 <name>hyperRAM</name> 246 <description>HyperRAM.</description> 247 <value>2</value> 248 </enumeratedValue> 249 </enumeratedValues> 250 </field> 251 <field> 252 <name>CRT</name> 253 <description>Configuration register target select.</description> 254 <bitOffset>5</bitOffset> 255 <bitWidth>1</bitWidth> 256 <enumeratedValues> 257 <enumeratedValue> 258 <name>mem_space</name> 259 <description>Access memory space.</description> 260 <value>0</value> 261 </enumeratedValue> 262 <enumeratedValue> 263 <name>config_reg_space</name> 264 <description>Access configuration register space.</description> 265 <value>1</value> 266 </enumeratedValue> 267 </enumeratedValues> 268 </field> 269 <field> 270 <name>READ_LATENCY</name> 271 <description>Xccela fixed read latency enable.</description> 272 <bitOffset>6</bitOffset> 273 <bitWidth>1</bitWidth> 274 <enumeratedValues> 275 <enumeratedValue> 276 <name>variable</name> 277 <description>Variable read latency.</description> 278 <value>0</value> 279 </enumeratedValue> 280 <enumeratedValue> 281 <name>fixed</name> 282 <description>Fixed read latency.</description> 283 <value>1</value> 284 </enumeratedValue> 285 </enumeratedValues> 286 </field> 287 <field> 288 <name>HSE</name> 289 <description>Xccela half sleep exit.</description> 290 <bitOffset>7</bitOffset> 291 <bitWidth>1</bitWidth> 292 <enumeratedValues> 293 <enumeratedValue> 294 <name>dis</name> 295 <description>Half-Sleep exit disabled.</description> 296 <value>0</value> 297 </enumeratedValue> 298 <enumeratedValue> 299 <name>en</name> 300 <description>Half-Sleep exit enabled.</description> 301 <value>1</value> 302 </enumeratedValue> 303 </enumeratedValues> 304 </field> 305 <field> 306 <name>MAXLEN</name> 307 <description>Maximum read/write..</description> 308 <bitOffset>18</bitOffset> 309 <bitWidth>9</bitWidth> 310 </field> 311 <field> 312 <name>MAXLEN_EN</name> 313 <description>Maximum CS# length enable.</description> 314 <bitOffset>31</bitOffset> 315 <bitWidth>1</bitWidth> 316 <enumeratedValues> 317 <enumeratedValue> 318 <name>dis</name> 319 <description>Configurable CS# low time disabled.</description> 320 <value>0</value> 321 </enumeratedValue> 322 <enumeratedValue> 323 <name>en</name> 324 <description>Configurable CS# low time enabled.</description> 325 <value>1</value> 326 </enumeratedValue> 327 </enumeratedValues> 328 </field> 329 </fields> 330 </register> 331 <register> 332 <dim>2</dim> 333 <dimIncrement>4</dimIncrement> 334 <name>MTR[%s]</name> 335 <description>HPB Memory Timing Register.</description> 336 <addressOffset>0x30</addressOffset> 337 <resetMask>0x00000000</resetMask> 338 <fields> 339 <field> 340 <name>LATENCY</name> 341 <description>RAM Latency Clock Cycles.</description> 342 <bitOffset>0</bitOffset> 343 <bitWidth>4</bitWidth> 344 <enumeratedValues> 345 <enumeratedValue> 346 <name>5CLK</name> 347 <description>5 clock cycles.</description> 348 <value>0</value> 349 </enumeratedValue> 350 <enumeratedValue> 351 <name>6CLK</name> 352 <description>6 clock cycles.</description> 353 <value>1</value> 354 </enumeratedValue> 355 <enumeratedValue> 356 <name>3CLK</name> 357 <description>3 clock cycles.</description> 358 <value>14</value> 359 </enumeratedValue> 360 <enumeratedValue> 361 <name>4CLK</name> 362 <description>4 clock cycles.</description> 363 <value>15</value> 364 </enumeratedValue> 365 </enumeratedValues> 366 </field> 367 <field> 368 <name>WCSH</name> 369 <description>Write chip select hold after CK falling edge.</description> 370 <bitOffset>8</bitOffset> 371 <bitWidth>4</bitWidth> 372 </field> 373 <field> 374 <name>RCSH</name> 375 <description>Read chip select hold after CK falling edge.</description> 376 <bitOffset>12</bitOffset> 377 <bitWidth>4</bitWidth> 378 </field> 379 <field> 380 <name>WCSS</name> 381 <description>Write chip select setup time to next CK rising edge.</description> 382 <bitOffset>16</bitOffset> 383 <bitWidth>4</bitWidth> 384 </field> 385 <field> 386 <name>RCSS</name> 387 <description>Read chip select setup time to next CK rising edge.</description> 388 <bitOffset>20</bitOffset> 389 <bitWidth>4</bitWidth> 390 </field> 391 <field> 392 <name>WCSHI</name> 393 <description>Write chip select high between operations.</description> 394 <bitOffset>24</bitOffset> 395 <bitWidth>4</bitWidth> 396 </field> 397 <field> 398 <name>RCSHI</name> 399 <description>Read chip select high between operations.</description> 400 <bitOffset>28</bitOffset> 401 <bitWidth>4</bitWidth> 402 </field> 403 </fields> 404 </register> 405 </registers> 406 </peripheral> 407 <!-- HPB :HyperBus Memory Controller --> 408</device>
