HPB HyperBus Memory Controller 0x40039000 0x00 0x1000 registers HPB HPB interrupt. 61 STATUS HPB Status Register. 0x00 0x00000000 RACT Read transaction in progress. 0 1 noRead No read transaction in progress. 0 read Read transaction in progress. 1 RDECERR Read address error. 8 1 noErr No error. 0 err Error. 1 RRSTOERR Reset during read error. 10 1 noErr No error. 0 err Error. 1 RDSSTALL Read data stall. 11 1 normalop Read operation normal. 0 stalled Read stalled. 1 WACT Write transaction in progress. 16 1 noWrite No write transaction in progress. 0 write Write transaction in progress. 1 WDECERR Write address error. 24 1 noErr No error. 0 err Error. 1 WRSTOERR Reset during write error. 26 1 noErr No error. 0 err Error. 1 INTEN HPB Interrupt Enable. 0x04 0x00000000 ERRINTE Error interrupt enable. 1 1 dis Disable error interrupt. 0 en Enable error interrupt. 1 INTFL HPB Interrupt Status Flags. 0x08 0x00000000 ERRINT Error interrupt status flags. 1 1 noInt No interrupt pending. 0 pending Error interrupt pending. 1 2 4 MBR[%s] HPB Memory Base Address. 0x10 0x00000000 ADDR Memory Base Address. 24 8 2 4 MCR[%s] HPB Memory Configuration Register. 0x20 0x00000000 DEV_TYPE Memory device type select. 3 2 hyperFlash HyperFlash. 0 xccelaPSRAM Xccela PSRAM. 1 hyperRAM HyperRAM. 2 CRT Configuration register target select. 5 1 mem_space Access memory space. 0 config_reg_space Access configuration register space. 1 READ_LATENCY Xccela fixed read latency enable. 6 1 variable Variable read latency. 0 fixed Fixed read latency. 1 HSE Xccela half sleep exit. 7 1 dis Half-Sleep exit disabled. 0 en Half-Sleep exit enabled. 1 MAXLEN Maximum read/write.. 18 9 MAXLEN_EN Maximum CS# length enable. 31 1 dis Configurable CS# low time disabled. 0 en Configurable CS# low time enabled. 1 2 4 MTR[%s] HPB Memory Timing Register. 0x30 0x00000000 LATENCY RAM Latency Clock Cycles. 0 4 5CLK 5 clock cycles. 0 6CLK 6 clock cycles. 1 3CLK 3 clock cycles. 14 4CLK 4 clock cycles. 15 WCSH Write chip select hold after CK falling edge. 8 4 RCSH Read chip select hold after CK falling edge. 12 4 WCSS Write chip select setup time to next CK rising edge. 16 4 RCSS Read chip select setup time to next CK rising edge. 20 4 WCSHI Write chip select high between operations. 24 4 RCSHI Read chip select high between operations. 28 4