1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>HPB</name> 5 <description>HyperBus Memory Controller Registers</description> 6 <baseAddress>0x40039000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>STAT</name> 15 <description>Hyperbus Status Register.</description> 16 <addressOffset>0x0000</addressOffset> 17 <fields> 18 <field> 19 <name>RDTXN</name> 20 <description>Read Transaction in Progress</description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>1</bitWidth> 23 <enumeratedValues> 24 <enumeratedValue> 25 <name>noread</name> 26 <description>No read transaction currently in progress.</description> 27 <value>0</value> 28 </enumeratedValue> 29 <enumeratedValue> 30 <name>read</name> 31 <description>Read transaction currently in progress.</description> 32 <value>1</value> 33 </enumeratedValue> 34 </enumeratedValues> 35 </field> 36 <field> 37 <name>RDADDRERR</name> 38 <description>Read Address Error</description> 39 <bitOffset>8</bitOffset> 40 <bitWidth>1</bitWidth> 41 <enumeratedValues> 42 <enumeratedValue> 43 <name>normal_op</name> 44 <description>No error.</description> 45 <value>0</value> 46 </enumeratedValue> 47 <enumeratedValue> 48 <name>err</name> 49 <description>External read address not responding.</description> 50 <value>1</value> 51 </enumeratedValue> 52 </enumeratedValues> 53 </field> 54 <field> 55 <name>RDSLVST</name> 56 <description>Read Slave Status.</description> 57 <bitOffset>9</bitOffset> 58 <bitWidth>1</bitWidth> 59 </field> 60 <field> 61 <name>RDRSTERR</name> 62 <description>Reset During Read Error. If this field is set a reset orrcured during a read.</description> 63 <bitOffset>10</bitOffset> 64 <bitWidth>1</bitWidth> 65 <enumeratedValues> 66 <enumeratedValue> 67 <name>normal_op</name> 68 <description>No error.</description> 69 <value>0</value> 70 </enumeratedValue> 71 <enumeratedValue> 72 <name>err</name> 73 <description>Memory controller was reset during read operation.</description> 74 <value>1</value> 75 </enumeratedValue> 76 </enumeratedValues> 77 </field> 78 <field> 79 <name>RDSTALL</name> 80 <description>Read Data Stall.</description> 81 <bitOffset>11</bitOffset> 82 <bitWidth>1</bitWidth> 83 <enumeratedValues> 84 <enumeratedValue> 85 <name>normal_op</name> 86 <description>Memory Controller operating normally.</description> 87 <value>0</value> 88 </enumeratedValue> 89 <enumeratedValue> 90 <name>stalled</name> 91 <description>Read transaction is stalled because RDS is low (stalled).</description> 92 <value>1</value> 93 </enumeratedValue> 94 </enumeratedValues> 95 </field> 96 <field> 97 <name>WRTXN</name> 98 <description>Write Transaction in Progress</description> 99 <bitOffset>16</bitOffset> 100 <bitWidth>1</bitWidth> 101 <enumeratedValues> 102 <enumeratedValue> 103 <name>nowrite</name> 104 <description>No write transaction currently in progress.</description> 105 <value>0</value> 106 </enumeratedValue> 107 <enumeratedValue> 108 <name>write</name> 109 <description>Write transaction currently in progress.</description> 110 <value>1</value> 111 </enumeratedValue> 112 </enumeratedValues> 113 </field> 114 <field> 115 <name>WRADDRERR</name> 116 <description>Write Address Error. If this field is set a write address error orrcured.</description> 117 <bitOffset>24</bitOffset> 118 <bitWidth>1</bitWidth> 119 <enumeratedValues> 120 <enumeratedValue> 121 <name>normal_op</name> 122 <description>No error.</description> 123 <value>0</value> 124 </enumeratedValue> 125 <enumeratedValue> 126 <name>err</name> 127 <description>The write address to external memory is invalid.</description> 128 <value>1</value> 129 </enumeratedValue> 130 </enumeratedValues> 131 </field> 132 <field> 133 <name>WRRSTERR</name> 134 <description>Reset During Write Error. If this field is set a reset orrcured during a write.</description> 135 <bitOffset>26</bitOffset> 136 <bitWidth>1</bitWidth> 137 <enumeratedValues> 138 <enumeratedValue> 139 <name>normal_op</name> 140 <description>No error.</description> 141 <value>0</value> 142 </enumeratedValue> 143 <enumeratedValue> 144 <name>err</name> 145 <description>Memory controller was reset during write operation.</description> 146 <value>1</value> 147 </enumeratedValue> 148 </enumeratedValues> 149 </field> 150 </fields> 151 </register> 152 <register> 153 <name>INTEN</name> 154 <description>Hyperbus Interrupt Enable Register.</description> 155 <addressOffset>0x0004</addressOffset> 156 <fields> 157 <field> 158 <name>MEM</name> 159 <description>Hyperbus Memory Interrupt Enable.</description> 160 <bitOffset>0</bitOffset> 161 <bitWidth>1</bitWidth> 162 <enumeratedValues> 163 <enumeratedValue> 164 <name>dis</name> 165 <description>Disable interrupt.</description> 166 <value>0</value> 167 </enumeratedValue> 168 <enumeratedValue> 169 <name>en</name> 170 <description>Enable interrupt.</description> 171 <value>1</value> 172 </enumeratedValue> 173 </enumeratedValues> 174 </field> 175 <field> 176 <name>ERR</name> 177 <description>Enables/disables the HPB error interrupt.</description> 178 <bitOffset>1</bitOffset> 179 <bitWidth>1</bitWidth> 180 <enumeratedValues> 181 <enumeratedValue> 182 <name>dis</name> 183 <description>Disable error interrupt.</description> 184 <value>0</value> 185 </enumeratedValue> 186 <enumeratedValue> 187 <name>en</name> 188 <description>Enable error interrupt.</description> 189 <value>1</value> 190 </enumeratedValue> 191 </enumeratedValues> 192 </field> 193 </fields> 194 </register> 195 <register> 196 <name>INTFL</name> 197 <description>Hyperbus Interrupt Flag Register.</description> 198 <addressOffset>0x0008</addressOffset> 199 <fields> 200 <field> 201 <name>MEM</name> 202 <description>Hyperbus Memory Status Flag.</description> 203 <bitOffset>0</bitOffset> 204 <bitWidth>1</bitWidth> 205 <enumeratedValues> 206 <enumeratedValue> 207 <name>noint</name> 208 <description>Memory interrupt not active.</description> 209 <value>0</value> 210 </enumeratedValue> 211 <enumeratedValue> 212 <name>pending</name> 213 <description>Memory interrupt currently pending.</description> 214 <value>1</value> 215 </enumeratedValue> 216 </enumeratedValues> 217 </field> 218 <field> 219 <name>ERR</name> 220 <description>Error interrupt status flag.</description> 221 <bitOffset>1</bitOffset> 222 <bitWidth>1</bitWidth> 223 <enumeratedValues> 224 <enumeratedValue> 225 <name>noint</name> 226 <description>Error interrupt not active.</description> 227 <value>0</value> 228 </enumeratedValue> 229 <enumeratedValue> 230 <name>pending</name> 231 <description>Error interrupt currently pending.</description> 232 <value>1</value> 233 </enumeratedValue> 234 </enumeratedValues> 235 </field> 236 </fields> 237 </register> 238 <register> 239 <dim>2</dim> 240 <dimIncrement>4</dimIncrement> 241 <name>MEMBADDR[%s]</name> 242 <description>Hyperbus Memory Base Address Register.</description> 243 <addressOffset>0x0010</addressOffset> 244 <fields> 245 <field> 246 <name>ADDR</name> 247 <description>Memory base address. This sets the base address of the addressable memory region where the port is mapped. Each address space is 512Mbytes. The lower 24 bits are read only and will always read 0.</description> 248 <bitOffset>0</bitOffset> 249 <bitWidth>32</bitWidth> 250 </field> 251 </fields> 252 </register> 253 <register> 254 <dim>2</dim> 255 <dimIncrement>4</dimIncrement> 256 <name>MEMCTRL[%s]</name> 257 <description>Hyperbus Memory Control Register.</description> 258 <addressOffset>0x0020</addressOffset> 259 <fields> 260 <field> 261 <name>WRAPSIZE</name> 262 <description>The wrap burst length of HyperBus memory. This bit is 263ignored when the asymmetry cache support bit is 0. When 264the asymmetry cache support is 1, this bit should be set the 265same as wrap size of configuration register in HyperBus 266memory. 267</description> 268 <bitOffset>0</bitOffset> 269 <bitWidth>2</bitWidth> 270 <enumeratedValues> 271 <enumeratedValue> 272 <name>64B</name> 273 <description>64 bytes</description> 274 <value>1</value> 275 </enumeratedValue> 276 <enumeratedValue> 277 <name>16B</name> 278 <description>16 bytes</description> 279 <value>2</value> 280 </enumeratedValue> 281 <enumeratedValue> 282 <name>32B</name> 283 <description>32 bytes</description> 284 <value>3</value> 285 </enumeratedValue> 286 </enumeratedValues> 287 </field> 288 <field> 289 <name>DEVTYPE</name> 290 <description>Select the memory device type.</description> 291 <bitOffset>3</bitOffset> 292 <bitWidth>2</bitWidth> 293 <enumeratedValues> 294 <enumeratedValue> 295 <name>hyperFlash</name> 296 <description>HyperFlash</description> 297 <value>0</value> 298 </enumeratedValue> 299 <enumeratedValue> 300 <name>xccela_psram</name> 301 <description>Xccela PSRAM</description> 302 <value>1</value> 303 </enumeratedValue> 304 <enumeratedValue> 305 <name>hyperRAM</name> 306 <description>HyperRAM</description> 307 <value>2</value> 308 </enumeratedValue> 309 </enumeratedValues> 310 </field> 311 <field> 312 <name>CRT</name> 313 <description>Configuration Register Target Select. For HyperRAM and Xccela Bus devices, this field selects between read/write target being the devices memory map or configuration register space. For HyperFlash set this field to 0.</description> 314 <bitOffset>5</bitOffset> 315 <bitWidth>1</bitWidth> 316 <enumeratedValues> 317 <enumeratedValue> 318 <name>mem_space</name> 319 <description>Access Memory space.</description> 320 <value>0</value> 321 </enumeratedValue> 322 <enumeratedValue> 323 <name>config_reg</name> 324 <description>Access Configuration Register space.</description> 325 <value>1</value> 326 </enumeratedValue> 327 </enumeratedValues> 328 </field> 329 <field> 330 <name>RDLAT_EN</name> 331 <description>Xccela Fixed Read Latency Enable. Set this bit to enable Xccela bus Fixed Read Latency. Set this field to match the latency Type configuration in the target PSRAM.</description> 332 <bitOffset>6</bitOffset> 333 <bitWidth>1</bitWidth> 334 <enumeratedValues> 335 <enumeratedValue> 336 <name>variable</name> 337 <description>Variable read latency.</description> 338 <value>0</value> 339 </enumeratedValue> 340 <enumeratedValue> 341 <name>fixed</name> 342 <description>Fixed read latency.</description> 343 <value>1</value> 344 </enumeratedValue> 345 </enumeratedValues> 346 </field> 347 <field> 348 <name>HSE</name> 349 <description>Xccela Half Sleep Exit. When half sleep exit is enabled, the CS# line is held low for ten clock cycles. This bit is automatically cleared by hardware when a Half Sleep Exit completes.</description> 350 <bitOffset>7</bitOffset> 351 <bitWidth>1</bitWidth> 352 <enumeratedValues> 353 <enumeratedValue> 354 <name>dis</name> 355 <description>Half Sleep Exit disabled.</description> 356 <value>0</value> 357 </enumeratedValue> 358 <enumeratedValue> 359 <name>en</name> 360 <description>Half Sleep Exit enabled.</description> 361 <value>1</value> 362 </enumeratedValue> 363 </enumeratedValues> 364 </field> 365 <field> 366 <name>MAXLEN</name> 367 <description>Maximum Read/Write. Set this field to the CS# low time in terms of clock cycles.</description> 368 <bitOffset>18</bitOffset> 369 <bitWidth>9</bitWidth> 370 </field> 371 <field> 372 <name>MAX_EN</name> 373 <description>Maximum CS# Length Enable.</description> 374 <bitOffset>31</bitOffset> 375 <bitWidth>1</bitWidth> 376 <enumeratedValues> 377 <enumeratedValue> 378 <name>dis</name> 379 <description>No configured CS# low time.</description> 380 <value>0</value> 381 </enumeratedValue> 382 <enumeratedValue> 383 <name>en</name> 384 <description>CS# low time is configured.</description> 385 <value>1</value> 386 </enumeratedValue> 387 </enumeratedValues> 388 </field> 389 </fields> 390 </register> 391 <register> 392 <dim>2</dim> 393 <dimIncrement>4</dimIncrement> 394 <name>MEMTIM[%s]</name> 395 <description>Hyperbus Memory Timing Register.</description> 396 <addressOffset>0x0030</addressOffset> 397 <fields> 398 <field> 399 <name>LAT</name> 400 <description>RAM Latency.</description> 401 <bitOffset>0</bitOffset> 402 <bitWidth>4</bitWidth> 403 <enumeratedValues> 404 <enumeratedValue> 405 <name>5clk</name> 406 <description>5 Clock cycles.</description> 407 <value>0</value> 408 </enumeratedValue> 409 <enumeratedValue> 410 <name>6clk</name> 411 <description>6 Clock cycles.</description> 412 <value>1</value> 413 </enumeratedValue> 414 <enumeratedValue> 415 <name>3clk</name> 416 <description>3 Clock cycles.</description> 417 <value>14</value> 418 </enumeratedValue> 419 <enumeratedValue> 420 <name>4clk</name> 421 <description>4 Clock cycles.</description> 422 <value>15</value> 423 </enumeratedValue> 424 </enumeratedValues> 425 </field> 426 <field> 427 <name>WRCSHD</name> 428 <description>Write Chip Select Hold after CK falling edge.</description> 429 <bitOffset>8</bitOffset> 430 <bitWidth>4</bitWidth> 431 </field> 432 <field> 433 <name>RDCSHD</name> 434 <description>Read Chip Select Hold after CK falling edge.</description> 435 <bitOffset>12</bitOffset> 436 <bitWidth>4</bitWidth> 437 </field> 438 <field> 439 <name>WRCSST</name> 440 <description>Write Chip Select Setup Time to Next CK Rising Edge.</description> 441 <bitOffset>16</bitOffset> 442 <bitWidth>4</bitWidth> 443 </field> 444 <field> 445 <name>RDCSST</name> 446 <description>Read Chip Select Setup Time to Next CK Rising Edge.</description> 447 <bitOffset>20</bitOffset> 448 <bitWidth>4</bitWidth> 449 </field> 450 <field> 451 <name>WRCSHI</name> 452 <description>Write Chip Select High Between Operations.</description> 453 <bitOffset>24</bitOffset> 454 <bitWidth>4</bitWidth> 455 </field> 456 <field> 457 <name>RDCSHI</name> 458 <description>Read Chip Select High Between Operations.</description> 459 <bitOffset>28</bitOffset> 460 <bitWidth>4</bitWidth> 461 </field> 462 </fields> 463 </register> 464 </registers> 465 </peripheral> 466 <!-- HPB: HyperBus Memory Controller Registers--> 467</device>
