HPB HyperBus Memory Controller Registers 0x40039000 0x00 0x1000 registers STAT Hyperbus Status Register. 0x0000 RDTXN Read Transaction in Progress 0 1 noread No read transaction currently in progress. 0 read Read transaction currently in progress. 1 RDADDRERR Read Address Error 8 1 normal_op No error. 0 err External read address not responding. 1 RDSLVST Read Slave Status. 9 1 RDRSTERR Reset During Read Error. If this field is set a reset orrcured during a read. 10 1 normal_op No error. 0 err Memory controller was reset during read operation. 1 RDSTALL Read Data Stall. 11 1 normal_op Memory Controller operating normally. 0 stalled Read transaction is stalled because RDS is low (stalled). 1 WRTXN Write Transaction in Progress 16 1 nowrite No write transaction currently in progress. 0 write Write transaction currently in progress. 1 WRADDRERR Write Address Error. If this field is set a write address error orrcured. 24 1 normal_op No error. 0 err The write address to external memory is invalid. 1 WRRSTERR Reset During Write Error. If this field is set a reset orrcured during a write. 26 1 normal_op No error. 0 err Memory controller was reset during write operation. 1 INTEN Hyperbus Interrupt Enable Register. 0x0004 MEM Hyperbus Memory Interrupt Enable. 0 1 dis Disable interrupt. 0 en Enable interrupt. 1 ERR Enables/disables the HPB error interrupt. 1 1 dis Disable error interrupt. 0 en Enable error interrupt. 1 INTFL Hyperbus Interrupt Flag Register. 0x0008 MEM Hyperbus Memory Status Flag. 0 1 noint Memory interrupt not active. 0 pending Memory interrupt currently pending. 1 ERR Error interrupt status flag. 1 1 noint Error interrupt not active. 0 pending Error interrupt currently pending. 1 2 4 MEMBADDR[%s] Hyperbus Memory Base Address Register. 0x0010 ADDR Memory base address. This sets the base address of the addressable memory region where the port is mapped. Each address space is 512Mbytes. The lower 24 bits are read only and will always read 0. 0 32 2 4 MEMCTRL[%s] Hyperbus Memory Control Register. 0x0020 WRAPSIZE The wrap burst length of HyperBus memory. This bit is ignored when the asymmetry cache support bit is 0. When the asymmetry cache support is 1, this bit should be set the same as wrap size of configuration register in HyperBus memory. 0 2 64B 64 bytes 1 16B 16 bytes 2 32B 32 bytes 3 DEVTYPE Select the memory device type. 3 2 hyperFlash HyperFlash 0 xccela_psram Xccela PSRAM 1 hyperRAM HyperRAM 2 CRT Configuration Register Target Select. For HyperRAM and Xccela Bus devices, this field selects between read/write target being the devices memory map or configuration register space. For HyperFlash set this field to 0. 5 1 mem_space Access Memory space. 0 config_reg Access Configuration Register space. 1 RDLAT_EN Xccela Fixed Read Latency Enable. Set this bit to enable Xccela bus Fixed Read Latency. Set this field to match the latency Type configuration in the target PSRAM. 6 1 variable Variable read latency. 0 fixed Fixed read latency. 1 HSE Xccela Half Sleep Exit. When half sleep exit is enabled, the CS# line is held low for ten clock cycles. This bit is automatically cleared by hardware when a Half Sleep Exit completes. 7 1 dis Half Sleep Exit disabled. 0 en Half Sleep Exit enabled. 1 MAXLEN Maximum Read/Write. Set this field to the CS# low time in terms of clock cycles. 18 9 MAX_EN Maximum CS# Length Enable. 31 1 dis No configured CS# low time. 0 en CS# low time is configured. 1 2 4 MEMTIM[%s] Hyperbus Memory Timing Register. 0x0030 LAT RAM Latency. 0 4 5clk 5 Clock cycles. 0 6clk 6 Clock cycles. 1 3clk 3 Clock cycles. 14 4clk 4 Clock cycles. 15 WRCSHD Write Chip Select Hold after CK falling edge. 8 4 RDCSHD Read Chip Select Hold after CK falling edge. 12 4 WRCSST Write Chip Select Setup Time to Next CK Rising Edge. 16 4 RDCSST Read Chip Select Setup Time to Next CK Rising Edge. 20 4 WRCSHI Write Chip Select High Between Operations. 24 4 RDCSHI Read Chip Select High Between Operations. 28 4