1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GPIO0</name> 5 <description>Individual I/O for each GPIO</description> 6 <groupName>GPIO</groupName> 7 <baseAddress>0x40008000</baseAddress> 8 <addressBlock> 9 <offset>0x00</offset> 10 <size>0x1000</size> 11 <usage>registers</usage> 12 </addressBlock> 13 <interrupt> 14 <name>GPIO0</name> 15 <description>GPIO0 interrupt.</description> 16 <value>24</value> 17 </interrupt> 18 <registers> 19 <register> 20 <name>EN</name> 21 <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description> 22 <addressOffset>0x00</addressOffset> 23 <fields> 24 <field> 25 <name>GPIO_EN</name> 26 <description>Mask of all of the pins on the port.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>32</bitWidth> 29 <enumeratedValues> 30 <enumeratedValue> 31 <name>alternate</name> 32 <description>Alternate function enabled.</description> 33 <value>0</value> 34 </enumeratedValue> 35 <enumeratedValue> 36 <name>GPIO</name> 37 <description>GPIO function is enabled.</description> 38 <value>1</value> 39 </enumeratedValue> 40 </enumeratedValues> 41 </field> 42 </fields> 43 </register> 44 <register> 45 <name>EN_SET</name> 46 <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description> 47 <addressOffset>0x04</addressOffset> 48 <fields> 49 <field> 50 <name>GPIO_EN_SET</name> 51 <description>Mask of all of the pins on the port.</description> 52 <bitOffset>0</bitOffset> 53 <bitWidth>32</bitWidth> 54 <enumeratedValues> 55 <enumeratedValue> 56 <name>no</name> 57 <description>No effect.</description> 58 <value>0</value> 59 </enumeratedValue> 60 <enumeratedValue> 61 <name>set</name> 62 <description>Set the corresponding bit in GPIO_EN register.</description> 63 <value>1</value> 64 </enumeratedValue> 65 </enumeratedValues> 66 </field> 67 </fields> 68 </register> 69 <register> 70 <name>EN_CLR</name> 71 <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description> 72 <addressOffset>0x08</addressOffset> 73 <fields> 74 <field> 75 <name>GPIO_EN_CLR</name> 76 <description>Mask of all of the pins on the port.</description> 77 <bitOffset>0</bitOffset> 78 <bitWidth>32</bitWidth> 79 <enumeratedValues> 80 <enumeratedValue> 81 <name>no</name> 82 <description>No effect.</description> 83 <value>0</value> 84 </enumeratedValue> 85 <enumeratedValue> 86 <name>clear</name> 87 <description>Clear the corresponding bit in GPIO_EN register.</description> 88 <value>1</value> 89 </enumeratedValue> 90 </enumeratedValues> 91 </field> 92 </fields> 93 </register> 94 <register> 95 <name>OUT_EN</name> 96 <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description> 97 <addressOffset>0x0C</addressOffset> 98 <fields> 99 <field> 100 <name>GPIO_OUT_EN</name> 101 <description>Mask of all of the pins on the port.</description> 102 <bitOffset>0</bitOffset> 103 <bitWidth>32</bitWidth> 104 <enumeratedValues> 105 <enumeratedValue> 106 <name>dis</name> 107 <description>GPIO Output Disable</description> 108 <value>0</value> 109 </enumeratedValue> 110 <enumeratedValue> 111 <name>en</name> 112 <description>GPIO Output Enable</description> 113 <value>1</value> 114 </enumeratedValue> 115 </enumeratedValues> 116 </field> 117 </fields> 118 </register> 119 <register> 120 <name>OUT_EN_SET</name> 121 <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description> 122 <addressOffset>0x10</addressOffset> 123 <fields> 124 <field> 125 <name>GPIO_OUT_EN_SET</name> 126 <description>Mask of all of the pins on the port.</description> 127 <bitOffset>0</bitOffset> 128 <bitWidth>32</bitWidth> 129 <enumeratedValues> 130 <enumeratedValue> 131 <name>no</name> 132 <description>No effect.</description> 133 <value>0</value> 134 </enumeratedValue> 135 <enumeratedValue> 136 <name>set</name> 137 <description>Set the corresponding bit in GPIO_OUT_EN register.</description> 138 <value>1</value> 139 </enumeratedValue> 140 </enumeratedValues> 141 </field> 142 </fields> 143 </register> 144 <register> 145 <name>OUT_EN_CLR</name> 146 <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description> 147 <addressOffset>0x14</addressOffset> 148 <fields> 149 <field> 150 <name>GPIO_OUT_EN_CLR</name> 151 <description>Mask of all of the pins on the port.</description> 152 <bitOffset>0</bitOffset> 153 <bitWidth>32</bitWidth> 154 <enumeratedValues> 155 <enumeratedValue> 156 <name>no</name> 157 <description>No effect.</description> 158 <value>0</value> 159 </enumeratedValue> 160 <enumeratedValue> 161 <name>clear</name> 162 <description>Clear the corresponding bit in GPIO_OUT_EN register.</description> 163 <value>1</value> 164 </enumeratedValue> 165 </enumeratedValues> 166 </field> 167 </fields> 168 </register> 169 <register> 170 <name>OUT</name> 171 <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description> 172 <addressOffset>0x18</addressOffset> 173 <fields> 174 <field> 175 <name>GPIO_OUT</name> 176 <description>Mask of all of the pins on the port.</description> 177 <bitOffset>0</bitOffset> 178 <bitWidth>32</bitWidth> 179 <enumeratedValues> 180 <enumeratedValue> 181 <name>low</name> 182 <description>Drive Logic 0 (low) on GPIO output.</description> 183 <value>0</value> 184 </enumeratedValue> 185 <enumeratedValue> 186 <name>high</name> 187 <description>Drive logic 1 (high) on GPIO output.</description> 188 <value>1</value> 189 </enumeratedValue> 190 </enumeratedValues> 191 </field> 192 </fields> 193 </register> 194 <register> 195 <name>OUT_SET</name> 196 <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description> 197 <addressOffset>0x1C</addressOffset> 198 <access>write-only</access> 199 <fields> 200 <field> 201 <name>GPIO_OUT_SET</name> 202 <description>Mask of all of the pins on the port.</description> 203 <bitOffset>0</bitOffset> 204 <bitWidth>32</bitWidth> 205 <enumeratedValues> 206 <enumeratedValue> 207 <name>no</name> 208 <description>No effect.</description> 209 <value>0</value> 210 </enumeratedValue> 211 <enumeratedValue> 212 <name>set</name> 213 <description>Set the corresponding bit in GPIO_OUT register.</description> 214 <value>1</value> 215 </enumeratedValue> 216 </enumeratedValues> 217 </field> 218 </fields> 219 </register> 220 <register> 221 <name>OUT_CLR</name> 222 <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description> 223 <addressOffset>0x20</addressOffset> 224 <access>write-only</access> 225 <fields> 226 <field> 227 <name>GPIO_OUT_CLR</name> 228 <description>Mask of all of the pins on the port.</description> 229 <bitOffset>0</bitOffset> 230 <bitWidth>32</bitWidth> 231 <enumeratedValues> 232 <enumeratedValue> 233 <name>no</name> 234 <description>No effect.</description> 235 <value>0</value> 236 </enumeratedValue> 237 <enumeratedValue> 238 <name>clear</name> 239 <description>Clear the corresponding bit in GPIO_OUT register.</description> 240 <value>1</value> 241 </enumeratedValue> 242 </enumeratedValues> 243 </field> 244 </fields> 245 </register> 246 <register> 247 <name>IN</name> 248 <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description> 249 <addressOffset>0x24</addressOffset> 250 <access>read-only</access> 251 <fields> 252 <field> 253 <name>GPIO_IN</name> 254 <description>Mask of all of the pins on the port.</description> 255 <bitOffset>0</bitOffset> 256 <bitWidth>32</bitWidth> 257 <enumeratedValues> 258 <enumeratedValue> 259 <name>low</name> 260 <description>Logic 0 (low) on GPIO input.</description> 261 <value>0</value> 262 </enumeratedValue> 263 <enumeratedValue> 264 <name>high</name> 265 <description>Logic 1 (high) on GPIO input.</description> 266 <value>1</value> 267 </enumeratedValue> 268 </enumeratedValues> 269 </field> 270 </fields> 271 </register> 272 <register> 273 <name>INT_MODE</name> 274 <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description> 275 <addressOffset>0x28</addressOffset> 276 <fields> 277 <field> 278 <name>GPIO_INT_MODE</name> 279 <description>Mask of all of the pins on the port.</description> 280 <bitOffset>0</bitOffset> 281 <bitWidth>32</bitWidth> 282 <enumeratedValues> 283 <enumeratedValue> 284 <name>level</name> 285 <description>Interrupts for this pin are level triggered.</description> 286 <value>0</value> 287 </enumeratedValue> 288 <enumeratedValue> 289 <name>edge</name> 290 <description>Interrupts for this pin are edge triggered.</description> 291 <value>1</value> 292 </enumeratedValue> 293 </enumeratedValues> 294 </field> 295 </fields> 296 </register> 297 <register> 298 <name>INT_POL</name> 299 <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description> 300 <addressOffset>0x2C</addressOffset> 301 <fields> 302 <field> 303 <name>GPIO_INT_POL</name> 304 <description>Mask of all of the pins on the port.</description> 305 <bitOffset>0</bitOffset> 306 <bitWidth>32</bitWidth> 307 <enumeratedValues> 308 <enumeratedValue> 309 <name>falling</name> 310 <description>Interrupts are latched on a falling edge or low level condition for this pin.</description> 311 <value>0</value> 312 </enumeratedValue> 313 <enumeratedValue> 314 <name>rising</name> 315 <description>Interrupts are latched on a rising edge or high condition for this pin.</description> 316 <value>1</value> 317 </enumeratedValue> 318 </enumeratedValues> 319 </field> 320 </fields> 321 </register> 322 <register> 323 <name>IN_EN</name> 324 <description>GPIO Port Input Enable.</description> 325 <addressOffset>0x30</addressOffset> 326 <fields> 327 <field> 328 <name>GPIO_IN_EN</name> 329 <description>Mask of all of the pins on the port.</description> 330 <bitOffset>0</bitOffset> 331 <bitWidth>32</bitWidth> 332 <enumeratedValues> 333 <enumeratedValue> 334 <name>dis</name> 335 <description>GPIO Input Disable</description> 336 <value>0</value> 337 </enumeratedValue> 338 <enumeratedValue> 339 <name>en</name> 340 <description>GPIO Input Enable</description> 341 <value>1</value> 342 </enumeratedValue> 343 </enumeratedValues> 344 </field> 345 </fields> 346 </register> 347 <register> 348 <name>INT_EN</name> 349 <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description> 350 <addressOffset>0x34</addressOffset> 351 <fields> 352 <field> 353 <name>GPIO_INT_EN</name> 354 <description>Mask of all of the pins on the port.</description> 355 <bitOffset>0</bitOffset> 356 <bitWidth>32</bitWidth> 357 <enumeratedValues> 358 <enumeratedValue> 359 <name>dis</name> 360 <description>Interrupts are disabled for this GPIO pin.</description> 361 <value>0</value> 362 </enumeratedValue> 363 <enumeratedValue> 364 <name>en</name> 365 <description>Interrupts are enabled for this GPIO pin.</description> 366 <value>1</value> 367 </enumeratedValue> 368 </enumeratedValues> 369 </field> 370 </fields> 371 </register> 372 <register> 373 <name>INT_EN_SET</name> 374 <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description> 375 <addressOffset>0x38</addressOffset> 376 <fields> 377 <field> 378 <name>GPIO_INT_EN_SET</name> 379 <description>Mask of all of the pins on the port.</description> 380 <bitOffset>0</bitOffset> 381 <bitWidth>32</bitWidth> 382 <enumeratedValues> 383 <enumeratedValue> 384 <name>no</name> 385 <description>No Effect.</description> 386 <value>0</value> 387 </enumeratedValue> 388 <enumeratedValue> 389 <name>set</name> 390 <description>Set GPIO_INT_EN bit in this position to '1'</description> 391 <value>1</value> 392 </enumeratedValue> 393 </enumeratedValues> 394 </field> 395 </fields> 396 </register> 397 <register> 398 <name>INT_EN_CLR</name> 399 <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description> 400 <addressOffset>0x3C</addressOffset> 401 <fields> 402 <field> 403 <name>GPIO_INT_EN_CLR</name> 404 <description>Mask of all of the pins on the port.</description> 405 <bitOffset>0</bitOffset> 406 <bitWidth>32</bitWidth> 407 <enumeratedValues> 408 <enumeratedValue> 409 <name>no</name> 410 <description>No Effect.</description> 411 <value>0</value> 412 </enumeratedValue> 413 <enumeratedValue> 414 <name>clear</name> 415 <description>Clear GPIO_INT_EN bit in this position to '0'</description> 416 <value>1</value> 417 </enumeratedValue> 418 </enumeratedValues> 419 </field> 420 </fields> 421 </register> 422 <register> 423 <name>INT_STAT</name> 424 <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description> 425 <addressOffset>0x40</addressOffset> 426 <access>read-only</access> 427 <fields> 428 <field> 429 <name>GPIO_INT_STAT</name> 430 <description>Mask of all of the pins on the port.</description> 431 <bitOffset>0</bitOffset> 432 <bitWidth>32</bitWidth> 433 <enumeratedValues> 434 <enumeratedValue> 435 <name>no</name> 436 <description>No Interrupt is pending on this GPIO pin.</description> 437 <value>0</value> 438 </enumeratedValue> 439 <enumeratedValue> 440 <name>pending</name> 441 <description>An Interrupt is pending on this GPIO pin.</description> 442 <value>1</value> 443 </enumeratedValue> 444 </enumeratedValues> 445 </field> 446 </fields> 447 </register> 448 <register> 449 <name>INT_CLR</name> 450 <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description> 451 <addressOffset>0x48</addressOffset> 452 <fields> 453 <field> 454 <name>GPIO_INT_CLR</name> 455 <description>Mask of all of the pins on the port.</description> 456 <bitOffset>0</bitOffset> 457 <bitWidth>32</bitWidth> 458 <enumeratedValues> 459 <enumeratedValue> 460 <name>no</name> 461 <description>No effect.</description> 462 <value>0</value> 463 </enumeratedValue> 464 <enumeratedValue> 465 <name>clear</name> 466 <description>Clear the corresponding bit in GPIO_INT_STAT register.</description> 467 <value>1</value> 468 </enumeratedValue> 469 </enumeratedValues> 470 </field> 471 </fields> 472 </register> 473 <register> 474 <name>WAKE_EN</name> 475 <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description> 476 <addressOffset>0x4C</addressOffset> 477 <fields> 478 <field> 479 <name>GPIO_WAKE_EN</name> 480 <description>Mask of all of the pins on the port.</description> 481 <bitOffset>0</bitOffset> 482 <bitWidth>32</bitWidth> 483 <enumeratedValues> 484 <enumeratedValue> 485 <name>dis</name> 486 <description>PMU wakeup for this GPIO is disabled.</description> 487 <value>0</value> 488 </enumeratedValue> 489 <enumeratedValue> 490 <name>en</name> 491 <description>PMU wakeup for this GPIO is enabled.</description> 492 <value>1</value> 493 </enumeratedValue> 494 </enumeratedValues> 495 </field> 496 </fields> 497 </register> 498 <register> 499 <name>WAKE_EN_SET</name> 500 <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description> 501 <addressOffset>0x50</addressOffset> 502 <fields> 503 <field> 504 <name>GPIO_WAKE_EN_SET</name> 505 <description>Mask of all of the pins on the port.</description> 506 <bitOffset>0</bitOffset> 507 <bitWidth>32</bitWidth> 508 <enumeratedValues> 509 <enumeratedValue> 510 <name>no</name> 511 <description>No effect.</description> 512 <value>0</value> 513 </enumeratedValue> 514 <enumeratedValue> 515 <name>set</name> 516 <description>Set the corresponding bit in GPIO_WAKE_EN register.</description> 517 <value>1</value> 518 </enumeratedValue> 519 </enumeratedValues> 520 </field> 521 </fields> 522 </register> 523 <register> 524 <name>WAKE_EN_CLR</name> 525 <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description> 526 <addressOffset>0x54</addressOffset> 527 <fields> 528 <field> 529 <name>GPIO_WAKE_EN_CLR</name> 530 <description>Mask of all of the pins on the port.</description> 531 <bitOffset>0</bitOffset> 532 <bitWidth>32</bitWidth> 533 <enumeratedValues> 534 <enumeratedValue> 535 <name>no</name> 536 <description>No effect.</description> 537 <value>0</value> 538 </enumeratedValue> 539 <enumeratedValue> 540 <name>clear</name> 541 <description>Clear the corresponding bit in GPIO_WAKE_EN register.</description> 542 <value>1</value> 543 </enumeratedValue> 544 </enumeratedValues> 545 </field> 546 </fields> 547 </register> 548 <register> 549 <name>INT_DUAL_EDGE</name> 550 <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description> 551 <addressOffset>0x5C</addressOffset> 552 <fields> 553 <field> 554 <name>GPIO_INT_DUAL_EDGE</name> 555 <description>Mask of all of the pins on the port.</description> 556 <bitOffset>0</bitOffset> 557 <bitWidth>32</bitWidth> 558 <enumeratedValues> 559 <enumeratedValue> 560 <name>no</name> 561 <description>No Effect.</description> 562 <value>0</value> 563 </enumeratedValue> 564 <enumeratedValue> 565 <name>dual</name> 566 <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description> 567 <value>1</value> 568 </enumeratedValue> 569 </enumeratedValues> 570 </field> 571 </fields> 572 </register> 573 <register> 574 <name>PDPU_SEL0</name> 575 <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 576 <addressOffset>0x60</addressOffset> 577 <fields> 578 <field> 579 <name>GPIO_PDPU_SEL0</name> 580 <description>The two bits in GPIO_PDPU_SEL0 and GPIO_PDPU_SEL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 581 <bitOffset>0</bitOffset> 582 <bitWidth>32</bitWidth> 583 <enumeratedValues> 584 <enumeratedValue> 585 <name>impedance</name> 586 <description>High Impedance.</description> 587 <value>0</value> 588 </enumeratedValue> 589 <enumeratedValue> 590 <name>pu</name> 591 <description>Pull-up mode.</description> 592 <value>1</value> 593 </enumeratedValue> 594 </enumeratedValues> 595 </field> 596 </fields> 597 </register> 598 <register> 599 <name>PDPU_SEL1</name> 600 <description>GPIO Input Mode Config 2. Each bit in this register enables the pull-down for the associated GPIO pin in this port.</description> 601 <addressOffset>0x64</addressOffset> 602 <fields> 603 <field> 604 <name>GPIO_PDPU_SEL1</name> 605 <description>The two bits in GPIO_PDPU_SEL0 and GPIO_PDPU_SEL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 606 <bitOffset>0</bitOffset> 607 <bitWidth>32</bitWidth> 608 <enumeratedValues> 609 <enumeratedValue> 610 <name>impedance</name> 611 <description>High Impedance.</description> 612 <value>0</value> 613 </enumeratedValue> 614 <enumeratedValue> 615 <name>pd</name> 616 <description>Pull-down mode.</description> 617 <value>1</value> 618 </enumeratedValue> 619 </enumeratedValues> 620 </field> 621 </fields> 622 </register> 623 <register> 624 <name>AF_SEL</name> 625 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 626 <addressOffset>0x68</addressOffset> 627 <fields> 628 <field> 629 <name>GPIO_AF_SEL</name> 630 <description>Mask of all of the pins on the port.</description> 631 <bitOffset>0</bitOffset> 632 <bitWidth>32</bitWidth> 633 <enumeratedValues> 634 <enumeratedValue> 635 <name>primary</name> 636 <description>Primary function selected.</description> 637 <value>0</value> 638 </enumeratedValue> 639 <enumeratedValue> 640 <name>secondary</name> 641 <description>Secondary function selected.</description> 642 <value>1</value> 643 </enumeratedValue> 644 </enumeratedValues> 645 </field> 646 </fields> 647 </register> 648 <register> 649 <name>AF_SEL_SET</name> 650 <description>GPIO Alternate Function Selectset. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description> 651 <addressOffset>0x6C</addressOffset> 652 <fields> 653 <field> 654 <name>AF_SEL_SET</name> 655 <description>Mask of all of the pins on the port.</description> 656 <bitOffset>0</bitOffset> 657 <bitWidth>32</bitWidth> 658 <enumeratedValues> 659 <enumeratedValue> 660 <name>no</name> 661 <description>No effect.</description> 662 <value>0</value> 663 </enumeratedValue> 664 <enumeratedValue> 665 <name>set</name> 666 <description>Set the corresponding bit in GPIO_AF_SEL register.</description> 667 <value>1</value> 668 </enumeratedValue> 669 </enumeratedValues> 670 </field> 671 </fields> 672 </register> 673 <register> 674 <name>AF_SEL_CLR</name> 675 <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description> 676 <addressOffset>0x70</addressOffset> 677 <fields> 678 <field> 679 <name>GPIO_AF_SEL_CLR</name> 680 <description>Mask of all of the pins on the port.</description> 681 <bitOffset>0</bitOffset> 682 <bitWidth>32</bitWidth> 683 <enumeratedValues> 684 <enumeratedValue> 685 <name>no</name> 686 <description>No effect.</description> 687 <value>0</value> 688 </enumeratedValue> 689 <enumeratedValue> 690 <name>clear</name> 691 <description>Clear the corresponding bit in GPIO_AF_SEL register.</description> 692 <value>1</value> 693 </enumeratedValue> 694 </enumeratedValues> 695 </field> 696 </fields> 697 </register> 698 <register> 699 <name>DS_SEL0</name> 700 <description>GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. The total drive strength multiplier is the multiplication between the two drive strength select registers.</description> 701 <addressOffset>0xB0</addressOffset> 702 <fields> 703 <field> 704 <name>GPIO_DS_SEL0</name> 705 <description>Mask of all of the pins on the port.</description> 706 <bitOffset>0</bitOffset> 707 <bitWidth>32</bitWidth> 708 <enumeratedValues> 709 <enumeratedValue> 710 <name>1X</name> 711 <description>1 x GPIO_DS_SEL1 = total drive strength multiplier.</description> 712 <value>0</value> 713 </enumeratedValue> 714 <enumeratedValue> 715 <name>2X</name> 716 <description>2 x GPIO_DS_SEL1 = total drive strength multiplier.</description> 717 <value>1</value> 718 </enumeratedValue> 719 </enumeratedValues> 720 </field> 721 </fields> 722 </register> 723 <register> 724 <name>DS_SEL1</name> 725 <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. The total drive strength multiplier is the multiplication between the two drive strength select registers.</description> 726 <addressOffset>0xB4</addressOffset> 727 <fields> 728 <field> 729 <name>GPIO_DS_SEL1</name> 730 <description>Mask of all of the pins on the port.</description> 731 <bitOffset>0</bitOffset> 732 <bitWidth>32</bitWidth> 733 <enumeratedValues> 734 <enumeratedValue> 735 <name>1X</name> 736 <description>1 x GPIO_DS_SEL0 = total drive strength multiplier.</description> 737 <value>0</value> 738 </enumeratedValue> 739 <enumeratedValue> 740 <name>4X</name> 741 <description>4 x GPIO_DS_SEL0 = total drive strength multiplier.</description> 742 <value>1</value> 743 </enumeratedValue> 744 </enumeratedValues> 745 </field> 746 </fields> 747 </register> 748 <register> 749 <name>PSSEL</name> 750 <description>GPIO Pull Select Mode.</description> 751 <addressOffset>0xB8</addressOffset> 752 <fields> 753 <field> 754 <name>GPIO_PSSEL</name> 755 <description>Mask of all of the pins on the port.</description> 756 <bitOffset>0</bitOffset> 757 <bitWidth>32</bitWidth> 758 <enumeratedValues> 759 <enumeratedValue> 760 <name>WEAK_PDPU</name> 761 <description>1MOhm Pull-Up/Down resistor connected to the input pin.</description> 762 <value>0</value> 763 </enumeratedValue> 764 <enumeratedValue> 765 <name>STRONG_PDPU</name> 766 <description>25KOhm Pull-Up/Down resistor connected to the input pin.</description> 767 <value>1</value> 768 </enumeratedValue> 769 </enumeratedValues> 770 </field> 771 </fields> 772 </register> 773 <register> 774 <name>VSSEL</name> 775 <description>GPIO Voltage Select.</description> 776 <addressOffset>0xC0</addressOffset> 777 <fields> 778 <field> 779 <name>GPIO_VSSEL</name> 780 <description>Mask of all of the pins on the port.</description> 781 <bitOffset>0</bitOffset> 782 <bitWidth>32</bitWidth> 783 <enumeratedValues> 784 <enumeratedValue> 785 <name>VDDIO</name> 786 <description>Vddio set as the pin's supply voltage.</description> 787 <value>0</value> 788 </enumeratedValue> 789 <enumeratedValue> 790 <name>VDDIOH</name> 791 <description>Vddioh set as the pin's supply voltage.</description> 792 <value>1</value> 793 </enumeratedValue> 794 </enumeratedValues> 795 </field> 796 </fields> 797 </register> 798 </registers> 799 </peripheral> 800 <!-- GPIO0: Individual I/O for Port 0 --> 801</device>
