GPIO0 Individual I/O for each GPIO GPIO 0x40008000 0x00 0x1000 registers GPIO0 GPIO0 interrupt. 24 EN GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. 0x00 GPIO_EN Mask of all of the pins on the port. 0 32 alternate Alternate function enabled. 0 GPIO GPIO function is enabled. 1 EN_SET GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. 0x04 GPIO_EN_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_EN register. 1 EN_CLR GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. 0x08 GPIO_EN_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_EN register. 1 OUT_EN GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. 0x0C GPIO_OUT_EN Mask of all of the pins on the port. 0 32 dis GPIO Output Disable 0 en GPIO Output Enable 1 OUT_EN_SET GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. 0x10 GPIO_OUT_EN_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_OUT_EN register. 1 OUT_EN_CLR GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. 0x14 GPIO_OUT_EN_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_OUT_EN register. 1 OUT GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. 0x18 GPIO_OUT Mask of all of the pins on the port. 0 32 low Drive Logic 0 (low) on GPIO output. 0 high Drive logic 1 (high) on GPIO output. 1 OUT_SET GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. 0x1C write-only GPIO_OUT_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_OUT register. 1 OUT_CLR GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. 0x20 write-only GPIO_OUT_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_OUT register. 1 IN GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. 0x24 read-only GPIO_IN Mask of all of the pins on the port. 0 32 low Logic 0 (low) on GPIO input. 0 high Logic 1 (high) on GPIO input. 1 INT_MODE GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. 0x28 GPIO_INT_MODE Mask of all of the pins on the port. 0 32 level Interrupts for this pin are level triggered. 0 edge Interrupts for this pin are edge triggered. 1 INT_POL GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. 0x2C GPIO_INT_POL Mask of all of the pins on the port. 0 32 falling Interrupts are latched on a falling edge or low level condition for this pin. 0 rising Interrupts are latched on a rising edge or high condition for this pin. 1 IN_EN GPIO Port Input Enable. 0x30 GPIO_IN_EN Mask of all of the pins on the port. 0 32 dis GPIO Input Disable 0 en GPIO Input Enable 1 INT_EN GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. 0x34 GPIO_INT_EN Mask of all of the pins on the port. 0 32 dis Interrupts are disabled for this GPIO pin. 0 en Interrupts are enabled for this GPIO pin. 1 INT_EN_SET GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. 0x38 GPIO_INT_EN_SET Mask of all of the pins on the port. 0 32 no No Effect. 0 set Set GPIO_INT_EN bit in this position to '1' 1 INT_EN_CLR GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. 0x3C GPIO_INT_EN_CLR Mask of all of the pins on the port. 0 32 no No Effect. 0 clear Clear GPIO_INT_EN bit in this position to '0' 1 INT_STAT GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. 0x40 read-only GPIO_INT_STAT Mask of all of the pins on the port. 0 32 no No Interrupt is pending on this GPIO pin. 0 pending An Interrupt is pending on this GPIO pin. 1 INT_CLR GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. 0x48 GPIO_INT_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_INT_STAT register. 1 WAKE_EN GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. 0x4C GPIO_WAKE_EN Mask of all of the pins on the port. 0 32 dis PMU wakeup for this GPIO is disabled. 0 en PMU wakeup for this GPIO is enabled. 1 WAKE_EN_SET GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. 0x50 GPIO_WAKE_EN_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_WAKE_EN register. 1 WAKE_EN_CLR GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. 0x54 GPIO_WAKE_EN_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_WAKE_EN register. 1 INT_DUAL_EDGE GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. 0x5C GPIO_INT_DUAL_EDGE Mask of all of the pins on the port. 0 32 no No Effect. 0 dual Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. 1 PDPU_SEL0 GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x60 GPIO_PDPU_SEL0 The two bits in GPIO_PDPU_SEL0 and GPIO_PDPU_SEL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Pull-up mode. 1 PDPU_SEL1 GPIO Input Mode Config 2. Each bit in this register enables the pull-down for the associated GPIO pin in this port. 0x64 GPIO_PDPU_SEL1 The two bits in GPIO_PDPU_SEL0 and GPIO_PDPU_SEL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pd Pull-down mode. 1 AF_SEL GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x68 GPIO_AF_SEL Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 AF_SEL_SET GPIO Alternate Function Selectset. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. 0x6C AF_SEL_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_AF_SEL register. 1 AF_SEL_CLR GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. 0x70 GPIO_AF_SEL_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_AF_SEL register. 1 DS_SEL0 GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. The total drive strength multiplier is the multiplication between the two drive strength select registers. 0xB0 GPIO_DS_SEL0 Mask of all of the pins on the port. 0 32 1X 1 x GPIO_DS_SEL1 = total drive strength multiplier. 0 2X 2 x GPIO_DS_SEL1 = total drive strength multiplier. 1 DS_SEL1 GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. The total drive strength multiplier is the multiplication between the two drive strength select registers. 0xB4 GPIO_DS_SEL1 Mask of all of the pins on the port. 0 32 1X 1 x GPIO_DS_SEL0 = total drive strength multiplier. 0 4X 4 x GPIO_DS_SEL0 = total drive strength multiplier. 1 PSSEL GPIO Pull Select Mode. 0xB8 GPIO_PSSEL Mask of all of the pins on the port. 0 32 WEAK_PDPU 1MOhm Pull-Up/Down resistor connected to the input pin. 0 STRONG_PDPU 25KOhm Pull-Up/Down resistor connected to the input pin. 1 VSSEL GPIO Voltage Select. 0xC0 GPIO_VSSEL Mask of all of the pins on the port. 0 32 VDDIO Vddio set as the pin's supply voltage. 0 VDDIOH Vddioh set as the pin's supply voltage. 1