1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>EMAC</name> 5 <description>10/100 Ethernet MAC.</description> 6 <baseAddress>0x4004F000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <interrupt> 13 <name>EMAC</name> 14 <description>EMAC IRQ</description> 15 <value>64</value> 16 </interrupt> 17 <registers> 18 <register> 19 <name>CN</name> 20 <description>Network Control Register.</description> 21 <addressOffset>0x00</addressOffset> 22 <resetValue>0x00</resetValue> 23 <fields> 24 <field> 25 <name>LB</name> 26 <description>Loopback.</description> 27 <bitOffset>0</bitOffset> 28 <bitWidth>1</bitWidth> 29 <access>read-write</access> 30 </field> 31 <field> 32 <name>LBL</name> 33 <description>Loopback local.</description> 34 <bitOffset>1</bitOffset> 35 <bitWidth>1</bitWidth> 36 <access>read-write</access> 37 </field> 38 <field> 39 <name>RXEN</name> 40 <description>Receive Enable.</description> 41 <bitOffset>2</bitOffset> 42 <bitWidth>1</bitWidth> 43 <access>read-write</access> 44 </field> 45 <field> 46 <name>TXEN</name> 47 <description>Transmit Enable.</description> 48 <bitOffset>3</bitOffset> 49 <bitWidth>1</bitWidth> 50 <access>read-write</access> 51 </field> 52 <field> 53 <name>MPEN</name> 54 <description>Management Port Enable.</description> 55 <bitOffset>4</bitOffset> 56 <bitWidth>1</bitWidth> 57 <access>read-write</access> 58 </field> 59 <field> 60 <name>CLST</name> 61 <description>Clear Statistics.</description> 62 <bitOffset>5</bitOffset> 63 <bitWidth>1</bitWidth> 64 <access>write-only</access> 65 </field> 66 <field> 67 <name>INCST</name> 68 <description>Increment Statistics.</description> 69 <bitOffset>6</bitOffset> 70 <bitWidth>1</bitWidth> 71 <access>write-only</access> 72 </field> 73 <field> 74 <name>WREN</name> 75 <description>Write enable for statistics registers.</description> 76 <bitOffset>7</bitOffset> 77 <bitWidth>1</bitWidth> 78 <access>read-write</access> 79 </field> 80 <field> 81 <name>BP</name> 82 <description>Back pressure.</description> 83 <bitOffset>8</bitOffset> 84 <bitWidth>1</bitWidth> 85 <access>read-write</access> 86 </field> 87 <field> 88 <name>TXSTART</name> 89 <description>Transmission start.</description> 90 <bitOffset>9</bitOffset> 91 <bitWidth>1</bitWidth> 92 <access>write-only</access> 93 </field> 94 <field> 95 <name>TXHALT</name> 96 <description>Transmit halt.</description> 97 <bitOffset>10</bitOffset> 98 <bitWidth>1</bitWidth> 99 <access>write-only</access> 100 </field> 101 <field> 102 <name>TXPF</name> 103 <description>Transmit pause frame.</description> 104 <bitOffset>11</bitOffset> 105 <bitWidth>1</bitWidth> 106 <access>write-only</access> 107 </field> 108 <field> 109 <name>TXZQPF</name> 110 <description>Transmit zero quantum pause frame.</description> 111 <bitOffset>12</bitOffset> 112 <bitWidth>1</bitWidth> 113 <access>write-only</access> 114 </field> 115 </fields> 116 </register> 117 <register> 118 <name>CFG</name> 119 <description>Network Configuration Register.</description> 120 <addressOffset>0x04</addressOffset> 121 <fields> 122 <field> 123 <name>SPD</name> 124 <description>Speed Select.</description> 125 <bitOffset>0</bitOffset> 126 <bitWidth>1</bitWidth> 127 <access>read-write</access> 128 </field> 129 <field> 130 <name>FULLDPLX</name> 131 <description>Full Duplex. If set to 1 the transmit block ignores the state of collision and carrier sense and allows Rx while transmitting.</description> 132 <bitOffset>1</bitOffset> 133 <bitWidth>1</bitWidth> 134 <access>read-write</access> 135 </field> 136 <field> 137 <name>BITRATE</name> 138 <description>Bit Rate. Writing 1 to this bit configures the interface for serial operation. </description> 139 <bitOffset>2</bitOffset> 140 <bitWidth>1</bitWidth> 141 <access>read-write</access> 142 </field> 143 <field> 144 <name>JUMBOFR</name> 145 <description>Jumbo Frames. Writing 1 to this bit enables jumbo frames of up to 10,240 bytes to be accepted.</description> 146 <bitOffset>3</bitOffset> 147 <bitWidth>1</bitWidth> 148 <access>read-write</access> 149 </field> 150 <field> 151 <name>COPYAF</name> 152 <description>Copy All Frames. If 1, all valid frames will be received.</description> 153 <bitOffset>4</bitOffset> 154 <bitWidth>1</bitWidth> 155 <access>read-write</access> 156 </field> 157 <field> 158 <name>NOBC</name> 159 <description>No Broadcast. If 1, frames addressed to the broadcast address of all ones will not be received.</description> 160 <bitOffset>5</bitOffset> 161 <bitWidth>1</bitWidth> 162 <access>write-only</access> 163 </field> 164 <field> 165 <name>MHEN</name> 166 <description>Multicast Hash Enable. If 1, multicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</description> 167 <bitOffset>6</bitOffset> 168 <bitWidth>1</bitWidth> 169 <access>write-only</access> 170 </field> 171 <field> 172 <name>UHEN</name> 173 <description>Unicast Hash Enable. If 1, unicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</description> 174 <bitOffset>7</bitOffset> 175 <bitWidth>1</bitWidth> 176 <access>read-write</access> 177 </field> 178 <field> 179 <name>RXFR</name> 180 <description>Receive 1536 Byte Frames. Writing 1 to this bit means the MAC receives packets up to 1536 bytes in length. Normally the MAC rejects any packet above 1518 bytes</description> 181 <bitOffset>8</bitOffset> 182 <bitWidth>1</bitWidth> 183 <access>read-write</access> 184 </field> 185 <field> 186 <name>EAE</name> 187 <description>TBD</description> 188 <bitOffset>9</bitOffset> 189 <bitWidth>1</bitWidth> 190 <access>read-write</access> 191 </field> 192 <field> 193 <name>MDCCLK</name> 194 <description>MDC Frequency. Set according to PCLK speed. This field determines by what number PCLK is divided to generate MDC.</description> 195 <bitOffset>10</bitOffset> 196 <bitWidth>2</bitWidth> 197 <access>write-only</access> 198 <enumeratedValues> 199 <enumeratedValue> 200 <name>div8</name> 201 <description>PCLK up to 20MHz</description> 202 <value>0</value> 203 </enumeratedValue> 204 <enumeratedValue> 205 <name>div16</name> 206 <description>PCLK up to 40MHz</description> 207 <value>1</value> 208 </enumeratedValue> 209 <enumeratedValue> 210 <name>div32</name> 211 <description>PCLK up to 80MHz</description> 212 <value>2</value> 213 </enumeratedValue> 214 <enumeratedValue> 215 <name>div64</name> 216 <description>PCLK up to 160MHz</description> 217 <value>3</value> 218 </enumeratedValue> 219 </enumeratedValues> 220 </field> 221 <field> 222 <name>TXPF</name> 223 <description>Transmit pause frame.</description> 224 <bitOffset>11</bitOffset> 225 <bitWidth>1</bitWidth> 226 <access>write-only</access> 227 </field> 228 <field> 229 <name>RTTST</name> 230 <description>Retry Test. Must be set to zero for normal operation. If set to 1, the back-off between collisions is always one slot time.</description> 231 <bitOffset>12</bitOffset> 232 <bitWidth>1</bitWidth> 233 <access>write-only</access> 234 </field> 235 <field> 236 <name>PAUSEEN</name> 237 <description>Pause Enable. If 1, Ethernet packet transmission pauses when a valid pause packet is received.</description> 238 <bitOffset>13</bitOffset> 239 <bitWidth>1</bitWidth> 240 <access>write-only</access> 241 </field> 242 <field> 243 <name>RXBUFFOFS</name> 244 <description>Receive buffer offset. These bits indicate the number of bytes by which the received data is offset from the start of the first receive buffer.</description> 245 <bitOffset>14</bitOffset> 246 <bitWidth>2</bitWidth> 247 <access>write-only</access> 248 </field> 249 <field> 250 <name>RXLFCEN</name> 251 <description>Receive length field checking enable. If 1, packets with measured lengths shorter than their length fields are discarded. Packets containing a type ID in bytes 13 and 14 (length/type field ≥0600) are not counted as length errors.</description> 252 <bitOffset>16</bitOffset> 253 <bitWidth>1</bitWidth> 254 <access>write-only</access> 255 </field> 256 <field> 257 <name>DCRXFCS</name> 258 <description>Discard receive FCS. If 1, the FCS field of received frames will not be copied to memory.</description> 259 <bitOffset>17</bitOffset> 260 <bitWidth>1</bitWidth> 261 <access>write-only</access> 262 </field> 263 <field> 264 <name>HDPLXRXEN</name> 265 <description>Enable packets to be received in half-duplex mode while transmitting.</description> 266 <bitOffset>18</bitOffset> 267 <bitWidth>1</bitWidth> 268 <access>write-only</access> 269 </field> 270 <field> 271 <name>IGNRXFCS</name> 272 <description>Ignore RX FCS. If 1, packets with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0.</description> 273 <bitOffset>19</bitOffset> 274 <bitWidth>1</bitWidth> 275 <access>write-only</access> 276 </field> 277 </fields> 278 </register> 279 <register> 280 <name>STATUS</name> 281 <description>Network Status Register.</description> 282 <addressOffset>0x08</addressOffset> 283 <access>read-only</access> 284 <fields> 285 <field> 286 <name>LINK</name> 287 <description>LINK pin status. Returns status of EMAC_LINK pin.</description> 288 <bitOffset>0</bitOffset> 289 <bitWidth>1</bitWidth> 290 <access>read-write</access> 291 </field> 292 <field> 293 <name>MDIO</name> 294 <description>MDIO pin status. Returns status of the EMAC_MDIO pin. Use the PHY maintenance register for reading managed frames rather than this bit.</description> 295 <bitOffset>1</bitOffset> 296 <bitWidth>1</bitWidth> 297 <access>read-write</access> 298 </field> 299 <field> 300 <name>IDLE</name> 301 <description>PHY management logic status.</description> 302 <bitOffset>2</bitOffset> 303 <bitWidth>1</bitWidth> 304 <access>read-write</access> 305 </field> 306 </fields> 307 </register> 308 <register> 309 <name>TX_ST</name> 310 <description>Transmit Status Register.</description> 311 <addressOffset>0x14</addressOffset> 312 <fields> 313 <field> 314 <name>UBR</name> 315 <description>Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Write 1 to clear this bit.</description> 316 <bitOffset>0</bitOffset> 317 <bitWidth>1</bitWidth> 318 <access>read-write</access> 319 </field> 320 <field> 321 <name>COLS</name> 322 <description>Collision Occurred. Set when a collision occurs. Write 1 to clear this bit.</description> 323 <bitOffset>1</bitOffset> 324 <bitWidth>1</bitWidth> 325 <access>read-write</access> 326 </field> 327 <field> 328 <name>RTYLIM</name> 329 <description>Retry Limit Exceeded. Set when the retry limit has been exceeded. Write 1 to clear this bit. </description> 330 <bitOffset>2</bitOffset> 331 <bitWidth>1</bitWidth> 332 <access>read-write</access> 333 </field> 334 <field> 335 <name>TXGO</name> 336 <description>Transmit Go. If 1, transmit is active.</description> 337 <bitOffset>3</bitOffset> 338 <bitWidth>1</bitWidth> 339 <access>read-write</access> 340 </field> 341 <field> 342 <name>BEMF</name> 343 <description>Buffers Exhausted Mid Frame. If the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and EMAC_TXER asserted. Write 1 to clear this bit.</description> 344 <bitOffset>4</bitOffset> 345 <bitWidth>1</bitWidth> 346 <access>read-write</access> 347 </field> 348 <field> 349 <name>TXCMPL</name> 350 <description>Transmit Complete. Set when a frame has been transmitted. Write 1 to clear this bit.</description> 351 <bitOffset>5</bitOffset> 352 <bitWidth>1</bitWidth> 353 <access>read-write</access> 354 </field> 355 <field> 356 <name>TXUR</name> 357 <description>Transmit Underrun. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad. Write 1 to clear this bit.</description> 358 <bitOffset>6</bitOffset> 359 <bitWidth>1</bitWidth> 360 <access>read-write</access> 361 </field> 362 </fields> 363 </register> 364 <register> 365 <name>RXBUF_PTR</name> 366 <description>Receive Buffer Queue Pointer Register.</description> 367 <addressOffset>0x18</addressOffset> 368 <fields> 369 <field> 370 <name>RXBUF</name> 371 <description>Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used.</description> 372 <bitOffset>2</bitOffset> 373 <bitWidth>30</bitWidth> 374 <access>read-write</access> 375 </field> 376 </fields> 377 </register> 378 <register> 379 <name>TXBUF_PTR</name> 380 <description>Transmit Buffer Queue Pointer Register.</description> 381 <addressOffset>0x1C</addressOffset> 382 <fields> 383 <field> 384 <name>TXBUF</name> 385 <description>Transmit buffer queue pointer. Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted.</description> 386 <bitOffset>2</bitOffset> 387 <bitWidth>30</bitWidth> 388 <access>read-write</access> 389 </field> 390 </fields> 391 </register> 392 <register> 393 <name>RX_ST</name> 394 <description>Receive Status Register.</description> 395 <addressOffset>0x20</addressOffset> 396 <fields> 397 <field> 398 <name>BNA</name> 399 <description>Buffer Not Available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time a new frame starts until a valid pointer is found. This bit will be set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Write 1 to clear this bit.</description> 400 <bitOffset>0</bitOffset> 401 <bitWidth>1</bitWidth> 402 <access>read-write</access> 403 </field> 404 <field> 405 <name>FR</name> 406 <description>Frame Received. One or more frames have been received and placed in memory. Write 1 to clear this bit.</description> 407 <bitOffset>1</bitOffset> 408 <bitWidth>1</bitWidth> 409 <access>read-write</access> 410 </field> 411 <field> 412 <name>RXOR</name> 413 <description>Receive Overrun. The DMA block was unable to store the receive frame to memory. Either because the AHB bus was not granted in time or because a not OK hresp was returned. The buffer will be recovered if this happens. Write 1 to clear this bit.</description> 414 <bitOffset>2</bitOffset> 415 <bitWidth>1</bitWidth> 416 <access>read-write</access> 417 </field> 418 </fields> 419 </register> 420 <register> 421 <name>INT_ST</name> 422 <description>Interrupt Status Register.</description> 423 <addressOffset>0x24</addressOffset> 424 <fields> 425 <field> 426 <name>MPS</name> 427 <description>Management Packet Sent Interrupt Status. The PHY maintenance register has completed its operation. Cleared when read.</description> 428 <bitOffset>0</bitOffset> 429 <bitWidth>1</bitWidth> 430 <access>read-write</access> 431 </field> 432 <field> 433 <name>RXCMPL</name> 434 <description>Receive Complete Interrupt Status. Set when a frame has been stored in memory. Cleared when read.</description> 435 <bitOffset>1</bitOffset> 436 <bitWidth>1</bitWidth> 437 <access>read-write</access> 438 </field> 439 <field> 440 <name>RXUBR</name> 441 <description>RX Used Bit Read Interrupt Status. Set when a receive buffer descriptor is read with its used bit set. Cleared when read.</description> 442 <bitOffset>2</bitOffset> 443 <bitWidth>1</bitWidth> 444 <access>read-write</access> 445 </field> 446 <field> 447 <name>TXUBR</name> 448 <description>TX Used Bit Read Interrupt Status. Set when a transmit buffer descriptor is read with its used bit set. Cleared when read</description> 449 <bitOffset>3</bitOffset> 450 <bitWidth>1</bitWidth> 451 <access>read-write</access> 452 </field> 453 <field> 454 <name>TXUR</name> 455 <description>Ethernet Transmit Underrun Interrupt Status. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad CRC and forces EMAC_TXER high. Cleared when read.</description> 456 <bitOffset>4</bitOffset> 457 <bitWidth>1</bitWidth> 458 <access>read-write</access> 459 </field> 460 <field> 461 <name>RLE</name> 462 <description>Retry Limit Exceeded Interrupt Status. Transmit error. Cleared when read.</description> 463 <bitOffset>5</bitOffset> 464 <bitWidth>1</bitWidth> 465 <access>read-write</access> 466 </field> 467 <field> 468 <name>TXERR</name> 469 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Status. Transmit error. Cleared when read.</description> 470 <bitOffset>6</bitOffset> 471 <bitWidth>1</bitWidth> 472 <access>read-write</access> 473 </field> 474 <field> 475 <name>TXCMPL</name> 476 <description>Transmit Complete Interrupt Status. Set when a frame has been transmitted. Cleared when read.</description> 477 <bitOffset>7</bitOffset> 478 <bitWidth>1</bitWidth> 479 <access>read-write</access> 480 </field> 481 <field> 482 <name>LC</name> 483 <description>Link Change Interrupt Status. Set when the external link signal changes. Cleared when read.</description> 484 <bitOffset>9</bitOffset> 485 <bitWidth>1</bitWidth> 486 <access>read-write</access> 487 </field> 488 <field> 489 <name>RXOR</name> 490 <description>Receive Overrun Interrupt Status. Set when the receive overrun status bit gets set. Cleared when read.</description> 491 <bitOffset>10</bitOffset> 492 <bitWidth>1</bitWidth> 493 <access>read-write</access> 494 </field> 495 <field> 496 <name>HRESPNO</name> 497 <description>hresp not OK Interrupt Status. Set when the DMA block sees hresp not OK. Cleared when read.</description> 498 <bitOffset>11</bitOffset> 499 <bitWidth>1</bitWidth> 500 <access>read-write</access> 501 </field> 502 <field> 503 <name>PPR</name> 504 <description>Pause Packet Received Interrupt Status. Indicates a valid pause packet has been received. Cleared when read.</description> 505 <bitOffset>12</bitOffset> 506 <bitWidth>1</bitWidth> 507 <access>read-write</access> 508 </field> 509 <field> 510 <name>PTZ</name> 511 <description>Pause Time Zero Interrupt Status. Set when the MAC Pause Time register (MAC_PT) decrements to zero. Cleared when read.</description> 512 <bitOffset>13</bitOffset> 513 <bitWidth>1</bitWidth> 514 <access>read-write</access> 515 </field> 516 </fields> 517 </register> 518 <register> 519 <name>INT_EN</name> 520 <description>Interrupt Enable Register.</description> 521 <addressOffset>0x28</addressOffset> 522 <access>write-only</access> 523 <fields> 524 <field> 525 <name>MPS</name> 526 <description>Management Packet Sent Interrupt Enable</description> 527 <bitOffset>0</bitOffset> 528 <bitWidth>1</bitWidth> 529 <access>read-write</access> 530 </field> 531 <field> 532 <name>RXCMPL</name> 533 <description>Receive Complete Interrupt Enable</description> 534 <bitOffset>1</bitOffset> 535 <bitWidth>1</bitWidth> 536 <access>read-write</access> 537 </field> 538 <field> 539 <name>RXUBR</name> 540 <description>RX Used Bit Read Interrupt Enable</description> 541 <bitOffset>2</bitOffset> 542 <bitWidth>1</bitWidth> 543 <access>read-write</access> 544 </field> 545 <field> 546 <name>TXUBR</name> 547 <description>TX Used Bit Read Interrupt Enable</description> 548 <bitOffset>3</bitOffset> 549 <bitWidth>1</bitWidth> 550 <access>read-write</access> 551 </field> 552 <field> 553 <name>TXUR</name> 554 <description>Ethernet Transmit Underrun Interrupt Enable</description> 555 <bitOffset>4</bitOffset> 556 <bitWidth>1</bitWidth> 557 <access>read-write</access> 558 </field> 559 <field> 560 <name>RLE</name> 561 <description>Retry Limit Exceeded Interrupt Enable</description> 562 <bitOffset>5</bitOffset> 563 <bitWidth>1</bitWidth> 564 <access>read-write</access> 565 </field> 566 <field> 567 <name>TXERR</name> 568 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Enable</description> 569 <bitOffset>6</bitOffset> 570 <bitWidth>1</bitWidth> 571 <access>read-write</access> 572 </field> 573 <field> 574 <name>TXCMPL</name> 575 <description>Transmit Complete Interrupt Enable</description> 576 <bitOffset>7</bitOffset> 577 <bitWidth>1</bitWidth> 578 <access>read-write</access> 579 </field> 580 <field> 581 <name>LC</name> 582 <description>Link Change Interrupt Enable</description> 583 <bitOffset>9</bitOffset> 584 <bitWidth>1</bitWidth> 585 <access>read-write</access> 586 </field> 587 <field> 588 <name>RXOR</name> 589 <description>Receive Overrun Interrupt Enable</description> 590 <bitOffset>10</bitOffset> 591 <bitWidth>1</bitWidth> 592 <access>read-write</access> 593 </field> 594 <field> 595 <name>HRESPNO</name> 596 <description>hresp not OK Interrupt Enable</description> 597 <bitOffset>11</bitOffset> 598 <bitWidth>1</bitWidth> 599 <access>read-write</access> 600 </field> 601 <field> 602 <name>PPR</name> 603 <description>Pause Packet Received Interrupt Enable</description> 604 <bitOffset>12</bitOffset> 605 <bitWidth>1</bitWidth> 606 <access>read-write</access> 607 </field> 608 <field> 609 <name>PTZ</name> 610 <description>Pause Time Zero Interrupt Enable</description> 611 <bitOffset>13</bitOffset> 612 <bitWidth>1</bitWidth> 613 <access>read-write</access> 614 </field> 615 </fields> 616 </register> 617 <register> 618 <name>INT_DIS</name> 619 <description>Interrupt Disable Register.</description> 620 <addressOffset>0x2C</addressOffset> 621 <access>write-only</access> 622 <fields> 623 <field> 624 <name>MPS</name> 625 <description>Management Packet Sent Interrupt Disable</description> 626 <bitOffset>0</bitOffset> 627 <bitWidth>1</bitWidth> 628 <access>read-write</access> 629 </field> 630 <field> 631 <name>RXCMPL</name> 632 <description>Receive Complete Interrupt Disable</description> 633 <bitOffset>1</bitOffset> 634 <bitWidth>1</bitWidth> 635 <access>read-write</access> 636 </field> 637 <field> 638 <name>RXUBR</name> 639 <description>RX Used Bit Read Interrupt Disable</description> 640 <bitOffset>2</bitOffset> 641 <bitWidth>1</bitWidth> 642 <access>read-write</access> 643 </field> 644 <field> 645 <name>TXUBR</name> 646 <description>TX Used Bit Read Interrupt Disable</description> 647 <bitOffset>3</bitOffset> 648 <bitWidth>1</bitWidth> 649 <access>read-write</access> 650 </field> 651 <field> 652 <name>TXUR</name> 653 <description>Ethernet Transmit Underrun Interrupt Disable</description> 654 <bitOffset>4</bitOffset> 655 <bitWidth>1</bitWidth> 656 <access>read-write</access> 657 </field> 658 <field> 659 <name>RLE</name> 660 <description>Retry Limit Exceeded Interrupt Disable</description> 661 <bitOffset>5</bitOffset> 662 <bitWidth>1</bitWidth> 663 <access>read-write</access> 664 </field> 665 <field> 666 <name>TXERR</name> 667 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Disable</description> 668 <bitOffset>6</bitOffset> 669 <bitWidth>1</bitWidth> 670 <access>read-write</access> 671 </field> 672 <field> 673 <name>TXCMPL</name> 674 <description>Transmit Complete Interrupt Disable</description> 675 <bitOffset>7</bitOffset> 676 <bitWidth>1</bitWidth> 677 <access>read-write</access> 678 </field> 679 <field> 680 <name>LC</name> 681 <description>Link Change Interrupt Disable</description> 682 <bitOffset>9</bitOffset> 683 <bitWidth>1</bitWidth> 684 <access>read-write</access> 685 </field> 686 <field> 687 <name>RXOR</name> 688 <description>Receive Overrun Interrupt Disable</description> 689 <bitOffset>10</bitOffset> 690 <bitWidth>1</bitWidth> 691 <access>read-write</access> 692 </field> 693 <field> 694 <name>HRESPNO</name> 695 <description>hresp not OK Interrupt Disable</description> 696 <bitOffset>11</bitOffset> 697 <bitWidth>1</bitWidth> 698 <access>read-write</access> 699 </field> 700 <field> 701 <name>PPR</name> 702 <description>Pause Packet Received Interrupt Disable</description> 703 <bitOffset>12</bitOffset> 704 <bitWidth>1</bitWidth> 705 <access>read-write</access> 706 </field> 707 <field> 708 <name>PTZ</name> 709 <description>Pause Time Zero Interrupt Disable</description> 710 <bitOffset>13</bitOffset> 711 <bitWidth>1</bitWidth> 712 <access>read-write</access> 713 </field> 714 </fields> 715 </register> 716 <register> 717 <name>INT_MASK</name> 718 <description>Interrupt Mask Register.</description> 719 <addressOffset>0x30</addressOffset> 720 <access>read-only</access> 721 <fields> 722 <field> 723 <name>MPS</name> 724 <description>Management Packet Sent Interrupt Mask</description> 725 <bitOffset>0</bitOffset> 726 <bitWidth>1</bitWidth> 727 <access>read-write</access> 728 </field> 729 <field> 730 <name>RXCMPL</name> 731 <description>Receive Complete Interrupt Mask</description> 732 <bitOffset>1</bitOffset> 733 <bitWidth>1</bitWidth> 734 <access>read-write</access> 735 </field> 736 <field> 737 <name>RXUBR</name> 738 <description>RX Used Bit Read Interrupt Mask</description> 739 <bitOffset>2</bitOffset> 740 <bitWidth>1</bitWidth> 741 <access>read-write</access> 742 </field> 743 <field> 744 <name>TXUBR</name> 745 <description>TX Used Bit Read Interrupt Mask</description> 746 <bitOffset>3</bitOffset> 747 <bitWidth>1</bitWidth> 748 <access>read-write</access> 749 </field> 750 <field> 751 <name>TXUR</name> 752 <description>Ethernet Transmit Underrun Interrupt Mask</description> 753 <bitOffset>4</bitOffset> 754 <bitWidth>1</bitWidth> 755 <access>read-write</access> 756 </field> 757 <field> 758 <name>RLE</name> 759 <description>Retry Limit Exceeded Interrupt Mask</description> 760 <bitOffset>5</bitOffset> 761 <bitWidth>1</bitWidth> 762 <access>read-write</access> 763 </field> 764 <field> 765 <name>TXERR</name> 766 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Mask</description> 767 <bitOffset>6</bitOffset> 768 <bitWidth>1</bitWidth> 769 <access>read-write</access> 770 </field> 771 <field> 772 <name>TXCMPL</name> 773 <description>Transmit Complete Interrupt Mask</description> 774 <bitOffset>7</bitOffset> 775 <bitWidth>1</bitWidth> 776 <access>read-write</access> 777 </field> 778 <field> 779 <name>LC</name> 780 <description>Link Change Interrupt Mask</description> 781 <bitOffset>9</bitOffset> 782 <bitWidth>1</bitWidth> 783 <access>read-write</access> 784 </field> 785 <field> 786 <name>RXOR</name> 787 <description>Receive Overrun Interrupt Mask</description> 788 <bitOffset>10</bitOffset> 789 <bitWidth>1</bitWidth> 790 <access>read-write</access> 791 </field> 792 <field> 793 <name>HRESPNO</name> 794 <description>hresp not OK Interrupt Mask</description> 795 <bitOffset>11</bitOffset> 796 <bitWidth>1</bitWidth> 797 <access>read-write</access> 798 </field> 799 <field> 800 <name>PPR</name> 801 <description>Pause Packet Received Interrupt Mask</description> 802 <bitOffset>12</bitOffset> 803 <bitWidth>1</bitWidth> 804 <access>read-write</access> 805 </field> 806 <field> 807 <name>PTZ</name> 808 <description>Pause Time Zero Interrupt Mask</description> 809 <bitOffset>13</bitOffset> 810 <bitWidth>1</bitWidth> 811 <access>read-write</access> 812 </field> 813 </fields> 814 </register> 815 <register> 816 <name>PHY_MT</name> 817 <description>PHY Maintenance Register.</description> 818 <addressOffset>0x34</addressOffset> 819 <fields> 820 <field> 821 <name>DATA</name> 822 <description>PHY Data. For a write operation this field is the data to be written to the PHY. </description> 823 <bitOffset>0</bitOffset> 824 <bitWidth>16</bitWidth> 825 <access>read-write</access> 826 </field> 827 <field> 828 <name>CODE</name> 829 <description>Has to be 10b </description> 830 <bitOffset>16</bitOffset> 831 <bitWidth>2</bitWidth> 832 <access>read-write</access> 833 </field> 834 <field> 835 <name>REGADDR</name> 836 <description>Register Address. Specifies the register in the PHY to access.</description> 837 <bitOffset>18</bitOffset> 838 <bitWidth>5</bitWidth> 839 <access>read-write</access> 840 </field> 841 <field> 842 <name>PHYADDR</name> 843 <description>PHY Address. Specifies the PHY to access.</description> 844 <bitOffset>23</bitOffset> 845 <bitWidth>5</bitWidth> 846 <access>read-write</access> 847 </field> 848 <field> 849 <name>OP</name> 850 <description>Operation</description> 851 <bitOffset>28</bitOffset> 852 <bitWidth>2</bitWidth> 853 <access>read-write</access> 854 <enumeratedValues> 855 <enumeratedValue> 856 <name>write</name> 857 <description>Write</description> 858 <value>1</value> 859 </enumeratedValue> 860 <enumeratedValue> 861 <name>read</name> 862 <description>Read</description> 863 <value>2</value> 864 </enumeratedValue> 865 </enumeratedValues> 866 </field> 867 <field> 868 <name>SOP</name> 869 <description>TBD </description> 870 <bitOffset>30</bitOffset> 871 <bitWidth>2</bitWidth> 872 <access>read-write</access> 873 </field> 874 </fields> 875 </register> 876 <register> 877 <name>PT</name> 878 <description>Pause Time Register.</description> 879 <addressOffset>0x38</addressOffset> 880 <access>read-only</access> 881 <fields> 882 <field> 883 <name>TIME</name> 884 <description>Pause Time. Stores the current value of the pause time register, which is decremented every 512 bit times.</description> 885 <bitOffset>0</bitOffset> 886 <bitWidth>16</bitWidth> 887 <access>read-write</access> 888 </field> 889 </fields> 890 </register> 891 <register> 892 <name>PFR</name> 893 <description>Pause Frame Received OK.</description> 894 <addressOffset>0x3C</addressOffset> 895 <fields> 896 <field> 897 <name>PFR</name> 898 <description>Pause Frames Received OK. A 16-bit register counting the number of good pause frames received. </description> 899 <bitOffset>0</bitOffset> 900 <bitWidth>16</bitWidth> 901 <access>read-write</access> 902 </field> 903 </fields> 904 </register> 905 <register> 906 <name>FTOK</name> 907 <description>Frames Transmitted OK.</description> 908 <addressOffset>0x40</addressOffset> 909 <fields> 910 <field> 911 <name>FTOK</name> 912 <description>Frames Transmitted OK. A 32-bit register counting the number of frames successfully transmitted, i.e. no underrun and not too many retries.</description> 913 <bitOffset>0</bitOffset> 914 <bitWidth>32</bitWidth> 915 <access>read-write</access> 916 </field> 917 </fields> 918 </register> 919 <register> 920 <name>SCF</name> 921 <description>Single Collision Frames.</description> 922 <addressOffset>0x44</addressOffset> 923 <fields> 924 <field> 925 <name>SCF</name> 926 <description>Single Collision Frames. A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no underrun.</description> 927 <bitOffset>0</bitOffset> 928 <bitWidth>16</bitWidth> 929 <access>read-write</access> 930 </field> 931 </fields> 932 </register> 933 <register> 934 <name>MCF</name> 935 <description>Multiple Collision Frames.</description> 936 <addressOffset>0x48</addressOffset> 937 <fields> 938 <field> 939 <name>MCF</name> 940 <description>Multiple Collision Frames. A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no underrun and not too many retries.</description> 941 <bitOffset>0</bitOffset> 942 <bitWidth>16</bitWidth> 943 <access>read-write</access> 944 </field> 945 </fields> 946 </register> 947 <register> 948 <name>FROK</name> 949 <description>Fames Received OK.</description> 950 <addressOffset>0x4C</addressOffset> 951 <fields> 952 <field> 953 <name>FROK</name> 954 <description>Frames Received OK. A 24-bit register counting the number of good packets received</description> 955 <bitOffset>0</bitOffset> 956 <bitWidth>24</bitWidth> 957 <access>read-write</access> 958 </field> 959 </fields> 960 </register> 961 <register> 962 <name>FCS_ERR</name> 963 <description>Frame Check Sequence Errors.</description> 964 <addressOffset>0x50</addressOffset> 965 <fields> 966 <field> 967 <name>FCSERR</name> 968 <description>Frame Check Sequence Errors.</description> 969 <bitOffset>0</bitOffset> 970 <bitWidth>8</bitWidth> 971 <access>read-write</access> 972 </field> 973 </fields> 974 </register> 975 <register> 976 <name>ALGN_ERR</name> 977 <description>Alignment Errors.</description> 978 <addressOffset>0x54</addressOffset> 979 <fields> 980 <field> 981 <name>ALGNERR</name> 982 <description>Alignment Errors. </description> 983 <bitOffset>0</bitOffset> 984 <bitWidth>8</bitWidth> 985 <access>read-write</access> 986 </field> 987 </fields> 988 </register> 989 <register> 990 <name>DFTXF</name> 991 <description>Deferred Transmission Frames.</description> 992 <addressOffset>0x58</addressOffset> 993 <fields> 994 <field> 995 <name>DFTXF</name> 996 <description>Deferred Transmission Frames. A 16-bit register counting the number of packets experiencing deferral due to carrier sense being active on their first attempt at transmission</description> 997 <bitOffset>0</bitOffset> 998 <bitWidth>16</bitWidth> 999 <access>read-write</access> 1000 </field> 1001 </fields> 1002 </register> 1003 <register> 1004 <name>LC</name> 1005 <description>Late Collisions.</description> 1006 <addressOffset>0x5C</addressOffset> 1007 <fields> 1008 <field> 1009 <name>LC</name> 1010 <description>Late Collisions. An 8-bit register counting the number of packets that experience a collision after the slot time (512 bits) has expired.</description> 1011 <bitOffset>0</bitOffset> 1012 <bitWidth>8</bitWidth> 1013 <access>read-write</access> 1014 </field> 1015 </fields> 1016 </register> 1017 <register> 1018 <name>EC</name> 1019 <description>Excessive Collisions.</description> 1020 <addressOffset>0x60</addressOffset> 1021 <fields> 1022 <field> 1023 <name>EC</name> 1024 <description>Excessive Collisions. An 8-bit register counting the number of packets that failed to be transmitted because they experienced 16 collisions.</description> 1025 <bitOffset>0</bitOffset> 1026 <bitWidth>8</bitWidth> 1027 <access>read-write</access> 1028 </field> 1029 </fields> 1030 </register> 1031 <register> 1032 <name>TUR_ERR</name> 1033 <description>Transmit Underrun Errors.</description> 1034 <addressOffset>0x64</addressOffset> 1035 <fields> 1036 <field> 1037 <name>TURERR</name> 1038 <description>Transmit Underrun Error. An 8-bit register counting the number of packets not transmitted due to a transmit FIFO underrun.</description> 1039 <bitOffset>0</bitOffset> 1040 <bitWidth>8</bitWidth> 1041 <access>read-write</access> 1042 </field> 1043 </fields> 1044 </register> 1045 <register> 1046 <name>CS_ERR</name> 1047 <description>Carrier Sense Errors.</description> 1048 <addressOffset>0x68</addressOffset> 1049 <fields> 1050 <field> 1051 <name>CSERR</name> 1052 <description>An 8-bit register counting the number of packets transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit packet without collision (no underrun).</description> 1053 <bitOffset>0</bitOffset> 1054 <bitWidth>8</bitWidth> 1055 <access>read-write</access> 1056 </field> 1057 </fields> 1058 </register> 1059 <register> 1060 <name>RR_ERR</name> 1061 <description>Receive Resource Errors.</description> 1062 <addressOffset>0x6C</addressOffset> 1063 <fields> 1064 <field> 1065 <name>RRERR</name> 1066 <description>Receive Resource Errors. A 16 bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available.</description> 1067 <bitOffset>0</bitOffset> 1068 <bitWidth>16</bitWidth> 1069 <access>read-write</access> 1070 </field> 1071 </fields> 1072 </register> 1073 <register> 1074 <name>ROR_ERR</name> 1075 <description>Receive Overrun Errors.</description> 1076 <addressOffset>0x70</addressOffset> 1077 <fields> 1078 <field> 1079 <name>RORERR</name> 1080 <description>Receive Overruns. An 8 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.</description> 1081 <bitOffset>0</bitOffset> 1082 <bitWidth>8</bitWidth> 1083 <access>read-write</access> 1084 </field> 1085 </fields> 1086 </register> 1087 <register> 1088 <name>RS_ERR</name> 1089 <description>Receive Symbol Errors.</description> 1090 <addressOffset>0x74</addressOffset> 1091 <fields> 1092 <field> 1093 <name>RSERR</name> 1094 <description>Receive Symbol Errors. An 8-bit register counting the number of packets that had EMAC_RXER asserted during reception.</description> 1095 <bitOffset>0</bitOffset> 1096 <bitWidth>8</bitWidth> 1097 <access>read-write</access> 1098 </field> 1099 </fields> 1100 </register> 1101 <register> 1102 <name>EL_ERR</name> 1103 <description>Excessive Length Errors.</description> 1104 <addressOffset>0x78</addressOffset> 1105 <fields> 1106 <field> 1107 <name>ELERR</name> 1108 <description>Excessive Length Errors. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register;</description> 1109 <bitOffset>0</bitOffset> 1110 <bitWidth>8</bitWidth> 1111 <access>read-write</access> 1112 </field> 1113 </fields> 1114 </register> 1115 <register> 1116 <name>RJ</name> 1117 <description>Receive Jabber.</description> 1118 <addressOffset>0x7C</addressOffset> 1119 <fields> 1120 <field> 1121 <name>RJERR</name> 1122 <description>Receive Jabbers. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register; </description> 1123 <bitOffset>0</bitOffset> 1124 <bitWidth>8</bitWidth> 1125 <access>read-write</access> 1126 </field> 1127 </fields> 1128 </register> 1129 <register> 1130 <name>USF</name> 1131 <description>Undersize Frames.</description> 1132 <addressOffset>0x80</addressOffset> 1133 <fields> 1134 <field> 1135 <name>USF</name> 1136 <description>Undersize Frames. An 8-bit register counting the number of packets received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.</description> 1137 <bitOffset>0</bitOffset> 1138 <bitWidth>8</bitWidth> 1139 <access>read-write</access> 1140 </field> 1141 </fields> 1142 </register> 1143 <register> 1144 <name>SQE_ERR</name> 1145 <description>SQE Test Errors.</description> 1146 <addressOffset>0x84</addressOffset> 1147 <fields> 1148 <field> 1149 <name>SQEERR</name> 1150 <description>SQE Test Errors. An 8-bit register counting the number of packets where collision was not asserted within 96 bit times (an interframe gap) of EMAC_TXEN being deasserted in half duplex mode.</description> 1151 <bitOffset>0</bitOffset> 1152 <bitWidth>8</bitWidth> 1153 <access>read-write</access> 1154 </field> 1155 </fields> 1156 </register> 1157 <register> 1158 <name>RLFM</name> 1159 <description>Received Length Field Mismatch.</description> 1160 <addressOffset>0x88</addressOffset> 1161 <fields> 1162 <field> 1163 <name>RLFM</name> 1164 <description>Receive length field mismatch </description> 1165 <bitOffset>0</bitOffset> 1166 <bitWidth>8</bitWidth> 1167 <access>read-write</access> 1168 </field> 1169 </fields> 1170 </register> 1171 <register> 1172 <name>TPF</name> 1173 <description>Transmitted Pause Frames.</description> 1174 <addressOffset>0x8C</addressOffset> 1175 <fields> 1176 <field> 1177 <name>TPF</name> 1178 <description>Transmitted Pause Frames. A 16-bit register counting the number of pause packets transmitted.</description> 1179 <bitOffset>0</bitOffset> 1180 <bitWidth>16</bitWidth> 1181 <access>read-write</access> 1182 </field> 1183 </fields> 1184 </register> 1185 <register> 1186 <name>HASHL</name> 1187 <description>Hash Register Bottom [31:0].</description> 1188 <addressOffset>0x90</addressOffset> 1189 <fields> 1190 <field> 1191 <name>HASH</name> 1192 <description>Bits 31:0 of the hash address register. See Hash Addressing</description> 1193 <bitOffset>0</bitOffset> 1194 <bitWidth>32</bitWidth> 1195 <access>read-write</access> 1196 </field> 1197 </fields> 1198 </register> 1199 <register> 1200 <name>HASHH</name> 1201 <description>Hash Register top [63:32].</description> 1202 <addressOffset>0x94</addressOffset> 1203 <fields> 1204 <field> 1205 <name>HASH</name> 1206 <description>Bits 63:32 of the hash address register. See Hash Addressing</description> 1207 <bitOffset>0</bitOffset> 1208 <bitWidth>32</bitWidth> 1209 <access>read-write</access> 1210 </field> 1211 </fields> 1212 </register> 1213 <register> 1214 <name>SA1L</name> 1215 <description>Specific Address 1 Bottom.</description> 1216 <addressOffset>0x98</addressOffset> 1217 <fields> 1218 <field> 1219 <name>ADDR</name> 1220 <description>MAC Specific Address 1 [31:0]. Least significant bits of the MAC specific address 1, i.e. bits 31:0. This field is used for transmission of pause packets</description> 1221 <bitOffset>0</bitOffset> 1222 <bitWidth>32</bitWidth> 1223 <access>read-write</access> 1224 </field> 1225 </fields> 1226 </register> 1227 <register> 1228 <name>SA1H</name> 1229 <description>Specific Address 1 Top.</description> 1230 <addressOffset>0x9C</addressOffset> 1231 <fields> 1232 <field> 1233 <name>ADDR</name> 1234 <description>MAC Specific Address 1 [47:32]. Most significant bits of the MAC specific address 1, i.e. bits 47:32.</description> 1235 <bitOffset>0</bitOffset> 1236 <bitWidth>16</bitWidth> 1237 <access>read-write</access> 1238 </field> 1239 </fields> 1240 </register> 1241 <register> 1242 <name>SA2L</name> 1243 <description>Specific Address 2 Bottom.</description> 1244 <addressOffset>0xA0</addressOffset> 1245 <fields> 1246 <field> 1247 <name>ADDR</name> 1248 <description>MAC Specific Address 2 [31:0]. Least significant bits of the MAC specific address 2, i.e. bits 31:0. This field is used for transmission of pause packets</description> 1249 <bitOffset>0</bitOffset> 1250 <bitWidth>32</bitWidth> 1251 <access>read-write</access> 1252 </field> 1253 </fields> 1254 </register> 1255 <register> 1256 <name>SA2H</name> 1257 <description>Specific Address 2 Top.</description> 1258 <addressOffset>0xA4</addressOffset> 1259 <fields> 1260 <field> 1261 <name>ADDR</name> 1262 <description>MAC Specific Address 2 [47:32]. Most significant bits of the MAC specific address 2, i.e. bits 47:32.</description> 1263 <bitOffset>0</bitOffset> 1264 <bitWidth>16</bitWidth> 1265 <access>read-write</access> 1266 </field> 1267 </fields> 1268 </register> 1269 <register> 1270 <name>SA3L</name> 1271 <description>Specific Address 3 Bottom.</description> 1272 <addressOffset>0xA8</addressOffset> 1273 <fields> 1274 <field> 1275 <name>ADDR</name> 1276 <description>MAC Specific Address 3 [31:0]. Least significant bits of the MAC specific address 3, i.e. bits 31:0. This field is used for transmission of pause packets</description> 1277 <bitOffset>0</bitOffset> 1278 <bitWidth>32</bitWidth> 1279 <access>read-write</access> 1280 </field> 1281 </fields> 1282 </register> 1283 <register> 1284 <name>SA3H</name> 1285 <description>Specific Address 3 Top.</description> 1286 <addressOffset>0xAC</addressOffset> 1287 <fields> 1288 <field> 1289 <name>ADDR</name> 1290 <description>MAC Specific Address 3 [47:32]. Most significant bits of the MAC specific address 3, i.e. bits 47:32.</description> 1291 <bitOffset>0</bitOffset> 1292 <bitWidth>16</bitWidth> 1293 <access>read-write</access> 1294 </field> 1295 </fields> 1296 </register> 1297 <register> 1298 <name>SA4L</name> 1299 <description>Specific Address 4 Bottom.</description> 1300 <addressOffset>0xB0</addressOffset> 1301 <fields> 1302 <field> 1303 <name>ADDR</name> 1304 <description>MAC Specific Address 4 [31:0]. Least significant bits of the MAC specific address 4, i.e. bits 31:0. This field is used for transmission of pause packets</description> 1305 <bitOffset>0</bitOffset> 1306 <bitWidth>32</bitWidth> 1307 <access>read-write</access> 1308 </field> 1309 </fields> 1310 </register> 1311 <register> 1312 <name>SA4H</name> 1313 <description>Specific Address 4 Top.</description> 1314 <addressOffset>0xB4</addressOffset> 1315 <fields> 1316 <field> 1317 <name>ADDR</name> 1318 <description>MAC Specific Address 4 [47:32]. Most significant bits of the MAC specific address 4, i.e. bits 47:32.</description> 1319 <bitOffset>0</bitOffset> 1320 <bitWidth>16</bitWidth> 1321 <access>read-write</access> 1322 </field> 1323 </fields> 1324 </register> 1325 <register> 1326 <name>TID_CK</name> 1327 <description>Type ID Checking.</description> 1328 <addressOffset>0xB8</addressOffset> 1329 <fields> 1330 <field> 1331 <name>TID</name> 1332 <description>Type ID Checking. For use in comparisons with received frames TypeID/Length field.</description> 1333 <bitOffset>0</bitOffset> 1334 <bitWidth>16</bitWidth> 1335 <access>read-write</access> 1336 </field> 1337 </fields> 1338 </register> 1339 <register> 1340 <name>TPQ</name> 1341 <description>Transmit Pause Quantum.</description> 1342 <addressOffset>0xBC</addressOffset> 1343 <fields> 1344 <field> 1345 <name>TPQ</name> 1346 <description>Transmit Pause Quantum. Used in hardware generation of transmitted pause packets as value for pause quantum</description> 1347 <bitOffset>0</bitOffset> 1348 <bitWidth>16</bitWidth> 1349 <access>read-write</access> 1350 </field> 1351 </fields> 1352 </register> 1353 <register> 1354 <name>USRIO</name> 1355 <description>User Input Output Register</description> 1356 <addressOffset>0xC0</addressOffset> 1357 <fields> 1358 <field> 1359 <name>MII</name> 1360 <description>TBD</description> 1361 <bitOffset>0</bitOffset> 1362 <bitWidth>1</bitWidth> 1363 <access>read-write</access> 1364 </field> 1365 </fields> 1366 </register> 1367 <register> 1368 <name>WOL</name> 1369 <description>Wake On LAN Register</description> 1370 <addressOffset>0xC4</addressOffset> 1371 <fields> 1372 <field> 1373 <name>IP</name> 1374 <description>TBD</description> 1375 <bitOffset>0</bitOffset> 1376 <bitWidth>16</bitWidth> 1377 <access>read-write</access> 1378 </field> 1379 <field> 1380 <name>MAG</name> 1381 <description>TBD</description> 1382 <bitOffset>16</bitOffset> 1383 <bitWidth>1</bitWidth> 1384 <access>read-write</access> 1385 </field> 1386 <field> 1387 <name>ARP</name> 1388 <description>TBD</description> 1389 <bitOffset>17</bitOffset> 1390 <bitWidth>1</bitWidth> 1391 <access>read-write</access> 1392 </field> 1393 <field> 1394 <name>SA1</name> 1395 <description>TBD</description> 1396 <bitOffset>18</bitOffset> 1397 <bitWidth>1</bitWidth> 1398 <access>read-write</access> 1399 </field> 1400 <field> 1401 <name>MTI</name> 1402 <description>TBD</description> 1403 <bitOffset>19</bitOffset> 1404 <bitWidth>1</bitWidth> 1405 <access>read-write</access> 1406 </field> 1407 </fields> 1408 </register> 1409 <register> 1410 <name>REV</name> 1411 <description>Revision register.</description> 1412 <addressOffset>0xFC</addressOffset> 1413 <access>read-only</access> 1414 <fields> 1415 <field> 1416 <name>REV</name> 1417 <description>Revision Reference. Fixed two byte value specific to revision of design.</description> 1418 <bitOffset>0</bitOffset> 1419 <bitWidth>16</bitWidth> 1420 <access>read-write</access> 1421 </field> 1422 <field> 1423 <name>PART</name> 1424 <description>Part Reference. For Ethernet MAC design, this is fixed at 0x01.</description> 1425 <bitOffset>16</bitOffset> 1426 <bitWidth>16</bitWidth> 1427 <access>read-write</access> 1428 </field> 1429 </fields> 1430 </register> 1431 </registers> 1432 </peripheral> 1433<!-- EMAC: 10/100 Ethernet MAC --> 1434</device> 1435
