EMAC 10/100 Ethernet MAC. 0x4004F000 0 0x1000 registers EMAC EMAC IRQ 64 CN Network Control Register. 0x00 0x00 LB Loopback. 0 1 read-write LBL Loopback local. 1 1 read-write RXEN Receive Enable. 2 1 read-write TXEN Transmit Enable. 3 1 read-write MPEN Management Port Enable. 4 1 read-write CLST Clear Statistics. 5 1 write-only INCST Increment Statistics. 6 1 write-only WREN Write enable for statistics registers. 7 1 read-write BP Back pressure. 8 1 read-write TXSTART Transmission start. 9 1 write-only TXHALT Transmit halt. 10 1 write-only TXPF Transmit pause frame. 11 1 write-only TXZQPF Transmit zero quantum pause frame. 12 1 write-only CFG Network Configuration Register. 0x04 SPD Speed Select. 0 1 read-write FULLDPLX Full Duplex. If set to 1 the transmit block ignores the state of collision and carrier sense and allows Rx while transmitting. 1 1 read-write BITRATE Bit Rate. Writing 1 to this bit configures the interface for serial operation. 2 1 read-write JUMBOFR Jumbo Frames. Writing 1 to this bit enables jumbo frames of up to 10,240 bytes to be accepted. 3 1 read-write COPYAF Copy All Frames. If 1, all valid frames will be received. 4 1 read-write NOBC No Broadcast. If 1, frames addressed to the broadcast address of all ones will not be received. 5 1 write-only MHEN Multicast Hash Enable. If 1, multicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register. 6 1 write-only UHEN Unicast Hash Enable. If 1, unicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register. 7 1 read-write RXFR Receive 1536 Byte Frames. Writing 1 to this bit means the MAC receives packets up to 1536 bytes in length. Normally the MAC rejects any packet above 1518 bytes 8 1 read-write EAE TBD 9 1 read-write MDCCLK MDC Frequency. Set according to PCLK speed. This field determines by what number PCLK is divided to generate MDC. 10 2 write-only div8 PCLK up to 20MHz 0 div16 PCLK up to 40MHz 1 div32 PCLK up to 80MHz 2 div64 PCLK up to 160MHz 3 TXPF Transmit pause frame. 11 1 write-only RTTST Retry Test. Must be set to zero for normal operation. If set to 1, the back-off between collisions is always one slot time. 12 1 write-only PAUSEEN Pause Enable. If 1, Ethernet packet transmission pauses when a valid pause packet is received. 13 1 write-only RXBUFFOFS Receive buffer offset. These bits indicate the number of bytes by which the received data is offset from the start of the first receive buffer. 14 2 write-only RXLFCEN Receive length field checking enable. If 1, packets with measured lengths shorter than their length fields are discarded. Packets containing a type ID in bytes 13 and 14 (length/type field ≥0600) are not counted as length errors. 16 1 write-only DCRXFCS Discard receive FCS. If 1, the FCS field of received frames will not be copied to memory. 17 1 write-only HDPLXRXEN Enable packets to be received in half-duplex mode while transmitting. 18 1 write-only IGNRXFCS Ignore RX FCS. If 1, packets with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0. 19 1 write-only STATUS Network Status Register. 0x08 read-only LINK LINK pin status. Returns status of EMAC_LINK pin. 0 1 read-write MDIO MDIO pin status. Returns status of the EMAC_MDIO pin. Use the PHY maintenance register for reading managed frames rather than this bit. 1 1 read-write IDLE PHY management logic status. 2 1 read-write TX_ST Transmit Status Register. 0x14 UBR Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Write 1 to clear this bit. 0 1 read-write COLS Collision Occurred. Set when a collision occurs. Write 1 to clear this bit. 1 1 read-write RTYLIM Retry Limit Exceeded. Set when the retry limit has been exceeded. Write 1 to clear this bit. 2 1 read-write TXGO Transmit Go. If 1, transmit is active. 3 1 read-write BEMF Buffers Exhausted Mid Frame. If the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and EMAC_TXER asserted. Write 1 to clear this bit. 4 1 read-write TXCMPL Transmit Complete. Set when a frame has been transmitted. Write 1 to clear this bit. 5 1 read-write TXUR Transmit Underrun. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad. Write 1 to clear this bit. 6 1 read-write RXBUF_PTR Receive Buffer Queue Pointer Register. 0x18 RXBUF Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. 2 30 read-write TXBUF_PTR Transmit Buffer Queue Pointer Register. 0x1C TXBUF Transmit buffer queue pointer. Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted. 2 30 read-write RX_ST Receive Status Register. 0x20 BNA Buffer Not Available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time a new frame starts until a valid pointer is found. This bit will be set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Write 1 to clear this bit. 0 1 read-write FR Frame Received. One or more frames have been received and placed in memory. Write 1 to clear this bit. 1 1 read-write RXOR Receive Overrun. The DMA block was unable to store the receive frame to memory. Either because the AHB bus was not granted in time or because a not OK hresp was returned. The buffer will be recovered if this happens. Write 1 to clear this bit. 2 1 read-write INT_ST Interrupt Status Register. 0x24 MPS Management Packet Sent Interrupt Status. The PHY maintenance register has completed its operation. Cleared when read. 0 1 read-write RXCMPL Receive Complete Interrupt Status. Set when a frame has been stored in memory. Cleared when read. 1 1 read-write RXUBR RX Used Bit Read Interrupt Status. Set when a receive buffer descriptor is read with its used bit set. Cleared when read. 2 1 read-write TXUBR TX Used Bit Read Interrupt Status. Set when a transmit buffer descriptor is read with its used bit set. Cleared when read 3 1 read-write TXUR Ethernet Transmit Underrun Interrupt Status. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad CRC and forces EMAC_TXER high. Cleared when read. 4 1 read-write RLE Retry Limit Exceeded Interrupt Status. Transmit error. Cleared when read. 5 1 read-write TXERR Transmit Buffers Exhausted In Mid-frame Interrupt Status. Transmit error. Cleared when read. 6 1 read-write TXCMPL Transmit Complete Interrupt Status. Set when a frame has been transmitted. Cleared when read. 7 1 read-write LC Link Change Interrupt Status. Set when the external link signal changes. Cleared when read. 9 1 read-write RXOR Receive Overrun Interrupt Status. Set when the receive overrun status bit gets set. Cleared when read. 10 1 read-write HRESPNO hresp not OK Interrupt Status. Set when the DMA block sees hresp not OK. Cleared when read. 11 1 read-write PPR Pause Packet Received Interrupt Status. Indicates a valid pause packet has been received. Cleared when read. 12 1 read-write PTZ Pause Time Zero Interrupt Status. Set when the MAC Pause Time register (MAC_PT) decrements to zero. Cleared when read. 13 1 read-write INT_EN Interrupt Enable Register. 0x28 write-only MPS Management Packet Sent Interrupt Enable 0 1 read-write RXCMPL Receive Complete Interrupt Enable 1 1 read-write RXUBR RX Used Bit Read Interrupt Enable 2 1 read-write TXUBR TX Used Bit Read Interrupt Enable 3 1 read-write TXUR Ethernet Transmit Underrun Interrupt Enable 4 1 read-write RLE Retry Limit Exceeded Interrupt Enable 5 1 read-write TXERR Transmit Buffers Exhausted In Mid-frame Interrupt Enable 6 1 read-write TXCMPL Transmit Complete Interrupt Enable 7 1 read-write LC Link Change Interrupt Enable 9 1 read-write RXOR Receive Overrun Interrupt Enable 10 1 read-write HRESPNO hresp not OK Interrupt Enable 11 1 read-write PPR Pause Packet Received Interrupt Enable 12 1 read-write PTZ Pause Time Zero Interrupt Enable 13 1 read-write INT_DIS Interrupt Disable Register. 0x2C write-only MPS Management Packet Sent Interrupt Disable 0 1 read-write RXCMPL Receive Complete Interrupt Disable 1 1 read-write RXUBR RX Used Bit Read Interrupt Disable 2 1 read-write TXUBR TX Used Bit Read Interrupt Disable 3 1 read-write TXUR Ethernet Transmit Underrun Interrupt Disable 4 1 read-write RLE Retry Limit Exceeded Interrupt Disable 5 1 read-write TXERR Transmit Buffers Exhausted In Mid-frame Interrupt Disable 6 1 read-write TXCMPL Transmit Complete Interrupt Disable 7 1 read-write LC Link Change Interrupt Disable 9 1 read-write RXOR Receive Overrun Interrupt Disable 10 1 read-write HRESPNO hresp not OK Interrupt Disable 11 1 read-write PPR Pause Packet Received Interrupt Disable 12 1 read-write PTZ Pause Time Zero Interrupt Disable 13 1 read-write INT_MASK Interrupt Mask Register. 0x30 read-only MPS Management Packet Sent Interrupt Mask 0 1 read-write RXCMPL Receive Complete Interrupt Mask 1 1 read-write RXUBR RX Used Bit Read Interrupt Mask 2 1 read-write TXUBR TX Used Bit Read Interrupt Mask 3 1 read-write TXUR Ethernet Transmit Underrun Interrupt Mask 4 1 read-write RLE Retry Limit Exceeded Interrupt Mask 5 1 read-write TXERR Transmit Buffers Exhausted In Mid-frame Interrupt Mask 6 1 read-write TXCMPL Transmit Complete Interrupt Mask 7 1 read-write LC Link Change Interrupt Mask 9 1 read-write RXOR Receive Overrun Interrupt Mask 10 1 read-write HRESPNO hresp not OK Interrupt Mask 11 1 read-write PPR Pause Packet Received Interrupt Mask 12 1 read-write PTZ Pause Time Zero Interrupt Mask 13 1 read-write PHY_MT PHY Maintenance Register. 0x34 DATA PHY Data. For a write operation this field is the data to be written to the PHY. 0 16 read-write CODE Has to be 10b 16 2 read-write REGADDR Register Address. Specifies the register in the PHY to access. 18 5 read-write PHYADDR PHY Address. Specifies the PHY to access. 23 5 read-write OP Operation 28 2 read-write write Write 1 read Read 2 SOP TBD 30 2 read-write PT Pause Time Register. 0x38 read-only TIME Pause Time. Stores the current value of the pause time register, which is decremented every 512 bit times. 0 16 read-write PFR Pause Frame Received OK. 0x3C PFR Pause Frames Received OK. A 16-bit register counting the number of good pause frames received. 0 16 read-write FTOK Frames Transmitted OK. 0x40 FTOK Frames Transmitted OK. A 32-bit register counting the number of frames successfully transmitted, i.e. no underrun and not too many retries. 0 32 read-write SCF Single Collision Frames. 0x44 SCF Single Collision Frames. A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no underrun. 0 16 read-write MCF Multiple Collision Frames. 0x48 MCF Multiple Collision Frames. A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no underrun and not too many retries. 0 16 read-write FROK Fames Received OK. 0x4C FROK Frames Received OK. A 24-bit register counting the number of good packets received 0 24 read-write FCS_ERR Frame Check Sequence Errors. 0x50 FCSERR Frame Check Sequence Errors. 0 8 read-write ALGN_ERR Alignment Errors. 0x54 ALGNERR Alignment Errors. 0 8 read-write DFTXF Deferred Transmission Frames. 0x58 DFTXF Deferred Transmission Frames. A 16-bit register counting the number of packets experiencing deferral due to carrier sense being active on their first attempt at transmission 0 16 read-write LC Late Collisions. 0x5C LC Late Collisions. An 8-bit register counting the number of packets that experience a collision after the slot time (512 bits) has expired. 0 8 read-write EC Excessive Collisions. 0x60 EC Excessive Collisions. An 8-bit register counting the number of packets that failed to be transmitted because they experienced 16 collisions. 0 8 read-write TUR_ERR Transmit Underrun Errors. 0x64 TURERR Transmit Underrun Error. An 8-bit register counting the number of packets not transmitted due to a transmit FIFO underrun. 0 8 read-write CS_ERR Carrier Sense Errors. 0x68 CSERR An 8-bit register counting the number of packets transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit packet without collision (no underrun). 0 8 read-write RR_ERR Receive Resource Errors. 0x6C RRERR Receive Resource Errors. A 16 bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 0 16 read-write ROR_ERR Receive Overrun Errors. 0x70 RORERR Receive Overruns. An 8 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun. 0 8 read-write RS_ERR Receive Symbol Errors. 0x74 RSERR Receive Symbol Errors. An 8-bit register counting the number of packets that had EMAC_RXER asserted during reception. 0 8 read-write EL_ERR Excessive Length Errors. 0x78 ELERR Excessive Length Errors. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register; 0 8 read-write RJ Receive Jabber. 0x7C RJERR Receive Jabbers. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register; 0 8 read-write USF Undersize Frames. 0x80 USF Undersize Frames. An 8-bit register counting the number of packets received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error. 0 8 read-write SQE_ERR SQE Test Errors. 0x84 SQEERR SQE Test Errors. An 8-bit register counting the number of packets where collision was not asserted within 96 bit times (an interframe gap) of EMAC_TXEN being deasserted in half duplex mode. 0 8 read-write RLFM Received Length Field Mismatch. 0x88 RLFM Receive length field mismatch 0 8 read-write TPF Transmitted Pause Frames. 0x8C TPF Transmitted Pause Frames. A 16-bit register counting the number of pause packets transmitted. 0 16 read-write HASHL Hash Register Bottom [31:0]. 0x90 HASH Bits 31:0 of the hash address register. See Hash Addressing 0 32 read-write HASHH Hash Register top [63:32]. 0x94 HASH Bits 63:32 of the hash address register. See Hash Addressing 0 32 read-write SA1L Specific Address 1 Bottom. 0x98 ADDR MAC Specific Address 1 [31:0]. Least significant bits of the MAC specific address 1, i.e. bits 31:0. This field is used for transmission of pause packets 0 32 read-write SA1H Specific Address 1 Top. 0x9C ADDR MAC Specific Address 1 [47:32]. Most significant bits of the MAC specific address 1, i.e. bits 47:32. 0 16 read-write SA2L Specific Address 2 Bottom. 0xA0 ADDR MAC Specific Address 2 [31:0]. Least significant bits of the MAC specific address 2, i.e. bits 31:0. This field is used for transmission of pause packets 0 32 read-write SA2H Specific Address 2 Top. 0xA4 ADDR MAC Specific Address 2 [47:32]. Most significant bits of the MAC specific address 2, i.e. bits 47:32. 0 16 read-write SA3L Specific Address 3 Bottom. 0xA8 ADDR MAC Specific Address 3 [31:0]. Least significant bits of the MAC specific address 3, i.e. bits 31:0. This field is used for transmission of pause packets 0 32 read-write SA3H Specific Address 3 Top. 0xAC ADDR MAC Specific Address 3 [47:32]. Most significant bits of the MAC specific address 3, i.e. bits 47:32. 0 16 read-write SA4L Specific Address 4 Bottom. 0xB0 ADDR MAC Specific Address 4 [31:0]. Least significant bits of the MAC specific address 4, i.e. bits 31:0. This field is used for transmission of pause packets 0 32 read-write SA4H Specific Address 4 Top. 0xB4 ADDR MAC Specific Address 4 [47:32]. Most significant bits of the MAC specific address 4, i.e. bits 47:32. 0 16 read-write TID_CK Type ID Checking. 0xB8 TID Type ID Checking. For use in comparisons with received frames TypeID/Length field. 0 16 read-write TPQ Transmit Pause Quantum. 0xBC TPQ Transmit Pause Quantum. Used in hardware generation of transmitted pause packets as value for pause quantum 0 16 read-write USRIO User Input Output Register 0xC0 MII TBD 0 1 read-write WOL Wake On LAN Register 0xC4 IP TBD 0 16 read-write MAG TBD 16 1 read-write ARP TBD 17 1 read-write SA1 TBD 18 1 read-write MTI TBD 19 1 read-write REV Revision register. 0xFC read-only REV Revision Reference. Fixed two byte value specific to revision of design. 0 16 read-write PART Part Reference. For Ethernet MAC design, this is fixed at 0x01. 16 16 read-write