1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3  <peripheral>
4    <!-- CSI2 -->
5    <name>CSI2</name>
6    <description>Camera Serial Interface Registers.</description>
7    <baseAddress>0x40062000</baseAddress>
8    <addressBlock>
9      <offset>0x00</offset>
10      <size>0x1000</size>
11      <usage>registers</usage>
12    </addressBlock>
13    <registers>
14      <!-- Base Configuration -->
15      <register>
16        <name>CFG_NUM_LANES</name>
17        <description>CFG_NUM_LANES.</description>
18        <addressOffset>0x000</addressOffset>
19        <size>32</size>
20        <fields>
21          <field>
22            <name>LANES</name>
23            <description>Num Lanes for RX controller.</description>
24            <bitOffset>0</bitOffset>
25            <bitWidth>4</bitWidth>
26          </field>
27        </fields>
28      </register>
29      <!-- PHY Control -->
30      <register>
31        <name>CFG_CLK_LANE_EN</name>
32        <description>CFG_CLK_LANE_EN.</description>
33        <addressOffset>0x004</addressOffset>
34        <size>32</size>
35        <fields>
36          <field>
37            <name>EN</name>
38            <description>Enable lane clock setting for controller.</description>
39            <bitOffset>0</bitOffset>
40            <bitWidth>1</bitWidth>
41          </field>
42        </fields>
43      </register>
44      <register>
45        <name>CFG_DATA_LANE_EN</name>
46        <description>CFG_DATA_LANE_EN.</description>
47        <addressOffset>0x008</addressOffset>
48        <size>32</size>
49        <fields>
50          <field>
51            <name>EN</name>
52            <description>Enable data lane setting for controller.</description>
53            <bitOffset>0</bitOffset>
54            <bitWidth>8</bitWidth>
55          </field>
56        </fields>
57      </register>
58      <!-- Clock Ratio Handling and Controller Error Reporting -->
59      <register>
60        <name>CFG_FLUSH_COUNT</name>
61        <description>CFG_FLUSH_COUNT.</description>
62        <addressOffset>0x00C</addressOffset>
63        <size>32</size>
64        <fields>
65          <field>
66            <name>COUNT</name>
67            <description>Flush count setting for controller.</description>
68            <bitOffset>0</bitOffset>
69            <bitWidth>4</bitWidth>
70          </field>
71        </fields>
72      </register>
73      <register>
74        <name>CFG_BIT_ERR</name>
75        <description>CFG_BIT_ERR.</description>
76        <addressOffset>0x010</addressOffset>
77        <size>32</size>
78        <fields>
79          <field>
80            <name>MBE</name>
81            <description>Multiple bit ECC error.</description>
82            <bitOffset>0</bitOffset>
83            <bitWidth>1</bitWidth>
84          </field>
85          <field>
86            <name>SBE</name>
87            <description>Single bit ECC error.</description>
88            <bitOffset>1</bitOffset>
89            <bitWidth>1</bitWidth>
90          </field>
91          <field>
92            <name>HEADER</name>
93            <description>Header bit location of single bit ECC error.</description>
94            <bitOffset>2</bitOffset>
95            <bitWidth>5</bitWidth>
96          </field>
97          <field>
98            <name>CRC</name>
99            <description>CRC error.</description>
100            <bitOffset>7</bitOffset>
101            <bitWidth>1</bitWidth>
102          </field>
103          <field>
104            <name>VID_ERR_SEND_LVL</name>
105            <description>Video Error Send Level.</description>
106            <bitOffset>8</bitOffset>
107            <bitWidth>1</bitWidth>
108          </field>
109          <field>
110            <name>VID_ERR_FIFO_WR_OV</name>
111            <description>Video Error Fifo Overflow.</description>
112            <bitOffset>9</bitOffset>
113            <bitWidth>1</bitWidth>
114          </field>
115        </fields>
116      </register>
117      <!-- IRQ Control -->
118      <register>
119        <name>IRQ_STATUS</name>
120        <description>IRQ_STATUS.</description>
121        <addressOffset>0x014</addressOffset>
122        <size>32</size>
123        <fields>
124          <field>
125            <name>CRC</name>
126            <description>CRC error.</description>
127            <bitOffset>0</bitOffset>
128            <bitWidth>1</bitWidth>
129          </field>
130          <field>
131            <name>SBE</name>
132            <description>Single bit ECC error.</description>
133            <bitOffset>1</bitOffset>
134            <bitWidth>1</bitWidth>
135          </field>
136          <field>
137            <name>MBE</name>
138            <description>Multiple bit ECC error.</description>
139            <bitOffset>2</bitOffset>
140            <bitWidth>1</bitWidth>
141          </field>
142          <field>
143            <name>ULPS_ACTIVE</name>
144            <description>ULPS active status change.</description>
145            <bitOffset>3</bitOffset>
146            <bitWidth>1</bitWidth>
147          </field>
148          <field>
149            <name>ULPS_MARK_ACTIVE</name>
150            <description>ULPS mark active status change.</description>
151            <bitOffset>4</bitOffset>
152            <bitWidth>1</bitWidth>
153          </field>
154          <field>
155            <name>VID_ERR_SEND_LVL</name>
156            <description>Video Error Send Level.</description>
157            <bitOffset>5</bitOffset>
158            <bitWidth>1</bitWidth>
159          </field>
160          <field>
161            <name>VID_ERR_FIFO_WR_OV</name>
162            <description>Video Error Fifo Overflow.</description>
163            <bitOffset>6</bitOffset>
164            <bitWidth>1</bitWidth>
165          </field>
166        </fields>
167      </register>
168      <register>
169        <name>IRQ_ENABLE</name>
170        <description>IRQ_ENABLE.</description>
171        <addressOffset>0x018</addressOffset>
172        <size>32</size>
173        <fields>
174          <field>
175            <name>CRC</name>
176            <description>CRC error.</description>
177            <bitOffset>0</bitOffset>
178            <bitWidth>1</bitWidth>
179          </field>
180          <field>
181            <name>SBE</name>
182            <description>Single bit ECC error.</description>
183            <bitOffset>1</bitOffset>
184            <bitWidth>1</bitWidth>
185          </field>
186          <field>
187            <name>MBE</name>
188            <description>Multiple bit ECC error.</description>
189            <bitOffset>2</bitOffset>
190            <bitWidth>1</bitWidth>
191          </field>
192          <field>
193            <name>ULPS_ACTIVE</name>
194            <description>ULPS active status change.</description>
195            <bitOffset>3</bitOffset>
196            <bitWidth>1</bitWidth>
197          </field>
198          <field>
199            <name>ULPS_MARK_ACTIVE</name>
200            <description>ULPS mark active status change.</description>
201            <bitOffset>4</bitOffset>
202            <bitWidth>1</bitWidth>
203          </field>
204          <field>
205            <name>VID_ERR_SEND_LVL</name>
206            <description>Video Error Send Level.</description>
207            <bitOffset>5</bitOffset>
208            <bitWidth>1</bitWidth>
209          </field>
210          <field>
211            <name>VID_ERR_FIFO_WR_OV</name>
212            <description>Video Error Fifo Overflow.</description>
213            <bitOffset>6</bitOffset>
214            <bitWidth>1</bitWidth>
215          </field>
216        </fields>
217      </register>
218      <register>
219        <name>IRQ_CLR</name>
220        <description>IRQ_CLR.</description>
221        <addressOffset>0x01C</addressOffset>
222        <size>32</size>
223        <fields>
224          <field>
225            <name>CRC</name>
226            <description>CRC error.</description>
227            <bitOffset>0</bitOffset>
228            <bitWidth>1</bitWidth>
229          </field>
230          <field>
231            <name>SBE</name>
232            <description>Single bit ECC error.</description>
233            <bitOffset>1</bitOffset>
234            <bitWidth>1</bitWidth>
235          </field>
236          <field>
237            <name>MBE</name>
238            <description>Multiple bit ECC error.</description>
239            <bitOffset>2</bitOffset>
240            <bitWidth>1</bitWidth>
241          </field>
242          <field>
243            <name>ULPS_ACTIVE</name>
244            <description>ULPS active status change.</description>
245            <bitOffset>3</bitOffset>
246            <bitWidth>1</bitWidth>
247          </field>
248          <field>
249            <name>ULPS_MARK_ACTIVE</name>
250            <description>ULPS mark active status change.</description>
251            <bitOffset>4</bitOffset>
252            <bitWidth>1</bitWidth>
253          </field>
254          <field>
255            <name>VID_ERR_SEND_LVL</name>
256            <description>Video Error Send Level.</description>
257            <bitOffset>5</bitOffset>
258            <bitWidth>1</bitWidth>
259          </field>
260          <field>
261            <name>VID_ERR_FIFO_WR_OV</name>
262            <description>Video Error Fifo Overflow.</description>
263            <bitOffset>6</bitOffset>
264            <bitWidth>1</bitWidth>
265          </field>
266        </fields>
267      </register>
268      <!-- ULPS Control -->
269      <register>
270        <name>ULPS_CLK_STATUS</name>
271        <description>ULPS_CLK_STATUS.</description>
272        <addressOffset>0x020</addressOffset>
273        <size>32</size>
274        <fields>
275          <field>
276            <name>FIFO</name>
277            <description>FIFO Read/Write register.</description>
278            <bitOffset>0</bitOffset>
279            <bitWidth>1</bitWidth>
280          </field>
281        </fields>
282      </register>
283      <register>
284        <name>ULPS_STATUS</name>
285        <description>ULPS_STATUS.</description>
286        <addressOffset>0x024</addressOffset>
287        <size>32</size>
288        <fields>
289          <field>
290            <name>DATA_LANE0</name>
291            <description>Data Lane 0.</description>
292            <bitOffset>0</bitOffset>
293            <bitWidth>1</bitWidth>
294          </field>
295          <field>
296            <name>DATA_LANE1</name>
297            <description>Data Lane 1.</description>
298            <bitOffset>1</bitOffset>
299            <bitWidth>1</bitWidth>
300          </field>
301        </fields>
302      </register>
303      <register>
304        <name>ULPS_CLK_MARK_STATUS</name>
305        <description>ULPS_CLK_MARK_STATUS.</description>
306        <addressOffset>0x028</addressOffset>
307        <size>32</size>
308        <fields>
309          <field>
310            <name>CLK_LANE</name>
311            <description>Clock Lane.</description>
312            <bitOffset>0</bitOffset>
313            <bitWidth>1</bitWidth>
314          </field>
315        </fields>
316      </register>
317      <register>
318        <name>ULPS_MARK_STATUS</name>
319        <description>ULPS_MARK_STATUS.</description>
320        <addressOffset>0x02C</addressOffset>
321        <size>32</size>
322        <fields>
323          <field>
324            <name>DATA_LANE0</name>
325            <description>Data Lane 0.</description>
326            <bitOffset>0</bitOffset>
327            <bitWidth>1</bitWidth>
328          </field>
329          <field>
330            <name>DATA_LANE1</name>
331            <description>Data Lane 1.</description>
332            <bitOffset>1</bitOffset>
333            <bitWidth>1</bitWidth>
334          </field>
335        </fields>
336      </register>
337      <!-- PHY Error Reporting -->
338      <register>
339        <name>PPI_ERRSOT_HS</name>
340        <description>PPI_ERRSOT_HS.</description>
341        <addressOffset>0x030</addressOffset>
342        <size>32</size>
343      </register>
344      <register>
345        <name>PPI_ERRSOTSYNC_HS</name>
346        <description>PPI_ERRSOTSYNC_HS.</description>
347        <addressOffset>0x034</addressOffset>
348        <size>32</size>
349      </register>
350      <register>
351        <name>PPI_ERRESC</name>
352        <description>PPI_ERRESC.</description>
353        <addressOffset>0x038</addressOffset>
354        <size>32</size>
355      </register>
356      <register>
357        <name>PPI_ERRSYNCESC</name>
358        <description>PPI_ERRSYNCESC.</description>
359        <addressOffset>0x03C</addressOffset>
360        <size>32</size>
361      </register>
362      <register>
363        <name>PPI_ERRCONTROL</name>
364        <description>PPI_ERRCONTROL.</description>
365        <addressOffset>0x040</addressOffset>
366        <size>32</size>
367      </register>
368      <!-- MODE Control -->
369      <register>
370        <name>CFG_CPHY_EN</name>
371        <description>CFG_CPHY_EN.</description>
372        <addressOffset>0x044</addressOffset>
373        <size>32</size>
374      </register>
375      <register>
376        <name>CFG_PPI_16_EN</name>
377        <description>CFG_PPI_16_EN.</description>
378        <addressOffset>0x048</addressOffset>
379        <size>32</size>
380      </register>
381      <register>
382        <name>CFG_PACKET_INTERFACE_EN</name>
383        <description>CFG_PACKET_INTERFACE_EN.</description>
384        <addressOffset>0x04C</addressOffset>
385        <size>32</size>
386      </register>
387      <register>
388        <name>CFG_VCX_EN</name>
389        <description>CFG_VCX_EN.</description>
390        <addressOffset>0x050</addressOffset>
391        <size>32</size>
392      </register>
393      <register>
394        <name>CFG_BYTE_DATA_FORMAT</name>
395        <description>CFG_BYTE_DATA_FORMAT.</description>
396        <addressOffset>0x054</addressOffset>
397        <size>32</size>
398      </register>
399      <!-- Data Type Disable Control -->
400      <register>
401        <name>CFG_DISABLE_PAYLOAD_0</name>
402        <description>CFG_DISABLE_PAYLOAD_0.</description>
403        <addressOffset>0x058</addressOffset>
404        <size>32</size>
405        <fields>
406          <field>
407            <name>NULL</name>
408            <description>NULL.</description>
409            <bitOffset>0</bitOffset>
410            <bitWidth>1</bitWidth>
411          </field>
412          <field>
413            <name>BLANK</name>
414            <description>BLANK.</description>
415            <bitOffset>1</bitOffset>
416            <bitWidth>1</bitWidth>
417          </field>
418          <field>
419            <name>EMBEDDED</name>
420            <description>EMBEDDED.</description>
421            <bitOffset>2</bitOffset>
422            <bitWidth>1</bitWidth>
423          </field>
424          <field>
425            <name>YUV420_8BIT</name>
426            <description>YUV420_8BIT.</description>
427            <bitOffset>8</bitOffset>
428            <bitWidth>1</bitWidth>
429          </field>
430          <field>
431            <name>YUV420_10BIT</name>
432            <description>YUV420_10BIT.</description>
433            <bitOffset>9</bitOffset>
434            <bitWidth>1</bitWidth>
435          </field>
436          <field>
437            <name>YUV420_8BIT_LEG</name>
438            <description>YUV420_8BIT_LEG.</description>
439            <bitOffset>10</bitOffset>
440            <bitWidth>1</bitWidth>
441          </field>
442          <field>
443            <name>YUV420_8BIT_CSP</name>
444            <description>YUV420_8BIT_CSP.</description>
445            <bitOffset>12</bitOffset>
446            <bitWidth>1</bitWidth>
447          </field>
448          <field>
449            <name>YUV420_10BIT_CSP</name>
450            <description>YUV420_10BIT_CSP.</description>
451            <bitOffset>13</bitOffset>
452            <bitWidth>1</bitWidth>
453          </field>
454          <field>
455            <name>YUV422_8BIT</name>
456            <description>YUV422_8BIT.</description>
457            <bitOffset>14</bitOffset>
458            <bitWidth>1</bitWidth>
459          </field>
460          <field>
461            <name>YUV422_10BIT</name>
462            <description>YUV422_10BIT.</description>
463            <bitOffset>15</bitOffset>
464            <bitWidth>1</bitWidth>
465          </field>
466          <field>
467            <name>RGB444</name>
468            <description>RGB444.</description>
469            <bitOffset>16</bitOffset>
470            <bitWidth>1</bitWidth>
471          </field>
472          <field>
473            <name>RGB555</name>
474            <description>RGB555.</description>
475            <bitOffset>17</bitOffset>
476            <bitWidth>1</bitWidth>
477          </field>
478          <field>
479            <name>RGB565</name>
480            <description>RGB565.</description>
481            <bitOffset>18</bitOffset>
482            <bitWidth>1</bitWidth>
483          </field>
484          <field>
485            <name>RGB666</name>
486            <description>RGB666.</description>
487            <bitOffset>19</bitOffset>
488            <bitWidth>1</bitWidth>
489          </field>
490          <field>
491            <name>RGB888</name>
492            <description>RGB888.</description>
493            <bitOffset>20</bitOffset>
494            <bitWidth>1</bitWidth>
495          </field>
496          <field>
497            <name>RAW6</name>
498            <description>RAW6.</description>
499            <bitOffset>24</bitOffset>
500            <bitWidth>1</bitWidth>
501          </field>
502          <field>
503            <name>RAW7</name>
504            <description>RAW7.</description>
505            <bitOffset>25</bitOffset>
506            <bitWidth>1</bitWidth>
507          </field>
508          <field>
509            <name>RAW8</name>
510            <description>RAW8.</description>
511            <bitOffset>26</bitOffset>
512            <bitWidth>1</bitWidth>
513          </field>
514          <field>
515            <name>RAW10</name>
516            <description>RAW10.</description>
517            <bitOffset>27</bitOffset>
518            <bitWidth>1</bitWidth>
519          </field>
520          <field>
521            <name>RAW12</name>
522            <description>RAW12.</description>
523            <bitOffset>28</bitOffset>
524            <bitWidth>1</bitWidth>
525          </field>
526          <field>
527            <name>RAW14</name>
528            <description>RAW14.</description>
529            <bitOffset>29</bitOffset>
530            <bitWidth>1</bitWidth>
531          </field>
532          <field>
533            <name>RAW16</name>
534            <description>RAW16.</description>
535            <bitOffset>30</bitOffset>
536            <bitWidth>1</bitWidth>
537          </field>
538          <field>
539            <name>RAW20</name>
540            <description>RAW20.</description>
541            <bitOffset>31</bitOffset>
542            <bitWidth>1</bitWidth>
543          </field>
544        </fields>
545      </register>
546      <register>
547        <name>CFG_DISABLE_PAYLOAD_1</name>
548        <description>CFG_DISABLE_PAYLOAD_1.</description>
549        <addressOffset>0x05C</addressOffset>
550        <size>32</size>
551        <fields>
552          <field>
553            <name>USR_DEF_TYPE30</name>
554            <description>User defined type 0x30.</description>
555            <bitOffset>0</bitOffset>
556            <bitWidth>1</bitWidth>
557          </field>
558          <field>
559            <name>USR_DEF_TYPE31</name>
560            <description>User defined type 0x31.</description>
561            <bitOffset>1</bitOffset>
562            <bitWidth>1</bitWidth>
563          </field>
564          <field>
565            <name>USR_DEF_TYPE32</name>
566            <description>User defined type 0x32.</description>
567            <bitOffset>2</bitOffset>
568            <bitWidth>1</bitWidth>
569          </field>
570          <field>
571            <name>USR_DEF_TYPE33</name>
572            <description>User defined type 0x33.</description>
573            <bitOffset>3</bitOffset>
574            <bitWidth>1</bitWidth>
575          </field>
576          <field>
577            <name>USR_DEF_TYPE34</name>
578            <description>User defined type 0x34.</description>
579            <bitOffset>4</bitOffset>
580            <bitWidth>1</bitWidth>
581          </field>
582          <field>
583            <name>USR_DEF_TYPE35</name>
584            <description>User defined type 0x35.</description>
585            <bitOffset>5</bitOffset>
586            <bitWidth>1</bitWidth>
587          </field>
588          <field>
589            <name>USR_DEF_TYPE36</name>
590            <description>User defined type 0x36.</description>
591            <bitOffset>6</bitOffset>
592            <bitWidth>1</bitWidth>
593          </field>
594          <field>
595            <name>USR_DEF_TYPE37</name>
596            <description>User defined type 0x37.</description>
597            <bitOffset>7</bitOffset>
598            <bitWidth>1</bitWidth>
599          </field>
600        </fields>
601      </register>
602      <!-- Video Interface Control -->
603      <register>
604        <name>CFG_VID_IGNORE_VC</name>
605        <description>CFG_VID_IGNORE_VC.</description>
606        <addressOffset>0x080</addressOffset>
607        <size>32</size>
608      </register>
609      <register>
610        <name>CFG_VID_VC</name>
611        <description>CFG_VID_VC.</description>
612        <addressOffset>0x084</addressOffset>
613        <size>32</size>
614      </register>
615      <register>
616        <name>CFG_P_FIFO_SEND_LEVEL</name>
617        <description>CFG_P_FIFO_SEND_LEVEL.</description>
618        <addressOffset>0x088</addressOffset>
619        <size>32</size>
620      </register>
621      <register>
622        <name>CFG_VID_VSYNC</name>
623        <description>CFG_VID_VSYNC.</description>
624        <addressOffset>0x08C</addressOffset>
625        <size>32</size>
626      </register>
627      <register>
628        <name>CFG_VID_HSYNC_FP</name>
629        <description>CFG_VID_HSYNC_FP.</description>
630        <addressOffset>0x090</addressOffset>
631        <size>32</size>
632      </register>
633      <register>
634        <name>CFG_VID_HSYNC</name>
635        <description>CFG_VID_HSYNC.</description>
636        <addressOffset>0x094</addressOffset>
637        <size>32</size>
638      </register>
639      <register>
640        <name>CFG_VID_HSYNC_BP</name>
641        <description>CFG_VID_HSYNC_BP.</description>
642        <addressOffset>0x098</addressOffset>
643        <size>32</size>
644      </register>
645      <!-- Configuration Signals -->
646      <register>
647        <name>CFG_DATABUS16_SEL</name>
648        <description>CFG_DATABUS16_SEL.</description>
649        <addressOffset>0x400</addressOffset>
650        <size>32</size>
651        <fields>
652          <field>
653            <name>EN</name>
654            <description>Enable 16-bit data bus.</description>
655            <bitOffset>0</bitOffset>
656            <bitWidth>1</bitWidth>
657          </field>
658        </fields>
659      </register>
660      <register>
661        <name>CFG_D0_SWAP_SEL</name>
662        <description>CFG_D0_SWAP_SEL.</description>
663        <addressOffset>0x404</addressOffset>
664        <size>32</size>
665        <fields>
666          <field>
667            <name>SRC</name>
668            <description>Control Source.</description>
669            <bitOffset>0</bitOffset>
670            <bitWidth>3</bitWidth>
671            <enumeratedValues>
672              <enumeratedValue>
673                <name>PAD_CDRX_L0</name>
674                <description>PAD_CDRX_L0.</description>
675                <value>0</value>
676              </enumeratedValue>
677              <enumeratedValue>
678                <name>PAD_CDRX_L1</name>
679                <description>PAD_CDRX_L1.</description>
680                <value>1</value>
681              </enumeratedValue>
682              <enumeratedValue>
683                <name>PAD_CDRX_L2</name>
684                <description>PAD_CDRX_L2.</description>
685                <value>2</value>
686              </enumeratedValue>
687              <enumeratedValue>
688                <name>PAD_CDRX_L3</name>
689                <description>PAD_CDRX_L3.</description>
690                <value>3</value>
691              </enumeratedValue>
692              <enumeratedValue>
693                <name>PAD_CDRX_L4</name>
694                <description>PAD_CDRX_L4.</description>
695                <value>4</value>
696              </enumeratedValue>
697            </enumeratedValues>
698          </field>
699        </fields>
700      </register>
701      <register>
702        <name>CFG_D1_SWAP_SEL</name>
703        <description>CFG_D1_SWAP_SEL.</description>
704        <addressOffset>0x408</addressOffset>
705        <size>32</size>
706        <fields>
707          <field>
708            <name>SRC</name>
709            <description>Control Source.</description>
710            <bitOffset>0</bitOffset>
711            <bitWidth>3</bitWidth>
712            <enumeratedValues>
713              <enumeratedValue>
714                <name>PAD_CDRX_L0</name>
715                <description>PAD_CDRX_L0.</description>
716                <value>0</value>
717              </enumeratedValue>
718              <enumeratedValue>
719                <name>PAD_CDRX_L1</name>
720                <description>PAD_CDRX_L1.</description>
721                <value>1</value>
722              </enumeratedValue>
723              <enumeratedValue>
724                <name>PAD_CDRX_L2</name>
725                <description>PAD_CDRX_L2.</description>
726                <value>2</value>
727              </enumeratedValue>
728              <enumeratedValue>
729                <name>PAD_CDRX_L3</name>
730                <description>PAD_CDRX_L3.</description>
731                <value>3</value>
732              </enumeratedValue>
733              <enumeratedValue>
734                <name>PAD_CDRX_L4</name>
735                <description>PAD_CDRX_L4.</description>
736                <value>4</value>
737              </enumeratedValue>
738            </enumeratedValues>
739          </field>
740        </fields>
741      </register>
742      <register>
743        <name>CFG_D2_SWAP_SEL</name>
744        <description>CFG_D2_SWAP_SEL.</description>
745        <addressOffset>0x40C</addressOffset>
746        <size>32</size>
747        <fields>
748          <field>
749            <name>SRC</name>
750            <description>Control Source.</description>
751            <bitOffset>0</bitOffset>
752            <bitWidth>3</bitWidth>
753            <enumeratedValues>
754              <enumeratedValue>
755                <name>PAD_CDRX_L0</name>
756                <description>PAD_CDRX_L0.</description>
757                <value>0</value>
758              </enumeratedValue>
759              <enumeratedValue>
760                <name>PAD_CDRX_L1</name>
761                <description>PAD_CDRX_L1.</description>
762                <value>1</value>
763              </enumeratedValue>
764              <enumeratedValue>
765                <name>PAD_CDRX_L2</name>
766                <description>PAD_CDRX_L2.</description>
767                <value>2</value>
768              </enumeratedValue>
769              <enumeratedValue>
770                <name>PAD_CDRX_L3</name>
771                <description>PAD_CDRX_L3.</description>
772                <value>3</value>
773              </enumeratedValue>
774              <enumeratedValue>
775                <name>PAD_CDRX_L4</name>
776                <description>PAD_CDRX_L4.</description>
777                <value>4</value>
778              </enumeratedValue>
779            </enumeratedValues>
780          </field>
781        </fields>
782      </register>
783      <register>
784        <name>CFG_D3_SWAP_SEL</name>
785        <description>CFG_D3_SWAP_SEL.</description>
786        <addressOffset>0x410</addressOffset>
787        <size>32</size>
788        <fields>
789          <field>
790            <name>SRC</name>
791            <description>Control Source.</description>
792            <bitOffset>0</bitOffset>
793            <bitWidth>3</bitWidth>
794            <enumeratedValues>
795              <enumeratedValue>
796                <name>PAD_CDRX_L0</name>
797                <description>PAD_CDRX_L0.</description>
798                <value>0</value>
799              </enumeratedValue>
800              <enumeratedValue>
801                <name>PAD_CDRX_L1</name>
802                <description>PAD_CDRX_L1.</description>
803                <value>1</value>
804              </enumeratedValue>
805              <enumeratedValue>
806                <name>PAD_CDRX_L2</name>
807                <description>PAD_CDRX_L2.</description>
808                <value>2</value>
809              </enumeratedValue>
810              <enumeratedValue>
811                <name>PAD_CDRX_L3</name>
812                <description>PAD_CDRX_L3.</description>
813                <value>3</value>
814              </enumeratedValue>
815              <enumeratedValue>
816                <name>PAD_CDRX_L4</name>
817                <description>PAD_CDRX_L4.</description>
818                <value>4</value>
819              </enumeratedValue>
820            </enumeratedValues>
821          </field>
822        </fields>
823      </register>
824      <register>
825        <name>CFG_C0_SWAP_SEL</name>
826        <description>CFG_C0_SWAP_SEL.</description>
827        <addressOffset>0x414</addressOffset>
828        <size>32</size>
829        <fields>
830          <field>
831            <name>SRC</name>
832            <description>Control Source.</description>
833            <bitOffset>0</bitOffset>
834            <bitWidth>3</bitWidth>
835            <enumeratedValues>
836              <enumeratedValue>
837                <name>PAD_CDRX_L0</name>
838                <description>PAD_CDRX_L0.</description>
839                <value>0</value>
840              </enumeratedValue>
841              <enumeratedValue>
842                <name>PAD_CDRX_L1</name>
843                <description>PAD_CDRX_L1.</description>
844                <value>1</value>
845              </enumeratedValue>
846              <enumeratedValue>
847                <name>PAD_CDRX_L2</name>
848                <description>PAD_CDRX_L2.</description>
849                <value>2</value>
850              </enumeratedValue>
851              <enumeratedValue>
852                <name>PAD_CDRX_L3</name>
853                <description>PAD_CDRX_L3.</description>
854                <value>3</value>
855              </enumeratedValue>
856              <enumeratedValue>
857                <name>PAD_CDRX_L4</name>
858                <description>PAD_CDRX_L4.</description>
859                <value>4</value>
860              </enumeratedValue>
861            </enumeratedValues>
862          </field>
863        </fields>
864      </register>
865      <register>
866        <name>CFG_DPDN_SWAP</name>
867        <description>CFG_DPDN_SWAP.</description>
868        <addressOffset>0x418</addressOffset>
869        <size>32</size>
870        <fields>
871          <field>
872            <name>SWAP_DATA_LANE0</name>
873            <description>SWAP_DATA_LANE0.</description>
874            <bitOffset>0</bitOffset>
875            <bitWidth>1</bitWidth>
876          </field>
877          <field>
878            <name>SWAP_DATA_LANE1</name>
879            <description>SWAP_DATA_LANE1.</description>
880            <bitOffset>1</bitOffset>
881            <bitWidth>1</bitWidth>
882          </field>
883          <field>
884            <name>SWAP_DATA_LANE2</name>
885            <description>SWAP_DATA_LANE2.</description>
886            <bitOffset>2</bitOffset>
887            <bitWidth>1</bitWidth>
888          </field>
889          <field>
890            <name>SWAP_DATA_LANE3</name>
891            <description>SWAP_DATA_LANE3.</description>
892            <bitOffset>3</bitOffset>
893            <bitWidth>1</bitWidth>
894          </field>
895          <field>
896            <name>SWAP_CLK_LANE</name>
897            <description>SWAP_CLK_LANE.</description>
898            <bitOffset>4</bitOffset>
899            <bitWidth>1</bitWidth>
900          </field>
901        </fields>
902      </register>
903      <register>
904        <name>RG_CFGCLK_1US_CNT</name>
905        <description>RG_CFGCLK_1US_CNT.</description>
906        <addressOffset>0x41C</addressOffset>
907        <size>32</size>
908      </register>
909      <register>
910        <name>RG_HSRX_CLK_PRE_TIME_GRP0</name>
911        <description>RG_HSRX_CLK_PRE_TIME_GRP0.</description>
912        <addressOffset>0x420</addressOffset>
913        <size>32</size>
914      </register>
915      <register>
916        <name>RG_HSRX_DATA_PRE_TIME_GRP0</name>
917        <description>RG_HSRX_DATA_PRE_TIME_GRP0.</description>
918        <addressOffset>0x424</addressOffset>
919        <size>32</size>
920      </register>
921      <!-- Non-PPI Control Signals -->
922      <register>
923        <name>RESET_DESKEW</name>
924        <description>RESET_DESKEW.</description>
925        <addressOffset>0x428</addressOffset>
926        <size>32</size>
927        <fields>
928          <field>
929            <name>DATA_LANE0</name>
930            <description>DATA_LANE0.</description>
931            <bitOffset>0</bitOffset>
932            <bitWidth>1</bitWidth>
933          </field>
934          <field>
935            <name>DATA_LANE1</name>
936            <description>DATA_LANE1.</description>
937            <bitOffset>1</bitOffset>
938            <bitWidth>1</bitWidth>
939          </field>
940          <field>
941            <name>DATA_LANE2</name>
942            <description>DATA_LANE2.</description>
943            <bitOffset>2</bitOffset>
944            <bitWidth>1</bitWidth>
945          </field>
946          <field>
947            <name>DATA_LANE3</name>
948            <description>DATA_LANE3.</description>
949            <bitOffset>3</bitOffset>
950            <bitWidth>1</bitWidth>
951          </field>
952        </fields>
953      </register>
954      <!-- Miscellaneous Signals -->
955      <register>
956        <name>PMA_RDY</name>
957        <description>PMA_RDY.</description>
958        <addressOffset>0x42C</addressOffset>
959        <size>32</size>
960      </register>
961      <!-- M31 Internal Used Signals -->
962      <register>
963        <name>XCFGI_DW00</name>
964        <description>XCFGI_DW00.</description>
965        <addressOffset>0x430</addressOffset>
966        <size>32</size>
967      </register>
968      <register>
969        <name>XCFGI_DW01</name>
970        <description>XCFGI_DW01.</description>
971        <addressOffset>0x434</addressOffset>
972        <size>32</size>
973      </register>
974      <register>
975        <name>XCFGI_DW02</name>
976        <description>XCFGI_DW02.</description>
977        <addressOffset>0x438</addressOffset>
978        <size>32</size>
979      </register>
980      <register>
981        <name>XCFGI_DW03</name>
982        <description>XCFGI_DW03.</description>
983        <addressOffset>0x43C</addressOffset>
984        <size>32</size>
985      </register>
986      <register>
987        <name>XCFGI_DW04</name>
988        <description>XCFGI_DW04.</description>
989        <addressOffset>0x440</addressOffset>
990        <size>32</size>
991      </register>
992      <register>
993        <name>XCFGI_DW05</name>
994        <description>XCFGI_DW05.</description>
995        <addressOffset>0x444</addressOffset>
996        <size>32</size>
997      </register>
998      <register>
999        <name>XCFGI_DW06</name>
1000        <description>XCFGI_DW06.</description>
1001        <addressOffset>0x448</addressOffset>
1002        <size>32</size>
1003      </register>
1004      <register>
1005        <name>XCFGI_DW07</name>
1006        <description>XCFGI_DW07.</description>
1007        <addressOffset>0x44C</addressOffset>
1008        <size>32</size>
1009      </register>
1010      <register>
1011        <name>XCFGI_DW08</name>
1012        <description>XCFGI_DW08.</description>
1013        <addressOffset>0x450</addressOffset>
1014        <size>32</size>
1015      </register>
1016      <register>
1017        <name>XCFGI_DW09</name>
1018        <description>XCFGI_DW09.</description>
1019        <addressOffset>0x454</addressOffset>
1020        <size>32</size>
1021      </register>
1022      <register>
1023        <name>XCFGI_DW0A</name>
1024        <description>XCFGI_DW0A.</description>
1025        <addressOffset>0x458</addressOffset>
1026        <size>32</size>
1027      </register>
1028      <register>
1029        <name>XCFGI_DW0B</name>
1030        <description>XCFGI_DW0B.</description>
1031        <addressOffset>0x45C</addressOffset>
1032        <size>32</size>
1033      </register>
1034      <register>
1035        <name>XCFGI_DW0C</name>
1036        <description>XCFGI_DW0C.</description>
1037        <addressOffset>0x460</addressOffset>
1038        <size>32</size>
1039      </register>
1040      <register>
1041        <name>XCFGI_DW0D</name>
1042        <description>XCFGI_DW0D.</description>
1043        <addressOffset>0x464</addressOffset>
1044        <size>32</size>
1045      </register>
1046      <register>
1047        <name>GPIO_MODE</name>
1048        <description>GPIO_MODE.</description>
1049        <addressOffset>0x468</addressOffset>
1050        <size>32</size>
1051      </register>
1052      <register>
1053        <name>GPIO_DP_IE</name>
1054        <description>GPIO_DP_IE.</description>
1055        <addressOffset>0x46C</addressOffset>
1056        <size>32</size>
1057      </register>
1058      <register>
1059        <name>GPIO_DN_IE</name>
1060        <description>GPIO_DN_IE.</description>
1061        <addressOffset>0x470</addressOffset>
1062        <size>32</size>
1063      </register>
1064      <register>
1065        <name>GPIO_DP_C</name>
1066        <description>GPIO_DP_C.</description>
1067        <addressOffset>0x474</addressOffset>
1068        <size>32</size>
1069      </register>
1070      <register>
1071        <name>GPIO_DN_C</name>
1072        <description>GPIO_DN_C.</description>
1073        <addressOffset>0x478</addressOffset>
1074        <size>32</size>
1075      </register>
1076      <!-- BIST Signals -->
1077      <register>
1078        <name>VCONTROL</name>
1079        <description>PMA_RDY.</description>
1080        <addressOffset>0x47C</addressOffset>
1081        <size>32</size>
1082        <fields>
1083          <field>
1084            <name>NORMAL_MODE</name>
1085            <description>NORMAL_MODE.</description>
1086            <bitOffset>0</bitOffset>
1087            <bitWidth>1</bitWidth>
1088          </field>
1089          <field>
1090            <name>LP_RX_DC_TEST</name>
1091            <description>LP_RX_DC_TEST.</description>
1092            <bitOffset>1</bitOffset>
1093            <bitWidth>1</bitWidth>
1094          </field>
1095          <field>
1096            <name>LP_RX_DC_1</name>
1097            <description>LP_RX_DC_1.</description>
1098            <bitOffset>2</bitOffset>
1099            <bitWidth>1</bitWidth>
1100          </field>
1101          <field>
1102            <name>LP_RX_DC_0</name>
1103            <description>LP_RX_DC_0.</description>
1104            <bitOffset>3</bitOffset>
1105            <bitWidth>1</bitWidth>
1106          </field>
1107          <field>
1108            <name>CAL_SEN_1</name>
1109            <description>CAL_SEN_1.</description>
1110            <bitOffset>4</bitOffset>
1111            <bitWidth>1</bitWidth>
1112          </field>
1113          <field>
1114            <name>CAL_SEN_0</name>
1115            <description>CAL_SEN_0.</description>
1116            <bitOffset>5</bitOffset>
1117            <bitWidth>1</bitWidth>
1118          </field>
1119          <field>
1120            <name>HSRT_0</name>
1121            <description>HSRT_0.</description>
1122            <bitOffset>7</bitOffset>
1123            <bitWidth>1</bitWidth>
1124          </field>
1125          <field>
1126            <name>HSRT_1</name>
1127            <description>HSRT_1.</description>
1128            <bitOffset>8</bitOffset>
1129            <bitWidth>1</bitWidth>
1130          </field>
1131          <field>
1132            <name>LP_RX_PARTBERT</name>
1133            <description>LP_RX_PARTBERT.</description>
1134            <bitOffset>10</bitOffset>
1135            <bitWidth>1</bitWidth>
1136          </field>
1137          <field>
1138            <name>HS_INT_LOOPBACK</name>
1139            <description>HS_INT_LOOPBACK.</description>
1140            <bitOffset>11</bitOffset>
1141            <bitWidth>1</bitWidth>
1142          </field>
1143          <field>
1144            <name>HS_RX_PARTBERT</name>
1145            <description>HS_RX_PARTBERT.</description>
1146            <bitOffset>27</bitOffset>
1147            <bitWidth>1</bitWidth>
1148          </field>
1149          <field>
1150            <name>HS_RX_PRBS9</name>
1151            <description>HS_RX_PRBS9.</description>
1152            <bitOffset>28</bitOffset>
1153            <bitWidth>1</bitWidth>
1154          </field>
1155          <field>
1156            <name>SUSPEND_MODE</name>
1157            <description>SUSPEND_MODE.</description>
1158            <bitOffset>31</bitOffset>
1159            <bitWidth>1</bitWidth>
1160          </field>
1161        </fields>
1162      </register>
1163      <register>
1164        <name>MPSOV1</name>
1165        <description>MPSOV1.</description>
1166        <addressOffset>0x480</addressOffset>
1167        <size>32</size>
1168      </register>
1169      <register>
1170        <name>MPSOV2</name>
1171        <description>MPSOV2.</description>
1172        <addressOffset>0x484</addressOffset>
1173        <size>32</size>
1174      </register>
1175      <register>
1176        <name>MPSOV3</name>
1177        <description>MPSOV3.</description>
1178        <addressOffset>0x488</addressOffset>
1179        <size>32</size>
1180      </register>
1181      <!-- Direct Configuration Signals of PMA -->
1182      <register>
1183        <name>RG_CDRX_DSIRX_EN</name>
1184        <description>RG_CDRX_DSIRX_EN.</description>
1185        <addressOffset>0x490</addressOffset>
1186        <size>32</size>
1187        <fields>
1188          <field>
1189            <name>RXMODE</name>
1190            <description>RXMODE.</description>
1191            <bitOffset>0</bitOffset>
1192            <bitWidth>1</bitWidth>
1193            <enumeratedValues>
1194              <enumeratedValue>
1195                <name>CSI</name>
1196                <description>CSI RX Mode.</description>
1197                <value>0</value>
1198              </enumeratedValue>
1199              <enumeratedValue>
1200                <name>DSI</name>
1201                <description>DSI RX Mode.</description>
1202                <value>1</value>
1203              </enumeratedValue>
1204            </enumeratedValues>
1205          </field>
1206        </fields>
1207      </register>
1208      <register>
1209        <name>RG_CDRX_L012_SUBLVDS_EN</name>
1210        <description>RG_CDRX_L012_SUBLVDS_EN.</description>
1211        <addressOffset>0x494</addressOffset>
1212        <size>32</size>
1213      </register>
1214      <register>
1215        <name>RG_CDRX_L012_HSRT_CTRL</name>
1216        <description>RG_CDRX_L012_HSRT_CTRL.</description>
1217        <addressOffset>0x498</addressOffset>
1218        <size>32</size>
1219      </register>
1220      <!-- Direct BIST Signals of PMA -->
1221      <register>
1222        <name>RG_CDRX_BISTHS_PLL_EN</name>
1223        <description>RG_CDRX_BISTHS_PLL_EN.</description>
1224        <addressOffset>0x49C</addressOffset>
1225        <size>32</size>
1226      </register>
1227      <register>
1228        <name>RG_CDRX_BISTHS_PLL_PRE_DIV2</name>
1229        <description>RG_CDRX_BISTHS_PLL_PRE_DIV2.</description>
1230        <addressOffset>0x4A0</addressOffset>
1231        <size>32</size>
1232        <fields>
1233          <field>
1234            <name>RXMODE</name>
1235            <description>RXMODE.</description>
1236            <bitOffset>0</bitOffset>
1237            <bitWidth>1</bitWidth>
1238            <enumeratedValues>
1239              <enumeratedValue>
1240                <name>CSI</name>
1241                <description>CSI RX Mode.</description>
1242                <value>0</value>
1243              </enumeratedValue>
1244              <enumeratedValue>
1245                <name>DSI</name>
1246                <description>DSI RX Mode.</description>
1247                <value>1</value>
1248              </enumeratedValue>
1249            </enumeratedValues>
1250          </field>
1251        </fields>
1252      </register>
1253      <register>
1254        <name>RG_CDRX_BISTHS_PLL_FBK_INT</name>
1255        <description>RG_CDRX_BISTHS_PLL_FBK_INT.</description>
1256        <addressOffset>0x4A4</addressOffset>
1257        <size>32</size>
1258      </register>
1259      <!-- M31 Debug Signals -->
1260      <register>
1261        <name>DBG1_MUX_SEL</name>
1262        <description>DBG1_MUX_SEL.</description>
1263        <addressOffset>0x4A8</addressOffset>
1264        <size>32</size>
1265      </register>
1266      <register>
1267        <name>DBG2_MUX_SEL</name>
1268        <description>DBG2_MUX_SEL.</description>
1269        <addressOffset>0x4AC</addressOffset>
1270        <size>32</size>
1271      </register>
1272      <register>
1273        <name>DBG1_MUX_DOUT</name>
1274        <description>DBG1_MUX_DOUT.</description>
1275        <addressOffset>0x4B0</addressOffset>
1276        <size>32</size>
1277      </register>
1278      <register>
1279        <name>DBG2_MUX_DOUT</name>
1280        <description>DBG2_MUX_DOUT.</description>
1281        <addressOffset>0x4B4</addressOffset>
1282        <size>32</size>
1283      </register>
1284      <register>
1285        <name>AON_POWER_READY_N</name>
1286        <description>AON_POWER_READY_N.</description>
1287        <addressOffset>0x4B8</addressOffset>
1288        <size>32</size>
1289      </register>
1290      <register>
1291        <name>DPHY_RST_N</name>
1292        <description>DPHY_RST_N.</description>
1293        <addressOffset>0x4BC</addressOffset>
1294        <size>32</size>
1295      </register>
1296      <register>
1297        <name>RXBYTECLKHS_INV</name>
1298        <description>RXBYTECLKHS_INV.</description>
1299        <addressOffset>0x4C0</addressOffset>
1300        <size>32</size>
1301      </register>
1302      <!-- Video FIFO Registers -->
1303      <register>
1304        <name>VFIFO_CFG0</name>
1305        <description>Video FIFO Configuration Register 0.</description>
1306        <addressOffset>0x500</addressOffset>
1307        <size>32</size>
1308        <fields>
1309          <field>
1310            <name>VC</name>
1311            <description>CSI Virtual Channel.</description>
1312            <bitOffset>0</bitOffset>
1313            <bitWidth>2</bitWidth>
1314          </field>
1315          <field>
1316            <name>DMAMODE</name>
1317            <description>DMA Mode, the condition to trigger DMA request..</description>
1318            <bitOffset>6</bitOffset>
1319            <bitWidth>2</bitWidth>
1320            <enumeratedValues>
1321              <enumeratedValue>
1322                <name>NO_DMA</name>
1323                <description>No DMA.</description>
1324                <value>0</value>
1325              </enumeratedValue>
1326              <enumeratedValue>
1327                <name>DMA_REQ</name>
1328                <description>Immediately send DMA request.</description>
1329                <value>1</value>
1330              </enumeratedValue>
1331              <enumeratedValue>
1332                <name>FIFO_THD</name>
1333                <description>Wait for FIFO above threshold.</description>
1334                <value>2</value>
1335              </enumeratedValue>
1336              <enumeratedValue>
1337                <name>FIFO_FULL</name>
1338                <description>Wait for FIFO is full.</description>
1339                <value>3</value>
1340              </enumeratedValue>
1341            </enumeratedValues>
1342          </field>
1343          <field>
1344            <name>AHBWAIT</name>
1345            <description>AHB Wait Enable.</description>
1346            <bitOffset>8</bitOffset>
1347            <bitWidth>1</bitWidth>
1348          </field>
1349          <field>
1350            <name>FIFORM</name>
1351            <description>FIFO Read Mode.</description>
1352            <bitOffset>9</bitOffset>
1353            <bitWidth>1</bitWidth>
1354          </field>
1355          <field>
1356            <name>ERRDE</name>
1357            <description>Error Detection Enable.</description>
1358            <bitOffset>10</bitOffset>
1359            <bitWidth>1</bitWidth>
1360          </field>
1361          <field>
1362            <name>FBWM</name>
1363            <description>Full Band Width mode.</description>
1364            <bitOffset>11</bitOffset>
1365            <bitWidth>1</bitWidth>
1366          </field>
1367        </fields>
1368      </register>
1369      <register>
1370        <name>VFIFO_CFG1</name>
1371        <description>Video FIFO Configuration Register 1.</description>
1372        <addressOffset>0x504</addressOffset>
1373        <size>32</size>
1374        <fields>
1375          <field>
1376            <name>AHBWCYC</name>
1377            <description>Maximal AHB Wait Clock Cycles.</description>
1378            <bitOffset>0</bitOffset>
1379            <bitWidth>16</bitWidth>
1380          </field>
1381          <field>
1382            <name>WAIT_FIRST_FS</name>
1383            <description>WAIT_FIRST_FS.</description>
1384            <bitOffset>16</bitOffset>
1385            <bitWidth>1</bitWidth>
1386          </field>
1387          <field>
1388            <name>ACCU_FRAME_CTRL</name>
1389            <description>ACCU_FRAME_CTRL.</description>
1390            <bitOffset>17</bitOffset>
1391            <bitWidth>1</bitWidth>
1392          </field>
1393          <field>
1394            <name>ACCU_LINE_CTRL</name>
1395            <description>ACCU_LINE_CTRL.</description>
1396            <bitOffset>18</bitOffset>
1397            <bitWidth>1</bitWidth>
1398          </field>
1399          <field>
1400            <name>ACCU_LINE_CNT</name>
1401            <description>ACCU_LINE_CNT.</description>
1402            <bitOffset>19</bitOffset>
1403            <bitWidth>1</bitWidth>
1404          </field>
1405          <field>
1406            <name>ACCU_PIXEL_CNT</name>
1407            <description>ACCU_PIXEL_CNT.</description>
1408            <bitOffset>20</bitOffset>
1409            <bitWidth>1</bitWidth>
1410          </field>
1411          <field>
1412            <name>ACCU_PIXEL_ZERO</name>
1413            <description>ACCU_PIXEL_ZERO.</description>
1414            <bitOffset>21</bitOffset>
1415            <bitWidth>1</bitWidth>
1416          </field>
1417        </fields>
1418      </register>
1419      <register>
1420        <name>VFIFO_CTRL</name>
1421        <description>Video FIFO Control Register.</description>
1422        <addressOffset>0x508</addressOffset>
1423        <size>32</size>
1424        <fields>
1425          <field>
1426            <name>FIFOEN</name>
1427            <description>Video FIFO Enable.</description>
1428            <bitOffset>0</bitOffset>
1429            <bitWidth>1</bitWidth>
1430            <enumeratedValues>
1431              <enumeratedValue>
1432                <name>DIS</name>
1433                <description>Disable.</description>
1434                <value>0</value>
1435              </enumeratedValue>
1436              <enumeratedValue>
1437                <name>EN</name>
1438                <description>Enable.</description>
1439                <value>1</value>
1440              </enumeratedValue>
1441            </enumeratedValues>
1442          </field>
1443          <field>
1444            <name>FLUSH</name>
1445            <description>Write 1 to flush FIFO contents.</description>
1446            <bitOffset>4</bitOffset>
1447            <bitWidth>1</bitWidth>
1448          </field>
1449          <field>
1450            <name>THD</name>
1451            <description>FIFO Threshold.</description>
1452            <bitOffset>8</bitOffset>
1453            <bitWidth>7</bitWidth>
1454          </field>
1455        </fields>
1456      </register>
1457      <register>
1458        <name>VFIFO_STS</name>
1459        <description>Video FIFO Status Register.</description>
1460        <addressOffset>0x50C</addressOffset>
1461        <size>32</size>
1462        <fields>
1463          <field>
1464            <name>FEMPTY</name>
1465            <description>FIFO empty.</description>
1466            <bitOffset>0</bitOffset>
1467            <bitWidth>1</bitWidth>
1468          </field>
1469          <field>
1470            <name>FTHD</name>
1471            <description>FIFO above threshold.</description>
1472            <bitOffset>1</bitOffset>
1473            <bitWidth>1</bitWidth>
1474          </field>
1475          <field>
1476            <name>FFULL</name>
1477            <description>FIFO full.</description>
1478            <bitOffset>2</bitOffset>
1479            <bitWidth>1</bitWidth>
1480          </field>
1481          <field>
1482            <name>UNDERRUN</name>
1483            <description>FIFO underrun</description>
1484            <bitOffset>3</bitOffset>
1485            <bitWidth>1</bitWidth>
1486          </field>
1487          <field>
1488            <name>OVERRUN</name>
1489            <description>FIFO overrun</description>
1490            <bitOffset>4</bitOffset>
1491            <bitWidth>1</bitWidth>
1492          </field>
1493          <field>
1494            <name>OUTSYNC</name>
1495            <description>CSI out of sync</description>
1496            <bitOffset>5</bitOffset>
1497            <bitWidth>1</bitWidth>
1498          </field>
1499          <field>
1500            <name>FMTERR</name>
1501            <description>CSI Pixel Format Error</description>
1502            <bitOffset>6</bitOffset>
1503            <bitWidth>1</bitWidth>
1504          </field>
1505          <field>
1506            <name>AHBWTO</name>
1507            <description>AHB wait time out</description>
1508            <bitOffset>7</bitOffset>
1509            <bitWidth>1</bitWidth>
1510          </field>
1511          <field>
1512            <name>FS</name>
1513            <description>CSI Frame Start</description>
1514            <bitOffset>8</bitOffset>
1515            <bitWidth>1</bitWidth>
1516          </field>
1517          <field>
1518            <name>FE</name>
1519            <description>CSI Frame End</description>
1520            <bitOffset>9</bitOffset>
1521            <bitWidth>1</bitWidth>
1522          </field>
1523          <field>
1524            <name>LS</name>
1525            <description>CSI Line Start</description>
1526            <bitOffset>10</bitOffset>
1527            <bitWidth>1</bitWidth>
1528          </field>
1529          <field>
1530            <name>LE</name>
1531            <description>CSI Line End</description>
1532            <bitOffset>11</bitOffset>
1533            <bitWidth>1</bitWidth>
1534          </field>
1535          <field>
1536            <name>FELT</name>
1537            <description>FIFO remaining entity count</description>
1538            <bitOffset>16</bitOffset>
1539            <bitWidth>7</bitWidth>
1540          </field>
1541          <field>
1542            <name>FMT</name>
1543            <description>CSI pixel format of current transaction</description>
1544            <bitOffset>24</bitOffset>
1545            <bitWidth>6</bitWidth>
1546          </field>
1547        </fields>
1548      </register>
1549      <register>
1550        <name>VFIFO_LINE_NUM</name>
1551        <description>Video FIFO CSI Line Number Per Frame.</description>
1552        <addressOffset>0x510</addressOffset>
1553        <size>32</size>
1554        <fields>
1555          <field>
1556            <name>LINE_NUM</name>
1557            <description>Number of lines per frame.</description>
1558            <bitOffset>0</bitOffset>
1559            <bitWidth>13</bitWidth>
1560          </field>
1561        </fields>
1562      </register>
1563      <register>
1564        <name>VFIFO_PIXEL_NUM</name>
1565        <description>Video FIFO CSI Pixel Number Per Line.</description>
1566        <addressOffset>0x514</addressOffset>
1567        <size>32</size>
1568        <fields>
1569          <field>
1570            <name>PIXEL_NUM</name>
1571            <description>Number of pixels per line.</description>
1572            <bitOffset>0</bitOffset>
1573            <bitWidth>14</bitWidth>
1574          </field>
1575        </fields>
1576      </register>
1577      <register>
1578        <name>VFIFO_LINE_CNT</name>
1579        <description>Video FIFO CSI Line Count.</description>
1580        <addressOffset>0x518</addressOffset>
1581        <size>32</size>
1582        <fields>
1583          <field>
1584            <name>LINE_CNT</name>
1585            <description>Number of received lines in current frame.</description>
1586            <bitOffset>0</bitOffset>
1587            <bitWidth>12</bitWidth>
1588          </field>
1589        </fields>
1590      </register>
1591      <register>
1592        <name>VFIFO_PIXEL_CNT</name>
1593        <description>Video FIFO CSI Pixel Count.</description>
1594        <addressOffset>0x51C</addressOffset>
1595        <size>32</size>
1596        <fields>
1597          <field>
1598            <name>PIXEL_CNT</name>
1599            <description>Number of received pixels in current line in a frame.</description>
1600            <bitOffset>0</bitOffset>
1601            <bitWidth>13</bitWidth>
1602          </field>
1603        </fields>
1604      </register>
1605      <register>
1606        <name>VFIFO_FRAME_STS</name>
1607        <description>Video FIFO Frame Status Register.</description>
1608        <addressOffset>0x520</addressOffset>
1609        <size>32</size>
1610        <fields>
1611          <field>
1612            <name>FRAME_STATE</name>
1613            <description>Frame State.</description>
1614            <bitOffset>0</bitOffset>
1615            <bitWidth>3</bitWidth>
1616          </field>
1617          <field>
1618            <name>ERROR_CODE</name>
1619            <description>Error Codes.</description>
1620            <bitOffset>3</bitOffset>
1621            <bitWidth>3</bitWidth>
1622          </field>
1623        </fields>
1624      </register>
1625      <register>
1626        <name>VFIFO_RAW_CTRL</name>
1627        <description>Video FIFO RAW-to-RGB Control Register.</description>
1628        <addressOffset>0x524</addressOffset>
1629        <size>32</size>
1630        <fields>
1631          <field>
1632            <name>RAW_CEN</name>
1633            <description>RAW conversion enable.</description>
1634            <bitOffset>0</bitOffset>
1635            <bitWidth>1</bitWidth>
1636          </field>
1637          <field>
1638            <name>RAW_FF_AFO</name>
1639            <description>RAW conversion FIFO automatic flush-out.</description>
1640            <bitOffset>1</bitOffset>
1641            <bitWidth>1</bitWidth>
1642          </field>
1643          <field>
1644            <name>RAW_FF_FO</name>
1645            <description>RAW conversion FIFO flush-out trigger.</description>
1646            <bitOffset>4</bitOffset>
1647            <bitWidth>1</bitWidth>
1648          </field>
1649          <field>
1650            <name>RAW_FMT</name>
1651            <description>RAW format.</description>
1652            <bitOffset>8</bitOffset>
1653            <bitWidth>2</bitWidth>
1654            <enumeratedValues>
1655              <enumeratedValue>
1656                <name>RGRG_GBGB</name>
1657                <description>RGRG GBGB</description>
1658                <value>0</value>
1659              </enumeratedValue>
1660              <enumeratedValue>
1661                <name>GRGR_BGBG</name>
1662                <description>GRGR BGBG</description>
1663                <value>1</value>
1664              </enumeratedValue>
1665              <enumeratedValue>
1666                <name>GBGB_RGRG</name>
1667                <description>GBGB RGRG</description>
1668                <value>2</value>
1669              </enumeratedValue>
1670              <enumeratedValue>
1671                <name>BGBG_GRGR</name>
1672                <description>BGBG GRGR</description>
1673                <value>3</value>
1674              </enumeratedValue>
1675            </enumeratedValues>
1676          </field>
1677          <field>
1678            <name>RGB_TYP</name>
1679            <description>RGB type.</description>
1680            <bitOffset>12</bitOffset>
1681            <bitWidth>3</bitWidth>
1682            <enumeratedValues>
1683              <enumeratedValue>
1684                <name>RGB444</name>
1685                <description>RGB444.</description>
1686                <value>0</value>
1687              </enumeratedValue>
1688              <enumeratedValue>
1689                <name>RGB555</name>
1690                <description>RGB555.</description>
1691                <value>1</value>
1692              </enumeratedValue>
1693              <enumeratedValue>
1694                <name>RGB565</name>
1695                <description>RGB565.</description>
1696                <value>2</value>
1697              </enumeratedValue>
1698              <enumeratedValue>
1699                <name>RGB666</name>
1700                <description>RGB666.</description>
1701                <value>3</value>
1702              </enumeratedValue>
1703              <enumeratedValue>
1704                <name>RGG888</name>
1705                <description>RGG888.</description>
1706                <value>4</value>
1707              </enumeratedValue>
1708            </enumeratedValues>
1709          </field>
1710        </fields>
1711      </register>
1712      <register>
1713        <name>VFIFO_RAW_BUF0_ADDR</name>
1714        <description>Video FIFO RAW-to-RGB Line Buffer0 Address.</description>
1715        <addressOffset>0x528</addressOffset>
1716        <size>32</size>
1717        <fields>
1718          <field>
1719            <name>ADDR</name>
1720            <description>RAM address for RAW conversion buffer 0, word-aligned.</description>
1721            <bitOffset>2</bitOffset>
1722            <bitWidth>30</bitWidth>
1723          </field>
1724        </fields>
1725      </register>
1726      <register>
1727        <name>VFIFO_RAW_BUF1_ADDR</name>
1728        <description>Video FIFO RAW-to-RGB Line Buffer1 Address.</description>
1729        <addressOffset>0x52C</addressOffset>
1730        <size>32</size>
1731        <fields>
1732          <field>
1733            <name>ADDR</name>
1734            <description>RAM address for RAW conversion buffer 1, word-aligned.</description>
1735            <bitOffset>2</bitOffset>
1736            <bitWidth>30</bitWidth>
1737          </field>
1738        </fields>
1739      </register>
1740      <register>
1741        <name>VFIFO_AHBM_CTRL</name>
1742        <description>Video FIFO AHB Master Control Register.</description>
1743        <addressOffset>0x530</addressOffset>
1744        <size>32</size>
1745        <fields>
1746          <field>
1747            <name>AHBMEN</name>
1748            <description>AHB Master Enable.</description>
1749            <bitOffset>0</bitOffset>
1750            <bitWidth>1</bitWidth>
1751          </field>
1752          <field>
1753            <name>AHBMCLR</name>
1754            <description>AHB Master Status Clear.</description>
1755            <bitOffset>1</bitOffset>
1756            <bitWidth>1</bitWidth>
1757          </field>
1758          <field>
1759            <name>BSTLEN</name>
1760            <description>AHB Burst Length.</description>
1761            <bitOffset>4</bitOffset>
1762            <bitWidth>2</bitWidth>
1763            <enumeratedValues>
1764              <enumeratedValue>
1765                <name>VFIFO_THD</name>
1766                <description>Video FIFO THD.</description>
1767                <value>0</value>
1768              </enumeratedValue>
1769              <enumeratedValue>
1770                <name>ONE_WORD</name>
1771                <description>ONE_WORD.</description>
1772                <value>1</value>
1773              </enumeratedValue>
1774              <enumeratedValue>
1775                <name>FOUR_WORDS</name>
1776                <description>FOUR_WORDS.</description>
1777                <value>2</value>
1778              </enumeratedValue>
1779              <enumeratedValue>
1780                <name>EIGHT_WORDS</name>
1781                <description>EIGHT_WORDS.</description>
1782                <value>3</value>
1783              </enumeratedValue>
1784            </enumeratedValues>
1785          </field>
1786        </fields>
1787      </register>
1788      <register>
1789        <name>VFIFO_AHBM_STS</name>
1790        <description>Video FIFO AHB Master Status Register.</description>
1791        <addressOffset>0x534</addressOffset>
1792        <size>32</size>
1793        <fields>
1794          <field>
1795            <name>HRDY_TO</name>
1796            <description>AHB master HREADY time-out.</description>
1797            <bitOffset>0</bitOffset>
1798            <bitWidth>1</bitWidth>
1799          </field>
1800          <field>
1801            <name>IDLE_TO</name>
1802            <description>AHB master Idle time-out.</description>
1803            <bitOffset>1</bitOffset>
1804            <bitWidth>1</bitWidth>
1805          </field>
1806          <field>
1807            <name>TRANS_MAX</name>
1808            <description>AHB master maximal transfer count occurrence.</description>
1809            <bitOffset>2</bitOffset>
1810            <bitWidth>1</bitWidth>
1811          </field>
1812        </fields>
1813      </register>
1814      <register>
1815        <name>VFIFO_AHBM_START_ADDR</name>
1816        <description>Video FIFO AHB Master Start Address Register.</description>
1817        <addressOffset>0x538</addressOffset>
1818        <size>32</size>
1819        <fields>
1820          <field>
1821            <name>AHBM_START_ADDR</name>
1822            <description>AHB master transfer starting address, word-aligned.</description>
1823            <bitOffset>2</bitOffset>
1824            <bitWidth>30</bitWidth>
1825          </field>
1826        </fields>
1827      </register>
1828      <register>
1829        <name>VFIFO_AHBM_ADDR_RANGE</name>
1830        <description>Video FIFO AHB Master Address Range Register.</description>
1831        <addressOffset>0x53C</addressOffset>
1832        <size>32</size>
1833        <fields>
1834          <field>
1835            <name>AHBM_ADDR_RANGE</name>
1836            <description>AHB master address range.</description>
1837            <bitOffset>2</bitOffset>
1838            <bitWidth>14</bitWidth>
1839          </field>
1840        </fields>
1841      </register>
1842      <register>
1843        <name>VFIFO_AHBM_MAX_TRANS</name>
1844        <description>Video FIFO AHB Master Maximal Transfer Number Register.</description>
1845        <addressOffset>0x540</addressOffset>
1846        <size>32</size>
1847        <fields>
1848          <field>
1849            <name>AHBM_MAX_TRANS</name>
1850            <description>AHB master maximal number of transfer word count.</description>
1851            <bitOffset>0</bitOffset>
1852            <bitWidth>32</bitWidth>
1853          </field>
1854        </fields>
1855      </register>
1856      <register>
1857        <name>VFIFO_AHBM_TRANS_CNT</name>
1858        <description>Video FIFO AHB Master Transfer Count Register.</description>
1859        <addressOffset>0x544</addressOffset>
1860        <size>32</size>
1861        <fields>
1862          <field>
1863            <name>AHBM_TRANS_CNT</name>
1864            <description>AHB master number of words been transferred.</description>
1865            <bitOffset>0</bitOffset>
1866            <bitWidth>32</bitWidth>
1867          </field>
1868        </fields>
1869      </register>
1870      <!-- Interrupt Control Registers -->
1871      <register>
1872        <name>RX_EINT_VFF_IE</name>
1873        <description>RX Video FIFO Interrupt Enable Register.</description>
1874        <addressOffset>0x600</addressOffset>
1875        <size>32</size>
1876        <fields>
1877          <field>
1878            <name>FNEMPTY</name>
1879            <description>Video FIFO not empty interrupt enable.</description>
1880            <bitOffset>0</bitOffset>
1881            <bitWidth>1</bitWidth>
1882          </field>
1883          <field>
1884            <name>FTHD</name>
1885            <description>Video FIFO above threshold interrupt enable.</description>
1886            <bitOffset>1</bitOffset>
1887            <bitWidth>1</bitWidth>
1888          </field>
1889          <field>
1890            <name>FFULL</name>
1891            <description>Video FIFO full interrupt enable.</description>
1892            <bitOffset>2</bitOffset>
1893            <bitWidth>1</bitWidth>
1894          </field>
1895          <field>
1896            <name>UNDERRUN</name>
1897            <description>Video FIFO underrun interrupt enable</description>
1898            <bitOffset>3</bitOffset>
1899            <bitWidth>1</bitWidth>
1900          </field>
1901          <field>
1902            <name>OVERRUN</name>
1903            <description>Video FIFO overrun interrupt enable</description>
1904            <bitOffset>4</bitOffset>
1905            <bitWidth>1</bitWidth>
1906          </field>
1907          <field>
1908            <name>OUTSYNC</name>
1909            <description>CSI out of sync interrupt enable</description>
1910            <bitOffset>5</bitOffset>
1911            <bitWidth>1</bitWidth>
1912          </field>
1913          <field>
1914            <name>FMTERR</name>
1915            <description>CSI Pixel Format Error interrupt enable</description>
1916            <bitOffset>6</bitOffset>
1917            <bitWidth>1</bitWidth>
1918          </field>
1919          <field>
1920            <name>AHBWTO</name>
1921            <description>AHB wait time out interrupt enable</description>
1922            <bitOffset>7</bitOffset>
1923            <bitWidth>1</bitWidth>
1924          </field>
1925          <field>
1926            <name>FS</name>
1927            <description>CSI Frame Start interrupt enable</description>
1928            <bitOffset>8</bitOffset>
1929            <bitWidth>1</bitWidth>
1930          </field>
1931          <field>
1932            <name>FE</name>
1933            <description>CSI Frame End interrupt enable</description>
1934            <bitOffset>9</bitOffset>
1935            <bitWidth>1</bitWidth>
1936          </field>
1937          <field>
1938            <name>LS</name>
1939            <description>CSI Line Start interrupt enable</description>
1940            <bitOffset>10</bitOffset>
1941            <bitWidth>1</bitWidth>
1942          </field>
1943          <field>
1944            <name>LE</name>
1945            <description>CSI Line End interrupt enable</description>
1946            <bitOffset>11</bitOffset>
1947            <bitWidth>1</bitWidth>
1948          </field>
1949          <field>
1950            <name>RAW_OVR</name>
1951            <description>Raw FIFO Overrun Interrupt Enable</description>
1952            <bitOffset>12</bitOffset>
1953            <bitWidth>1</bitWidth>
1954          </field>
1955          <field>
1956            <name>RAW_AHBERR</name>
1957            <description>Raw AHB Error Interrupt Enable</description>
1958            <bitOffset>13</bitOffset>
1959            <bitWidth>1</bitWidth>
1960          </field>
1961          <field>
1962            <name>FNEMP_MD</name>
1963            <description>Video FIFO not empty detection mode</description>
1964            <bitOffset>16</bitOffset>
1965            <bitWidth>1</bitWidth>
1966          </field>
1967          <field>
1968            <name>FTHD_MD</name>
1969            <description>Video FIFO threshold detection mode</description>
1970            <bitOffset>17</bitOffset>
1971            <bitWidth>1</bitWidth>
1972          </field>
1973          <field>
1974            <name>FFUL_MD</name>
1975            <description>Video FIFO full detection mode</description>
1976            <bitOffset>18</bitOffset>
1977            <bitWidth>1</bitWidth>
1978          </field>
1979          <field>
1980            <name>AHBM_RDTO</name>
1981            <description>AHBM_RDTO</description>
1982            <bitOffset>24</bitOffset>
1983            <bitWidth>1</bitWidth>
1984          </field>
1985          <field>
1986            <name>AHBM_IDTO</name>
1987            <description>AHBM_IDTO</description>
1988            <bitOffset>25</bitOffset>
1989            <bitWidth>1</bitWidth>
1990          </field>
1991          <field>
1992            <name>AHBM_MAX</name>
1993            <description>AHBM_MAX</description>
1994            <bitOffset>26</bitOffset>
1995            <bitWidth>1</bitWidth>
1996          </field>
1997        </fields>
1998      </register>
1999      <register>
2000        <name>RX_EINT_VFF_IF</name>
2001        <description>RX Video FIFO Interrupt Flag Register.</description>
2002        <addressOffset>0x604</addressOffset>
2003        <size>32</size>
2004        <fields>
2005          <field>
2006            <name>FNEMPTY</name>
2007            <description>Video FIFO not empty interrupt flag.</description>
2008            <bitOffset>0</bitOffset>
2009            <bitWidth>1</bitWidth>
2010          </field>
2011          <field>
2012            <name>FTHD</name>
2013            <description>Video FIFO above threshold interrupt flag.</description>
2014            <bitOffset>1</bitOffset>
2015            <bitWidth>1</bitWidth>
2016          </field>
2017          <field>
2018            <name>FFULL</name>
2019            <description>Video FIFO full interrupt flag.</description>
2020            <bitOffset>2</bitOffset>
2021            <bitWidth>1</bitWidth>
2022          </field>
2023          <field>
2024            <name>UNDERRUN</name>
2025            <description>Video FIFO underrun interrupt flag</description>
2026            <bitOffset>3</bitOffset>
2027            <bitWidth>1</bitWidth>
2028          </field>
2029          <field>
2030            <name>OVERRUN</name>
2031            <description>Video FIFO overrun interrupt flag</description>
2032            <bitOffset>4</bitOffset>
2033            <bitWidth>1</bitWidth>
2034          </field>
2035          <field>
2036            <name>OUTSYNC</name>
2037            <description>CSI out of sync interrupt flag</description>
2038            <bitOffset>5</bitOffset>
2039            <bitWidth>1</bitWidth>
2040          </field>
2041          <field>
2042            <name>FMTERR</name>
2043            <description>CSI Pixel Format Error interrupt flag</description>
2044            <bitOffset>6</bitOffset>
2045            <bitWidth>1</bitWidth>
2046          </field>
2047          <field>
2048            <name>AHBWTO</name>
2049            <description>AHB wait time out interrupt flag</description>
2050            <bitOffset>7</bitOffset>
2051            <bitWidth>1</bitWidth>
2052          </field>
2053          <field>
2054            <name>FS</name>
2055            <description>CSI Frame Start interrupt flag</description>
2056            <bitOffset>8</bitOffset>
2057            <bitWidth>1</bitWidth>
2058          </field>
2059          <field>
2060            <name>FE</name>
2061            <description>CSI Frame End interrupt flag</description>
2062            <bitOffset>9</bitOffset>
2063            <bitWidth>1</bitWidth>
2064          </field>
2065          <field>
2066            <name>LS</name>
2067            <description>CSI Line Start interrupt flag</description>
2068            <bitOffset>10</bitOffset>
2069            <bitWidth>1</bitWidth>
2070          </field>
2071          <field>
2072            <name>LE</name>
2073            <description>CSI Line End interrupt flag</description>
2074            <bitOffset>11</bitOffset>
2075            <bitWidth>1</bitWidth>
2076          </field>
2077          <field>
2078            <name>RAW_OVR</name>
2079            <description>Raw FIFO Overrun Interrupt Enable</description>
2080            <bitOffset>12</bitOffset>
2081            <bitWidth>1</bitWidth>
2082          </field>
2083          <field>
2084            <name>RAW_AHBERR</name>
2085            <description>Raw AHB Error Interrupt Enable</description>
2086            <bitOffset>13</bitOffset>
2087            <bitWidth>1</bitWidth>
2088          </field>
2089          <field>
2090            <name>AHBM_RDTO</name>
2091            <description>AHBM_RDTO</description>
2092            <bitOffset>24</bitOffset>
2093            <bitWidth>1</bitWidth>
2094          </field>
2095          <field>
2096            <name>AHBM_IDTO</name>
2097            <description>AHBM_IDTO</description>
2098            <bitOffset>25</bitOffset>
2099            <bitWidth>1</bitWidth>
2100          </field>
2101          <field>
2102            <name>AHBM_MAX</name>
2103            <description>AHBM_MAX</description>
2104            <bitOffset>26</bitOffset>
2105            <bitWidth>1</bitWidth>
2106          </field>
2107        </fields>
2108      </register>
2109      <register>
2110        <name>RX_EINT_PPI_IE</name>
2111        <description>RX D-PHY Interrupt Enable Register.</description>
2112        <addressOffset>0x608</addressOffset>
2113        <size>32</size>
2114        <fields>
2115          <field>
2116            <name>DL0STOP</name>
2117            <description>DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt enable.</description>
2118            <bitOffset>0</bitOffset>
2119            <bitWidth>1</bitWidth>
2120          </field>
2121          <field>
2122            <name>DL1STOP</name>
2123            <description>DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt enable.</description>
2124            <bitOffset>1</bitOffset>
2125            <bitWidth>1</bitWidth>
2126          </field>
2127          <field>
2128            <name>CL0STOP</name>
2129            <description>DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt enable.</description>
2130            <bitOffset>4</bitOffset>
2131            <bitWidth>1</bitWidth>
2132          </field>
2133          <field>
2134            <name>DL0ECONT0</name>
2135            <description>DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt enable</description>
2136            <bitOffset>6</bitOffset>
2137            <bitWidth>1</bitWidth>
2138          </field>
2139          <field>
2140            <name>DL0ECONT1</name>
2141            <description>DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt enable</description>
2142            <bitOffset>7</bitOffset>
2143            <bitWidth>1</bitWidth>
2144          </field>
2145          <field>
2146            <name>DL0ESOT</name>
2147            <description>DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt enable</description>
2148            <bitOffset>8</bitOffset>
2149            <bitWidth>1</bitWidth>
2150          </field>
2151          <field>
2152            <name>DL1ESOT</name>
2153            <description>DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt enable</description>
2154            <bitOffset>9</bitOffset>
2155            <bitWidth>1</bitWidth>
2156          </field>
2157          <field>
2158            <name>DL0ESOTS</name>
2159            <description>DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt enable</description>
2160            <bitOffset>12</bitOffset>
2161            <bitWidth>1</bitWidth>
2162          </field>
2163          <field>
2164            <name>DL1ESOTS</name>
2165            <description>DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt enable</description>
2166            <bitOffset>13</bitOffset>
2167            <bitWidth>1</bitWidth>
2168          </field>
2169          <field>
2170            <name>DL0EESC</name>
2171            <description>DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt enable</description>
2172            <bitOffset>16</bitOffset>
2173            <bitWidth>1</bitWidth>
2174          </field>
2175          <field>
2176            <name>DL1EESC</name>
2177            <description>DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt enable</description>
2178            <bitOffset>17</bitOffset>
2179            <bitWidth>1</bitWidth>
2180          </field>
2181          <field>
2182            <name>DL0ESESC</name>
2183            <description>DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable</description>
2184            <bitOffset>20</bitOffset>
2185            <bitWidth>1</bitWidth>
2186          </field>
2187          <field>
2188            <name>DL1ESESC</name>
2189            <description>DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable</description>
2190            <bitOffset>21</bitOffset>
2191            <bitWidth>1</bitWidth>
2192          </field>
2193          <field>
2194            <name>DL0ECTL</name>
2195            <description>DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt enable</description>
2196            <bitOffset>24</bitOffset>
2197            <bitWidth>1</bitWidth>
2198          </field>
2199          <field>
2200            <name>DL1ECTL</name>
2201            <description>DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt enable</description>
2202            <bitOffset>25</bitOffset>
2203            <bitWidth>1</bitWidth>
2204          </field>
2205        </fields>
2206      </register>
2207      <register>
2208        <name>RX_EINT_PPI_IF</name>
2209        <description>RX D-PHY Interrupt Flag Register.</description>
2210        <addressOffset>0x60C</addressOffset>
2211        <size>32</size>
2212        <fields>
2213          <field>
2214            <name>DL0STOP</name>
2215            <description>DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt flag.</description>
2216            <bitOffset>0</bitOffset>
2217            <bitWidth>1</bitWidth>
2218          </field>
2219          <field>
2220            <name>DL1STOP</name>
2221            <description>DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt flag.</description>
2222            <bitOffset>1</bitOffset>
2223            <bitWidth>1</bitWidth>
2224          </field>
2225          <field>
2226            <name>CL0STOP</name>
2227            <description>DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt flag.</description>
2228            <bitOffset>4</bitOffset>
2229            <bitWidth>1</bitWidth>
2230          </field>
2231          <field>
2232            <name>DL0ECONT0</name>
2233            <description>DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt flag</description>
2234            <bitOffset>6</bitOffset>
2235            <bitWidth>1</bitWidth>
2236          </field>
2237          <field>
2238            <name>DL0ECONT1</name>
2239            <description>DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt flag</description>
2240            <bitOffset>7</bitOffset>
2241            <bitWidth>1</bitWidth>
2242          </field>
2243          <field>
2244            <name>DL0ESOT</name>
2245            <description>DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt flag</description>
2246            <bitOffset>8</bitOffset>
2247            <bitWidth>1</bitWidth>
2248          </field>
2249          <field>
2250            <name>DL1ESOT</name>
2251            <description>DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt flag</description>
2252            <bitOffset>9</bitOffset>
2253            <bitWidth>1</bitWidth>
2254          </field>
2255          <field>
2256            <name>DL0ESOTS</name>
2257            <description>DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt flag</description>
2258            <bitOffset>12</bitOffset>
2259            <bitWidth>1</bitWidth>
2260          </field>
2261          <field>
2262            <name>DL1ESOTS</name>
2263            <description>DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt flag</description>
2264            <bitOffset>13</bitOffset>
2265            <bitWidth>1</bitWidth>
2266          </field>
2267          <field>
2268            <name>DL0EESC</name>
2269            <description>DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt flag</description>
2270            <bitOffset>16</bitOffset>
2271            <bitWidth>1</bitWidth>
2272          </field>
2273          <field>
2274            <name>DL1EESC</name>
2275            <description>DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt flag</description>
2276            <bitOffset>17</bitOffset>
2277            <bitWidth>1</bitWidth>
2278          </field>
2279          <field>
2280            <name>DL0ESESC</name>
2281            <description>DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag</description>
2282            <bitOffset>20</bitOffset>
2283            <bitWidth>1</bitWidth>
2284          </field>
2285          <field>
2286            <name>DL1ESESC</name>
2287            <description>DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag</description>
2288            <bitOffset>21</bitOffset>
2289            <bitWidth>1</bitWidth>
2290          </field>
2291          <field>
2292            <name>DL0ECTL</name>
2293            <description>DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt flag</description>
2294            <bitOffset>24</bitOffset>
2295            <bitWidth>1</bitWidth>
2296          </field>
2297          <field>
2298            <name>DL1ECTL</name>
2299            <description>DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt flag</description>
2300            <bitOffset>25</bitOffset>
2301            <bitWidth>1</bitWidth>
2302          </field>
2303        </fields>
2304      </register>
2305      <register>
2306        <name>RX_EINT_CTRL_IE</name>
2307        <description>RX Controller Interrupt Enable Register.</description>
2308        <addressOffset>0x610</addressOffset>
2309        <size>32</size>
2310        <fields>
2311          <field>
2312            <name>EECC2</name>
2313            <description>CSI RX ECC 2-bit Error interrupt enable.</description>
2314            <bitOffset>0</bitOffset>
2315            <bitWidth>1</bitWidth>
2316          </field>
2317          <field>
2318            <name>EECC1</name>
2319            <description>CSI RX ECC 1-bit Error interrupt enable.</description>
2320            <bitOffset>1</bitOffset>
2321            <bitWidth>1</bitWidth>
2322          </field>
2323          <field>
2324            <name>ECRC</name>
2325            <description>CSI RX CRC Error interrupt enable.</description>
2326            <bitOffset>2</bitOffset>
2327            <bitWidth>1</bitWidth>
2328          </field>
2329          <field>
2330            <name>EID</name>
2331            <description>CSI RX Packet Header Data ID Error interrupt enable</description>
2332            <bitOffset>3</bitOffset>
2333            <bitWidth>1</bitWidth>
2334          </field>
2335          <field>
2336            <name>PKTFFOV</name>
2337            <description>CSI RX Packet FIFO Overrun interrupt enable</description>
2338            <bitOffset>4</bitOffset>
2339            <bitWidth>1</bitWidth>
2340          </field>
2341          <field>
2342            <name>DL0ULPSA</name>
2343            <description>CSI Data Lane0 ULPSS Active interrupt enable</description>
2344            <bitOffset>8</bitOffset>
2345            <bitWidth>1</bitWidth>
2346          </field>
2347          <field>
2348            <name>DL1ULPSA</name>
2349            <description>CSI Data Lane1 ULPSS Active interrupt enable</description>
2350            <bitOffset>9</bitOffset>
2351            <bitWidth>1</bitWidth>
2352          </field>
2353          <field>
2354            <name>DL0ULPSM</name>
2355            <description>CSI Data Lane0 ULPSS Mark interrupt enable</description>
2356            <bitOffset>12</bitOffset>
2357            <bitWidth>1</bitWidth>
2358          </field>
2359          <field>
2360            <name>DL1ULPSM</name>
2361            <description>CSI Data Lane1 ULPSS Mark interrupt enable</description>
2362            <bitOffset>13</bitOffset>
2363            <bitWidth>1</bitWidth>
2364          </field>
2365          <field>
2366            <name>CL0ULPSA</name>
2367            <description>CSI Clock Lane0 ULPSS Active interrupt enable</description>
2368            <bitOffset>16</bitOffset>
2369            <bitWidth>1</bitWidth>
2370          </field>
2371          <field>
2372            <name>CL0ULPSM</name>
2373            <description>CSI Data Lane0 ULPSS Mark interrupt enable</description>
2374            <bitOffset>17</bitOffset>
2375            <bitWidth>1</bitWidth>
2376          </field>
2377        </fields>
2378      </register>
2379      <register>
2380        <name>RX_EINT_CTRL_IF</name>
2381        <description>RX Controller Interrupt Flag Register.</description>
2382        <addressOffset>0x614</addressOffset>
2383        <size>32</size>
2384        <fields>
2385          <field>
2386            <name>EECC2</name>
2387            <description>CSI RX ECC 2-bit Error interrupt flag.</description>
2388            <bitOffset>0</bitOffset>
2389            <bitWidth>1</bitWidth>
2390          </field>
2391          <field>
2392            <name>EECC1</name>
2393            <description>CSI RX ECC 1-bit Error interrupt flag.</description>
2394            <bitOffset>1</bitOffset>
2395            <bitWidth>1</bitWidth>
2396          </field>
2397          <field>
2398            <name>ECRC</name>
2399            <description>CSI RX CRC Error interrupt flag.</description>
2400            <bitOffset>2</bitOffset>
2401            <bitWidth>1</bitWidth>
2402          </field>
2403          <field>
2404            <name>EID</name>
2405            <description>CSI RX Packet Header Data ID Error interrupt flag</description>
2406            <bitOffset>3</bitOffset>
2407            <bitWidth>1</bitWidth>
2408          </field>
2409          <field>
2410            <name>PKTFFOV</name>
2411            <description>CSI RX Packet FIFO Overrun interrupt flag</description>
2412            <bitOffset>4</bitOffset>
2413            <bitWidth>1</bitWidth>
2414          </field>
2415          <field>
2416            <name>DL0ULPSA</name>
2417            <description>CSI Data Lane0 ULPSS Active interrupt flag</description>
2418            <bitOffset>8</bitOffset>
2419            <bitWidth>1</bitWidth>
2420          </field>
2421          <field>
2422            <name>DL1ULPSA</name>
2423            <description>CSI Data Lane1 ULPSS Active interrupt flag</description>
2424            <bitOffset>9</bitOffset>
2425            <bitWidth>1</bitWidth>
2426          </field>
2427          <field>
2428            <name>DL0ULPSM</name>
2429            <description>CSI Data Lane0 ULPSS Mark interrupt flag</description>
2430            <bitOffset>12</bitOffset>
2431            <bitWidth>1</bitWidth>
2432          </field>
2433          <field>
2434            <name>DL1ULPSM</name>
2435            <description>CSI Data Lane1 ULPSS Mark interrupt flag</description>
2436            <bitOffset>13</bitOffset>
2437            <bitWidth>1</bitWidth>
2438          </field>
2439          <field>
2440            <name>CL0ULPSA</name>
2441            <description>CSI Clock Lane0 ULPSS Active interrupt flag</description>
2442            <bitOffset>16</bitOffset>
2443            <bitWidth>1</bitWidth>
2444          </field>
2445          <field>
2446            <name>CL0ULPSM</name>
2447            <description>CSI Data Lane0 ULPSS Mark interrupt flag</description>
2448            <bitOffset>17</bitOffset>
2449            <bitWidth>1</bitWidth>
2450          </field>
2451        </fields>
2452      </register>
2453      <register>
2454        <name>PPI_STOPSTATE</name>
2455        <description>DPHY PPI Stop State Register.</description>
2456        <addressOffset>0x700</addressOffset>
2457        <size>32</size>
2458        <fields>
2459          <field>
2460            <name>DL0STOP</name>
2461            <description>CSI Data Lane0 Stop State.</description>
2462            <bitOffset>0</bitOffset>
2463            <bitWidth>1</bitWidth>
2464          </field>
2465          <field>
2466            <name>DL1STOP</name>
2467            <description>CSI Data Lane1 Stop State.</description>
2468            <bitOffset>1</bitOffset>
2469            <bitWidth>1</bitWidth>
2470          </field>
2471          <field>
2472            <name>CL0STOP</name>
2473            <description>CSI Clock Lane0 Stop State.</description>
2474            <bitOffset>2</bitOffset>
2475            <bitWidth>1</bitWidth>
2476          </field>
2477        </fields>
2478      </register>
2479      <register>
2480        <name>PPI_TURNAROUND_CFG</name>
2481        <description>DPHY PPI Turn-Around Configuration Register.</description>
2482        <addressOffset>0x704</addressOffset>
2483        <size>32</size>
2484        <fields>
2485          <field>
2486            <name>DL0TAREQ</name>
2487            <description>CSI Data Lane0 turn around request.</description>
2488            <bitOffset>0</bitOffset>
2489            <bitWidth>1</bitWidth>
2490          </field>
2491          <field>
2492            <name>DL0TADIS</name>
2493            <description>CSI Data Lane0 turn around disable.</description>
2494            <bitOffset>1</bitOffset>
2495            <bitWidth>1</bitWidth>
2496          </field>
2497          <field>
2498            <name>DL0FRCRX</name>
2499            <description>CSI Data Lane0 force RX mode.</description>
2500            <bitOffset>2</bitOffset>
2501            <bitWidth>1</bitWidth>
2502          </field>
2503        </fields>
2504      </register>
2505    </registers>
2506  </peripheral>
2507  <!-- CSI2 -->
2508</device>