CSI2 Camera Serial Interface Registers. 0x40062000 0x00 0x1000 registers CFG_NUM_LANES CFG_NUM_LANES. 0x000 32 LANES Num Lanes for RX controller. 0 4 CFG_CLK_LANE_EN CFG_CLK_LANE_EN. 0x004 32 EN Enable lane clock setting for controller. 0 1 CFG_DATA_LANE_EN CFG_DATA_LANE_EN. 0x008 32 EN Enable data lane setting for controller. 0 8 CFG_FLUSH_COUNT CFG_FLUSH_COUNT. 0x00C 32 COUNT Flush count setting for controller. 0 4 CFG_BIT_ERR CFG_BIT_ERR. 0x010 32 MBE Multiple bit ECC error. 0 1 SBE Single bit ECC error. 1 1 HEADER Header bit location of single bit ECC error. 2 5 CRC CRC error. 7 1 VID_ERR_SEND_LVL Video Error Send Level. 8 1 VID_ERR_FIFO_WR_OV Video Error Fifo Overflow. 9 1 IRQ_STATUS IRQ_STATUS. 0x014 32 CRC CRC error. 0 1 SBE Single bit ECC error. 1 1 MBE Multiple bit ECC error. 2 1 ULPS_ACTIVE ULPS active status change. 3 1 ULPS_MARK_ACTIVE ULPS mark active status change. 4 1 VID_ERR_SEND_LVL Video Error Send Level. 5 1 VID_ERR_FIFO_WR_OV Video Error Fifo Overflow. 6 1 IRQ_ENABLE IRQ_ENABLE. 0x018 32 CRC CRC error. 0 1 SBE Single bit ECC error. 1 1 MBE Multiple bit ECC error. 2 1 ULPS_ACTIVE ULPS active status change. 3 1 ULPS_MARK_ACTIVE ULPS mark active status change. 4 1 VID_ERR_SEND_LVL Video Error Send Level. 5 1 VID_ERR_FIFO_WR_OV Video Error Fifo Overflow. 6 1 IRQ_CLR IRQ_CLR. 0x01C 32 CRC CRC error. 0 1 SBE Single bit ECC error. 1 1 MBE Multiple bit ECC error. 2 1 ULPS_ACTIVE ULPS active status change. 3 1 ULPS_MARK_ACTIVE ULPS mark active status change. 4 1 VID_ERR_SEND_LVL Video Error Send Level. 5 1 VID_ERR_FIFO_WR_OV Video Error Fifo Overflow. 6 1 ULPS_CLK_STATUS ULPS_CLK_STATUS. 0x020 32 FIFO FIFO Read/Write register. 0 1 ULPS_STATUS ULPS_STATUS. 0x024 32 DATA_LANE0 Data Lane 0. 0 1 DATA_LANE1 Data Lane 1. 1 1 ULPS_CLK_MARK_STATUS ULPS_CLK_MARK_STATUS. 0x028 32 CLK_LANE Clock Lane. 0 1 ULPS_MARK_STATUS ULPS_MARK_STATUS. 0x02C 32 DATA_LANE0 Data Lane 0. 0 1 DATA_LANE1 Data Lane 1. 1 1 PPI_ERRSOT_HS PPI_ERRSOT_HS. 0x030 32 PPI_ERRSOTSYNC_HS PPI_ERRSOTSYNC_HS. 0x034 32 PPI_ERRESC PPI_ERRESC. 0x038 32 PPI_ERRSYNCESC PPI_ERRSYNCESC. 0x03C 32 PPI_ERRCONTROL PPI_ERRCONTROL. 0x040 32 CFG_CPHY_EN CFG_CPHY_EN. 0x044 32 CFG_PPI_16_EN CFG_PPI_16_EN. 0x048 32 CFG_PACKET_INTERFACE_EN CFG_PACKET_INTERFACE_EN. 0x04C 32 CFG_VCX_EN CFG_VCX_EN. 0x050 32 CFG_BYTE_DATA_FORMAT CFG_BYTE_DATA_FORMAT. 0x054 32 CFG_DISABLE_PAYLOAD_0 CFG_DISABLE_PAYLOAD_0. 0x058 32 NULL NULL. 0 1 BLANK BLANK. 1 1 EMBEDDED EMBEDDED. 2 1 YUV420_8BIT YUV420_8BIT. 8 1 YUV420_10BIT YUV420_10BIT. 9 1 YUV420_8BIT_LEG YUV420_8BIT_LEG. 10 1 YUV420_8BIT_CSP YUV420_8BIT_CSP. 12 1 YUV420_10BIT_CSP YUV420_10BIT_CSP. 13 1 YUV422_8BIT YUV422_8BIT. 14 1 YUV422_10BIT YUV422_10BIT. 15 1 RGB444 RGB444. 16 1 RGB555 RGB555. 17 1 RGB565 RGB565. 18 1 RGB666 RGB666. 19 1 RGB888 RGB888. 20 1 RAW6 RAW6. 24 1 RAW7 RAW7. 25 1 RAW8 RAW8. 26 1 RAW10 RAW10. 27 1 RAW12 RAW12. 28 1 RAW14 RAW14. 29 1 RAW16 RAW16. 30 1 RAW20 RAW20. 31 1 CFG_DISABLE_PAYLOAD_1 CFG_DISABLE_PAYLOAD_1. 0x05C 32 USR_DEF_TYPE30 User defined type 0x30. 0 1 USR_DEF_TYPE31 User defined type 0x31. 1 1 USR_DEF_TYPE32 User defined type 0x32. 2 1 USR_DEF_TYPE33 User defined type 0x33. 3 1 USR_DEF_TYPE34 User defined type 0x34. 4 1 USR_DEF_TYPE35 User defined type 0x35. 5 1 USR_DEF_TYPE36 User defined type 0x36. 6 1 USR_DEF_TYPE37 User defined type 0x37. 7 1 CFG_VID_IGNORE_VC CFG_VID_IGNORE_VC. 0x080 32 CFG_VID_VC CFG_VID_VC. 0x084 32 CFG_P_FIFO_SEND_LEVEL CFG_P_FIFO_SEND_LEVEL. 0x088 32 CFG_VID_VSYNC CFG_VID_VSYNC. 0x08C 32 CFG_VID_HSYNC_FP CFG_VID_HSYNC_FP. 0x090 32 CFG_VID_HSYNC CFG_VID_HSYNC. 0x094 32 CFG_VID_HSYNC_BP CFG_VID_HSYNC_BP. 0x098 32 CFG_DATABUS16_SEL CFG_DATABUS16_SEL. 0x400 32 EN Enable 16-bit data bus. 0 1 CFG_D0_SWAP_SEL CFG_D0_SWAP_SEL. 0x404 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_D1_SWAP_SEL CFG_D1_SWAP_SEL. 0x408 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_D2_SWAP_SEL CFG_D2_SWAP_SEL. 0x40C 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_D3_SWAP_SEL CFG_D3_SWAP_SEL. 0x410 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_C0_SWAP_SEL CFG_C0_SWAP_SEL. 0x414 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_DPDN_SWAP CFG_DPDN_SWAP. 0x418 32 SWAP_DATA_LANE0 SWAP_DATA_LANE0. 0 1 SWAP_DATA_LANE1 SWAP_DATA_LANE1. 1 1 SWAP_DATA_LANE2 SWAP_DATA_LANE2. 2 1 SWAP_DATA_LANE3 SWAP_DATA_LANE3. 3 1 SWAP_CLK_LANE SWAP_CLK_LANE. 4 1 RG_CFGCLK_1US_CNT RG_CFGCLK_1US_CNT. 0x41C 32 RG_HSRX_CLK_PRE_TIME_GRP0 RG_HSRX_CLK_PRE_TIME_GRP0. 0x420 32 RG_HSRX_DATA_PRE_TIME_GRP0 RG_HSRX_DATA_PRE_TIME_GRP0. 0x424 32 RESET_DESKEW RESET_DESKEW. 0x428 32 DATA_LANE0 DATA_LANE0. 0 1 DATA_LANE1 DATA_LANE1. 1 1 DATA_LANE2 DATA_LANE2. 2 1 DATA_LANE3 DATA_LANE3. 3 1 PMA_RDY PMA_RDY. 0x42C 32 XCFGI_DW00 XCFGI_DW00. 0x430 32 XCFGI_DW01 XCFGI_DW01. 0x434 32 XCFGI_DW02 XCFGI_DW02. 0x438 32 XCFGI_DW03 XCFGI_DW03. 0x43C 32 XCFGI_DW04 XCFGI_DW04. 0x440 32 XCFGI_DW05 XCFGI_DW05. 0x444 32 XCFGI_DW06 XCFGI_DW06. 0x448 32 XCFGI_DW07 XCFGI_DW07. 0x44C 32 XCFGI_DW08 XCFGI_DW08. 0x450 32 XCFGI_DW09 XCFGI_DW09. 0x454 32 XCFGI_DW0A XCFGI_DW0A. 0x458 32 XCFGI_DW0B XCFGI_DW0B. 0x45C 32 XCFGI_DW0C XCFGI_DW0C. 0x460 32 XCFGI_DW0D XCFGI_DW0D. 0x464 32 GPIO_MODE GPIO_MODE. 0x468 32 GPIO_DP_IE GPIO_DP_IE. 0x46C 32 GPIO_DN_IE GPIO_DN_IE. 0x470 32 GPIO_DP_C GPIO_DP_C. 0x474 32 GPIO_DN_C GPIO_DN_C. 0x478 32 VCONTROL PMA_RDY. 0x47C 32 NORMAL_MODE NORMAL_MODE. 0 1 LP_RX_DC_TEST LP_RX_DC_TEST. 1 1 LP_RX_DC_1 LP_RX_DC_1. 2 1 LP_RX_DC_0 LP_RX_DC_0. 3 1 CAL_SEN_1 CAL_SEN_1. 4 1 CAL_SEN_0 CAL_SEN_0. 5 1 HSRT_0 HSRT_0. 7 1 HSRT_1 HSRT_1. 8 1 LP_RX_PARTBERT LP_RX_PARTBERT. 10 1 HS_INT_LOOPBACK HS_INT_LOOPBACK. 11 1 HS_RX_PARTBERT HS_RX_PARTBERT. 27 1 HS_RX_PRBS9 HS_RX_PRBS9. 28 1 SUSPEND_MODE SUSPEND_MODE. 31 1 MPSOV1 MPSOV1. 0x480 32 MPSOV2 MPSOV2. 0x484 32 MPSOV3 MPSOV3. 0x488 32 RG_CDRX_DSIRX_EN RG_CDRX_DSIRX_EN. 0x490 32 RXMODE RXMODE. 0 1 CSI CSI RX Mode. 0 DSI DSI RX Mode. 1 RG_CDRX_L012_SUBLVDS_EN RG_CDRX_L012_SUBLVDS_EN. 0x494 32 RG_CDRX_L012_HSRT_CTRL RG_CDRX_L012_HSRT_CTRL. 0x498 32 RG_CDRX_BISTHS_PLL_EN RG_CDRX_BISTHS_PLL_EN. 0x49C 32 RG_CDRX_BISTHS_PLL_PRE_DIV2 RG_CDRX_BISTHS_PLL_PRE_DIV2. 0x4A0 32 RXMODE RXMODE. 0 1 CSI CSI RX Mode. 0 DSI DSI RX Mode. 1 RG_CDRX_BISTHS_PLL_FBK_INT RG_CDRX_BISTHS_PLL_FBK_INT. 0x4A4 32 DBG1_MUX_SEL DBG1_MUX_SEL. 0x4A8 32 DBG2_MUX_SEL DBG2_MUX_SEL. 0x4AC 32 DBG1_MUX_DOUT DBG1_MUX_DOUT. 0x4B0 32 DBG2_MUX_DOUT DBG2_MUX_DOUT. 0x4B4 32 AON_POWER_READY_N AON_POWER_READY_N. 0x4B8 32 DPHY_RST_N DPHY_RST_N. 0x4BC 32 RXBYTECLKHS_INV RXBYTECLKHS_INV. 0x4C0 32 VFIFO_CFG0 Video FIFO Configuration Register 0. 0x500 32 VC CSI Virtual Channel. 0 2 DMAMODE DMA Mode, the condition to trigger DMA request.. 6 2 NO_DMA No DMA. 0 DMA_REQ Immediately send DMA request. 1 FIFO_THD Wait for FIFO above threshold. 2 FIFO_FULL Wait for FIFO is full. 3 AHBWAIT AHB Wait Enable. 8 1 FIFORM FIFO Read Mode. 9 1 ERRDE Error Detection Enable. 10 1 FBWM Full Band Width mode. 11 1 VFIFO_CFG1 Video FIFO Configuration Register 1. 0x504 32 AHBWCYC Maximal AHB Wait Clock Cycles. 0 16 WAIT_FIRST_FS WAIT_FIRST_FS. 16 1 ACCU_FRAME_CTRL ACCU_FRAME_CTRL. 17 1 ACCU_LINE_CTRL ACCU_LINE_CTRL. 18 1 ACCU_LINE_CNT ACCU_LINE_CNT. 19 1 ACCU_PIXEL_CNT ACCU_PIXEL_CNT. 20 1 ACCU_PIXEL_ZERO ACCU_PIXEL_ZERO. 21 1 VFIFO_CTRL Video FIFO Control Register. 0x508 32 FIFOEN Video FIFO Enable. 0 1 DIS Disable. 0 EN Enable. 1 FLUSH Write 1 to flush FIFO contents. 4 1 THD FIFO Threshold. 8 7 VFIFO_STS Video FIFO Status Register. 0x50C 32 FEMPTY FIFO empty. 0 1 FTHD FIFO above threshold. 1 1 FFULL FIFO full. 2 1 UNDERRUN FIFO underrun 3 1 OVERRUN FIFO overrun 4 1 OUTSYNC CSI out of sync 5 1 FMTERR CSI Pixel Format Error 6 1 AHBWTO AHB wait time out 7 1 FS CSI Frame Start 8 1 FE CSI Frame End 9 1 LS CSI Line Start 10 1 LE CSI Line End 11 1 FELT FIFO remaining entity count 16 7 FMT CSI pixel format of current transaction 24 6 VFIFO_LINE_NUM Video FIFO CSI Line Number Per Frame. 0x510 32 LINE_NUM Number of lines per frame. 0 13 VFIFO_PIXEL_NUM Video FIFO CSI Pixel Number Per Line. 0x514 32 PIXEL_NUM Number of pixels per line. 0 14 VFIFO_LINE_CNT Video FIFO CSI Line Count. 0x518 32 LINE_CNT Number of received lines in current frame. 0 12 VFIFO_PIXEL_CNT Video FIFO CSI Pixel Count. 0x51C 32 PIXEL_CNT Number of received pixels in current line in a frame. 0 13 VFIFO_FRAME_STS Video FIFO Frame Status Register. 0x520 32 FRAME_STATE Frame State. 0 3 ERROR_CODE Error Codes. 3 3 VFIFO_RAW_CTRL Video FIFO RAW-to-RGB Control Register. 0x524 32 RAW_CEN RAW conversion enable. 0 1 RAW_FF_AFO RAW conversion FIFO automatic flush-out. 1 1 RAW_FF_FO RAW conversion FIFO flush-out trigger. 4 1 RAW_FMT RAW format. 8 2 RGRG_GBGB RGRG GBGB 0 GRGR_BGBG GRGR BGBG 1 GBGB_RGRG GBGB RGRG 2 BGBG_GRGR BGBG GRGR 3 RGB_TYP RGB type. 12 3 RGB444 RGB444. 0 RGB555 RGB555. 1 RGB565 RGB565. 2 RGB666 RGB666. 3 RGG888 RGG888. 4 VFIFO_RAW_BUF0_ADDR Video FIFO RAW-to-RGB Line Buffer0 Address. 0x528 32 ADDR RAM address for RAW conversion buffer 0, word-aligned. 2 30 VFIFO_RAW_BUF1_ADDR Video FIFO RAW-to-RGB Line Buffer1 Address. 0x52C 32 ADDR RAM address for RAW conversion buffer 1, word-aligned. 2 30 VFIFO_AHBM_CTRL Video FIFO AHB Master Control Register. 0x530 32 AHBMEN AHB Master Enable. 0 1 AHBMCLR AHB Master Status Clear. 1 1 BSTLEN AHB Burst Length. 4 2 VFIFO_THD Video FIFO THD. 0 ONE_WORD ONE_WORD. 1 FOUR_WORDS FOUR_WORDS. 2 EIGHT_WORDS EIGHT_WORDS. 3 VFIFO_AHBM_STS Video FIFO AHB Master Status Register. 0x534 32 HRDY_TO AHB master HREADY time-out. 0 1 IDLE_TO AHB master Idle time-out. 1 1 TRANS_MAX AHB master maximal transfer count occurrence. 2 1 VFIFO_AHBM_START_ADDR Video FIFO AHB Master Start Address Register. 0x538 32 AHBM_START_ADDR AHB master transfer starting address, word-aligned. 2 30 VFIFO_AHBM_ADDR_RANGE Video FIFO AHB Master Address Range Register. 0x53C 32 AHBM_ADDR_RANGE AHB master address range. 2 14 VFIFO_AHBM_MAX_TRANS Video FIFO AHB Master Maximal Transfer Number Register. 0x540 32 AHBM_MAX_TRANS AHB master maximal number of transfer word count. 0 32 VFIFO_AHBM_TRANS_CNT Video FIFO AHB Master Transfer Count Register. 0x544 32 AHBM_TRANS_CNT AHB master number of words been transferred. 0 32 RX_EINT_VFF_IE RX Video FIFO Interrupt Enable Register. 0x600 32 FNEMPTY Video FIFO not empty interrupt enable. 0 1 FTHD Video FIFO above threshold interrupt enable. 1 1 FFULL Video FIFO full interrupt enable. 2 1 UNDERRUN Video FIFO underrun interrupt enable 3 1 OVERRUN Video FIFO overrun interrupt enable 4 1 OUTSYNC CSI out of sync interrupt enable 5 1 FMTERR CSI Pixel Format Error interrupt enable 6 1 AHBWTO AHB wait time out interrupt enable 7 1 FS CSI Frame Start interrupt enable 8 1 FE CSI Frame End interrupt enable 9 1 LS CSI Line Start interrupt enable 10 1 LE CSI Line End interrupt enable 11 1 RAW_OVR Raw FIFO Overrun Interrupt Enable 12 1 RAW_AHBERR Raw AHB Error Interrupt Enable 13 1 FNEMP_MD Video FIFO not empty detection mode 16 1 FTHD_MD Video FIFO threshold detection mode 17 1 FFUL_MD Video FIFO full detection mode 18 1 AHBM_RDTO AHBM_RDTO 24 1 AHBM_IDTO AHBM_IDTO 25 1 AHBM_MAX AHBM_MAX 26 1 RX_EINT_VFF_IF RX Video FIFO Interrupt Flag Register. 0x604 32 FNEMPTY Video FIFO not empty interrupt flag. 0 1 FTHD Video FIFO above threshold interrupt flag. 1 1 FFULL Video FIFO full interrupt flag. 2 1 UNDERRUN Video FIFO underrun interrupt flag 3 1 OVERRUN Video FIFO overrun interrupt flag 4 1 OUTSYNC CSI out of sync interrupt flag 5 1 FMTERR CSI Pixel Format Error interrupt flag 6 1 AHBWTO AHB wait time out interrupt flag 7 1 FS CSI Frame Start interrupt flag 8 1 FE CSI Frame End interrupt flag 9 1 LS CSI Line Start interrupt flag 10 1 LE CSI Line End interrupt flag 11 1 RAW_OVR Raw FIFO Overrun Interrupt Enable 12 1 RAW_AHBERR Raw AHB Error Interrupt Enable 13 1 AHBM_RDTO AHBM_RDTO 24 1 AHBM_IDTO AHBM_IDTO 25 1 AHBM_MAX AHBM_MAX 26 1 RX_EINT_PPI_IE RX D-PHY Interrupt Enable Register. 0x608 32 DL0STOP DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt enable. 0 1 DL1STOP DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt enable. 1 1 CL0STOP DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt enable. 4 1 DL0ECONT0 DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt enable 6 1 DL0ECONT1 DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt enable 7 1 DL0ESOT DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt enable 8 1 DL1ESOT DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt enable 9 1 DL0ESOTS DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt enable 12 1 DL1ESOTS DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt enable 13 1 DL0EESC DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt enable 16 1 DL1EESC DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt enable 17 1 DL0ESESC DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable 20 1 DL1ESESC DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable 21 1 DL0ECTL DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt enable 24 1 DL1ECTL DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt enable 25 1 RX_EINT_PPI_IF RX D-PHY Interrupt Flag Register. 0x60C 32 DL0STOP DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt flag. 0 1 DL1STOP DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt flag. 1 1 CL0STOP DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt flag. 4 1 DL0ECONT0 DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt flag 6 1 DL0ECONT1 DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt flag 7 1 DL0ESOT DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt flag 8 1 DL1ESOT DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt flag 9 1 DL0ESOTS DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt flag 12 1 DL1ESOTS DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt flag 13 1 DL0EESC DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt flag 16 1 DL1EESC DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt flag 17 1 DL0ESESC DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag 20 1 DL1ESESC DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag 21 1 DL0ECTL DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt flag 24 1 DL1ECTL DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt flag 25 1 RX_EINT_CTRL_IE RX Controller Interrupt Enable Register. 0x610 32 EECC2 CSI RX ECC 2-bit Error interrupt enable. 0 1 EECC1 CSI RX ECC 1-bit Error interrupt enable. 1 1 ECRC CSI RX CRC Error interrupt enable. 2 1 EID CSI RX Packet Header Data ID Error interrupt enable 3 1 PKTFFOV CSI RX Packet FIFO Overrun interrupt enable 4 1 DL0ULPSA CSI Data Lane0 ULPSS Active interrupt enable 8 1 DL1ULPSA CSI Data Lane1 ULPSS Active interrupt enable 9 1 DL0ULPSM CSI Data Lane0 ULPSS Mark interrupt enable 12 1 DL1ULPSM CSI Data Lane1 ULPSS Mark interrupt enable 13 1 CL0ULPSA CSI Clock Lane0 ULPSS Active interrupt enable 16 1 CL0ULPSM CSI Data Lane0 ULPSS Mark interrupt enable 17 1 RX_EINT_CTRL_IF RX Controller Interrupt Flag Register. 0x614 32 EECC2 CSI RX ECC 2-bit Error interrupt flag. 0 1 EECC1 CSI RX ECC 1-bit Error interrupt flag. 1 1 ECRC CSI RX CRC Error interrupt flag. 2 1 EID CSI RX Packet Header Data ID Error interrupt flag 3 1 PKTFFOV CSI RX Packet FIFO Overrun interrupt flag 4 1 DL0ULPSA CSI Data Lane0 ULPSS Active interrupt flag 8 1 DL1ULPSA CSI Data Lane1 ULPSS Active interrupt flag 9 1 DL0ULPSM CSI Data Lane0 ULPSS Mark interrupt flag 12 1 DL1ULPSM CSI Data Lane1 ULPSS Mark interrupt flag 13 1 CL0ULPSA CSI Clock Lane0 ULPSS Active interrupt flag 16 1 CL0ULPSM CSI Data Lane0 ULPSS Mark interrupt flag 17 1 PPI_STOPSTATE DPHY PPI Stop State Register. 0x700 32 DL0STOP CSI Data Lane0 Stop State. 0 1 DL1STOP CSI Data Lane1 Stop State. 1 1 CL0STOP CSI Clock Lane0 Stop State. 2 1 PPI_TURNAROUND_CFG DPHY PPI Turn-Around Configuration Register. 0x704 32 DL0TAREQ CSI Data Lane0 turn around request. 0 1 DL0TADIS CSI Data Lane0 turn around disable. 1 1 DL0FRCRX CSI Data Lane0 force RX mode. 2 1