1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>CLCD</name> 5 <description>Color LCD Controller</description> 6 <baseAddress>0x40031000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0xFFF</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>CLK_CTRL</name> 15 <description>LCD Clock Control Register</description> 16 <addressOffset>0x000</addressOffset> 17 <fields> 18 <field> 19 <name>LCD_CLKDIV</name> 20 <description>Clock divsor</description> 21 <bitOffset>0</bitOffset> 22 <bitWidth>8</bitWidth> 23 </field> 24 <field> 25 <name>STN_AC_BIAS</name> 26 <description>AC Bias Frequency Control. THis fiels sets the AC Bias Frequency output on the CLCD_VDEN pin for Color StN display mode.</description> 27 <bitOffset>8</bitOffset> 28 <bitWidth>8</bitWidth> 29 </field> 30 <field> 31 <name>VDEN_POL</name> 32 <description>CLCD_VDEN Polarity Selection. This field sets the polarity of the video enable signal output pin.</description> 33 <bitOffset>16</bitOffset> 34 <bitWidth>1</bitWidth> 35 <enumeratedValues> 36 <enumeratedValue> 37 <name>ACTIVELO</name> 38 <description>Active Low</description> 39 <value>0</value> 40 </enumeratedValue> 41 <enumeratedValue> 42 <name>ACTIVEHI</name> 43 <description>Active High</description> 44 <value>1</value> 45 </enumeratedValue> 46 </enumeratedValues> 47 </field> 48 <field> 49 <name>VSYNC_POL</name> 50 <description>VSYNC Polarity Selection. This field sets the polarity of the vertical sync signal output pin.</description> 51 <bitOffset>17</bitOffset> 52 <bitWidth>1</bitWidth> 53 <enumeratedValues> 54 <enumeratedValue> 55 <name>ACTIVELO</name> 56 <description>Active Low</description> 57 <value>0</value> 58 </enumeratedValue> 59 <enumeratedValue> 60 <name>ACTIVEHI</name> 61 <description>Active Hi</description> 62 <value>1</value> 63 </enumeratedValue> 64 </enumeratedValues> 65 </field> 66 <field> 67 <name>HSYNC_POL</name> 68 <description>HSYNC Polarity Selection. This field sets the polarity of the horizontal sync signal output pin.</description> 69 <bitOffset>18</bitOffset> 70 <bitWidth>1</bitWidth> 71 <enumeratedValues> 72 <enumeratedValue> 73 <name>ACTIVELO</name> 74 <description>Active Low</description> 75 <value>0</value> 76 </enumeratedValue> 77 <enumeratedValue> 78 <name>ACTIVEHI</name> 79 <description>Active Hi</description> 80 <value>1</value> 81 </enumeratedValue> 82 </enumeratedValues> 83 </field> 84 <field> 85 <name>CLK_EDGE_SEL</name> 86 <description>Clock Edge Selection. This field controls the clock edge that is used by the LCD panel to sample the data and signal lines.</description> 87 <bitOffset>19</bitOffset> 88 <bitWidth>1</bitWidth> 89 <enumeratedValues> 90 <enumeratedValue> 91 <name>RISING</name> 92 <description>Rising edge</description> 93 <value>0</value> 94 </enumeratedValue> 95 <enumeratedValue> 96 <name>FALLING</name> 97 <description>Falling Edge</description> 98 <value>1</value> 99 </enumeratedValue> 100 </enumeratedValues> 101 </field> 102 <field> 103 <name>CLK_ACTIVE</name> 104 <description>Clock Active on Data. If the display type is Color STN 8-bit, this bit selects if the CLCD_CLK output is active always or only during data output to the display.</description> 105 <bitOffset>20</bitOffset> 106 <bitWidth>1</bitWidth> 107 <enumeratedValues> 108 <enumeratedValue> 109 <name>ALWAYS</name> 110 <description>Always Active</description> 111 <value>0</value> 112 </enumeratedValue> 113 <enumeratedValue> 114 <name>ONDATA</name> 115 <description>ACTIVE ON DATA</description> 116 <value>1</value> 117 </enumeratedValue> 118 </enumeratedValues> 119 </field> 120 </fields> 121 </register> 122 <register> 123 <name>VTIM_0</name> 124 <description>LCD Vertical Timing 0 Register</description> 125 <addressOffset>0x004</addressOffset> 126 <fields> 127 <field> 128 <name>VLINES</name> 129 <description>V Lines</description> 130 <bitOffset>0</bitOffset> 131 <bitWidth>8</bitWidth> 132 </field> 133 <field> 134 <name>VBP_WIDTH</name> 135 <description>V BACK PORCH</description> 136 <bitOffset>16</bitOffset> 137 <bitWidth>8</bitWidth> 138 </field> 139 </fields> 140 </register> 141 <register> 142 <name>VTIM_1</name> 143 <description>LCD Vertical Timing 1 Register</description> 144 <addressOffset>0x008</addressOffset> 145 <fields> 146 <field> 147 <name>VSYNC_WIDTH</name> 148 <description>V Sync Width</description> 149 <bitOffset>0</bitOffset> 150 <bitWidth>8</bitWidth> 151 </field> 152 <field> 153 <name>VFP_WIDTH</name> 154 <description>V Front PORCH</description> 155 <bitOffset>16</bitOffset> 156 <bitWidth>8</bitWidth> 157 </field> 158 </fields> 159 </register> 160 <register> 161 <name>HTIM</name> 162 <description>LCD Horizontal Timing Register.</description> 163 <addressOffset>0x00C</addressOffset> 164 <fields> 165 <field> 166 <name>HSYNC_WIDTH</name> 167 <description>Horizontal Sync Width in CLCD Clocks from 1 to 256 HSync Width = HSYNCWIDTH+1 Clocks</description> 168 <bitOffset>0</bitOffset> 169 <bitWidth>8</bitWidth> 170 </field> 171 <field> 172 <name>HFP_WIDTH</name> 173 <description>Horizontal Front Porch size in lines from 1 to 256</description> 174 <bitOffset>8</bitOffset> 175 <bitWidth>8</bitWidth> 176 </field> 177 <field> 178 <name>HSIZE_INDEX</name> 179 <description>Horizontal Front Porch Size in Pixels = (HSIZE + 1) *16</description> 180 <bitOffset>16</bitOffset> 181 <bitWidth>8</bitWidth> 182 </field> 183 <field> 184 <name>HBP_WIDTH</name> 185 <description>Horizontal Back Porch size in CLCD Clocks from 1 to 256 -> HBP= (HBACKPORCH+1) </description> 186 <bitOffset>24</bitOffset> 187 <bitWidth>8</bitWidth> 188 </field> 189 </fields> 190 </register> 191 <register> 192 <name>CTRL</name> 193 <description>LCD Control Register</description> 194 <addressOffset>0x010</addressOffset> 195 <fields> 196 <field> 197 <name>CLCD_ENABLE</name> 198 <description>LCD Enable</description> 199 <bitOffset>0</bitOffset> 200 <bitWidth>1</bitWidth> 201 <enumeratedValues> 202 <enumeratedValue> 203 <name>dis</name> 204 <description>Disable</description> 205 <value>0</value> 206 </enumeratedValue> 207 <enumeratedValue> 208 <name>en</name> 209 <description>Enable</description> 210 <value>1</value> 211 </enumeratedValue> 212 </enumeratedValues> 213 </field> 214 <field> 215 <name>VCI_SEL</name> 216 <description>Vertical Compare Interrupt Source Select</description> 217 <bitOffset>1</bitOffset> 218 <bitWidth>2</bitWidth> 219 <enumeratedValues> 220 <enumeratedValue> 221 <name>ON_VSYNC</name> 222 <description>On Vertical Sync</description> 223 <value>0</value> 224 </enumeratedValue> 225 <enumeratedValue> 226 <name>ON_VBP</name> 227 <description>On Vertical Back Porch</description> 228 <value>1</value> 229 </enumeratedValue> 230 <enumeratedValue> 231 <name>ON_VDEN</name> 232 <description>On Active Video</description> 233 <value>2</value> 234 </enumeratedValue> 235 <enumeratedValue> 236 <name>ON_VFP</name> 237 <description>On Vertical Front Porch</description> 238 <value>3</value> 239 </enumeratedValue> 240 </enumeratedValues> 241 </field> 242 <field> 243 <name>DISPTYPE</name> 244 <description>Display Type</description> 245 <bitOffset>4</bitOffset> 246 <bitWidth>4</bitWidth> 247 <enumeratedValues> 248 <enumeratedValue> 249 <name>8BITCOLORSTN</name> 250 <description>STN Color 8 bit</description> 251 <value>4</value> 252 </enumeratedValue> 253 <enumeratedValue> 254 <name>TFT</name> 255 <description>TFT</description> 256 <value>8</value> 257 </enumeratedValue> 258 </enumeratedValues> 259 </field> 260 <field> 261 <name>BPP</name> 262 <description>BPP</description> 263 <bitOffset>8</bitOffset> 264 <bitWidth>3</bitWidth> 265 <enumeratedValues> 266 <enumeratedValue> 267 <name>BPP1</name> 268 <description>BPP 1</description> 269 <value>0</value> 270 </enumeratedValue> 271 <enumeratedValue> 272 <name>BPP2</name> 273 <description>BPP 2</description> 274 <value>1</value> 275 </enumeratedValue> 276 <enumeratedValue> 277 <name>BPP4</name> 278 <description>BPP 4</description> 279 <value>2</value> 280 </enumeratedValue> 281 <enumeratedValue> 282 <name>BPP8</name> 283 <description>BPP 8</description> 284 <value>3</value> 285 </enumeratedValue> 286 <enumeratedValue> 287 <name>BPP16</name> 288 <description>BPP 16</description> 289 <value>4</value> 290 </enumeratedValue> 291 <enumeratedValue> 292 <name>BPP24</name> 293 <description>BPP 24</description> 294 <value>5</value> 295 </enumeratedValue> 296 </enumeratedValues> 297 </field> 298 <field> 299 <name>MODE565</name> 300 <description>MODE565</description> 301 <bitOffset>11</bitOffset> 302 <bitWidth>1</bitWidth> 303 <enumeratedValues> 304 <enumeratedValue> 305 <name>BGR556</name> 306 <description>MODE 556</description> 307 <value>0</value> 308 </enumeratedValue> 309 <enumeratedValue> 310 <name>RGB565</name> 311 <description>MODE 565</description> 312 <value>1</value> 313 </enumeratedValue> 314 </enumeratedValues> 315 </field> 316 <field> 317 <name>ENDIAN</name> 318 <description>EMODE</description> 319 <bitOffset>12</bitOffset> 320 <bitWidth>2</bitWidth> 321 <enumeratedValues> 322 <enumeratedValue> 323 <name>LBLP</name> 324 <description>LLBP</description> 325 <value>0</value> 326 </enumeratedValue> 327 <enumeratedValue> 328 <name>BBBP</name> 329 <description>BBBP</description> 330 <value>1</value> 331 </enumeratedValue> 332 <enumeratedValue> 333 <name>LBBP</name> 334 <description>LBBP</description> 335 <value>2</value> 336 </enumeratedValue> 337 <enumeratedValue> 338 <name>RFU</name> 339 <description>RFU</description> 340 <value>3</value> 341 </enumeratedValue> 342 </enumeratedValues> 343 </field> 344 <field> 345 <name>COMPACT_24b</name> 346 <description>C24</description> 347 <bitOffset>15</bitOffset> 348 <bitWidth>1</bitWidth> 349 <enumeratedValues> 350 <enumeratedValue> 351 <name>1_PFR</name> 352 <description>1 pixel per frame buffer entry</description> 353 <value>0</value> 354 </enumeratedValue> 355 <enumeratedValue> 356 <name>1ANDA3RD_PFR</name> 357 <description>1 and 1/3 pixels per fram buffer entry</description> 358 <value>1</value> 359 </enumeratedValue> 360 </enumeratedValues> 361 </field> 362 <field> 363 <name>BURST_SIZE</name> 364 <description>BURST</description> 365 <bitOffset>19</bitOffset> 366 <bitWidth>2</bitWidth> 367 <enumeratedValues> 368 <enumeratedValue> 369 <name>4WORDS</name> 370 <description>4 32-bit words.</description> 371 <value>0</value> 372 </enumeratedValue> 373 <enumeratedValue> 374 <name>8WORDS</name> 375 <description>8 32-bit words.</description> 376 <value>1</value> 377 </enumeratedValue> 378 <enumeratedValue> 379 <name>16WORDS</name> 380 <description>16 32-bit words.</description> 381 <value>2</value> 382 </enumeratedValue> 383 </enumeratedValues> 384 </field> 385 <field> 386 <name>LEND_POL</name> 387 <description>LEND Polarity Selection. This field sets the polarity of the line end signal output pin.</description> 388 <bitOffset>21</bitOffset> 389 <bitWidth>1</bitWidth> 390 <enumeratedValues> 391 <enumeratedValue> 392 <name>ACTIVELO</name> 393 <description>Active Low</description> 394 <value>0</value> 395 </enumeratedValue> 396 <enumeratedValue> 397 <name>ACTIVEHI</name> 398 <description>Active High</description> 399 <value>1</value> 400 </enumeratedValue> 401 </enumeratedValues> 402 </field> 403 <field> 404 <name>PWR_ENABLE</name> 405 <description>Display Power Enable. Enables power to the display using the PWREN output pin.</description> 406 <bitOffset>22</bitOffset> 407 <bitWidth>1</bitWidth> 408 <enumeratedValues> 409 <enumeratedValue> 410 <name>LO</name> 411 <description>Power enable pin is set low.</description> 412 <value>0</value> 413 </enumeratedValue> 414 <enumeratedValue> 415 <name>HI</name> 416 <description>Power enable pin is set high.</description> 417 <value>1</value> 418 </enumeratedValue> 419 </enumeratedValues> 420 </field> 421 </fields> 422 </register> 423 <register> 424 <name>FRBUF</name> 425 <description>Frame buffer.</description> 426 <addressOffset>0x18</addressOffset> 427 <fields> 428 <field> 429 <name>FRAME_ADDR</name> 430 <description>Set this field to the beginning of the fram buffer data to display.</description> 431 <bitOffset>0</bitOffset> 432 <bitWidth>32</bitWidth> 433 </field> 434 </fields> 435 </register> 436 <register> 437 <name>INT_EN</name> 438 <description>LCD Interrupt Enable Register.</description> 439 <addressOffset>0x020</addressOffset> 440 <fields> 441 <field> 442 <name>UNDERFLOW_IE</name> 443 <description>Under FLow Interupt Enable</description> 444 <bitOffset>0</bitOffset> 445 <bitWidth>1</bitWidth> 446 <enumeratedValues> 447 <enumeratedValue> 448 <name>dis</name> 449 <description>Interrupt disabled.</description> 450 <value>0</value> 451 </enumeratedValue> 452 <enumeratedValue> 453 <name>en</name> 454 <description>Interrupt enabled.</description> 455 <value>1</value> 456 </enumeratedValue> 457 </enumeratedValues> 458 </field> 459 <field> 460 <name>ADDR_RDY_IE</name> 461 <description>Address Ready Interupt Enable</description> 462 <bitOffset>1</bitOffset> 463 <bitWidth>1</bitWidth> 464 <enumeratedValues> 465 <enumeratedValue> 466 <name>dis</name> 467 <description>Interrupt disabled.</description> 468 <value>0</value> 469 </enumeratedValue> 470 <enumeratedValue> 471 <name>en</name> 472 <description>Interrupt enabled.</description> 473 <value>1</value> 474 </enumeratedValue> 475 </enumeratedValues> 476 </field> 477 <field> 478 <name>VCI_IE</name> 479 <description>VCI Interupt Enable</description> 480 <bitOffset>2</bitOffset> 481 <bitWidth>1</bitWidth> 482 <enumeratedValues> 483 <enumeratedValue> 484 <name>dis</name> 485 <description>Interrupt disabled.</description> 486 <value>0</value> 487 </enumeratedValue> 488 <enumeratedValue> 489 <name>en</name> 490 <description>Interrupt enabled.</description> 491 <value>1</value> 492 </enumeratedValue> 493 </enumeratedValues> 494 </field> 495 <field> 496 <name>BUS_ERROR_IE</name> 497 <description>BERR Interupt Enable</description> 498 <bitOffset>3</bitOffset> 499 <bitWidth>1</bitWidth> 500 <enumeratedValues> 501 <enumeratedValue> 502 <name>dis</name> 503 <description>Interrupt disabled.</description> 504 <value>0</value> 505 </enumeratedValue> 506 <enumeratedValue> 507 <name>en</name> 508 <description>Interrupt enabled.</description> 509 <value>1</value> 510 </enumeratedValue> 511 </enumeratedValues> 512 </field> 513 </fields> 514 </register> 515 <register> 516 <name>INT_STAT</name> 517 <description>LCD Status Register.</description> 518 <addressOffset>0x024</addressOffset> 519 <modifiedWriteValues>oneToClear</modifiedWriteValues> 520 <fields> 521 <field> 522 <name>UNDERFLOW</name> 523 <description>Under FLow Interupt Status</description> 524 <bitOffset>0</bitOffset> 525 <bitWidth>1</bitWidth> 526 <enumeratedValues> 527 <usage>read</usage> 528 <enumeratedValue> 529 <name>inactive</name> 530 <description>No interrupt pending</description> 531 <value>0</value> 532 </enumeratedValue> 533 <enumeratedValue> 534 <name>pend</name> 535 <description>Interrupt pending</description> 536 <value>1</value> 537 </enumeratedValue> 538 </enumeratedValues> 539 <enumeratedValues> 540 <usage>write</usage> 541 <enumeratedValue> 542 <name>clear</name> 543 <description>Clears the interrupt flag</description> 544 <value>1</value> 545 </enumeratedValue> 546 </enumeratedValues> 547 </field> 548 <field> 549 <name>ADDR_RDY</name> 550 <description>Address Ready Interupt Status</description> 551 <bitOffset>1</bitOffset> 552 <bitWidth>1</bitWidth> 553 <enumeratedValues> 554 <usage>read</usage> 555 <enumeratedValue> 556 <name>inactive</name> 557 <description>No interrupt pending</description> 558 <value>0</value> 559 </enumeratedValue> 560 <enumeratedValue> 561 <name>pend</name> 562 <description>Interrupt pending</description> 563 <value>1</value> 564 </enumeratedValue> 565 </enumeratedValues> 566 <enumeratedValues> 567 <usage>write</usage> 568 <enumeratedValue> 569 <name>clear</name> 570 <description>Clears the interrupt flag</description> 571 <value>1</value> 572 </enumeratedValue> 573 </enumeratedValues> 574 </field> 575 <field> 576 <name>VCI</name> 577 <description>VCI Interupt Status</description> 578 <bitOffset>2</bitOffset> 579 <bitWidth>1</bitWidth> 580 <enumeratedValues> 581 <usage>read</usage> 582 <enumeratedValue> 583 <name>inactive</name> 584 <description>No interrupt pending</description> 585 <value>0</value> 586 </enumeratedValue> 587 <enumeratedValue> 588 <name>pend</name> 589 <description>Interrupt pending</description> 590 <value>1</value> 591 </enumeratedValue> 592 </enumeratedValues> 593 <enumeratedValues> 594 <usage>write</usage> 595 <enumeratedValue> 596 <name>clear</name> 597 <description>Clears the interrupt flag</description> 598 <value>1</value> 599 </enumeratedValue> 600 </enumeratedValues> 601 </field> 602 <field> 603 <name>BUS_ERROR</name> 604 <description>BERR Interupt Status</description> 605 <bitOffset>3</bitOffset> 606 <bitWidth>1</bitWidth> 607 <enumeratedValues> 608 <usage>read</usage> 609 <enumeratedValue> 610 <name>inactive</name> 611 <description>No interrupt pending</description> 612 <value>0</value> 613 </enumeratedValue> 614 <enumeratedValue> 615 <name>pend</name> 616 <description>Interrupt pending</description> 617 <value>1</value> 618 </enumeratedValue> 619 </enumeratedValues> 620 <enumeratedValues> 621 <usage>write</usage> 622 <enumeratedValue> 623 <name>clear</name> 624 <description>Clears the interrupt flag</description> 625 <value>1</value> 626 </enumeratedValue> 627 </enumeratedValues> 628 </field> 629 <field> 630 <name>CLCD_IDLE</name> 631 <description>LCD IDLE Staus</description> 632 <bitOffset>8</bitOffset> 633 <bitWidth>1</bitWidth> 634 <enumeratedValues> 635 <enumeratedValue> 636 <name>IDLE</name> 637 <description>Idle.</description> 638 <value>0</value> 639 </enumeratedValue> 640 <enumeratedValue> 641 <name>BUSY</name> 642 <description>Busy.</description> 643 <value>1</value> 644 </enumeratedValue> 645 </enumeratedValues> 646 </field> 647 </fields> 648 </register> 649 <register> 650 <dim>256</dim> 651 <dimIncrement>4</dimIncrement> 652 <name>PALETTE_RAM[%s]</name> 653 <description>Palette</description> 654 <addressOffset>0x400</addressOffset> 655 <fields> 656 <field> 657 <name>RED</name> 658 <description>Red Data for Pallet Entry.</description> 659 <bitOffset>0</bitOffset> 660 <bitWidth>8</bitWidth> 661 </field> 662 <field> 663 <name>GREEN</name> 664 <description>Green Data for Pallet Entry.</description> 665 <bitOffset>8</bitOffset> 666 <bitWidth>8</bitWidth> 667 </field> 668 <field> 669 <name>BLUE</name> 670 <description>Blue Data for Pallet Entry.</description> 671 <bitOffset>16</bitOffset> 672 <bitWidth>8</bitWidth> 673 </field> 674 </fields> 675 </register> 676 </registers> 677 </peripheral> 678</device> 679<!-- CLCD : 680 CLCD -->
