CLCD Color LCD Controller 0x40031000 0x00 0xFFF registers CLK_CTRL LCD Clock Control Register 0x000 LCD_CLKDIV Clock divsor 0 8 STN_AC_BIAS AC Bias Frequency Control. THis fiels sets the AC Bias Frequency output on the CLCD_VDEN pin for Color StN display mode. 8 8 VDEN_POL CLCD_VDEN Polarity Selection. This field sets the polarity of the video enable signal output pin. 16 1 ACTIVELO Active Low 0 ACTIVEHI Active High 1 VSYNC_POL VSYNC Polarity Selection. This field sets the polarity of the vertical sync signal output pin. 17 1 ACTIVELO Active Low 0 ACTIVEHI Active Hi 1 HSYNC_POL HSYNC Polarity Selection. This field sets the polarity of the horizontal sync signal output pin. 18 1 ACTIVELO Active Low 0 ACTIVEHI Active Hi 1 CLK_EDGE_SEL Clock Edge Selection. This field controls the clock edge that is used by the LCD panel to sample the data and signal lines. 19 1 RISING Rising edge 0 FALLING Falling Edge 1 CLK_ACTIVE Clock Active on Data. If the display type is Color STN 8-bit, this bit selects if the CLCD_CLK output is active always or only during data output to the display. 20 1 ALWAYS Always Active 0 ONDATA ACTIVE ON DATA 1 VTIM_0 LCD Vertical Timing 0 Register 0x004 VLINES V Lines 0 8 VBP_WIDTH V BACK PORCH 16 8 VTIM_1 LCD Vertical Timing 1 Register 0x008 VSYNC_WIDTH V Sync Width 0 8 VFP_WIDTH V Front PORCH 16 8 HTIM LCD Horizontal Timing Register. 0x00C HSYNC_WIDTH Horizontal Sync Width in CLCD Clocks from 1 to 256 HSync Width = HSYNCWIDTH+1 Clocks 0 8 HFP_WIDTH Horizontal Front Porch size in lines from 1 to 256 8 8 HSIZE_INDEX Horizontal Front Porch Size in Pixels = (HSIZE + 1) *16 16 8 HBP_WIDTH Horizontal Back Porch size in CLCD Clocks from 1 to 256 -> HBP= (HBACKPORCH+1) 24 8 CTRL LCD Control Register 0x010 CLCD_ENABLE LCD Enable 0 1 dis Disable 0 en Enable 1 VCI_SEL Vertical Compare Interrupt Source Select 1 2 ON_VSYNC On Vertical Sync 0 ON_VBP On Vertical Back Porch 1 ON_VDEN On Active Video 2 ON_VFP On Vertical Front Porch 3 DISPTYPE Display Type 4 4 8BITCOLORSTN STN Color 8 bit 4 TFT TFT 8 BPP BPP 8 3 BPP1 BPP 1 0 BPP2 BPP 2 1 BPP4 BPP 4 2 BPP8 BPP 8 3 BPP16 BPP 16 4 BPP24 BPP 24 5 MODE565 MODE565 11 1 BGR556 MODE 556 0 RGB565 MODE 565 1 ENDIAN EMODE 12 2 LBLP LLBP 0 BBBP BBBP 1 LBBP LBBP 2 RFU RFU 3 COMPACT_24b C24 15 1 1_PFR 1 pixel per frame buffer entry 0 1ANDA3RD_PFR 1 and 1/3 pixels per fram buffer entry 1 BURST_SIZE BURST 19 2 4WORDS 4 32-bit words. 0 8WORDS 8 32-bit words. 1 16WORDS 16 32-bit words. 2 LEND_POL LEND Polarity Selection. This field sets the polarity of the line end signal output pin. 21 1 ACTIVELO Active Low 0 ACTIVEHI Active High 1 PWR_ENABLE Display Power Enable. Enables power to the display using the PWREN output pin. 22 1 LO Power enable pin is set low. 0 HI Power enable pin is set high. 1 FRBUF Frame buffer. 0x18 FRAME_ADDR Set this field to the beginning of the fram buffer data to display. 0 32 INT_EN LCD Interrupt Enable Register. 0x020 UNDERFLOW_IE Under FLow Interupt Enable 0 1 dis Interrupt disabled. 0 en Interrupt enabled. 1 ADDR_RDY_IE Address Ready Interupt Enable 1 1 dis Interrupt disabled. 0 en Interrupt enabled. 1 VCI_IE VCI Interupt Enable 2 1 dis Interrupt disabled. 0 en Interrupt enabled. 1 BUS_ERROR_IE BERR Interupt Enable 3 1 dis Interrupt disabled. 0 en Interrupt enabled. 1 INT_STAT LCD Status Register. 0x024 oneToClear UNDERFLOW Under FLow Interupt Status 0 1 read inactive No interrupt pending 0 pend Interrupt pending 1 write clear Clears the interrupt flag 1 ADDR_RDY Address Ready Interupt Status 1 1 read inactive No interrupt pending 0 pend Interrupt pending 1 write clear Clears the interrupt flag 1 VCI VCI Interupt Status 2 1 read inactive No interrupt pending 0 pend Interrupt pending 1 write clear Clears the interrupt flag 1 BUS_ERROR BERR Interupt Status 3 1 read inactive No interrupt pending 0 pend Interrupt pending 1 write clear Clears the interrupt flag 1 CLCD_IDLE LCD IDLE Staus 8 1 IDLE Idle. 0 BUSY Busy. 1 256 4 PALETTE_RAM[%s] Palette 0x400 RED Red Data for Pallet Entry. 0 8 GREEN Green Data for Pallet Entry. 8 8 BLUE Blue Data for Pallet Entry. 16 8