1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>CAN0</name> 5 <description>Controller Area Network Registers</description> 6 <baseAddress>0x40064000</baseAddress> 7 <addressBlock> 8 <offset>0x00</offset> 9 <size>0x1000</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>MODE</name> 15 <description>Mode Register.</description> 16 <addressOffset>0x0000</addressOffset> 17 <size>8</size> 18 <access>read-write</access> 19 <fields> 20 <field> 21 <name>AFM</name> 22 <description>Hardware acceptance filter scheme.</description> 23 <bitOffset>0</bitOffset> 24 <bitWidth>1</bitWidth> 25 </field> 26 <field> 27 <name>LOM</name> 28 <description>Listen Only Mode.</description> 29 <bitOffset>1</bitOffset> 30 <bitWidth>1</bitWidth> 31 </field> 32 <field> 33 <name>RST</name> 34 <description>Reset Mode.</description> 35 <bitOffset>2</bitOffset> 36 <bitWidth>1</bitWidth> 37 </field> 38 <field> 39 <name>RXTRIG</name> 40 <description>Receive FIFO trigger in 32bit word.</description> 41 <bitOffset>3</bitOffset> 42 <bitWidth>3</bitWidth> 43 <enumeratedValues> 44 <enumeratedValue> 45 <name>1W</name> 46 <description>1 word</description> 47 <value>0</value> 48 </enumeratedValue> 49 <enumeratedValue> 50 <name>4W</name> 51 <description>4 word</description> 52 <value>1</value> 53 </enumeratedValue> 54 <enumeratedValue> 55 <name>8W</name> 56 <description>8 word</description> 57 <value>2</value> 58 </enumeratedValue> 59 <enumeratedValue> 60 <name>16W</name> 61 <description>16 word</description> 62 <value>3</value> 63 </enumeratedValue> 64 <enumeratedValue> 65 <name>32W</name> 66 <description>32 word</description> 67 <value>4</value> 68 </enumeratedValue> 69 <enumeratedValue> 70 <name>64W</name> 71 <description>64 word</description> 72 <value>5</value> 73 </enumeratedValue> 74 </enumeratedValues> 75 </field> 76 <field> 77 <name>DMA</name> 78 <description>Enable DMA mode.</description> 79 <bitOffset>6</bitOffset> 80 <bitWidth>1</bitWidth> 81 </field> 82 <field> 83 <name>SLP</name> 84 <description>Sleep mode.</description> 85 <bitOffset>7</bitOffset> 86 <bitWidth>1</bitWidth> 87 <enumeratedValues> 88 <enumeratedValue> 89 <name>enter</name> 90 <description>Enter sleep mode.</description> 91 <value>1</value> 92 </enumeratedValue> 93 <enumeratedValue> 94 <name>leave</name> 95 <description>Leave sleep mode.</description> 96 <value>0</value> 97 </enumeratedValue> 98 </enumeratedValues> 99 </field> 100 </fields> 101 </register> 102 <register> 103 <name>CMD</name> 104 <description>Command Register.</description> 105 <addressOffset>0x0001</addressOffset> 106 <size>8</size> 107 <access>read-write</access> 108 <fields> 109 <field> 110 <name>ABORT</name> 111 <description>Abort Transmission</description> 112 <bitOffset>1</bitOffset> 113 <bitWidth>1</bitWidth> 114 </field> 115 <field> 116 <name>TXREQ</name> 117 <description>Transmit Request.</description> 118 <bitOffset>2</bitOffset> 119 <bitWidth>1</bitWidth> 120 </field> 121 </fields> 122 </register> 123 <register> 124 <name>STAT</name> 125 <description>Status Register.</description> 126 <addressOffset>0x0002</addressOffset> 127 <size>8</size> 128 <access>read-only</access> 129 <fields> 130 <field> 131 <name>BUS_OFF</name> 132 <description>Bus off Status.</description> 133 <bitOffset>0</bitOffset> 134 <bitWidth>1</bitWidth> 135 </field> 136 <field> 137 <name>ERR</name> 138 <description>Error Status.</description> 139 <bitOffset>1</bitOffset> 140 <bitWidth>1</bitWidth> 141 </field> 142 <field> 143 <name>TX</name> 144 <description>Transmit Status.</description> 145 <bitOffset>2</bitOffset> 146 <bitWidth>1</bitWidth> 147 </field> 148 <field> 149 <name>RX</name> 150 <description>Receive Status.</description> 151 <bitOffset>3</bitOffset> 152 <bitWidth>1</bitWidth> 153 </field> 154 <field> 155 <name>TXBUF</name> 156 <description>Transmit Buffer Status.</description> 157 <bitOffset>5</bitOffset> 158 <bitWidth>1</bitWidth> 159 </field> 160 <field> 161 <name>DOR</name> 162 <description>Data Overrun Status.</description> 163 <bitOffset>6</bitOffset> 164 <bitWidth>1</bitWidth> 165 </field> 166 <field> 167 <name>RXBUF</name> 168 <description>Receive Buffer Status.</description> 169 <bitOffset>7</bitOffset> 170 <bitWidth>1</bitWidth> 171 </field> 172 </fields> 173 </register> 174 <register> 175 <name>INTFL</name> 176 <description>Interrupt Status Register.</description> 177 <addressOffset>0x0003</addressOffset> 178 <size>8</size> 179 <access>read-write</access> 180 <fields> 181 <field> 182 <name>DOR</name> 183 <description>Data Overrun Interrupt.</description> 184 <bitOffset>0</bitOffset> 185 <bitWidth>1</bitWidth> 186 </field> 187 <field> 188 <name>BERR</name> 189 <description>Bus Error Interrupt.</description> 190 <bitOffset>1</bitOffset> 191 <bitWidth>1</bitWidth> 192 </field> 193 <field> 194 <name>TX</name> 195 <description>Transmission Interrupt.</description> 196 <bitOffset>2</bitOffset> 197 <bitWidth>1</bitWidth> 198 </field> 199 <field> 200 <name>RX</name> 201 <description>Receive Interrupt.</description> 202 <bitOffset>3</bitOffset> 203 <bitWidth>1</bitWidth> 204 </field> 205 <field> 206 <name>ERPSV</name> 207 <description>Error Passive Interrupt.</description> 208 <bitOffset>4</bitOffset> 209 <bitWidth>1</bitWidth> 210 </field> 211 <field> 212 <name>ERWARN</name> 213 <description>Error Warning Interrupt.</description> 214 <bitOffset>5</bitOffset> 215 <bitWidth>1</bitWidth> 216 </field> 217 <field> 218 <name>AL</name> 219 <description>Arbitration Lost Interrupt.</description> 220 <bitOffset>6</bitOffset> 221 <bitWidth>1</bitWidth> 222 </field> 223 <field> 224 <name>WU</name> 225 <description>Wake-up Interrupt.</description> 226 <bitOffset>7</bitOffset> 227 <bitWidth>1</bitWidth> 228 </field> 229 </fields> 230 </register> 231 <register> 232 <name>INTEN</name> 233 <description>Interrupt Enable Register.</description> 234 <addressOffset>0x0004</addressOffset> 235 <size>8</size> 236 <access>read-write</access> 237 <fields> 238 <field> 239 <name>DOR</name> 240 <description>Data Overrun Interrupt.</description> 241 <bitOffset>0</bitOffset> 242 <bitWidth>1</bitWidth> 243 </field> 244 <field> 245 <name>BERR</name> 246 <description>Bus Error Interrupt.</description> 247 <bitOffset>1</bitOffset> 248 <bitWidth>1</bitWidth> 249 </field> 250 <field> 251 <name>TX</name> 252 <description>Transmit Interrupt.</description> 253 <bitOffset>2</bitOffset> 254 <bitWidth>1</bitWidth> 255 </field> 256 <field> 257 <name>RX</name> 258 <description>Receive Interrupt.</description> 259 <bitOffset>3</bitOffset> 260 <bitWidth>1</bitWidth> 261 </field> 262 <field> 263 <name>ERPSV</name> 264 <description>Error Passive Interrupt.</description> 265 <bitOffset>4</bitOffset> 266 <bitWidth>1</bitWidth> 267 </field> 268 <field> 269 <name>ERWARN</name> 270 <description>Error Warning Interrupt.</description> 271 <bitOffset>5</bitOffset> 272 <bitWidth>1</bitWidth> 273 </field> 274 <field> 275 <name>AL</name> 276 <description>Arbitration Lost Interrupt.</description> 277 <bitOffset>6</bitOffset> 278 <bitWidth>1</bitWidth> 279 </field> 280 <field> 281 <name>WU</name> 282 <description>Wakeup interrupt.</description> 283 <bitOffset>7</bitOffset> 284 <bitWidth>1</bitWidth> 285 </field> 286 </fields> 287 </register> 288 <register> 289 <name>RMC</name> 290 <description>Receive Message Counter Register.</description> 291 <addressOffset>0x0005</addressOffset> 292 <size>8</size> 293 <access>read-write</access> 294 <fields> 295 <field> 296 <name>NUM_MSGS</name> 297 <description>Number of stored message frames.</description> 298 <bitOffset>0</bitOffset> 299 <bitWidth>5</bitWidth> 300 </field> 301 </fields> 302 </register> 303 <register> 304 <name>BUSTIM0</name> 305 <description>Bus Timing Register 0.</description> 306 <addressOffset>0x0006</addressOffset> 307 <size>8</size> 308 <access>read-write</access> 309 <fields> 310 <field> 311 <name>BR_CLKDIV</name> 312 <description>Baud Rate Prescaler.</description> 313 <bitOffset>0</bitOffset> 314 <bitWidth>6</bitWidth> 315 </field> 316 <field> 317 <name>SJW</name> 318 <description>Synchronization Jump Width.</description> 319 <bitOffset>6</bitOffset> 320 <bitWidth>2</bitWidth> 321 </field> 322 </fields> 323 </register> 324 <register> 325 <name>BUSTIM1</name> 326 <description>Bus Timing Register 1.</description> 327 <addressOffset>0x0007</addressOffset> 328 <size>8</size> 329 <access>read-write</access> 330 <fields> 331 <field> 332 <name>TSEG1</name> 333 <description>Number of clock cycles per Time Segment 1</description> 334 <bitOffset>0</bitOffset> 335 <bitWidth>4</bitWidth> 336 </field> 337 <field> 338 <name>TSEG2</name> 339 <description>Number of clock cycles per Time Segment 2</description> 340 <bitOffset>4</bitOffset> 341 <bitWidth>3</bitWidth> 342 </field> 343 <field> 344 <name>SAM</name> 345 <description>Number of bus level samples.</description> 346 <bitOffset>7</bitOffset> 347 <bitWidth>1</bitWidth> 348 </field> 349 </fields> 350 </register> 351 <register> 352 <name>TXFIFO32</name> 353 <description>Transmit FIFO Register.</description> 354 <addressOffset>0x0008</addressOffset> 355 <size>32</size> 356 <access>read-write</access> 357 <fields> 358 <field> 359 <name>DATA</name> 360 <description>Write to put into TX FIFO.</description> 361 <bitOffset>0</bitOffset> 362 <bitWidth>32</bitWidth> 363 </field> 364 </fields> 365 </register> 366 <register> 367 <dim>2</dim> 368 <dimIncrement>2</dimIncrement> 369 <name>TXFIFO16[%s]</name> 370 <description>Transmit FIFO Register.</description> 371 <addressOffset>0x0008</addressOffset> 372 <size>16</size> 373 <access>read-write</access> 374 <fields> 375 <field> 376 <name>DATA</name> 377 <description>Write to put into TX FIFO.</description> 378 <bitOffset>0</bitOffset> 379 <bitWidth>16</bitWidth> 380 </field> 381 </fields> 382 </register> 383 <register> 384 <dim>4</dim> 385 <dimIncrement>1</dimIncrement> 386 <name>TXFIFO8[%s]</name> 387 <description>Transmit FIFO Register.</description> 388 <addressOffset>0x0008</addressOffset> 389 <size>8</size> 390 <access>read-write</access> 391 <fields> 392 <field> 393 <name>DATA</name> 394 <description>Write to put into TX FIFO.</description> 395 <bitOffset>0</bitOffset> 396 <bitWidth>8</bitWidth> 397 </field> 398 </fields> 399 </register> 400 <register> 401 <name>RXFIFO32</name> 402 <description>Receive FIFO Register.</description> 403 <addressOffset>0x000C</addressOffset> 404 <access>read-only</access> 405 <fields> 406 <field> 407 <name>DATA</name> 408 <description>Read from RX FIFO.</description> 409 <bitOffset>0</bitOffset> 410 <bitWidth>32</bitWidth> 411 </field> 412 </fields> 413 </register> 414 <register> 415 <dim>2</dim> 416 <dimIncrement>2</dimIncrement> 417 <name>RXFIFO16[%s]</name> 418 <description>Receive FIFO Register.</description> 419 <addressOffset>0x000C</addressOffset> 420 <size>16</size> 421 <access>read-only</access> 422 <fields> 423 <field> 424 <name>DATA</name> 425 <description>Read from RX FIFO.</description> 426 <bitOffset>0</bitOffset> 427 <bitWidth>16</bitWidth> 428 </field> 429 </fields> 430 </register> 431 <register> 432 <dim>4</dim> 433 <dimIncrement>1</dimIncrement> 434 <name>RXFIFO8[%s]</name> 435 <description>Receive FIFO Register.</description> 436 <addressOffset>0x000C</addressOffset> 437 <size>8</size> 438 <access>read-only</access> 439 <fields> 440 <field> 441 <name>DATA</name> 442 <description>Read from RX FIFO.</description> 443 <bitOffset>0</bitOffset> 444 <bitWidth>8</bitWidth> 445 </field> 446 </fields> 447 </register> 448 <register> 449 <name>ACR32</name> 450 <description>Acceptance Code Register.</description> 451 <addressOffset>0x0010</addressOffset> 452 <access>read-write</access> 453 <fields> 454 <field> 455 <name>ACR</name> 456 <description>Acceptance Code.</description> 457 <bitOffset>0</bitOffset> 458 <bitWidth>32</bitWidth> 459 </field> 460 </fields> 461 </register> 462 <register> 463 <dim>2</dim> 464 <dimIncrement>2</dimIncrement> 465 <name>ACR16[%s]</name> 466 <description>Acceptance Code Register.</description> 467 <addressOffset>0x0010</addressOffset> 468 <size>16</size> 469 <access>read-write</access> 470 <fields> 471 <field> 472 <name>ACR</name> 473 <description>Acceptance Code.</description> 474 <bitOffset>0</bitOffset> 475 <bitWidth>16</bitWidth> 476 </field> 477 </fields> 478 </register> 479 <register> 480 <dim>4</dim> 481 <dimIncrement>1</dimIncrement> 482 <name>ACR8[%s]</name> 483 <description>Acceptance Code Register.</description> 484 <addressOffset>0x0010</addressOffset> 485 <size>8</size> 486 <access>read-write</access> 487 <fields> 488 <field> 489 <name>ACR</name> 490 <description>Acceptance Code.</description> 491 <bitOffset>0</bitOffset> 492 <bitWidth>8</bitWidth> 493 </field> 494 </fields> 495 </register> 496 <register> 497 <name>AMR32</name> 498 <description>Acceptance Mask Register.</description> 499 <addressOffset>0x0014</addressOffset> 500 <access>read-write</access> 501 <fields> 502 <field> 503 <name>AMR</name> 504 <description>Acceptance Mask.</description> 505 <bitOffset>0</bitOffset> 506 <bitWidth>32</bitWidth> 507 </field> 508 </fields> 509 </register> 510 <register> 511 <dim>2</dim> 512 <dimIncrement>2</dimIncrement> 513 <name>AMR16[%s]</name> 514 <description>Acceptance Mask Register.</description> 515 <addressOffset>0x0014</addressOffset> 516 <size>16</size> 517 <access>read-write</access> 518 <fields> 519 <field> 520 <name>AMR</name> 521 <description>Acceptance Mask.</description> 522 <bitOffset>0</bitOffset> 523 <bitWidth>16</bitWidth> 524 </field> 525 </fields> 526 </register> 527 <register> 528 <dim>4</dim> 529 <dimIncrement>1</dimIncrement> 530 <name>AMR8[%s]</name> 531 <description>Acceptance Mask Register.</description> 532 <addressOffset>0x0014</addressOffset> 533 <size>8</size> 534 <access>read-write</access> 535 <fields> 536 <field> 537 <name>AMR</name> 538 <description>Acceptance Mask.</description> 539 <bitOffset>0</bitOffset> 540 <bitWidth>8</bitWidth> 541 </field> 542 </fields> 543 </register> 544 <register> 545 <name>ECC</name> 546 <description>Error Code Capture Register.</description> 547 <addressOffset>0x0018</addressOffset> 548 <size>8</size> 549 <access>read-only</access> 550 <fields> 551 <field> 552 <name>BER</name> 553 <description>Bit Error Occurred.</description> 554 <bitOffset>0</bitOffset> 555 <bitWidth>1</bitWidth> 556 </field> 557 <field> 558 <name>STFER</name> 559 <description>Stuff Error Occurred.</description> 560 <bitOffset>1</bitOffset> 561 <bitWidth>1</bitWidth> 562 </field> 563 <field> 564 <name>CRCER</name> 565 <description>CRC Error Occurred.</description> 566 <bitOffset>2</bitOffset> 567 <bitWidth>1</bitWidth> 568 </field> 569 <field> 570 <name>FRMER</name> 571 <description>Form Error Occurred.</description> 572 <bitOffset>3</bitOffset> 573 <bitWidth>1</bitWidth> 574 </field> 575 <field> 576 <name>ACKER</name> 577 <description>ACK Error Occurred.</description> 578 <bitOffset>4</bitOffset> 579 <bitWidth>1</bitWidth> 580 </field> 581 <field> 582 <name>EDIR</name> 583 <description>Direction of transfer while error occurred.</description> 584 <bitOffset>5</bitOffset> 585 <bitWidth>1</bitWidth> 586 <enumeratedValues> 587 <enumeratedValue> 588 <name>TX</name> 589 <description>Transmission</description> 590 <value>0</value> 591 </enumeratedValue> 592 <enumeratedValue> 593 <name>RX</name> 594 <description>Reception</description> 595 <value>1</value> 596 </enumeratedValue> 597 </enumeratedValues> 598 </field> 599 <field> 600 <name>TXWRN</name> 601 <description>Set when TXERR counter is greater than or equal to 96.</description> 602 <bitOffset>6</bitOffset> 603 <bitWidth>1</bitWidth> 604 </field> 605 <field> 606 <name>RXWRN</name> 607 <description>Set when RXERR counter is greater than or equal to 96.</description> 608 <bitOffset>7</bitOffset> 609 <bitWidth>1</bitWidth> 610 </field> 611 </fields> 612 </register> 613 <register> 614 <name>RXERR</name> 615 <description>Receive Error Counter.</description> 616 <addressOffset>0x0019</addressOffset> 617 <size>8</size> 618 <access>read-write</access> 619 <fields> 620 <field> 621 <name>RXERR</name> 622 <description>Receive Error Counter.</description> 623 <bitOffset>0</bitOffset> 624 <bitWidth>8</bitWidth> 625 </field> 626 </fields> 627 </register> 628 <register> 629 <name>TXERR</name> 630 <description>Invalidate All Registers.</description> 631 <addressOffset>0x001A</addressOffset> 632 <size>8</size> 633 <access>read-write</access> 634 <fields> 635 <field> 636 <name>TXERR</name> 637 <description>Transmit Error Counter.</description> 638 <bitOffset>0</bitOffset> 639 <bitWidth>8</bitWidth> 640 </field> 641 </fields> 642 </register> 643 <register> 644 <name>ALC</name> 645 <description>Arbitration Lost Code Capture Register.</description> 646 <addressOffset>0x001B</addressOffset> 647 <size>8</size> 648 <access>read-only</access> 649 <fields> 650 <field> 651 <name>ALC</name> 652 <description>Arbitration Lost Capture.</description> 653 <bitOffset>0</bitOffset> 654 <bitWidth>5</bitWidth> 655 </field> 656 </fields> 657 </register> 658 <register> 659 <name>NBT</name> 660 <description>Nominal Bit Timing Register.</description> 661 <addressOffset>0x001C</addressOffset> 662 <access>read-write</access> 663 <fields> 664 <field> 665 <name>NBRP</name> 666 <description>Baudrate Prescaler Used in Arbitration Phase.</description> 667 <bitOffset>0</bitOffset> 668 <bitWidth>10</bitWidth> 669 </field> 670 <field> 671 <name>NSEG1</name> 672 <description>The time segment before the sample point in Abritration Phase.</description> 673 <bitOffset>10</bitOffset> 674 <bitWidth>8</bitWidth> 675 </field> 676 <field> 677 <name>NSEG2</name> 678 <description>The time segment after the sample point in Abritration Phase.</description> 679 <bitOffset>18</bitOffset> 680 <bitWidth>7</bitWidth> 681 </field> 682 <field> 683 <name>NSJW</name> 684 <description>Synchronization Jump Width in Arbitration Phase.</description> 685 <bitOffset>25</bitOffset> 686 <bitWidth>7</bitWidth> 687 </field> 688 </fields> 689 </register> 690 <register> 691 <name>DBT_SSPP</name> 692 <description>Data Bit Timing Register.</description> 693 <addressOffset>0x0020</addressOffset> 694 <access>read-write</access> 695 <fields> 696 <field> 697 <name>DBRP</name> 698 <description>Baudrate Prescaler in Data Phase.</description> 699 <bitOffset>0</bitOffset> 700 <bitWidth>10</bitWidth> 701 </field> 702 <field> 703 <name>DSEG1</name> 704 <description>The time segment before the sample point in Data Phase.</description> 705 <bitOffset>10</bitOffset> 706 <bitWidth>6</bitWidth> 707 </field> 708 <field> 709 <name>DSEG2</name> 710 <description>The time segment before the sample point in Data Phase.</description> 711 <bitOffset>16</bitOffset> 712 <bitWidth>4</bitWidth> 713 </field> 714 <field> 715 <name>DSJW</name> 716 <description>Synchronization Jump Width in Data Phase</description> 717 <bitOffset>20</bitOffset> 718 <bitWidth>4</bitWidth> 719 </field> 720 <field> 721 <name>SSPP</name> 722 <description>Position of the secondary sample point.</description> 723 <bitOffset>24</bitOffset> 724 <bitWidth>7</bitWidth> 725 </field> 726 </fields> 727 </register> 728 <register> 729 <name>FDCTRL</name> 730 <description>FD Control Register.</description> 731 <addressOffset>0x0024</addressOffset> 732 <size>8</size> 733 <access>read-write</access> 734 <fields> 735 <field> 736 <name>FDEN</name> 737 <description>FD Frame format/ Extended data length. This bit indicates CAN FD frame format.</description> 738 <bitOffset>0</bitOffset> 739 <bitWidth>1</bitWidth> 740 <enumeratedValues> 741 <enumeratedValue> 742 <name>fd</name> 743 <description>CAN FD Frame Format</description> 744 <value>1</value> 745 </enumeratedValue> 746 <enumeratedValue> 747 <name>classic</name> 748 <description>Classic CAN Frame Format.</description> 749 <value>0</value> 750 </enumeratedValue> 751 </enumeratedValues> 752 </field> 753 <field> 754 <name>BRSEN</name> 755 <description>This bit indicates whether the bit rate is switched in Data phase.</description> 756 <bitOffset>1</bitOffset> 757 <bitWidth>1</bitWidth> 758 <enumeratedValues> 759 <enumeratedValue> 760 <name>NOSW</name> 761 <description>Bit rate is not switced inside of CAN FD frame.</description> 762 <value>0</value> 763 </enumeratedValue> 764 <enumeratedValue> 765 <name>SW</name> 766 <description>Bit rate is switched from nominal bit rate of the arbitration phase to alternate bit rate of data phase.</description> 767 <value>1</value> 768 </enumeratedValue> 769 </enumeratedValues> 770 </field> 771 <field> 772 <name>EXTBT</name> 773 <description>This bit configure the Bit Time prescaler in Arbitration phase.</description> 774 <bitOffset>2</bitOffset> 775 <bitWidth>1</bitWidth> 776 <enumeratedValues> 777 <enumeratedValue> 778 <name>BT</name> 779 <description>Use contents of BT register to configure bit time in arbitration phase.</description> 780 <value>0</value> 781 </enumeratedValue> 782 <enumeratedValue> 783 <name>NBT</name> 784 <description>Use contents of NBT register to configure bit time in arbitration phase.</description> 785 <value>1</value> 786 </enumeratedValue> 787 </enumeratedValues> 788 </field> 789 <field> 790 <name>ISO</name> 791 <description>ISO CAN FD Format Selection.</description> 792 <bitOffset>3</bitOffset> 793 <bitWidth>1</bitWidth> 794 <enumeratedValues> 795 <enumeratedValue> 796 <name>BOSCH</name> 797 <description>Frame format according to Bosch CAN FD specification.</description> 798 <value>0</value> 799 </enumeratedValue> 800 <enumeratedValue> 801 <name>ISO</name> 802 <description>Frame format according to ISO 11898 1, 2015.</description> 803 <value>1</value> 804 </enumeratedValue> 805 </enumeratedValues> 806 </field> 807 <field> 808 <name>DAR</name> 809 <description>Disable Auto Retransmission</description> 810 <bitOffset>4</bitOffset> 811 <bitWidth>1</bitWidth> 812 <enumeratedValues> 813 <enumeratedValue> 814 <name>EN</name> 815 <description>Automatic retransmission enabled.</description> 816 <value>0</value> 817 </enumeratedValue> 818 <enumeratedValue> 819 <name>DIS</name> 820 <description>Automatic retransmission disabled.</description> 821 <value>1</value> 822 </enumeratedValue> 823 </enumeratedValues> 824 </field> 825 <field> 826 <name>REOM</name> 827 <description>Restricted Operation Mode.</description> 828 <bitOffset>5</bitOffset> 829 <bitWidth>1</bitWidth> 830 </field> 831 <field> 832 <name>PED</name> 833 <description>Protocol Exception Disable.</description> 834 <bitOffset>6</bitOffset> 835 <bitWidth>1</bitWidth> 836 </field> 837 </fields> 838 </register> 839 <register> 840 <name>FDSTAT</name> 841 <description>Invalidate All Registers.</description> 842 <addressOffset>0x0025</addressOffset> 843 <size>8</size> 844 <access>read-only</access> 845 <fields> 846 <field> 847 <name>BITERR</name> 848 <description>Bit Error Indicator. When this bit is set the inconsistency occurs between the transmitted and the received bit in CAN FD frame.</description> 849 <bitOffset>0</bitOffset> 850 <bitWidth>1</bitWidth> 851 </field> 852 <field> 853 <name>CRCERR</name> 854 <description>Cyclic Redundancy Check Error indicator. This indicates that calculated CRC is different from received in CAN FD frame</description> 855 <bitOffset>1</bitOffset> 856 <bitWidth>1</bitWidth> 857 </field> 858 <field> 859 <name>FRMERR</name> 860 <description>Form Error indicator. This bit indicates, that a fixed form bit field contains at least one illegal bit in Data phase of CAN FD frame with the BRS 861bit set</description> 862 <bitOffset>2</bitOffset> 863 <bitWidth>1</bitWidth> 864 </field> 865 <field> 866 <name>STFERR</name> 867 <description>Stuff Error Indicator. This bit indicates stuff error occurred in Data phase in CAN FD frame with the BRS bit set 868</description> 869 <bitOffset>3</bitOffset> 870 <bitWidth>1</bitWidth> 871 </field> 872 <field> 873 <name>PEE</name> 874 <description>Protocol Exception Event indicator. Indicates that core detects recessive state on res position and enter to Bus integration state.</description> 875 <bitOffset>4</bitOffset> 876 <bitWidth>1</bitWidth> 877 </field> 878 <field> 879 <name>STATE</name> 880 <description>Operation state.</description> 881 <bitOffset>6</bitOffset> 882 <bitWidth>2</bitWidth> 883 <enumeratedValues> 884 <enumeratedValue> 885 <name>INT</name> 886 <description>Waiting for 11 recessive bit after reset or bus off</description> 887 <value>0</value> 888 </enumeratedValue> 889 <enumeratedValue> 890 <name>IDLE</name> 891 <description>Waiting for Start of Frame.</description> 892 <value>1</value> 893 </enumeratedValue> 894 <enumeratedValue> 895 <name>RX</name> 896 <description>Node operating as Receiver.</description> 897 <value>2</value> 898 </enumeratedValue> 899 <enumeratedValue> 900 <name>TX</name> 901 <description>Node operating as Transmitter.</description> 902 <value>3</value> 903 </enumeratedValue> 904 </enumeratedValues> 905 </field> 906 </fields> 907 </register> 908 <register> 909 <name>DPERR</name> 910 <description>Data Phase Error Counter Register.</description> 911 <addressOffset>0x0026</addressOffset> 912 <size>8</size> 913 <access>read-only</access> 914 <fields> 915 <field> 916 <name>DPERR</name> 917 <description>Data Phase Error Counter.</description> 918 <bitOffset>0</bitOffset> 919 <bitWidth>8</bitWidth> 920 </field> 921 </fields> 922 </register> 923 <register> 924 <name>APERR</name> 925 <description>Arbitration Phase Error Counter Register.</description> 926 <addressOffset>0x0027</addressOffset> 927 <size>8</size> 928 <access>read-only</access> 929 <fields> 930 <field> 931 <name>APERR</name> 932 <description>Arbitration Error Counter.</description> 933 <bitOffset>0</bitOffset> 934 <bitWidth>8</bitWidth> 935 </field> 936 </fields> 937 </register> 938 <register> 939 <name>TEST</name> 940 <description>Invalidate All Registers.</description> 941 <addressOffset>0x0028</addressOffset> 942 <size>8</size> 943 <access>read-write</access> 944 <fields> 945 <field> 946 <name>LBEN</name> 947 <description>Loopback mode.</description> 948 <bitOffset>0</bitOffset> 949 <bitWidth>1</bitWidth> 950 </field> 951 <field> 952 <name>TXC</name> 953 <description>Transmitted frame.</description> 954 <bitOffset>1</bitOffset> 955 <bitWidth>1</bitWidth> 956 </field> 957 </fields> 958 </register> 959 <register> 960 <name>WUPCLKDIV</name> 961 <description>Wake-up timer prescaler.</description> 962 <addressOffset>0x0029</addressOffset> 963 <size>8</size> 964 <access>read-write</access> 965 <fields> 966 <field> 967 <name>WUPDIV</name> 968 <description>Wake-up timer prescaler.</description> 969 <bitOffset>0</bitOffset> 970 <bitWidth>8</bitWidth> 971 </field> 972 </fields> 973 </register> 974 <register> 975 <name>WUPFT</name> 976 <description>Wake up Filter Time Register.</description> 977 <addressOffset>0x002A</addressOffset> 978 <size>16</size> 979 <access>read-write</access> 980 <fields> 981 <field> 982 <name>WUPFT</name> 983 <description>Wake-up pattern filter time.</description> 984 <bitOffset>0</bitOffset> 985 <bitWidth>16</bitWidth> 986 </field> 987 </fields> 988 </register> 989 <register> 990 <name>WUPET</name> 991 <description>Wake-up Expire Time Register.</description> 992 <addressOffset>0x002C</addressOffset> 993 <access>read-write</access> 994 <fields> 995 <field> 996 <name>WUPET</name> 997 <description>Wake up patter expire time.</description> 998 <bitOffset>0</bitOffset> 999 <bitWidth>20</bitWidth> 1000 </field> 1001 </fields> 1002 </register> 1003 <register> 1004 <name>RXDCNT</name> 1005 <description>RX FIFO Data Counter Register.</description> 1006 <addressOffset>0x0030</addressOffset> 1007 <size>16</size> 1008 <access>read-write</access> 1009 <fields> 1010 <field> 1011 <name>RXDCNT</name> 1012 <description>RX FIFO data counter.</description> 1013 <bitOffset>0</bitOffset> 1014 <bitWidth>16</bitWidth> 1015 </field> 1016 </fields> 1017 </register> 1018 <register> 1019 <name>TXSCNT</name> 1020 <description>TX FIFO Space Counter.</description> 1021 <addressOffset>0x0032</addressOffset> 1022 <size>8</size> 1023 <access>read-write</access> 1024 <fields> 1025 <field> 1026 <name>TXSCNT</name> 1027 <description>TX FIFO Space Counter.</description> 1028 <bitOffset>0</bitOffset> 1029 <bitWidth>8</bitWidth> 1030 </field> 1031 </fields> 1032 </register> 1033 <register> 1034 <name>TXDECMP</name> 1035 <description>Invalidate All Registers.</description> 1036 <addressOffset>0x0033</addressOffset> 1037 <size>8</size> 1038 <access>read-write</access> 1039 <fields> 1040 <field> 1041 <name>TDCO</name> 1042 <description>Transceiver Delay Compensation Offset. This bit field contains the offset value added to the measured transceiver loop delay</description> 1043 <bitOffset>0</bitOffset> 1044 <bitWidth>7</bitWidth> 1045 </field> 1046 <field> 1047 <name>TDCEN</name> 1048 <description>Transceiver Delay Compensation Enable.</description> 1049 <bitOffset>7</bitOffset> 1050 <bitWidth>1</bitWidth> 1051 </field> 1052 </fields> 1053 </register> 1054 <register> 1055 <name>EINTFL</name> 1056 <description>Extended Interrupt Flag Register.</description> 1057 <addressOffset>0x0034</addressOffset> 1058 <size>8</size> 1059 <access>read-write</access> 1060 <fields> 1061 <field> 1062 <name>RX_THD</name> 1063 <description>RX FIFO reach programmed trigger level, it is set when the RX FIFO reaches programmed trigger level (RT[2:0] in MR register). To clear the 1064RXFT interrupt, write this bit 1</description> 1065 <bitOffset>0</bitOffset> 1066 <bitWidth>1</bitWidth> 1067 </field> 1068 <field> 1069 <name>RX_TO</name> 1070 <description>RX FIFO Timeout Indicator. It is set when there is no write or read from/in to RX FIFO for the user defined time (RXFTO register) and there is at 1071least 1 entry in RX FIFO during this time, this bit is clear by write 1</description> 1072 <bitOffset>1</bitOffset> 1073 <bitWidth>1</bitWidth> 1074 </field> 1075 </fields> 1076 </register> 1077 <register> 1078 <name>EINTEN</name> 1079 <description>Extended Interrupt Enable Register.</description> 1080 <addressOffset>0x0035</addressOffset> 1081 <size>8</size> 1082 <access>read-write</access> 1083 <fields> 1084 <field> 1085 <name>RX_THD</name> 1086 <description>RX FIFO reach programmed trigger level, it is set when the RX FIFO reaches programmed trigger level (RT[2:0] in MR register). To clear the 1087RXFT interrupt, write this bit 1</description> 1088 <bitOffset>0</bitOffset> 1089 <bitWidth>1</bitWidth> 1090 </field> 1091 <field> 1092 <name>RX_TO</name> 1093 <description>RX FIFO Timeout Indicator. It is set when there is no write or read from/in to RX FIFO for the user defined time (RXFTO register) and there is at 1094least 1 entry in RX FIFO during this time, this bit is clear by write 1</description> 1095 <bitOffset>1</bitOffset> 1096 <bitWidth>1</bitWidth> 1097 </field> 1098 </fields> 1099 </register> 1100 <register> 1101 <name>RXTO</name> 1102 <description>RX FIFO Timeout Register.</description> 1103 <addressOffset>0x0036</addressOffset> 1104 <size>16</size> 1105 <access>read-write</access> 1106 <fields> 1107 <field> 1108 <name>RX_TO</name> 1109 <description>RX FIFO Timeout</description> 1110 <bitOffset>0</bitOffset> 1111 <bitWidth>16</bitWidth> 1112 </field> 1113 </fields> 1114 </register> 1115 </registers> 1116 </peripheral> 1117 <!--CAN: Controller Area Network Registers--> 1118</device>
