CAN0 Controller Area Network Registers 0x40064000 0x00 0x1000 registers MODE Mode Register. 0x0000 8 read-write AFM Hardware acceptance filter scheme. 0 1 LOM Listen Only Mode. 1 1 RST Reset Mode. 2 1 RXTRIG Receive FIFO trigger in 32bit word. 3 3 1W 1 word 0 4W 4 word 1 8W 8 word 2 16W 16 word 3 32W 32 word 4 64W 64 word 5 DMA Enable DMA mode. 6 1 SLP Sleep mode. 7 1 enter Enter sleep mode. 1 leave Leave sleep mode. 0 CMD Command Register. 0x0001 8 read-write ABORT Abort Transmission 1 1 TXREQ Transmit Request. 2 1 STAT Status Register. 0x0002 8 read-only BUS_OFF Bus off Status. 0 1 ERR Error Status. 1 1 TX Transmit Status. 2 1 RX Receive Status. 3 1 TXBUF Transmit Buffer Status. 5 1 DOR Data Overrun Status. 6 1 RXBUF Receive Buffer Status. 7 1 INTFL Interrupt Status Register. 0x0003 8 read-write DOR Data Overrun Interrupt. 0 1 BERR Bus Error Interrupt. 1 1 TX Transmission Interrupt. 2 1 RX Receive Interrupt. 3 1 ERPSV Error Passive Interrupt. 4 1 ERWARN Error Warning Interrupt. 5 1 AL Arbitration Lost Interrupt. 6 1 WU Wake-up Interrupt. 7 1 INTEN Interrupt Enable Register. 0x0004 8 read-write DOR Data Overrun Interrupt. 0 1 BERR Bus Error Interrupt. 1 1 TX Transmit Interrupt. 2 1 RX Receive Interrupt. 3 1 ERPSV Error Passive Interrupt. 4 1 ERWARN Error Warning Interrupt. 5 1 AL Arbitration Lost Interrupt. 6 1 WU Wakeup interrupt. 7 1 RMC Receive Message Counter Register. 0x0005 8 read-write NUM_MSGS Number of stored message frames. 0 5 BUSTIM0 Bus Timing Register 0. 0x0006 8 read-write BR_CLKDIV Baud Rate Prescaler. 0 6 SJW Synchronization Jump Width. 6 2 BUSTIM1 Bus Timing Register 1. 0x0007 8 read-write TSEG1 Number of clock cycles per Time Segment 1 0 4 TSEG2 Number of clock cycles per Time Segment 2 4 3 SAM Number of bus level samples. 7 1 TXFIFO32 Transmit FIFO Register. 0x0008 32 read-write DATA Write to put into TX FIFO. 0 32 2 2 TXFIFO16[%s] Transmit FIFO Register. 0x0008 16 read-write DATA Write to put into TX FIFO. 0 16 4 1 TXFIFO8[%s] Transmit FIFO Register. 0x0008 8 read-write DATA Write to put into TX FIFO. 0 8 RXFIFO32 Receive FIFO Register. 0x000C read-only DATA Read from RX FIFO. 0 32 2 2 RXFIFO16[%s] Receive FIFO Register. 0x000C 16 read-only DATA Read from RX FIFO. 0 16 4 1 RXFIFO8[%s] Receive FIFO Register. 0x000C 8 read-only DATA Read from RX FIFO. 0 8 ACR32 Acceptance Code Register. 0x0010 read-write ACR Acceptance Code. 0 32 2 2 ACR16[%s] Acceptance Code Register. 0x0010 16 read-write ACR Acceptance Code. 0 16 4 1 ACR8[%s] Acceptance Code Register. 0x0010 8 read-write ACR Acceptance Code. 0 8 AMR32 Acceptance Mask Register. 0x0014 read-write AMR Acceptance Mask. 0 32 2 2 AMR16[%s] Acceptance Mask Register. 0x0014 16 read-write AMR Acceptance Mask. 0 16 4 1 AMR8[%s] Acceptance Mask Register. 0x0014 8 read-write AMR Acceptance Mask. 0 8 ECC Error Code Capture Register. 0x0018 8 read-only BER Bit Error Occurred. 0 1 STFER Stuff Error Occurred. 1 1 CRCER CRC Error Occurred. 2 1 FRMER Form Error Occurred. 3 1 ACKER ACK Error Occurred. 4 1 EDIR Direction of transfer while error occurred. 5 1 TX Transmission 0 RX Reception 1 TXWRN Set when TXERR counter is greater than or equal to 96. 6 1 RXWRN Set when RXERR counter is greater than or equal to 96. 7 1 RXERR Receive Error Counter. 0x0019 8 read-write RXERR Receive Error Counter. 0 8 TXERR Invalidate All Registers. 0x001A 8 read-write TXERR Transmit Error Counter. 0 8 ALC Arbitration Lost Code Capture Register. 0x001B 8 read-only ALC Arbitration Lost Capture. 0 5 NBT Nominal Bit Timing Register. 0x001C read-write NBRP Baudrate Prescaler Used in Arbitration Phase. 0 10 NSEG1 The time segment before the sample point in Abritration Phase. 10 8 NSEG2 The time segment after the sample point in Abritration Phase. 18 7 NSJW Synchronization Jump Width in Arbitration Phase. 25 7 DBT_SSPP Data Bit Timing Register. 0x0020 read-write DBRP Baudrate Prescaler in Data Phase. 0 10 DSEG1 The time segment before the sample point in Data Phase. 10 6 DSEG2 The time segment before the sample point in Data Phase. 16 4 DSJW Synchronization Jump Width in Data Phase 20 4 SSPP Position of the secondary sample point. 24 7 FDCTRL FD Control Register. 0x0024 8 read-write FDEN FD Frame format/ Extended data length. This bit indicates CAN FD frame format. 0 1 fd CAN FD Frame Format 1 classic Classic CAN Frame Format. 0 BRSEN This bit indicates whether the bit rate is switched in Data phase. 1 1 NOSW Bit rate is not switced inside of CAN FD frame. 0 SW Bit rate is switched from nominal bit rate of the arbitration phase to alternate bit rate of data phase. 1 EXTBT This bit configure the Bit Time prescaler in Arbitration phase. 2 1 BT Use contents of BT register to configure bit time in arbitration phase. 0 NBT Use contents of NBT register to configure bit time in arbitration phase. 1 ISO ISO CAN FD Format Selection. 3 1 BOSCH Frame format according to Bosch CAN FD specification. 0 ISO Frame format according to ISO 11898 1, 2015. 1 DAR Disable Auto Retransmission 4 1 EN Automatic retransmission enabled. 0 DIS Automatic retransmission disabled. 1 REOM Restricted Operation Mode. 5 1 PED Protocol Exception Disable. 6 1 FDSTAT Invalidate All Registers. 0x0025 8 read-only BITERR Bit Error Indicator. When this bit is set the inconsistency occurs between the transmitted and the received bit in CAN FD frame. 0 1 CRCERR Cyclic Redundancy Check Error indicator. This indicates that calculated CRC is different from received in CAN FD frame 1 1 FRMERR Form Error indicator. This bit indicates, that a fixed form bit field contains at least one illegal bit in Data phase of CAN FD frame with the BRS bit set 2 1 STFERR Stuff Error Indicator. This bit indicates stuff error occurred in Data phase in CAN FD frame with the BRS bit set 3 1 PEE Protocol Exception Event indicator. Indicates that core detects recessive state on res position and enter to Bus integration state. 4 1 STATE Operation state. 6 2 INT Waiting for 11 recessive bit after reset or bus off 0 IDLE Waiting for Start of Frame. 1 RX Node operating as Receiver. 2 TX Node operating as Transmitter. 3 DPERR Data Phase Error Counter Register. 0x0026 8 read-only DPERR Data Phase Error Counter. 0 8 APERR Arbitration Phase Error Counter Register. 0x0027 8 read-only APERR Arbitration Error Counter. 0 8 TEST Invalidate All Registers. 0x0028 8 read-write LBEN Loopback mode. 0 1 TXC Transmitted frame. 1 1 WUPCLKDIV Wake-up timer prescaler. 0x0029 8 read-write WUPDIV Wake-up timer prescaler. 0 8 WUPFT Wake up Filter Time Register. 0x002A 16 read-write WUPFT Wake-up pattern filter time. 0 16 WUPET Wake-up Expire Time Register. 0x002C read-write WUPET Wake up patter expire time. 0 20 RXDCNT RX FIFO Data Counter Register. 0x0030 16 read-write RXDCNT RX FIFO data counter. 0 16 TXSCNT TX FIFO Space Counter. 0x0032 8 read-write TXSCNT TX FIFO Space Counter. 0 8 TXDECMP Invalidate All Registers. 0x0033 8 read-write TDCO Transceiver Delay Compensation Offset. This bit field contains the offset value added to the measured transceiver loop delay 0 7 TDCEN Transceiver Delay Compensation Enable. 7 1 EINTFL Extended Interrupt Flag Register. 0x0034 8 read-write RX_THD RX FIFO reach programmed trigger level, it is set when the RX FIFO reaches programmed trigger level (RT[2:0] in MR register). To clear the RXFT interrupt, write this bit 1 0 1 RX_TO RX FIFO Timeout Indicator. It is set when there is no write or read from/in to RX FIFO for the user defined time (RXFTO register) and there is at least 1 entry in RX FIFO during this time, this bit is clear by write 1 1 1 EINTEN Extended Interrupt Enable Register. 0x0035 8 read-write RX_THD RX FIFO reach programmed trigger level, it is set when the RX FIFO reaches programmed trigger level (RT[2:0] in MR register). To clear the RXFT interrupt, write this bit 1 0 1 RX_TO RX FIFO Timeout Indicator. It is set when there is no write or read from/in to RX FIFO for the user defined time (RXFTO register) and there is at least 1 entry in RX FIFO during this time, this bit is clear by write 1 1 1 RXTO RX FIFO Timeout Register. 0x0036 16 read-write RX_TO RX FIFO Timeout 0 16