1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>CAMERAIF</name> 5 <description>CameraIF Interface.</description> 6 <baseAddress>0x4000E000</baseAddress> 7 <size>32</size> 8 <access>read-write</access> 9 <addressBlock> 10 <offset>0</offset> 11 <size>0x1000</size> 12 <usage>registers</usage> 13 </addressBlock> 14 <interrupt> 15 <name>CameraIF</name> 16 <value>91</value> 17 </interrupt> 18 <registers> 19<!-- VER: Version --> 20 <register> 21 <name>VER</name> 22 <description>CameraIF Version</description> 23 <addressOffset>0x0000</addressOffset> 24 <access>read-write</access> 25 <fields> 26 <field> 27 <name>minor</name> 28 <description>Minor version number</description> 29 <bitRange>[7:0]</bitRange> 30 <access>read-write</access> 31 </field> 32 <field> 33 <name>major</name> 34 <description>Major version number</description> 35 <bitRange>[15:8]</bitRange> 36 <access>read-write</access> 37 </field> 38 </fields> 39 </register> 40<!-- FIFO_SIZE: Size of FIFO --> 41 <register> 42 <name>FIFO_SIZE</name> 43 <description>1-Wire Master Clock Divisor.</description> 44 <addressOffset>0x0004</addressOffset> 45 <access>read-write</access> 46 <fields> 47 <field> 48 <name>fifo_size</name> 49 <description>Fifo Size.</description> 50 <bitRange>[7:0]</bitRange> 51 <access>read-write</access> 52 </field> 53 </fields> 54 </register> 55<!-- CTRL: CTRL Register --> 56 <register> 57 <name>CTRL</name> 58 <description>Control register </description> 59 <addressOffset>0x0008</addressOffset> 60 <access>read-write</access> 61 <fields> 62 <field> 63 <name>READ_MODE</name> 64 <description>Read Mode</description> 65 <bitOffset>0</bitOffset> 66 <bitWidth>2</bitWidth> 67 <access>read-write</access> 68 <enumeratedValues> 69 <enumeratedValue> 70 <name>dis</name> 71 <description>Camera interface disabled</description> 72 <value>0</value> 73 </enumeratedValue> 74 <enumeratedValue> 75 <name>single_img</name> 76 <description>single image captured</description> 77 <value>1</value> 78 </enumeratedValue> 79 <enumeratedValue> 80 <name>continuous</name> 81 <description>Continuous image captured</description> 82 <value>2</value> 83 </enumeratedValue> 84 </enumeratedValues> 85 </field> 86 <field> 87 <name>DATA_WIDTH</name> 88 <description>Data Width</description> 89 <bitOffset>2</bitOffset> 90 <bitWidth>2</bitWidth> 91 <access>read-write</access> 92 <enumeratedValues> 93 <enumeratedValue> 94 <name>8bit</name> 95 <description>8 bit</description> 96 <value>0</value> 97 </enumeratedValue> 98 <enumeratedValue> 99 <name>10bit</name> 100 <description>10 bit</description> 101 <value>1</value> 102 </enumeratedValue> 103 <enumeratedValue> 104 <name>12bit</name> 105 <description>12 bit</description> 106 <value>2</value> 107 </enumeratedValue> 108 </enumeratedValues> 109 </field> 110 <field> 111 <name>DS_TIMING_EN</name> 112 <description>Ds timing enabled</description> 113 <bitOffset>4</bitOffset> 114 <bitWidth>1</bitWidth> 115 <access>read-write</access> 116 <enumeratedValues> 117 <enumeratedValue> 118 <name>dis</name> 119 <description>timing from VSYNC,HSYNC</description> 120 <value>0</value> 121 </enumeratedValue> 122 <enumeratedValue> 123 <name>en</name> 124 <description>timing embedded in data using SAV EAV codes.</description> 125 <value>1</value> 126 </enumeratedValue> 127 </enumeratedValues> 128 </field> 129 <field> 130 <name>FIFO_THRSH</name> 131 <description>Data FIFO threshold Setting</description> 132 <bitOffset>5</bitOffset> 133 <bitWidth>5</bitWidth> 134 <access>read-write</access> 135 </field> 136 <field> 137 <name>RX_DMA</name> 138 <description>DMA mode enabled</description> 139 <bitOffset>10</bitOffset> 140 <bitWidth>1</bitWidth> 141 <access>read-write</access> 142 <enumeratedValues> 143 <enumeratedValue> 144 <name>dis</name> 145 <description>DMA mode disabled.</description> 146 <value>0</value> 147 </enumeratedValue> 148 <enumeratedValue> 149 <name>en</name> 150 <description>DMA mode enabled.</description> 151 <value>1</value> 152 </enumeratedValue> 153 </enumeratedValues> 154 </field> 155 <field> 156 <name>RX_DMA_THRSH</name> 157 <description>DMA mode threshold Level</description> 158 <bitOffset>11</bitOffset> 159 <bitWidth>4</bitWidth> 160 <access>read-write</access> 161 </field> 162 <field> 163 <name>PCIF_SYS</name> 164 <description>PCIF control</description> 165 <bitOffset>15</bitOffset> 166 <bitWidth>1</bitWidth> 167 <access>read-write</access> 168 <enumeratedValues> 169 <enumeratedValue> 170 <name>dis</name> 171 <description>PCIF disabled.</description> 172 <value>0</value> 173 </enumeratedValue> 174 <enumeratedValue> 175 <name>en</name> 176 <description>PCIF enabled.</description> 177 <value>1</value> 178 </enumeratedValue> 179 </enumeratedValues> 180 </field> 181 </fields> 182 </register> 183<!-- INT_EN: INT_EN Register --> 184 <register> 185 <name>INT_EN</name> 186 <description>Interupt Enable register </description> 187 <addressOffset>0x000C</addressOffset> 188 <access>read-write</access> 189 <fields> 190 <field> 191 <name>IMG_DONE</name> 192 <description>Image done</description> 193 <bitOffset>0</bitOffset> 194 <bitWidth>1</bitWidth> 195 <access>read-write</access> 196 </field> 197 <field> 198 <name>FIFO_FULL</name> 199 <description>FIFO Full</description> 200 <bitOffset>1</bitOffset> 201 <bitWidth>1</bitWidth> 202 <access>read-write</access> 203 </field> 204 <field> 205 <name>FIFO_THRESH</name> 206 <description>FIFO Threshold Level Met</description> 207 <bitOffset>2</bitOffset> 208 <bitWidth>1</bitWidth> 209 <access>read-write</access> 210 </field> 211 <field> 212 <name>FIFO_NOT_EMPTY</name> 213 <description>FIFO Threshold Level Met</description> 214 <bitOffset>3</bitOffset> 215 <bitWidth>1</bitWidth> 216 <access>read-write</access> 217 </field> 218 </fields> 219 </register> 220<!-- INT_FL: INT_FL Register --> 221 <register> 222 <name>INT_FL</name> 223 <description>Interupt Flags register </description> 224 <addressOffset>0x0010</addressOffset> 225 <access>read-write</access> 226 <fields> 227 <field> 228 <name>IMG_DONE</name> 229 <description>Image done</description> 230 <bitOffset>0</bitOffset> 231 <bitWidth>1</bitWidth> 232 <access>read-write</access> 233 </field> 234 <field> 235 <name>FIFO_FULL</name> 236 <description>FIFO Full</description> 237 <bitOffset>1</bitOffset> 238 <bitWidth>1</bitWidth> 239 <access>read-write</access> 240 </field> 241 <field> 242 <name>FIFO_THRESH</name> 243 <description>FIFO Threshold Level Met</description> 244 <bitOffset>2</bitOffset> 245 <bitWidth>1</bitWidth> 246 <access>read-write</access> 247 </field> 248 <field> 249 <name>FIFO_NOT_EMPTY</name> 250 <description>FIFO Threshold Level Met</description> 251 <bitOffset>3</bitOffset> 252 <bitWidth>1</bitWidth> 253 <access>read-write</access> 254 </field> 255 </fields> 256 </register> 257<!-- DS_TIMING_CODES: DS_TIMING_CODES Register --> 258 <register> 259 <name>DS_TIMING_CODES</name> 260 <description>DS Timing Codes register </description> 261 <addressOffset>0x0014</addressOffset> 262 <access>read-write</access> 263 <fields> 264 <field> 265 <name>SAV</name> 266 <description>Start active video code</description> 267 <bitRange>[7:0]</bitRange> 268 <access>read-write</access> 269 </field> 270 <field> 271 <name>EAV</name> 272 <description>End active video code</description> 273 <bitRange>[15:8]</bitRange> 274 <access>read-write</access> 275 </field> 276 </fields> 277 </register> 278<!-- FIFO_DATA: FIFO_DATA Register --> 279 <register> 280 <name>FIFO_DATA</name> 281 <description>FIFO DATA register </description> 282 <addressOffset>0x0030</addressOffset> 283 <access>read-write</access> 284 <fields> 285 <field> 286 <name>FIFO_DATA</name> 287 <description>Data From the fifo to be read by the dma.</description> 288 <bitRange>[31:0]</bitRange> 289 <access>read-write</access> 290 </field> 291 </fields> 292 </register> 293 </registers> 294 </peripheral> 295<!-- Camera IF --> 296</device> 297
