1 /** 2 * @file dma.h 3 * @brief Direct Memory Access (DMA) driver function prototypes and data types. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78002_DMA_H_ 27 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78002_DMA_H_ 28 29 /* **** Includes **** */ 30 #include <stdbool.h> 31 #include "mxc_device.h" 32 #include "dma_regs.h" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /** 39 * @defgroup dma Direct Memory Access (DMA) 40 * @ingroup periphlibs 41 * @{ 42 */ 43 44 /* **** Definitions **** */ 45 46 /** 47 * @brief Enumeration for the DMA Channel's priority level. 48 * 49 */ 50 typedef enum { 51 MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority 52 MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority 53 MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority 54 MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority 55 } mxc_dma_priority_t; 56 57 /** @brief DMA request select */ 58 typedef enum { 59 MXC_DMA_REQUEST_MEMTOMEM = 60 MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection 61 MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection 62 MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection 63 MXC_DMA_REQUEST_UART0RX = 64 MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection 65 MXC_DMA_REQUEST_UART1RX = 66 MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection 67 MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection 68 MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection 69 MXC_DMA_REQUEST_ADC = MXC_S_DMA_CTRL_REQUEST_ADC, ///< ADC Receive DMA Request Selection 70 MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection 71 MXC_DMA_REQUEST_CSI2RX = MXC_S_DMA_CTRL_REQUEST_CSI2RX, ///< CSI2 Receive DMA Request Selection 72 MXC_DMA_REQUEST_PCIFRX = MXC_S_DMA_CTRL_REQUEST_PCIFRX, ///< PCIF Receive DMA Request Selection 73 MXC_DMA_REQUEST_UART2RX = 74 MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection 75 MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection 76 MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection 77 MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection 78 MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection 79 MXC_DMA_REQUEST_UART0TX = 80 MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection 81 MXC_DMA_REQUEST_UART1TX = 82 MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection 83 MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection 84 MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection 85 MXC_DMA_REQUEST_I2C2TX = 86 MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection */ 87 MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection */ 88 MXC_DMA_REQUEST_UART2TX = 89 MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection 90 MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection 91 MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection 92 } mxc_dma_reqsel_t; 93 94 /** @brief Enumeration for the DMA prescaler */ 95 typedef enum { 96 MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled 97 MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256 98 MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536 99 MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216 100 } mxc_dma_prescale_t; 101 102 /** @brief Enumeration for the DMA timeout value */ 103 typedef enum { 104 MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks 105 MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks 106 MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks 107 MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks 108 MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks 109 MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks 110 MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks 111 MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks 112 } mxc_dma_timeout_t; 113 114 /** @brief DMA transfer data width */ 115 typedef enum { 116 /* Using the '_V_' define instead of the '_S_' since these same values will be used to 117 specify the DSTWD also. The API functions will shift the value the correct amount 118 prior to writing the cfg register. */ 119 MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes 120 MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words 121 MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words 122 } mxc_dma_width_t; 123 124 /** 125 * @brief The basic configuration information to set up a DMA channel 126 * and prepare it for transfers. 127 * 128 */ 129 typedef struct { 130 int ch; ///< The channel to load the configuration data into 131 mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral) 132 mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) 133 mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) 134 int srcinc_en; ///< Whether to increment the source address during the transfer 135 int dstinc_en; ///< Whether to increment the source address during the transfer 136 } mxc_dma_config_t; 137 138 /** 139 * @brief The information needed to complete a DMA transfer 140 * 141 */ 142 typedef struct { 143 int ch; ///< The channel to use for the transfer 144 void *source; ///< Pointer to the source address, if applicable 145 void *dest; ///< Pointer to the destination address, if applicable 146 int len; ///< Number of bytes to transfer 147 } mxc_dma_srcdst_t; 148 149 /** 150 * @brief The advanced configuration options, these are optional but could 151 * be needed in cases where multiple DMA channels are running concurrently 152 * or DMA is being used with low bandwidth peripherals. 153 * 154 */ 155 typedef struct { 156 int ch; ///< The channel to use for the transfer 157 mxc_dma_priority_t prio; ///< The DMA priority for the channel 158 unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer 159 mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout 160 mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer 161 unsigned int burst_size; ///< Number of bytes moved in a single burst 162 } mxc_dma_adv_config_t; 163 164 /** 165 * @brief The callback called on completion of a DMA_MemCpy() transfer 166 * 167 * @param dest Pointer to the destination of the copy 168 */ 169 typedef void (*mxc_dma_complete_cb_t)(void *dest); 170 171 /** 172 * @brief The callback called on completion of a transfer, 173 * @note This callback is used with MXC_DMA_DoTransfer() 174 * to allow the user to chain an unlimited number of 175 * DMA Transfers. 176 * 177 * @param trans Struct of the completed transfer 178 * 179 * @return Returns the next transfer to be completed, or NULL 180 * if no more transfers will be done 181 */ 182 typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); 183 184 /* **** Function Prototypes **** */ 185 /*************************/ 186 /* Low Level Functions */ 187 /*************************/ 188 /** 189 * @brief Initialize DMA resources 190 * @details This initialization is required before using the DMA driver functions. 191 * @note On default this function enables DMA peripheral clock. 192 * if you wish to manage clock and gpio related things in upper level instead of here. 193 * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. 194 * By this flag this function will remove clock and gpio related codes from file. 195 * @return #E_NO_ERROR if successful 196 */ 197 int MXC_DMA_Init(void); 198 199 /** 200 * @brief De-Initialize DMA resources. 201 */ 202 void MXC_DMA_DeInit(void); 203 204 /** 205 * @brief Request DMA channel 206 * @details Returns a handle to the first free DMA channel, which can be used via API calls 207 * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. 208 * @return Non-negative channel handle (inclusive of zero). 209 * @return #E_NONE_AVAIL All channels in use. 210 * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. 211 * @return #E_BUSY DMA is currently busy (locked), try again later. 212 */ 213 int MXC_DMA_AcquireChannel(void); 214 215 /** 216 * @brief Release DMA channel 217 * @details Stops any DMA operation on the channel and returns it to the pool of free channels. 218 * 219 * @param ch channel handle to release 220 * 221 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 222 */ 223 int MXC_DMA_ReleaseChannel(int ch); 224 225 /** 226 * @brief Configure the DMA channel 227 * @details Configures the channel, which was previously requested by MXC_DMA_Getchannel() 228 * 229 * @param config Struct containing DMA configuration parameters 230 * @param srcdst Struct containing pointers and length of DMA operation 231 * 232 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 233 */ 234 int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); 235 236 /** 237 * @brief Configure the DMA channel with more advanced parameters 238 * 239 * @param advConfig Struct containing advanced DMA parameters 240 * 241 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 242 */ 243 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); 244 245 /** 246 * @brief Set channel source, destination, and count for the transfer 247 * @param srcdst Struct containing the channel, source, destination, and count for the channel 248 * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, 249 * either src_addr or dst_addr will be ignored by the DMA engine. 250 * In these cases, the address is a don't-care. See the User's 251 * Guide for more information. 252 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 253 */ 254 int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); 255 256 /** 257 * @brief Get channel source, destination, and count for transfer 258 * 259 * @param srcdst Pointer to struct with the correct channel number 260 * 261 * @return See \ref MXC_Error_Codes for a list of return values 262 */ 263 int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); 264 265 /** 266 * @brief Set channel reload source, destination, and count for the transfer 267 * @param srcdstReload Struct containing the channel, source, destination, and count for the channel 268 * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, 269 * either src_addr or dst_addr will be ignored by the DMA engine. 270 * In these cases, the address is a don't-care. See the User's 271 * Guide for more information. 272 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 273 */ 274 int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); 275 276 /** 277 * @brief Get channel reload source, destination, and count for transfer 278 * 279 * @param srcdstReload Pointer to struct with the correct channel number 280 * 281 * @return See \ref MXC_Error_Codes for a list of return values 282 */ 283 int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); 284 285 /** 286 * @brief Set channel interrupt callback 287 * @param ch channel handle 288 * @param callback Pointer to a function to call when the channel 289 * interrupt flag is set and interrupts are enabled or 290 * when DMA is shutdown by the driver. 291 * @details Configures the channel interrupt callback. The @p callback 292 * function is called for two conditions: 293 * -# When the channel's interrupt flag is set and DMA interrupts 294 * are enabled. 295 * -# If the driver calls the MXC_DMA_Shutdown() function. The 296 * callback function prototype is: 297 * @code 298 * void callback_fn(int ch, int reason); 299 * @endcode 300 * @p ch indicates the channel that generated the callback, @p 301 * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN 302 * if the DMA is being shutdown. 303 * 304 * @return #E_BAD_PARAM if an unused or invalid channel handle, 305 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 306 */ 307 int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); 308 309 /** 310 * @brief Set channel interrupt 311 * @note Each channel has two interrupts (complete, and count to zero). 312 * To enable complete, pass true for chdis. To enable count to zero, 313 * pass true for ctz. 314 * @param ch Channel Handle 315 * @param chdis Enable channel complete interrupt 316 * @param ctz Enable channel count to zero interrupt. 317 * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise 318 */ 319 int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); 320 321 /** 322 * @brief Enable channel interrupt 323 * @note Each channel has two interrupts (complete, and count to zero) 324 which must also be enabled with MXC_DMA_SetChannelInterruptEn() 325 * @param ch channel handle 326 * @param flags The flags to enable 327 * @return #E_BAD_PARAM if an unused or invalid channel handle, 328 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 329 */ 330 int MXC_DMA_ChannelEnableInt(int ch, int flags); 331 332 /** 333 * @brief Disable channel interrupt 334 * @param ch channel handle 335 * @param flags The flags to disable 336 * @return #E_BAD_PARAM if an unused or invalid channel handle, 337 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 338 */ 339 int MXC_DMA_ChannelDisableInt(int ch, int flags); 340 341 /** 342 * @brief Read channel interrupt flags 343 * @param ch channel handle 344 * @return #E_BAD_PARAM if an unused or invalid channel handle, 345 * flags otherwise, \ref MXC_Error_Codes 346 */ 347 int MXC_DMA_ChannelGetFlags(int ch); 348 349 /** 350 * @brief Clear channel interrupt flags 351 * @param ch channel handle 352 * @param flags The flags to clear 353 * @return #E_BAD_PARAM if an unused or invalid channel handle, 354 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 355 */ 356 int MXC_DMA_ChannelClearFlags(int ch, int flags); 357 358 /** 359 * @brief Enable channel interrupt 360 * @note Each channel has two interrupts (complete, and count to zero) 361 which must also be enabled with MXC_DMA_SetChannelInterruptEn() 362 * @param ch channel handle 363 * @return #E_BAD_PARAM if an unused or invalid channel handle, 364 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 365 */ 366 int MXC_DMA_EnableInt(int ch); 367 368 /** 369 * @brief Disable channel interrupt 370 * @param ch channel handle 371 * @return #E_BAD_PARAM if an unused or invalid channel handle, 372 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 373 */ 374 int MXC_DMA_DisableInt(int ch); 375 376 /** 377 * @brief Start transfer 378 * @param ch channel handle 379 * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. 380 * @return #E_BAD_PARAM if an unused or invalid channel handle, 381 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 382 */ 383 int MXC_DMA_Start(int ch); 384 385 /** 386 * @brief Stop DMA transfer, irrespective of status (complete or in-progress) 387 * @param ch channel handle 388 * @return #E_BAD_PARAM if an unused or invalid channel handle, 389 * #E_NO_ERROR otherwise, \ref MXC_Error_Codes 390 */ 391 int MXC_DMA_Stop(int ch); 392 393 /** 394 * @brief Get a pointer to the DMA channel registers 395 * @param ch channel handle 396 * @details If direct access to DMA channel registers is required, this 397 * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). 398 * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise 399 */ 400 mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); 401 402 /** 403 * @brief Interrupt handler function 404 * @details Call this function as the ISR for each DMA channel under driver control. 405 * Interrupt flags for channel ch will be automatically cleared before return. 406 */ 407 void MXC_DMA_Handler(void); 408 409 /*************************/ 410 /* High Level Functions */ 411 /*************************/ 412 413 /** 414 * @brief Performs a memcpy, using DMA, optionally asynchronous 415 * @note The user must have the DMA interrupt enabled and call 416 * MXC_DMA_Handler() from the ISR. 417 * 418 * @param dest pointer to destination memory 419 * @param src pointer to source memory 420 * @param len number of bytes to copy 421 * @param callback function to call when transfer is complete 422 * 423 * @return see \ref MXC_Error_Codes 424 */ 425 int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); 426 427 /** 428 * @brief Performs a memcpy, using DMA, optionally asynchronous 429 * @note The user must have the DMA interrupt enabled and call 430 * MXC_DMA_Handler() from the ISR. 431 * 432 * @param config The channel config struct 433 * @param firstSrcDst The source, destination, and count for the first transfer 434 * @param callback function is called when transfer is complete 435 * 436 * @return see \ref MXC_Error_Codes 437 */ 438 int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, 439 mxc_dma_trans_chain_t callback); 440 /** 441 * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver 442 */ 443 444 /**@} end of group dma */ 445 #ifdef __cplusplus 446 } 447 #endif 448 449 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78002_DMA_H_ 450
