1<?xml version='1.0' encoding='utf-8'?>
2<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xsi:noNamespaceSchemaLocation="svd_schema.xsd">
3 <vendor>Maxim-Integrated</vendor>
4 <vendorID>Maxim</vendorID>
5 <name>max78002</name>
6 <series>ARMCM4</series>
7 <version>1.0</version>
8 <description>MAX78002 Machine Learning System-on-Chip.</description>
9 <cpu>
10  <name>CM4</name>
11  <revision>r2p1</revision>
12  <endian>little</endian>
13  <mpuPresent>true</mpuPresent>
14  <fpuPresent>true</fpuPresent>
15  <nvicPrioBits>3</nvicPrioBits>
16  <vendorSystickConfig>false</vendorSystickConfig>
17 </cpu>
18 <addressUnitBits>8</addressUnitBits>
19 <width>32</width>
20 <size>0x20</size>
21 <access>read-write</access>
22 <resetValue>0x00000000</resetValue>
23 <resetMask>0xFFFFFFFF</resetMask>
24 <peripherals>
25  <peripheral>
26   <name>ADC</name>
27   <description>Inter-Integrated Circuit.</description>
28   <groupName>ADC</groupName>
29   <baseAddress>0x40034000</baseAddress>
30   <size>32</size>
31   <addressBlock>
32    <offset>0x00</offset>
33    <size>0x1000</size>
34    <usage>registers</usage>
35   </addressBlock>
36   <interrupt>
37    <name>ADC</name>
38    <description>ADC IRQ</description>
39    <value>20</value>
40   </interrupt>
41   <registers>
42    <register>
43     <name>CTRL0</name>
44     <description>Control Register 0.</description>
45     <addressOffset>0x00</addressOffset>
46     <fields>
47      <field>
48       <name>ADC_EN</name>
49       <description>ADC Enable.</description>
50       <bitRange>[0:0]</bitRange>
51       <access>read-write</access>
52       <enumeratedValues>
53        <enumeratedValue>
54         <name>dis</name>
55         <description>Disable ADC.</description>
56         <value>0</value>
57        </enumeratedValue>
58        <enumeratedValue>
59         <name>en</name>
60         <description>enable ADC.</description>
61         <value>1</value>
62        </enumeratedValue>
63       </enumeratedValues>
64      </field>
65      <field>
66       <name>BIAS_EN</name>
67       <description>Bias Enable.</description>
68       <bitRange>[1:1]</bitRange>
69       <access>read-write</access>
70       <enumeratedValues>
71        <enumeratedValue>
72         <name>dis</name>
73         <description>Disable Bias.</description>
74         <value>0</value>
75        </enumeratedValue>
76        <enumeratedValue>
77         <name>en</name>
78         <description>Enable Bias.</description>
79         <value>1</value>
80        </enumeratedValue>
81       </enumeratedValues>
82      </field>
83      <field>
84       <name>SKIP_CAL</name>
85       <description>Skip Calibration Enable.</description>
86       <bitRange>[2:2]</bitRange>
87       <access>read-write</access>
88       <enumeratedValues>
89        <enumeratedValue>
90         <name>no_skip</name>
91         <description>Do not skip calibration.</description>
92         <value>0</value>
93        </enumeratedValue>
94        <enumeratedValue>
95         <name>skip</name>
96         <description>Skip calibration.</description>
97         <value>1</value>
98        </enumeratedValue>
99       </enumeratedValues>
100      </field>
101      <field>
102       <name>CHOP_FORCE</name>
103       <description>Chop Force Control.</description>
104       <bitRange>[3:3]</bitRange>
105       <access>read-write</access>
106       <enumeratedValues>
107        <enumeratedValue>
108         <name>dis</name>
109         <description>Do not force chop mode.</description>
110         <value>0</value>
111        </enumeratedValue>
112        <enumeratedValue>
113         <name>en</name>
114         <description>Force chop Mode.</description>
115         <value>1</value>
116        </enumeratedValue>
117       </enumeratedValues>
118      </field>
119      <field>
120       <name>RESETB</name>
121       <description>Reset ADC.</description>
122       <bitRange>[4:4]</bitRange>
123       <access>read-write</access>
124       <enumeratedValues>
125        <enumeratedValue>
126         <name>reset</name>
127         <description>reset ADC.</description>
128         <value>0</value>
129        </enumeratedValue>
130        <enumeratedValue>
131         <name>activate</name>
132         <description>activate ADC.</description>
133         <value>1</value>
134        </enumeratedValue>
135       </enumeratedValues>
136      </field>
137     </fields>
138    </register>
139    <register>
140     <name>CTRL1</name>
141     <description>Control Register 1.</description>
142     <addressOffset>0x04</addressOffset>
143     <fields>
144      <field>
145       <name>START</name>
146       <description>Start conversion control.</description>
147       <bitRange>[0:0]</bitRange>
148       <access>read-write</access>
149       <enumeratedValues>
150        <enumeratedValue>
151         <name>stop</name>
152         <description>Stop conversions.</description>
153         <value>0</value>
154        </enumeratedValue>
155        <enumeratedValue>
156         <name>start</name>
157         <description>Start conversions.</description>
158         <value>1</value>
159        </enumeratedValue>
160       </enumeratedValues>
161      </field>
162      <field>
163       <name>TRIG_MODE</name>
164       <description>Trigger mode control.</description>
165       <bitRange>[1:1]</bitRange>
166       <access>read-write</access>
167       <enumeratedValues>
168        <enumeratedValue>
169         <name>software</name>
170         <description>software trigger mode.</description>
171         <value>0</value>
172        </enumeratedValue>
173        <enumeratedValue>
174         <name>hardware</name>
175         <description>hardware trigger mode.</description>
176         <value>1</value>
177        </enumeratedValue>
178       </enumeratedValues>
179      </field>
180      <field>
181       <name>CNV_MODE</name>
182       <description>Conversion mode control.</description>
183       <bitRange>[2:2]</bitRange>
184       <access>read-write</access>
185       <enumeratedValues>
186        <enumeratedValue>
187         <name>atomic</name>
188         <description>Do one conversion sequence.</description>
189         <value>0</value>
190        </enumeratedValue>
191        <enumeratedValue>
192         <name>continuous</name>
193         <description>Do continuous conversion sequences.</description>
194         <value>1</value>
195        </enumeratedValue>
196       </enumeratedValues>
197      </field>
198      <field>
199       <name>SAMP_CK_OFF</name>
200       <description>Sample clock off control.</description>
201       <bitRange>[3:3]</bitRange>
202       <access>read-write</access>
203       <enumeratedValues>
204        <enumeratedValue>
205         <name>always</name>
206         <description>Sample clock always generated.</description>
207         <value>0</value>
208        </enumeratedValue>
209        <enumeratedValue>
210         <name>cnv_only</name>
211         <description>Sample clock generated only when converting.</description>
212         <value>1</value>
213        </enumeratedValue>
214       </enumeratedValues>
215      </field>
216      <field>
217       <name>TRIG_SEL</name>
218       <description>Hardware trigger source select.</description>
219       <bitRange>[6:4]</bitRange>
220       <access>read-write</access>
221      </field>
222      <field>
223       <name>TS_SEL</name>
224       <description>Temp sensor select.</description>
225       <bitRange>[7:7]</bitRange>
226       <access>read-write</access>
227       <enumeratedValues>
228        <enumeratedValue>
229         <name>dis</name>
230         <description>Temp sensor is not one of the slots in the sequence.</description>
231         <value>0</value>
232        </enumeratedValue>
233        <enumeratedValue>
234         <name>en</name>
235         <description>Temp sensor is one of the slots in the sequence.</description>
236         <value>1</value>
237        </enumeratedValue>
238       </enumeratedValues>
239      </field>
240      <field>
241       <name>AVG</name>
242       <description>Number of samples to average for each output data code.</description>
243       <bitRange>[10:8]</bitRange>
244       <access>read-write</access>
245       <enumeratedValues>
246        <enumeratedValue>
247         <name>avg1</name>
248         <description>1 Sample per output code.</description>
249         <value>0</value>
250        </enumeratedValue>
251        <enumeratedValue>
252         <name>avg2</name>
253         <description>2 Samples per output code.</description>
254         <value>1</value>
255        </enumeratedValue>
256        <enumeratedValue>
257         <name>avg4</name>
258         <description>4 Samples per output code.</description>
259         <value>2</value>
260        </enumeratedValue>
261        <enumeratedValue>
262         <name>avg8</name>
263         <description>8 Samples per output code.</description>
264         <value>3</value>
265        </enumeratedValue>
266        <enumeratedValue>
267         <name>avg16</name>
268         <description>16 Samples per output code.</description>
269         <value>4</value>
270        </enumeratedValue>
271        <enumeratedValue>
272         <name>avg32</name>
273         <description>32 Samples per output code.</description>
274         <value>5</value>
275        </enumeratedValue>
276       </enumeratedValues>
277      </field>
278      <field>
279       <name>NUM_SLOTS</name>
280       <description>Number of slots enabled for the conversion sequence</description>
281       <bitRange>[20:16]</bitRange>
282       <access>read-write</access>
283      </field>
284     </fields>
285    </register>
286    <register>
287     <name>CLKCTRL</name>
288     <description>Clock Control Register.</description>
289     <addressOffset>0x08</addressOffset>
290     <fields>
291      <field>
292       <name>CLKSEL</name>
293       <description>Clock source select.</description>
294       <bitRange>[1:0]</bitRange>
295       <access>read-write</access>
296       <enumeratedValues>
297        <enumeratedValue>
298         <name>HCLK</name>
299         <description>Select HCLK.</description>
300         <value>0</value>
301        </enumeratedValue>
302        <enumeratedValue>
303         <name>CLK_ADC0</name>
304         <description>Select CLK_ADC0.</description>
305         <value>1</value>
306        </enumeratedValue>
307        <enumeratedValue>
308         <name>CLK_ADC1</name>
309         <description>Select CLK_ADC1.</description>
310         <value>2</value>
311        </enumeratedValue>
312        <enumeratedValue>
313         <name>CLK_ADC2</name>
314         <description>Select CLK_ADC2.</description>
315         <value>3</value>
316        </enumeratedValue>
317       </enumeratedValues>
318      </field>
319      <field>
320       <name>CLKDIV</name>
321       <description>Clock divider control.</description>
322       <bitRange>[6:4]</bitRange>
323       <access>read-write</access>
324       <enumeratedValues>
325        <enumeratedValue>
326         <name>DIV2</name>
327         <description>Divide by 2.</description>
328         <value>0</value>
329        </enumeratedValue>
330        <enumeratedValue>
331         <name>DIV4</name>
332         <description>Divide by 4.</description>
333         <value>1</value>
334        </enumeratedValue>
335        <enumeratedValue>
336         <name>DIV8</name>
337         <description>Divide by 8.</description>
338         <value>2</value>
339        </enumeratedValue>
340        <enumeratedValue>
341         <name>DIV16</name>
342         <description>Divide by 16.</description>
343         <value>3</value>
344        </enumeratedValue>
345        <enumeratedValue>
346         <name>DIV1</name>
347         <description>Divide by 1.</description>
348         <value>4</value>
349        </enumeratedValue>
350       </enumeratedValues>
351      </field>
352     </fields>
353    </register>
354    <register>
355     <name>SAMPCLKCTRL</name>
356     <description>Sample Clock Control Register.</description>
357     <addressOffset>0x0C</addressOffset>
358     <access>read-write</access>
359     <fields>
360      <field>
361       <name>TRACK_CNT</name>
362       <description>Number of cycles for SAMPLE_CLK high time.</description>
363       <bitRange>[7:0]</bitRange>
364       <access>read-write</access>
365      </field>
366      <field>
367       <name>IDLE_CNT</name>
368       <description>Number of cycles for SAMPLE_CLK low time.</description>
369       <bitRange>[31:16]</bitRange>
370       <access>read-write</access>
371      </field>
372     </fields>
373    </register>
374    <register>
375     <name>CHSEL0</name>
376     <description>Channel Select Register 0.</description>
377     <addressOffset>0x10</addressOffset>
378     <fields>
379      <field>
380       <name>slot0_id</name>
381       <description>channel assignment for slot 0.</description>
382       <bitRange>[4:0]</bitRange>
383       <access>read-write</access>
384      </field>
385      <field>
386       <name>slot1_id</name>
387       <description>channel assignment for slot 1.</description>
388       <bitRange>[12:8]</bitRange>
389       <access>read-write</access>
390      </field>
391      <field>
392       <name>slot2_id</name>
393       <description>channel assignment for slot 2.</description>
394       <bitRange>[20:16]</bitRange>
395       <access>read-write</access>
396      </field>
397      <field>
398       <name>slot3_id</name>
399       <description>channel assignment for slot 3.</description>
400       <bitRange>[28:24]</bitRange>
401       <access>read-write</access>
402      </field>
403     </fields>
404    </register>
405    <register>
406     <name>CHSEL1</name>
407     <description>Channel Select Register 1.</description>
408     <addressOffset>0x14</addressOffset>
409     <fields>
410      <field>
411       <name>slot4_id</name>
412       <description>channel assignment for slot 4.</description>
413       <bitRange>[4:0]</bitRange>
414       <access>read-write</access>
415      </field>
416      <field>
417       <name>slot5_id</name>
418       <description>channel assignment for slot 5.</description>
419       <bitRange>[12:8]</bitRange>
420       <access>read-write</access>
421      </field>
422      <field>
423       <name>slot6_id</name>
424       <description>channel assignment for slot 6.</description>
425       <bitRange>[20:16]</bitRange>
426       <access>read-write</access>
427      </field>
428      <field>
429       <name>slot7_id</name>
430       <description>channel assignment for slot 7.</description>
431       <bitRange>[28:24]</bitRange>
432       <access>read-write</access>
433      </field>
434     </fields>
435    </register>
436    <register>
437     <name>CHSEL2</name>
438     <description>Channel Select Register 2.</description>
439     <addressOffset>0x18</addressOffset>
440     <fields>
441      <field>
442       <name>slot8_id</name>
443       <description>channel assignment for slot 8.</description>
444       <bitRange>[4:0]</bitRange>
445       <access>read-write</access>
446      </field>
447      <field>
448       <name>slot9_id</name>
449       <description>channel assignment for slot 9.</description>
450       <bitRange>[12:8]</bitRange>
451       <access>read-write</access>
452      </field>
453      <field>
454       <name>slot10_id</name>
455       <description>channel assignment for slot 10.</description>
456       <bitRange>[20:16]</bitRange>
457       <access>read-write</access>
458      </field>
459      <field>
460       <name>slot11_id</name>
461       <description>channel assignment for slot 11.</description>
462       <bitRange>[28:24]</bitRange>
463       <access>read-write</access>
464      </field>
465     </fields>
466    </register>
467    <register>
468     <name>CHSEL3</name>
469     <description>Channel Select Register 3.</description>
470     <addressOffset>0x1C</addressOffset>
471     <fields>
472      <field>
473       <name>slot12_id</name>
474       <description>channel assignment for slot 12.</description>
475       <bitRange>[4:0]</bitRange>
476       <access>read-write</access>
477      </field>
478      <field>
479       <name>slot13_id</name>
480       <description>channel assignment for slot 13.</description>
481       <bitRange>[12:8]</bitRange>
482       <access>read-write</access>
483      </field>
484      <field>
485       <name>slot14_id</name>
486       <description>channel assignment for slot 14.</description>
487       <bitRange>[20:16]</bitRange>
488       <access>read-write</access>
489      </field>
490      <field>
491       <name>slot15_id</name>
492       <description>channel assignment for slot 15.</description>
493       <bitRange>[28:24]</bitRange>
494       <access>read-write</access>
495      </field>
496     </fields>
497    </register>
498    <register>
499     <name>CHSEL4</name>
500     <description>Channel Select Register 4.</description>
501     <addressOffset>0x20</addressOffset>
502     <fields>
503      <field>
504       <name>slot16_id</name>
505       <description>channel assignment for slot 16.</description>
506       <bitRange>[4:0]</bitRange>
507       <access>read-write</access>
508      </field>
509      <field>
510       <name>slot17_id</name>
511       <description>channel assignment for slot 17.</description>
512       <bitRange>[12:8]</bitRange>
513       <access>read-write</access>
514      </field>
515      <field>
516       <name>slot18_id</name>
517       <description>channel assignment for slot 18.</description>
518       <bitRange>[20:16]</bitRange>
519       <access>read-write</access>
520      </field>
521      <field>
522       <name>slot19_id</name>
523       <description>channel assignment for slot 19.</description>
524       <bitRange>[28:24]</bitRange>
525       <access>read-write</access>
526      </field>
527     </fields>
528    </register>
529    <register>
530     <name>CHSEL5</name>
531     <description>Channel Select Register 5.</description>
532     <addressOffset>0x24</addressOffset>
533     <fields>
534      <field>
535       <name>slot20_id</name>
536       <description>channel assignment for slot 20.</description>
537       <bitRange>[4:0]</bitRange>
538       <access>read-write</access>
539      </field>
540      <field>
541       <name>slot21_id</name>
542       <description>channel assignment for slot 21.</description>
543       <bitRange>[12:8]</bitRange>
544       <access>read-write</access>
545      </field>
546      <field>
547       <name>slot22_id</name>
548       <description>channel assignment for slot 22.</description>
549       <bitRange>[20:16]</bitRange>
550       <access>read-write</access>
551      </field>
552      <field>
553       <name>slot23_id</name>
554       <description>channel assignment for slot 23.</description>
555       <bitRange>[28:24]</bitRange>
556       <access>read-write</access>
557      </field>
558     </fields>
559    </register>
560    <register>
561     <name>CHSEL6</name>
562     <description>Channel Select Register 6.</description>
563     <addressOffset>0x28</addressOffset>
564     <fields>
565      <field>
566       <name>slot24_id</name>
567       <description>channel assignment for slot 24.</description>
568       <bitRange>[4:0]</bitRange>
569       <access>read-write</access>
570      </field>
571      <field>
572       <name>slot25_id</name>
573       <description>channel assignment for slot 25.</description>
574       <bitRange>[12:8]</bitRange>
575       <access>read-write</access>
576      </field>
577      <field>
578       <name>slot26_id</name>
579       <description>channel assignment for slot 26.</description>
580       <bitRange>[20:16]</bitRange>
581       <access>read-write</access>
582      </field>
583      <field>
584       <name>slot27_id</name>
585       <description>channel assignment for slot 27.</description>
586       <bitRange>[28:24]</bitRange>
587       <access>read-write</access>
588      </field>
589     </fields>
590    </register>
591    <register>
592     <name>CHSEL7</name>
593     <description>Channel Select Register 7.</description>
594     <addressOffset>0x2C</addressOffset>
595     <fields>
596      <field>
597       <name>slot28_id</name>
598       <description>channel assignment for slot 28.</description>
599       <bitRange>[4:0]</bitRange>
600       <access>read-write</access>
601      </field>
602      <field>
603       <name>slot29_id</name>
604       <description>channel assignment for slot 29.</description>
605       <bitRange>[12:8]</bitRange>
606       <access>read-write</access>
607      </field>
608      <field>
609       <name>slot30_id</name>
610       <description>channel assignment for slot 30.</description>
611       <bitRange>[20:16]</bitRange>
612       <access>read-write</access>
613      </field>
614      <field>
615       <name>slot31_id</name>
616       <description>channel assignment for slot 31.</description>
617       <bitRange>[28:24]</bitRange>
618       <access>read-write</access>
619      </field>
620     </fields>
621    </register>
622    <register>
623     <name>RESTART</name>
624     <description>Restart Count Control Register</description>
625     <addressOffset>0x30</addressOffset>
626     <fields>
627      <field>
628       <name>CNT</name>
629       <description>Number of sample periods to skip before restarting a continuous mode sequence</description>
630       <bitRange>[15:0]</bitRange>
631       <access>read-write</access>
632      </field>
633     </fields>
634    </register>
635    <register>
636     <name>DATAFMT</name>
637     <description>Channel Data Format Register</description>
638     <addressOffset>0x3C</addressOffset>
639     <fields>
640      <field>
641       <name>MODE</name>
642       <description>Data format control</description>
643       <bitRange>[31:0]</bitRange>
644       <access>read-write</access>
645      </field>
646     </fields>
647    </register>
648    <register>
649     <name>FIFODMACTRL</name>
650     <description>FIFO and DMA control</description>
651     <addressOffset>0x40</addressOffset>
652     <fields>
653      <field>
654       <name>DMA_EN</name>
655       <description>DMA Enable.</description>
656       <bitRange>[0:0]</bitRange>
657       <access>read-write</access>
658       <enumeratedValues>
659        <enumeratedValue>
660         <name>dis</name>
661         <description>Disable DMA.</description>
662         <value>0</value>
663        </enumeratedValue>
664        <enumeratedValue>
665         <name>en</name>
666         <description>Enable DMA.</description>
667         <value>1</value>
668        </enumeratedValue>
669       </enumeratedValues>
670      </field>
671      <field>
672       <name>FLUSH</name>
673       <description>FIFO Flush.</description>
674       <bitRange>[1:1]</bitRange>
675       <access>read-write</access>
676       <enumeratedValues>
677        <enumeratedValue>
678         <name>normal</name>
679         <description>Normal FIFO operation.</description>
680         <value>0</value>
681        </enumeratedValue>
682        <enumeratedValue>
683         <name>flush</name>
684         <description>Flush FIFO.</description>
685         <value>1</value>
686        </enumeratedValue>
687       </enumeratedValues>
688      </field>
689      <field>
690       <name>DATA_FORMAT</name>
691       <description>DATA format control.</description>
692       <bitRange>[3:2]</bitRange>
693       <access>read-write</access>
694       <enumeratedValues>
695        <enumeratedValue>
696         <name>data_status</name>
697         <description>Data and Status in FIFO.</description>
698         <value>0</value>
699        </enumeratedValue>
700        <enumeratedValue>
701         <name>data_only</name>
702         <description>Only Data in FIFO.</description>
703         <value>1</value>
704        </enumeratedValue>
705        <enumeratedValue>
706         <name>raw_data_only</name>
707         <description>Only Raw Data in FIFO.</description>
708         <value>2</value>
709        </enumeratedValue>
710       </enumeratedValues>
711      </field>
712      <field>
713       <name>THRESH</name>
714       <description>FIFO Threshold. These bits define the FIFO interrupt threshold.</description>
715       <bitRange>[15:8]</bitRange>
716       <access>read-write</access>
717      </field>
718     </fields>
719    </register>
720    <register>
721     <name>DATA</name>
722     <description>Data Register (FIFO).</description>
723     <addressOffset>0x44</addressOffset>
724     <fields>
725      <field>
726       <name>DATA</name>
727       <description>Conversion data.</description>
728       <bitRange>[15:0]</bitRange>
729       <access>read-only</access>
730      </field>
731      <field>
732       <name>CHAN</name>
733       <description>Channel for the data.</description>
734       <bitRange>[20:16]</bitRange>
735       <access>read-only</access>
736      </field>
737      <field>
738       <name>INVALID</name>
739       <description>Invalid status for the data.</description>
740       <bitRange>[24:24]</bitRange>
741       <access>read-only</access>
742      </field>
743      <field>
744       <name>CLIPPED</name>
745       <description>Clipped status for the data.</description>
746       <bitRange>[31:31]</bitRange>
747       <access>read-only</access>
748      </field>
749     </fields>
750    </register>
751    <register>
752     <name>STATUS</name>
753     <description>Status Register</description>
754     <addressOffset>0x48</addressOffset>
755     <fields>
756      <field>
757       <name>READY</name>
758       <description>Indication that the ADC is in ON power state</description>
759       <bitRange>[0:0]</bitRange>
760       <access>read-only</access>
761      </field>
762      <field>
763       <name>EMPTY</name>
764       <description>FIFO Empty</description>
765       <bitRange>[1:1]</bitRange>
766       <access>read-only</access>
767      </field>
768      <field>
769       <name>FULL</name>
770       <description>FIFO full</description>
771       <bitRange>[2:2]</bitRange>
772       <access>read-only</access>
773      </field>
774      <field>
775       <name>FIFO_LEVEL</name>
776       <description>Number of entries in FIFO available to read</description>
777       <bitRange>[15:8]</bitRange>
778       <access>read-only</access>
779      </field>
780     </fields>
781    </register>
782    <register>
783     <name>CHSTATUS</name>
784     <description>Channel Status</description>
785     <addressOffset>0x4C</addressOffset>
786     <fields>
787      <field>
788       <name>CLIPPED</name>
789       <description />
790       <bitRange>[31:0]</bitRange>
791       <access>read-write</access>
792      </field>
793     </fields>
794    </register>
795    <register>
796     <name>INTEN</name>
797     <description>Interrupt Enable Register.</description>
798     <addressOffset>0x50</addressOffset>
799     <fields>
800      <field>
801       <name>READY</name>
802       <description>ADC is ready.</description>
803       <bitRange>[0:0]</bitRange>
804       <access>read-write</access>
805      </field>
806      <field>
807       <name>ABORT</name>
808       <description>Conversion start is aborted.</description>
809       <bitRange>[2:2]</bitRange>
810       <access>read-write</access>
811      </field>
812      <field>
813       <name>START_DET</name>
814       <description>Conversion start is detected.</description>
815       <bitRange>[3:3]</bitRange>
816       <access>read-write</access>
817      </field>
818      <field>
819       <name>SEQ_STARTED</name>
820       <bitRange>[4:4]</bitRange>
821       <access>read-write</access>
822      </field>
823      <field>
824       <name>SEQ_DONE</name>
825       <bitRange>[5:5]</bitRange>
826       <access>read-write</access>
827      </field>
828      <field>
829       <name>CONV_DONE</name>
830       <bitRange>[6:6]</bitRange>
831       <access>read-write</access>
832      </field>
833      <field>
834       <name>CLIPPED</name>
835       <bitRange>[7:7]</bitRange>
836       <access>read-write</access>
837      </field>
838      <field>
839       <name>FIFO_LVL</name>
840       <bitRange>[8:8]</bitRange>
841       <access>read-write</access>
842      </field>
843      <field>
844       <name>FIFO_UFL</name>
845       <bitRange>[9:9]</bitRange>
846       <access>read-write</access>
847      </field>
848      <field>
849       <name>FIFO_OFL</name>
850       <bitRange>[10:10]</bitRange>
851       <access>read-write</access>
852      </field>
853     </fields>
854    </register>
855    <register>
856     <name>INTFL</name>
857     <description>Interrupt Flags Register.</description>
858     <addressOffset>0x54</addressOffset>
859     <fields>
860      <field>
861       <name>READY</name>
862       <description>ADC is ready.</description>
863       <bitRange>[0:0]</bitRange>
864       <access>read-write</access>
865       <modifiedWriteValues>oneToClear</modifiedWriteValues>
866      </field>
867      <field>
868       <name>ABORT</name>
869       <description>Conversion start is aborted.</description>
870       <bitRange>[2:2]</bitRange>
871       <access>read-write</access>
872       <modifiedWriteValues>oneToClear</modifiedWriteValues>
873      </field>
874      <field>
875       <name>START_DET</name>
876       <description>Conversion start is detected.</description>
877       <bitRange>[3:3]</bitRange>
878       <access>read-write</access>
879       <modifiedWriteValues>oneToClear</modifiedWriteValues>
880      </field>
881      <field>
882       <name>SEQ_STARTED</name>
883       <bitRange>[4:4]</bitRange>
884       <access>read-write</access>
885       <modifiedWriteValues>oneToClear</modifiedWriteValues>
886      </field>
887      <field>
888       <name>SEQ_DONE</name>
889       <bitRange>[5:5]</bitRange>
890       <access>read-write</access>
891       <modifiedWriteValues>oneToClear</modifiedWriteValues>
892      </field>
893      <field>
894       <name>CONV_DONE</name>
895       <bitRange>[6:6]</bitRange>
896       <access>read-write</access>
897       <modifiedWriteValues>oneToClear</modifiedWriteValues>
898      </field>
899      <field>
900       <name>CLIPPED</name>
901       <bitRange>[7:7]</bitRange>
902       <access>read-write</access>
903       <modifiedWriteValues>oneToClear</modifiedWriteValues>
904      </field>
905      <field>
906       <name>FIFO_LVL</name>
907       <bitRange>[8:8]</bitRange>
908       <access>read-write</access>
909       <modifiedWriteValues>oneToClear</modifiedWriteValues>
910      </field>
911      <field>
912       <name>FIFO_UFL</name>
913       <bitRange>[9:9]</bitRange>
914       <access>read-write</access>
915       <modifiedWriteValues>oneToClear</modifiedWriteValues>
916      </field>
917      <field>
918       <name>FIFO_OFL</name>
919       <bitRange>[10:10]</bitRange>
920       <access>read-write</access>
921       <modifiedWriteValues>oneToClear</modifiedWriteValues>
922      </field>
923     </fields>
924    </register>
925    <register>
926     <name>SFRADDROFFSET</name>
927     <description>SFR Address Offset Register</description>
928     <addressOffset>0x60</addressOffset>
929     <fields>
930      <field>
931       <name>OFFSET</name>
932       <description>Address Offset for SAR Digital</description>
933       <bitRange>[7:0]</bitRange>
934       <access>read-write</access>
935      </field>
936     </fields>
937    </register>
938    <register>
939     <name>SFRADDR</name>
940     <description>SFR Address Register</description>
941     <addressOffset>0x64</addressOffset>
942     <fields>
943      <field>
944       <name>ADDR</name>
945       <description>Address to SAR Digital</description>
946       <bitRange>[7:0]</bitRange>
947       <access>read-write</access>
948      </field>
949     </fields>
950    </register>
951    <register>
952     <name>SFRWRDATA</name>
953     <description>SFR Write Data Register</description>
954     <addressOffset>0x68</addressOffset>
955     <fields>
956      <field>
957       <name>DATA</name>
958       <description>DATA to SAR Digital</description>
959       <bitRange>[7:0]</bitRange>
960       <access>read-write</access>
961      </field>
962     </fields>
963    </register>
964    <register>
965     <name>SFRRDDATA</name>
966     <description>SFR Read Data Register</description>
967     <addressOffset>0x6C</addressOffset>
968     <fields>
969      <field>
970       <name>DATA</name>
971       <description>DATA from SAR Digital</description>
972       <bitRange>[7:0]</bitRange>
973       <access>read-only</access>
974      </field>
975     </fields>
976    </register>
977    <register>
978     <name>SFRSTATUS</name>
979     <description>SFR Status Register</description>
980     <addressOffset>0x70</addressOffset>
981     <fields>
982      <field>
983       <name>NACK</name>
984       <description>NACK status for SAR Digital SFR communication</description>
985       <bitRange>[0:0]</bitRange>
986       <access>read-only</access>
987      </field>
988     </fields>
989    </register>
990   </registers>
991  </peripheral>
992<!--ADC Inter-Integrated Circuit.-->
993  <peripheral>
994   <name>AES</name>
995   <description>AES Keys.</description>
996   <baseAddress>0x40007400</baseAddress>
997   <addressBlock>
998    <offset>0x00</offset>
999    <size>0x400</size>
1000    <usage>registers</usage>
1001   </addressBlock>
1002   <registers>
1003    <register>
1004     <name>CTRL</name>
1005     <description>AES Control Register</description>
1006     <addressOffset>0x0000</addressOffset>
1007     <size>32</size>
1008     <fields>
1009      <field>
1010       <name>EN</name>
1011       <description>AES Enable</description>
1012       <bitRange>[0:0]</bitRange>
1013       <access>read-write</access>
1014      </field>
1015      <field>
1016       <name>DMA_RX_EN</name>
1017       <description>DMA Request To Read Data Output FIFO</description>
1018       <bitRange>[1:1]</bitRange>
1019       <access>read-write</access>
1020      </field>
1021      <field>
1022       <name>DMA_TX_EN</name>
1023       <description>DMA Request To Write Data Input FIFO</description>
1024       <bitRange>[2:2]</bitRange>
1025       <access>read-write</access>
1026      </field>
1027      <field>
1028       <name>START</name>
1029       <description>Start AES Calculation</description>
1030       <bitRange>[3:3]</bitRange>
1031       <access>read-write</access>
1032      </field>
1033      <field>
1034       <name>INPUT_FLUSH</name>
1035       <description>Flush the data input FIFO</description>
1036       <bitRange>[4:4]</bitRange>
1037       <access>read-write</access>
1038      </field>
1039      <field>
1040       <name>OUTPUT_FLUSH</name>
1041       <description>Flush the data output FIFO</description>
1042       <bitRange>[5:5]</bitRange>
1043       <access>read-write</access>
1044      </field>
1045      <field>
1046       <name>KEY_SIZE</name>
1047       <description>Encryption Key Size</description>
1048       <bitRange>[7:6]</bitRange>
1049       <access>read-write</access>
1050       <enumeratedValues>
1051        <enumeratedValue>
1052         <name>AES128</name>
1053         <description>128 Bits.</description>
1054         <value>0</value>
1055        </enumeratedValue>
1056        <enumeratedValue>
1057         <name>AES192</name>
1058         <description>192 Bits.</description>
1059         <value>1</value>
1060        </enumeratedValue>
1061        <enumeratedValue>
1062         <name>AES256</name>
1063         <description>256 Bits.</description>
1064         <value>2</value>
1065        </enumeratedValue>
1066       </enumeratedValues>
1067      </field>
1068      <field>
1069       <name>TYPE</name>
1070       <description>Encryption Type Selection</description>
1071       <bitRange>[9:8]</bitRange>
1072       <access>read-write</access>
1073      </field>
1074     </fields>
1075    </register>
1076    <register>
1077     <name>STATUS</name>
1078     <description>AES Status Register</description>
1079     <addressOffset>0x0004</addressOffset>
1080     <fields>
1081      <field>
1082       <name>BUSY</name>
1083       <description>AES Busy Status</description>
1084       <bitRange>[0:0]</bitRange>
1085       <access>read-write</access>
1086      </field>
1087      <field>
1088       <name>INPUT_EM</name>
1089       <description>Data input FIFO empty status</description>
1090       <bitRange>[1:1]</bitRange>
1091       <access>read-write</access>
1092      </field>
1093      <field>
1094       <name>INPUT_FULL</name>
1095       <description>Data input FIFO full status</description>
1096       <bitRange>[2:2]</bitRange>
1097       <access>read-write</access>
1098      </field>
1099      <field>
1100       <name>OUTPUT_EM</name>
1101       <description>Data output FIFO empty status</description>
1102       <bitRange>[3:3]</bitRange>
1103       <access>read-write</access>
1104      </field>
1105      <field>
1106       <name>OUTPUT_FULL</name>
1107       <description>Data output FIFO full status</description>
1108       <bitRange>[4:4]</bitRange>
1109       <access>read-write</access>
1110      </field>
1111     </fields>
1112    </register>
1113    <register>
1114     <name>INTFL</name>
1115     <description>AES Interrupt Flag Register</description>
1116     <addressOffset>0x0008</addressOffset>
1117     <fields>
1118      <field>
1119       <name>DONE</name>
1120       <description>AES Done Interrupt</description>
1121       <bitRange>[0:0]</bitRange>
1122       <access>read-write</access>
1123      </field>
1124      <field>
1125       <name>KEY_CHANGE</name>
1126       <description>External AES Key Changed Interrupt</description>
1127       <bitRange>[1:1]</bitRange>
1128       <access>read-write</access>
1129      </field>
1130      <field>
1131       <name>KEY_ZERO</name>
1132       <description>External AES Key Zero Interrupt</description>
1133       <bitRange>[2:2]</bitRange>
1134       <access>read-write</access>
1135      </field>
1136      <field>
1137       <name>OV</name>
1138       <description>Data Output FIFO Overrun Interrupt</description>
1139       <bitRange>[3:3]</bitRange>
1140       <access>read-write</access>
1141      </field>
1142      <field>
1143       <name>KEY_ONE</name>
1144       <description>KEY_ONE</description>
1145       <bitRange>[4:4]</bitRange>
1146       <access>read-write</access>
1147      </field>
1148     </fields>
1149    </register>
1150    <register>
1151     <name>INTEN</name>
1152     <description>AES Interrupt Enable Register</description>
1153     <addressOffset>0x000C</addressOffset>
1154     <fields>
1155      <field>
1156       <name>DONE</name>
1157       <description>AES Done Interrupt Enable</description>
1158       <bitRange>[0:0]</bitRange>
1159       <access>read-write</access>
1160      </field>
1161      <field>
1162       <name>KEY_CHANGE</name>
1163       <description>External AES Key Changed Interrupt Enable</description>
1164       <bitRange>[1:1]</bitRange>
1165       <access>read-write</access>
1166      </field>
1167      <field>
1168       <name>KEY_ZERO</name>
1169       <description>External AES Key Zero Interrupt Enable</description>
1170       <bitRange>[2:2]</bitRange>
1171       <access>read-write</access>
1172      </field>
1173      <field>
1174       <name>OV</name>
1175       <description>Data Output FIFO Overrun Interrupt Enable</description>
1176       <bitRange>[3:3]</bitRange>
1177       <access>read-write</access>
1178      </field>
1179      <field>
1180       <name>KEY_ONE</name>
1181       <description>KEY_ONE</description>
1182       <bitRange>[4:4]</bitRange>
1183       <access>read-write</access>
1184      </field>
1185     </fields>
1186    </register>
1187    <register>
1188     <name>FIFO</name>
1189     <description>AES Data Register</description>
1190     <addressOffset>0x0010</addressOffset>
1191     <fields>
1192      <field>
1193       <name>DATA</name>
1194       <description>AES FIFO</description>
1195       <bitRange>[0:0]</bitRange>
1196       <access>read-write</access>
1197      </field>
1198     </fields>
1199    </register>
1200   </registers>
1201  </peripheral>
1202<!--AES AES Keys.-->
1203  <peripheral>
1204   <name>AESKEYS</name>
1205   <description>AES Key Registers.</description>
1206   <baseAddress>0x40007800</baseAddress>
1207   <addressBlock>
1208    <offset>0x00</offset>
1209    <size>0x400</size>
1210    <usage>registers</usage>
1211   </addressBlock>
1212   <registers>
1213    <register>
1214     <name>KEY0</name>
1215     <description>AES Key 0.</description>
1216     <addressOffset>0x000</addressOffset>
1217     <size>32</size>
1218    </register>
1219    <register>
1220     <name>KEY1</name>
1221     <description>AES Key 1.</description>
1222     <addressOffset>0x080</addressOffset>
1223     <size>32</size>
1224    </register>
1225    <register>
1226     <name>KEY2</name>
1227     <description>AES Key 2.</description>
1228     <addressOffset>0x100</addressOffset>
1229     <size>32</size>
1230    </register>
1231    <register>
1232     <name>KEY3</name>
1233     <description>AES Key 3.</description>
1234     <addressOffset>0x180</addressOffset>
1235     <size>32</size>
1236    </register>
1237   </registers>
1238  </peripheral>
1239<!--AESKEYS AES Key Registers.-->
1240  <peripheral>
1241   <name>CAMERAIF</name>
1242   <description>Parallel Camera Interface.</description>
1243   <baseAddress>0x4000E000</baseAddress>
1244   <size>32</size>
1245   <access>read-write</access>
1246   <addressBlock>
1247    <offset>0</offset>
1248    <size>0x1000</size>
1249    <usage>registers</usage>
1250   </addressBlock>
1251   <interrupt>
1252    <name>CameraIF</name>
1253    <value>91</value>
1254   </interrupt>
1255   <registers>
1256    <register>
1257     <name>VER</name>
1258     <description>Hardware Version.</description>
1259     <addressOffset>0x0000</addressOffset>
1260     <access>read-write</access>
1261     <fields>
1262      <field>
1263       <name>minor</name>
1264       <description>Minor Version Number.</description>
1265       <bitRange>[7:0]</bitRange>
1266       <access>read-write</access>
1267      </field>
1268      <field>
1269       <name>major</name>
1270       <description>Major Version Number.</description>
1271       <bitRange>[15:8]</bitRange>
1272       <access>read-write</access>
1273      </field>
1274     </fields>
1275    </register>
1276    <register>
1277     <name>FIFO_SIZE</name>
1278     <description>FIFO Depth.</description>
1279     <addressOffset>0x0004</addressOffset>
1280     <access>read-write</access>
1281     <fields>
1282      <field>
1283       <name>fifo_size</name>
1284       <description>FIFO size.</description>
1285       <bitRange>[7:0]</bitRange>
1286       <access>read-write</access>
1287      </field>
1288     </fields>
1289    </register>
1290    <register>
1291     <name>CTRL</name>
1292     <description>Control Register.</description>
1293     <addressOffset>0x0008</addressOffset>
1294     <access>read-write</access>
1295     <fields>
1296      <field>
1297       <name>READ_MODE</name>
1298       <description>Read Mode.</description>
1299       <bitOffset>0</bitOffset>
1300       <bitWidth>2</bitWidth>
1301       <access>read-write</access>
1302       <enumeratedValues>
1303        <enumeratedValue>
1304         <name>dis</name>
1305         <description>Camera Interface Disabled.</description>
1306         <value>0</value>
1307        </enumeratedValue>
1308        <enumeratedValue>
1309         <name>single_img</name>
1310         <description>Single Image Capture.</description>
1311         <value>1</value>
1312        </enumeratedValue>
1313        <enumeratedValue>
1314         <name>continuous</name>
1315         <description>Continuous Image Capture.</description>
1316         <value>2</value>
1317        </enumeratedValue>
1318       </enumeratedValues>
1319      </field>
1320      <field>
1321       <name>DATA_WIDTH</name>
1322       <description>Data Width.</description>
1323       <bitOffset>2</bitOffset>
1324       <bitWidth>2</bitWidth>
1325       <access>read-write</access>
1326       <enumeratedValues>
1327        <enumeratedValue>
1328         <name>8bit</name>
1329         <description>8 bit.</description>
1330         <value>0</value>
1331        </enumeratedValue>
1332        <enumeratedValue>
1333         <name>10bit</name>
1334         <description>10 bit.</description>
1335         <value>1</value>
1336        </enumeratedValue>
1337        <enumeratedValue>
1338         <name>12bit</name>
1339         <description>12 bit.</description>
1340         <value>2</value>
1341        </enumeratedValue>
1342       </enumeratedValues>
1343      </field>
1344      <field>
1345       <name>DS_TIMING_EN</name>
1346       <description>DS Timing Enable.</description>
1347       <bitOffset>4</bitOffset>
1348       <bitWidth>1</bitWidth>
1349       <access>read-write</access>
1350       <enumeratedValues>
1351        <enumeratedValue>
1352         <name>dis</name>
1353         <description>Timing from VSYNC and HSYNC.</description>
1354         <value>0</value>
1355        </enumeratedValue>
1356        <enumeratedValue>
1357         <name>en</name>
1358         <description>Timing embedded in data using SAV and EAV codes.</description>
1359         <value>1</value>
1360        </enumeratedValue>
1361       </enumeratedValues>
1362      </field>
1363      <field>
1364       <name>FIFO_THRSH</name>
1365       <description>Data FIFO Threshold.</description>
1366       <bitOffset>5</bitOffset>
1367       <bitWidth>5</bitWidth>
1368       <access>read-write</access>
1369      </field>
1370      <field>
1371       <name>RX_DMA</name>
1372       <description>DMA Enable.</description>
1373       <bitOffset>16</bitOffset>
1374       <bitWidth>1</bitWidth>
1375       <access>read-write</access>
1376       <enumeratedValues>
1377        <enumeratedValue>
1378         <name>dis</name>
1379         <description>DMA disabled.</description>
1380         <value>0</value>
1381        </enumeratedValue>
1382        <enumeratedValue>
1383         <name>en</name>
1384         <description>DMA enabled.</description>
1385         <value>1</value>
1386        </enumeratedValue>
1387       </enumeratedValues>
1388      </field>
1389      <field>
1390       <name>RX_DMA_THRSH</name>
1391       <description>DMA Threshold.</description>
1392       <bitOffset>17</bitOffset>
1393       <bitWidth>4</bitWidth>
1394       <access>read-write</access>
1395      </field>
1396      <field>
1397       <name>THREE_CH_EN</name>
1398       <description>Three-channel mode enable.</description>
1399       <bitOffset>30</bitOffset>
1400       <bitWidth>1</bitWidth>
1401       <access>read-write</access>
1402      </field>
1403      <field>
1404       <name>PCIF_SYS</name>
1405       <description>PCIF Control.</description>
1406       <bitOffset>31</bitOffset>
1407       <bitWidth>1</bitWidth>
1408       <access>read-write</access>
1409       <enumeratedValues>
1410        <enumeratedValue>
1411         <name>dis</name>
1412         <description>PCIF disabled.</description>
1413         <value>0</value>
1414        </enumeratedValue>
1415        <enumeratedValue>
1416         <name>en</name>
1417         <description>PCIF enabled.</description>
1418         <value>1</value>
1419        </enumeratedValue>
1420       </enumeratedValues>
1421      </field>
1422     </fields>
1423    </register>
1424    <register>
1425     <name>INT_EN</name>
1426     <description>Interupt Enable Register.</description>
1427     <addressOffset>0x000C</addressOffset>
1428     <access>read-write</access>
1429     <fields>
1430      <field>
1431       <name>IMG_DONE</name>
1432       <description>Image Done.</description>
1433       <bitOffset>0</bitOffset>
1434       <bitWidth>1</bitWidth>
1435       <access>read-write</access>
1436      </field>
1437      <field>
1438       <name>FIFO_FULL</name>
1439       <description>FIFO Full.</description>
1440       <bitOffset>1</bitOffset>
1441       <bitWidth>1</bitWidth>
1442       <access>read-write</access>
1443      </field>
1444      <field>
1445       <name>FIFO_THRESH</name>
1446       <description>FIFO Threshold Level Met.</description>
1447       <bitOffset>2</bitOffset>
1448       <bitWidth>1</bitWidth>
1449       <access>read-write</access>
1450      </field>
1451      <field>
1452       <name>FIFO_NOT_EMPTY</name>
1453       <description>FIFO Not Empty.</description>
1454       <bitOffset>3</bitOffset>
1455       <bitWidth>1</bitWidth>
1456       <access>read-write</access>
1457      </field>
1458     </fields>
1459    </register>
1460    <register>
1461     <name>INT_FL</name>
1462     <description>Interupt Flag Register.</description>
1463     <addressOffset>0x0010</addressOffset>
1464     <access>read-write</access>
1465     <fields>
1466      <field>
1467       <name>IMG_DONE</name>
1468       <description>Image Done.</description>
1469       <bitOffset>0</bitOffset>
1470       <bitWidth>1</bitWidth>
1471       <access>read-write</access>
1472      </field>
1473      <field>
1474       <name>FIFO_FULL</name>
1475       <description>FIFO Full.</description>
1476       <bitOffset>1</bitOffset>
1477       <bitWidth>1</bitWidth>
1478       <access>read-write</access>
1479      </field>
1480      <field>
1481       <name>FIFO_THRESH</name>
1482       <description>FIFO Threshold Level Met.</description>
1483       <bitOffset>2</bitOffset>
1484       <bitWidth>1</bitWidth>
1485       <access>read-write</access>
1486      </field>
1487      <field>
1488       <name>FIFO_NOT_EMPTY</name>
1489       <description>FIFO Not Empty.</description>
1490       <bitOffset>3</bitOffset>
1491       <bitWidth>1</bitWidth>
1492       <access>read-write</access>
1493      </field>
1494     </fields>
1495    </register>
1496    <register>
1497     <name>DS_TIMING_CODES</name>
1498     <description>DS Timing Code Register.</description>
1499     <addressOffset>0x0014</addressOffset>
1500     <access>read-write</access>
1501     <fields>
1502      <field>
1503       <name>SAV</name>
1504       <description>Start Active Video Code.</description>
1505       <bitRange>[7:0]</bitRange>
1506       <access>read-write</access>
1507      </field>
1508      <field>
1509       <name>EAV</name>
1510       <description>End Active Video Code.</description>
1511       <bitRange>[15:8]</bitRange>
1512       <access>read-write</access>
1513      </field>
1514     </fields>
1515    </register>
1516    <register>
1517     <name>FIFO_DATA</name>
1518     <description>FIFO DATA Register.</description>
1519     <addressOffset>0x0030</addressOffset>
1520     <access>read-write</access>
1521     <fields>
1522      <field>
1523       <name>DATA</name>
1524       <description>Data from FIFO to be read by DMA.</description>
1525       <bitRange>[31:0]</bitRange>
1526       <access>read-write</access>
1527      </field>
1528     </fields>
1529    </register>
1530   </registers>
1531  </peripheral>
1532<!--CAMERAIF Parallel Camera Interface.-->
1533  <peripheral>
1534   <name>CRC</name>
1535   <description>CRC Registers.</description>
1536   <baseAddress>0x4000F000</baseAddress>
1537   <addressBlock>
1538    <offset>0x00</offset>
1539    <size>0x1000</size>
1540    <usage>registers</usage>
1541   </addressBlock>
1542   <registers>
1543    <register>
1544     <name>CTRL</name>
1545     <description>CRC Control</description>
1546     <addressOffset>0x0000</addressOffset>
1547     <size>32</size>
1548     <fields>
1549      <field>
1550       <name>EN</name>
1551       <description>CRC Enable</description>
1552       <bitRange>[0:0]</bitRange>
1553       <access>read-write</access>
1554      </field>
1555      <field>
1556       <name>DMA_EN</name>
1557       <description>DMA Request Enable</description>
1558       <bitRange>[1:1]</bitRange>
1559       <access>read-write</access>
1560      </field>
1561      <field>
1562       <name>MSB</name>
1563       <description>MSB Select</description>
1564       <bitRange>[2:2]</bitRange>
1565       <access>read-write</access>
1566      </field>
1567      <field>
1568       <name>BYTE_SWAP_IN</name>
1569       <description>Byte Swap CRC Data Input</description>
1570       <bitRange>[3:3]</bitRange>
1571       <access>read-write</access>
1572      </field>
1573      <field>
1574       <name>BYTE_SWAP_OUT</name>
1575       <description>Byte Swap CRC Value Output</description>
1576       <bitRange>[4:4]</bitRange>
1577       <access>read-write</access>
1578      </field>
1579      <field>
1580       <name>BUSY</name>
1581       <description>CRC Busy</description>
1582       <bitRange>[16:16]</bitRange>
1583       <access>read-write</access>
1584      </field>
1585     </fields>
1586    </register>
1587    <register>
1588     <name>DATAIN32</name>
1589     <description>CRC Data Input</description>
1590     <addressOffset>0x0004</addressOffset>
1591     <fields>
1592      <field>
1593       <name>DATA</name>
1594       <description>CRC Data</description>
1595       <bitRange>[31:0]</bitRange>
1596       <access>read-write</access>
1597      </field>
1598     </fields>
1599    </register>
1600    <register>
1601     <dim>2</dim>
1602     <dimIncrement>2</dimIncrement>
1603     <name>DATAIN16[%s]</name>
1604     <description>CRC Data Input</description>
1605     <addressOffset>0x0004</addressOffset>
1606     <size>16</size>
1607     <access>read-write</access>
1608     <fields>
1609      <field>
1610       <name>DATA</name>
1611       <description>CRC Data</description>
1612       <bitOffset>0</bitOffset>
1613       <bitWidth>16</bitWidth>
1614       <access>read-write</access>
1615      </field>
1616     </fields>
1617    </register>
1618    <register>
1619     <dim>4</dim>
1620     <dimIncrement>1</dimIncrement>
1621     <name>DATAIN8[%s]</name>
1622     <description>CRC Data Input</description>
1623     <addressOffset>0x0004</addressOffset>
1624     <size>8</size>
1625     <access>read-write</access>
1626     <fields>
1627      <field>
1628       <name>DATA</name>
1629       <description>CRC Data</description>
1630       <bitOffset>0</bitOffset>
1631       <bitWidth>8</bitWidth>
1632       <access>read-write</access>
1633      </field>
1634     </fields>
1635    </register>
1636    <register>
1637     <name>POLY</name>
1638     <description>CRC Polynomial</description>
1639     <addressOffset>0x0008</addressOffset>
1640     <fields>
1641      <field>
1642       <name>POLY</name>
1643       <description>CRC Polynomial</description>
1644       <bitRange>[31:0]</bitRange>
1645       <access>read-write</access>
1646      </field>
1647     </fields>
1648    </register>
1649    <register>
1650     <name>VAL</name>
1651     <description>Current CRC Value</description>
1652     <addressOffset>0x000C</addressOffset>
1653     <fields>
1654      <field>
1655       <name>VALUE</name>
1656       <description>Current CRC Value</description>
1657       <bitRange>[31:0]</bitRange>
1658       <access>read-write</access>
1659      </field>
1660     </fields>
1661    </register>
1662   </registers>
1663  </peripheral>
1664<!--CRC CRC Registers.-->
1665  <peripheral>
1666   <name>CSI2</name>
1667   <description>Camera Serial Interface Registers.</description>
1668   <baseAddress>0x40062000</baseAddress>
1669   <addressBlock>
1670    <offset>0x00</offset>
1671    <size>0x1000</size>
1672    <usage>registers</usage>
1673   </addressBlock>
1674   <registers>
1675    <register>
1676     <name>CFG_NUM_LANES</name>
1677     <description>CFG_NUM_LANES.</description>
1678     <addressOffset>0x000</addressOffset>
1679     <size>32</size>
1680     <fields>
1681      <field>
1682       <name>LANES</name>
1683       <description>Num Lanes for RX controller.</description>
1684       <bitOffset>0</bitOffset>
1685       <bitWidth>4</bitWidth>
1686      </field>
1687     </fields>
1688    </register>
1689    <register>
1690     <name>CFG_CLK_LANE_EN</name>
1691     <description>CFG_CLK_LANE_EN.</description>
1692     <addressOffset>0x004</addressOffset>
1693     <size>32</size>
1694     <fields>
1695      <field>
1696       <name>EN</name>
1697       <description>Enable lane clock setting for controller.</description>
1698       <bitOffset>0</bitOffset>
1699       <bitWidth>1</bitWidth>
1700      </field>
1701     </fields>
1702    </register>
1703    <register>
1704     <name>CFG_DATA_LANE_EN</name>
1705     <description>CFG_DATA_LANE_EN.</description>
1706     <addressOffset>0x008</addressOffset>
1707     <size>32</size>
1708     <fields>
1709      <field>
1710       <name>EN</name>
1711       <description>Enable data lane setting for controller.</description>
1712       <bitOffset>0</bitOffset>
1713       <bitWidth>8</bitWidth>
1714      </field>
1715     </fields>
1716    </register>
1717    <register>
1718     <name>CFG_FLUSH_COUNT</name>
1719     <description>CFG_FLUSH_COUNT.</description>
1720     <addressOffset>0x00C</addressOffset>
1721     <size>32</size>
1722     <fields>
1723      <field>
1724       <name>COUNT</name>
1725       <description>Flush count setting for controller.</description>
1726       <bitOffset>0</bitOffset>
1727       <bitWidth>4</bitWidth>
1728      </field>
1729     </fields>
1730    </register>
1731    <register>
1732     <name>CFG_BIT_ERR</name>
1733     <description>CFG_BIT_ERR.</description>
1734     <addressOffset>0x010</addressOffset>
1735     <size>32</size>
1736     <fields>
1737      <field>
1738       <name>MBE</name>
1739       <description>Multiple bit ECC error.</description>
1740       <bitOffset>0</bitOffset>
1741       <bitWidth>1</bitWidth>
1742      </field>
1743      <field>
1744       <name>SBE</name>
1745       <description>Single bit ECC error.</description>
1746       <bitOffset>1</bitOffset>
1747       <bitWidth>1</bitWidth>
1748      </field>
1749      <field>
1750       <name>HEADER</name>
1751       <description>Header bit location of single bit ECC error.</description>
1752       <bitOffset>2</bitOffset>
1753       <bitWidth>5</bitWidth>
1754      </field>
1755      <field>
1756       <name>CRC</name>
1757       <description>CRC error.</description>
1758       <bitOffset>7</bitOffset>
1759       <bitWidth>1</bitWidth>
1760      </field>
1761      <field>
1762       <name>VID_ERR_SEND_LVL</name>
1763       <description>Video Error Send Level.</description>
1764       <bitOffset>8</bitOffset>
1765       <bitWidth>1</bitWidth>
1766      </field>
1767      <field>
1768       <name>VID_ERR_FIFO_WR_OV</name>
1769       <description>Video Error Fifo Overflow.</description>
1770       <bitOffset>9</bitOffset>
1771       <bitWidth>1</bitWidth>
1772      </field>
1773     </fields>
1774    </register>
1775    <register>
1776     <name>IRQ_STATUS</name>
1777     <description>IRQ_STATUS.</description>
1778     <addressOffset>0x014</addressOffset>
1779     <size>32</size>
1780     <fields>
1781      <field>
1782       <name>CRC</name>
1783       <description>CRC error.</description>
1784       <bitOffset>0</bitOffset>
1785       <bitWidth>1</bitWidth>
1786      </field>
1787      <field>
1788       <name>SBE</name>
1789       <description>Single bit ECC error.</description>
1790       <bitOffset>1</bitOffset>
1791       <bitWidth>1</bitWidth>
1792      </field>
1793      <field>
1794       <name>MBE</name>
1795       <description>Multiple bit ECC error.</description>
1796       <bitOffset>2</bitOffset>
1797       <bitWidth>1</bitWidth>
1798      </field>
1799      <field>
1800       <name>ULPS_ACTIVE</name>
1801       <description>ULPS active status change.</description>
1802       <bitOffset>3</bitOffset>
1803       <bitWidth>1</bitWidth>
1804      </field>
1805      <field>
1806       <name>ULPS_MARK_ACTIVE</name>
1807       <description>ULPS mark active status change.</description>
1808       <bitOffset>4</bitOffset>
1809       <bitWidth>1</bitWidth>
1810      </field>
1811      <field>
1812       <name>VID_ERR_SEND_LVL</name>
1813       <description>Video Error Send Level.</description>
1814       <bitOffset>5</bitOffset>
1815       <bitWidth>1</bitWidth>
1816      </field>
1817      <field>
1818       <name>VID_ERR_FIFO_WR_OV</name>
1819       <description>Video Error Fifo Overflow.</description>
1820       <bitOffset>6</bitOffset>
1821       <bitWidth>1</bitWidth>
1822      </field>
1823     </fields>
1824    </register>
1825    <register>
1826     <name>IRQ_ENABLE</name>
1827     <description>IRQ_ENABLE.</description>
1828     <addressOffset>0x018</addressOffset>
1829     <size>32</size>
1830     <fields>
1831      <field>
1832       <name>CRC</name>
1833       <description>CRC error.</description>
1834       <bitOffset>0</bitOffset>
1835       <bitWidth>1</bitWidth>
1836      </field>
1837      <field>
1838       <name>SBE</name>
1839       <description>Single bit ECC error.</description>
1840       <bitOffset>1</bitOffset>
1841       <bitWidth>1</bitWidth>
1842      </field>
1843      <field>
1844       <name>MBE</name>
1845       <description>Multiple bit ECC error.</description>
1846       <bitOffset>2</bitOffset>
1847       <bitWidth>1</bitWidth>
1848      </field>
1849      <field>
1850       <name>ULPS_ACTIVE</name>
1851       <description>ULPS active status change.</description>
1852       <bitOffset>3</bitOffset>
1853       <bitWidth>1</bitWidth>
1854      </field>
1855      <field>
1856       <name>ULPS_MARK_ACTIVE</name>
1857       <description>ULPS mark active status change.</description>
1858       <bitOffset>4</bitOffset>
1859       <bitWidth>1</bitWidth>
1860      </field>
1861      <field>
1862       <name>VID_ERR_SEND_LVL</name>
1863       <description>Video Error Send Level.</description>
1864       <bitOffset>5</bitOffset>
1865       <bitWidth>1</bitWidth>
1866      </field>
1867      <field>
1868       <name>VID_ERR_FIFO_WR_OV</name>
1869       <description>Video Error Fifo Overflow.</description>
1870       <bitOffset>6</bitOffset>
1871       <bitWidth>1</bitWidth>
1872      </field>
1873     </fields>
1874    </register>
1875    <register>
1876     <name>IRQ_CLR</name>
1877     <description>IRQ_CLR.</description>
1878     <addressOffset>0x01C</addressOffset>
1879     <size>32</size>
1880     <fields>
1881      <field>
1882       <name>CRC</name>
1883       <description>CRC error.</description>
1884       <bitOffset>0</bitOffset>
1885       <bitWidth>1</bitWidth>
1886      </field>
1887      <field>
1888       <name>SBE</name>
1889       <description>Single bit ECC error.</description>
1890       <bitOffset>1</bitOffset>
1891       <bitWidth>1</bitWidth>
1892      </field>
1893      <field>
1894       <name>MBE</name>
1895       <description>Multiple bit ECC error.</description>
1896       <bitOffset>2</bitOffset>
1897       <bitWidth>1</bitWidth>
1898      </field>
1899      <field>
1900       <name>ULPS_ACTIVE</name>
1901       <description>ULPS active status change.</description>
1902       <bitOffset>3</bitOffset>
1903       <bitWidth>1</bitWidth>
1904      </field>
1905      <field>
1906       <name>ULPS_MARK_ACTIVE</name>
1907       <description>ULPS mark active status change.</description>
1908       <bitOffset>4</bitOffset>
1909       <bitWidth>1</bitWidth>
1910      </field>
1911      <field>
1912       <name>VID_ERR_SEND_LVL</name>
1913       <description>Video Error Send Level.</description>
1914       <bitOffset>5</bitOffset>
1915       <bitWidth>1</bitWidth>
1916      </field>
1917      <field>
1918       <name>VID_ERR_FIFO_WR_OV</name>
1919       <description>Video Error Fifo Overflow.</description>
1920       <bitOffset>6</bitOffset>
1921       <bitWidth>1</bitWidth>
1922      </field>
1923     </fields>
1924    </register>
1925    <register>
1926     <name>ULPS_CLK_STATUS</name>
1927     <description>ULPS_CLK_STATUS.</description>
1928     <addressOffset>0x020</addressOffset>
1929     <size>32</size>
1930     <fields>
1931      <field>
1932       <name>FIFO</name>
1933       <description>FIFO Read/Write register.</description>
1934       <bitOffset>0</bitOffset>
1935       <bitWidth>1</bitWidth>
1936      </field>
1937     </fields>
1938    </register>
1939    <register>
1940     <name>ULPS_STATUS</name>
1941     <description>ULPS_STATUS.</description>
1942     <addressOffset>0x024</addressOffset>
1943     <size>32</size>
1944     <fields>
1945      <field>
1946       <name>DATA_LANE0</name>
1947       <description>Data Lane 0.</description>
1948       <bitOffset>0</bitOffset>
1949       <bitWidth>1</bitWidth>
1950      </field>
1951      <field>
1952       <name>DATA_LANE1</name>
1953       <description>Data Lane 1.</description>
1954       <bitOffset>1</bitOffset>
1955       <bitWidth>1</bitWidth>
1956      </field>
1957     </fields>
1958    </register>
1959    <register>
1960     <name>ULPS_CLK_MARK_STATUS</name>
1961     <description>ULPS_CLK_MARK_STATUS.</description>
1962     <addressOffset>0x028</addressOffset>
1963     <size>32</size>
1964     <fields>
1965      <field>
1966       <name>CLK_LANE</name>
1967       <description>Clock Lane.</description>
1968       <bitOffset>0</bitOffset>
1969       <bitWidth>1</bitWidth>
1970      </field>
1971     </fields>
1972    </register>
1973    <register>
1974     <name>ULPS_MARK_STATUS</name>
1975     <description>ULPS_MARK_STATUS.</description>
1976     <addressOffset>0x02C</addressOffset>
1977     <size>32</size>
1978     <fields>
1979      <field>
1980       <name>DATA_LANE0</name>
1981       <description>Data Lane 0.</description>
1982       <bitOffset>0</bitOffset>
1983       <bitWidth>1</bitWidth>
1984      </field>
1985      <field>
1986       <name>DATA_LANE1</name>
1987       <description>Data Lane 1.</description>
1988       <bitOffset>1</bitOffset>
1989       <bitWidth>1</bitWidth>
1990      </field>
1991     </fields>
1992    </register>
1993    <register>
1994     <name>PPI_ERRSOT_HS</name>
1995     <description>PPI_ERRSOT_HS.</description>
1996     <addressOffset>0x030</addressOffset>
1997     <size>32</size>
1998    </register>
1999    <register>
2000     <name>PPI_ERRSOTSYNC_HS</name>
2001     <description>PPI_ERRSOTSYNC_HS.</description>
2002     <addressOffset>0x034</addressOffset>
2003     <size>32</size>
2004    </register>
2005    <register>
2006     <name>PPI_ERRESC</name>
2007     <description>PPI_ERRESC.</description>
2008     <addressOffset>0x038</addressOffset>
2009     <size>32</size>
2010    </register>
2011    <register>
2012     <name>PPI_ERRSYNCESC</name>
2013     <description>PPI_ERRSYNCESC.</description>
2014     <addressOffset>0x03C</addressOffset>
2015     <size>32</size>
2016    </register>
2017    <register>
2018     <name>PPI_ERRCONTROL</name>
2019     <description>PPI_ERRCONTROL.</description>
2020     <addressOffset>0x040</addressOffset>
2021     <size>32</size>
2022    </register>
2023    <register>
2024     <name>CFG_CPHY_EN</name>
2025     <description>CFG_CPHY_EN.</description>
2026     <addressOffset>0x044</addressOffset>
2027     <size>32</size>
2028    </register>
2029    <register>
2030     <name>CFG_PPI_16_EN</name>
2031     <description>CFG_PPI_16_EN.</description>
2032     <addressOffset>0x048</addressOffset>
2033     <size>32</size>
2034    </register>
2035    <register>
2036     <name>CFG_PACKET_INTERFACE_EN</name>
2037     <description>CFG_PACKET_INTERFACE_EN.</description>
2038     <addressOffset>0x04C</addressOffset>
2039     <size>32</size>
2040    </register>
2041    <register>
2042     <name>CFG_VCX_EN</name>
2043     <description>CFG_VCX_EN.</description>
2044     <addressOffset>0x050</addressOffset>
2045     <size>32</size>
2046    </register>
2047    <register>
2048     <name>CFG_BYTE_DATA_FORMAT</name>
2049     <description>CFG_BYTE_DATA_FORMAT.</description>
2050     <addressOffset>0x054</addressOffset>
2051     <size>32</size>
2052    </register>
2053    <register>
2054     <name>CFG_DISABLE_PAYLOAD_0</name>
2055     <description>CFG_DISABLE_PAYLOAD_0.</description>
2056     <addressOffset>0x058</addressOffset>
2057     <size>32</size>
2058     <fields>
2059      <field>
2060       <name>NULL</name>
2061       <description>NULL.</description>
2062       <bitOffset>0</bitOffset>
2063       <bitWidth>1</bitWidth>
2064      </field>
2065      <field>
2066       <name>BLANK</name>
2067       <description>BLANK.</description>
2068       <bitOffset>1</bitOffset>
2069       <bitWidth>1</bitWidth>
2070      </field>
2071      <field>
2072       <name>EMBEDDED</name>
2073       <description>EMBEDDED.</description>
2074       <bitOffset>2</bitOffset>
2075       <bitWidth>1</bitWidth>
2076      </field>
2077      <field>
2078       <name>YUV420_8BIT</name>
2079       <description>YUV420_8BIT.</description>
2080       <bitOffset>8</bitOffset>
2081       <bitWidth>1</bitWidth>
2082      </field>
2083      <field>
2084       <name>YUV420_10BIT</name>
2085       <description>YUV420_10BIT.</description>
2086       <bitOffset>9</bitOffset>
2087       <bitWidth>1</bitWidth>
2088      </field>
2089      <field>
2090       <name>YUV420_8BIT_LEG</name>
2091       <description>YUV420_8BIT_LEG.</description>
2092       <bitOffset>10</bitOffset>
2093       <bitWidth>1</bitWidth>
2094      </field>
2095      <field>
2096       <name>YUV420_8BIT_CSP</name>
2097       <description>YUV420_8BIT_CSP.</description>
2098       <bitOffset>12</bitOffset>
2099       <bitWidth>1</bitWidth>
2100      </field>
2101      <field>
2102       <name>YUV420_10BIT_CSP</name>
2103       <description>YUV420_10BIT_CSP.</description>
2104       <bitOffset>13</bitOffset>
2105       <bitWidth>1</bitWidth>
2106      </field>
2107      <field>
2108       <name>YUV422_8BIT</name>
2109       <description>YUV422_8BIT.</description>
2110       <bitOffset>14</bitOffset>
2111       <bitWidth>1</bitWidth>
2112      </field>
2113      <field>
2114       <name>YUV422_10BIT</name>
2115       <description>YUV422_10BIT.</description>
2116       <bitOffset>15</bitOffset>
2117       <bitWidth>1</bitWidth>
2118      </field>
2119      <field>
2120       <name>RGB444</name>
2121       <description>RGB444.</description>
2122       <bitOffset>16</bitOffset>
2123       <bitWidth>1</bitWidth>
2124      </field>
2125      <field>
2126       <name>RGB555</name>
2127       <description>RGB555.</description>
2128       <bitOffset>17</bitOffset>
2129       <bitWidth>1</bitWidth>
2130      </field>
2131      <field>
2132       <name>RGB565</name>
2133       <description>RGB565.</description>
2134       <bitOffset>18</bitOffset>
2135       <bitWidth>1</bitWidth>
2136      </field>
2137      <field>
2138       <name>RGB666</name>
2139       <description>RGB666.</description>
2140       <bitOffset>19</bitOffset>
2141       <bitWidth>1</bitWidth>
2142      </field>
2143      <field>
2144       <name>RGB888</name>
2145       <description>RGB888.</description>
2146       <bitOffset>20</bitOffset>
2147       <bitWidth>1</bitWidth>
2148      </field>
2149      <field>
2150       <name>RAW6</name>
2151       <description>RAW6.</description>
2152       <bitOffset>24</bitOffset>
2153       <bitWidth>1</bitWidth>
2154      </field>
2155      <field>
2156       <name>RAW7</name>
2157       <description>RAW7.</description>
2158       <bitOffset>25</bitOffset>
2159       <bitWidth>1</bitWidth>
2160      </field>
2161      <field>
2162       <name>RAW8</name>
2163       <description>RAW8.</description>
2164       <bitOffset>26</bitOffset>
2165       <bitWidth>1</bitWidth>
2166      </field>
2167      <field>
2168       <name>RAW10</name>
2169       <description>RAW10.</description>
2170       <bitOffset>27</bitOffset>
2171       <bitWidth>1</bitWidth>
2172      </field>
2173      <field>
2174       <name>RAW12</name>
2175       <description>RAW12.</description>
2176       <bitOffset>28</bitOffset>
2177       <bitWidth>1</bitWidth>
2178      </field>
2179      <field>
2180       <name>RAW14</name>
2181       <description>RAW14.</description>
2182       <bitOffset>29</bitOffset>
2183       <bitWidth>1</bitWidth>
2184      </field>
2185      <field>
2186       <name>RAW16</name>
2187       <description>RAW16.</description>
2188       <bitOffset>30</bitOffset>
2189       <bitWidth>1</bitWidth>
2190      </field>
2191      <field>
2192       <name>RAW20</name>
2193       <description>RAW20.</description>
2194       <bitOffset>31</bitOffset>
2195       <bitWidth>1</bitWidth>
2196      </field>
2197     </fields>
2198    </register>
2199    <register>
2200     <name>CFG_DISABLE_PAYLOAD_1</name>
2201     <description>CFG_DISABLE_PAYLOAD_1.</description>
2202     <addressOffset>0x05C</addressOffset>
2203     <size>32</size>
2204     <fields>
2205      <field>
2206       <name>USR_DEF_TYPE30</name>
2207       <description>User defined type 0x30.</description>
2208       <bitOffset>0</bitOffset>
2209       <bitWidth>1</bitWidth>
2210      </field>
2211      <field>
2212       <name>USR_DEF_TYPE31</name>
2213       <description>User defined type 0x31.</description>
2214       <bitOffset>1</bitOffset>
2215       <bitWidth>1</bitWidth>
2216      </field>
2217      <field>
2218       <name>USR_DEF_TYPE32</name>
2219       <description>User defined type 0x32.</description>
2220       <bitOffset>2</bitOffset>
2221       <bitWidth>1</bitWidth>
2222      </field>
2223      <field>
2224       <name>USR_DEF_TYPE33</name>
2225       <description>User defined type 0x33.</description>
2226       <bitOffset>3</bitOffset>
2227       <bitWidth>1</bitWidth>
2228      </field>
2229      <field>
2230       <name>USR_DEF_TYPE34</name>
2231       <description>User defined type 0x34.</description>
2232       <bitOffset>4</bitOffset>
2233       <bitWidth>1</bitWidth>
2234      </field>
2235      <field>
2236       <name>USR_DEF_TYPE35</name>
2237       <description>User defined type 0x35.</description>
2238       <bitOffset>5</bitOffset>
2239       <bitWidth>1</bitWidth>
2240      </field>
2241      <field>
2242       <name>USR_DEF_TYPE36</name>
2243       <description>User defined type 0x36.</description>
2244       <bitOffset>6</bitOffset>
2245       <bitWidth>1</bitWidth>
2246      </field>
2247      <field>
2248       <name>USR_DEF_TYPE37</name>
2249       <description>User defined type 0x37.</description>
2250       <bitOffset>7</bitOffset>
2251       <bitWidth>1</bitWidth>
2252      </field>
2253     </fields>
2254    </register>
2255    <register>
2256     <name>CFG_VID_IGNORE_VC</name>
2257     <description>CFG_VID_IGNORE_VC.</description>
2258     <addressOffset>0x080</addressOffset>
2259     <size>32</size>
2260    </register>
2261    <register>
2262     <name>CFG_VID_VC</name>
2263     <description>CFG_VID_VC.</description>
2264     <addressOffset>0x084</addressOffset>
2265     <size>32</size>
2266    </register>
2267    <register>
2268     <name>CFG_P_FIFO_SEND_LEVEL</name>
2269     <description>CFG_P_FIFO_SEND_LEVEL.</description>
2270     <addressOffset>0x088</addressOffset>
2271     <size>32</size>
2272    </register>
2273    <register>
2274     <name>CFG_VID_VSYNC</name>
2275     <description>CFG_VID_VSYNC.</description>
2276     <addressOffset>0x08C</addressOffset>
2277     <size>32</size>
2278    </register>
2279    <register>
2280     <name>CFG_VID_HSYNC_FP</name>
2281     <description>CFG_VID_HSYNC_FP.</description>
2282     <addressOffset>0x090</addressOffset>
2283     <size>32</size>
2284    </register>
2285    <register>
2286     <name>CFG_VID_HSYNC</name>
2287     <description>CFG_VID_HSYNC.</description>
2288     <addressOffset>0x094</addressOffset>
2289     <size>32</size>
2290    </register>
2291    <register>
2292     <name>CFG_VID_HSYNC_BP</name>
2293     <description>CFG_VID_HSYNC_BP.</description>
2294     <addressOffset>0x098</addressOffset>
2295     <size>32</size>
2296    </register>
2297    <register>
2298     <name>CFG_DATABUS16_SEL</name>
2299     <description>CFG_DATABUS16_SEL.</description>
2300     <addressOffset>0x400</addressOffset>
2301     <size>32</size>
2302     <fields>
2303      <field>
2304       <name>EN</name>
2305       <description>Enable 16-bit data bus.</description>
2306       <bitOffset>0</bitOffset>
2307       <bitWidth>1</bitWidth>
2308      </field>
2309     </fields>
2310    </register>
2311    <register>
2312     <name>CFG_D0_SWAP_SEL</name>
2313     <description>CFG_D0_SWAP_SEL.</description>
2314     <addressOffset>0x404</addressOffset>
2315     <size>32</size>
2316     <fields>
2317      <field>
2318       <name>SRC</name>
2319       <description>Control Source.</description>
2320       <bitOffset>0</bitOffset>
2321       <bitWidth>3</bitWidth>
2322       <enumeratedValues>
2323        <enumeratedValue>
2324         <name>PAD_CDRX_L0</name>
2325         <description>PAD_CDRX_L0.</description>
2326         <value>0</value>
2327        </enumeratedValue>
2328        <enumeratedValue>
2329         <name>PAD_CDRX_L1</name>
2330         <description>PAD_CDRX_L1.</description>
2331         <value>1</value>
2332        </enumeratedValue>
2333        <enumeratedValue>
2334         <name>PAD_CDRX_L2</name>
2335         <description>PAD_CDRX_L2.</description>
2336         <value>2</value>
2337        </enumeratedValue>
2338        <enumeratedValue>
2339         <name>PAD_CDRX_L3</name>
2340         <description>PAD_CDRX_L3.</description>
2341         <value>3</value>
2342        </enumeratedValue>
2343        <enumeratedValue>
2344         <name>PAD_CDRX_L4</name>
2345         <description>PAD_CDRX_L4.</description>
2346         <value>4</value>
2347        </enumeratedValue>
2348       </enumeratedValues>
2349      </field>
2350     </fields>
2351    </register>
2352    <register>
2353     <name>CFG_D1_SWAP_SEL</name>
2354     <description>CFG_D1_SWAP_SEL.</description>
2355     <addressOffset>0x408</addressOffset>
2356     <size>32</size>
2357     <fields>
2358      <field>
2359       <name>SRC</name>
2360       <description>Control Source.</description>
2361       <bitOffset>0</bitOffset>
2362       <bitWidth>3</bitWidth>
2363       <enumeratedValues>
2364        <enumeratedValue>
2365         <name>PAD_CDRX_L0</name>
2366         <description>PAD_CDRX_L0.</description>
2367         <value>0</value>
2368        </enumeratedValue>
2369        <enumeratedValue>
2370         <name>PAD_CDRX_L1</name>
2371         <description>PAD_CDRX_L1.</description>
2372         <value>1</value>
2373        </enumeratedValue>
2374        <enumeratedValue>
2375         <name>PAD_CDRX_L2</name>
2376         <description>PAD_CDRX_L2.</description>
2377         <value>2</value>
2378        </enumeratedValue>
2379        <enumeratedValue>
2380         <name>PAD_CDRX_L3</name>
2381         <description>PAD_CDRX_L3.</description>
2382         <value>3</value>
2383        </enumeratedValue>
2384        <enumeratedValue>
2385         <name>PAD_CDRX_L4</name>
2386         <description>PAD_CDRX_L4.</description>
2387         <value>4</value>
2388        </enumeratedValue>
2389       </enumeratedValues>
2390      </field>
2391     </fields>
2392    </register>
2393    <register>
2394     <name>CFG_D2_SWAP_SEL</name>
2395     <description>CFG_D2_SWAP_SEL.</description>
2396     <addressOffset>0x40C</addressOffset>
2397     <size>32</size>
2398     <fields>
2399      <field>
2400       <name>SRC</name>
2401       <description>Control Source.</description>
2402       <bitOffset>0</bitOffset>
2403       <bitWidth>3</bitWidth>
2404       <enumeratedValues>
2405        <enumeratedValue>
2406         <name>PAD_CDRX_L0</name>
2407         <description>PAD_CDRX_L0.</description>
2408         <value>0</value>
2409        </enumeratedValue>
2410        <enumeratedValue>
2411         <name>PAD_CDRX_L1</name>
2412         <description>PAD_CDRX_L1.</description>
2413         <value>1</value>
2414        </enumeratedValue>
2415        <enumeratedValue>
2416         <name>PAD_CDRX_L2</name>
2417         <description>PAD_CDRX_L2.</description>
2418         <value>2</value>
2419        </enumeratedValue>
2420        <enumeratedValue>
2421         <name>PAD_CDRX_L3</name>
2422         <description>PAD_CDRX_L3.</description>
2423         <value>3</value>
2424        </enumeratedValue>
2425        <enumeratedValue>
2426         <name>PAD_CDRX_L4</name>
2427         <description>PAD_CDRX_L4.</description>
2428         <value>4</value>
2429        </enumeratedValue>
2430       </enumeratedValues>
2431      </field>
2432     </fields>
2433    </register>
2434    <register>
2435     <name>CFG_D3_SWAP_SEL</name>
2436     <description>CFG_D3_SWAP_SEL.</description>
2437     <addressOffset>0x410</addressOffset>
2438     <size>32</size>
2439     <fields>
2440      <field>
2441       <name>SRC</name>
2442       <description>Control Source.</description>
2443       <bitOffset>0</bitOffset>
2444       <bitWidth>3</bitWidth>
2445       <enumeratedValues>
2446        <enumeratedValue>
2447         <name>PAD_CDRX_L0</name>
2448         <description>PAD_CDRX_L0.</description>
2449         <value>0</value>
2450        </enumeratedValue>
2451        <enumeratedValue>
2452         <name>PAD_CDRX_L1</name>
2453         <description>PAD_CDRX_L1.</description>
2454         <value>1</value>
2455        </enumeratedValue>
2456        <enumeratedValue>
2457         <name>PAD_CDRX_L2</name>
2458         <description>PAD_CDRX_L2.</description>
2459         <value>2</value>
2460        </enumeratedValue>
2461        <enumeratedValue>
2462         <name>PAD_CDRX_L3</name>
2463         <description>PAD_CDRX_L3.</description>
2464         <value>3</value>
2465        </enumeratedValue>
2466        <enumeratedValue>
2467         <name>PAD_CDRX_L4</name>
2468         <description>PAD_CDRX_L4.</description>
2469         <value>4</value>
2470        </enumeratedValue>
2471       </enumeratedValues>
2472      </field>
2473     </fields>
2474    </register>
2475    <register>
2476     <name>CFG_C0_SWAP_SEL</name>
2477     <description>CFG_C0_SWAP_SEL.</description>
2478     <addressOffset>0x414</addressOffset>
2479     <size>32</size>
2480     <fields>
2481      <field>
2482       <name>SRC</name>
2483       <description>Control Source.</description>
2484       <bitOffset>0</bitOffset>
2485       <bitWidth>3</bitWidth>
2486       <enumeratedValues>
2487        <enumeratedValue>
2488         <name>PAD_CDRX_L0</name>
2489         <description>PAD_CDRX_L0.</description>
2490         <value>0</value>
2491        </enumeratedValue>
2492        <enumeratedValue>
2493         <name>PAD_CDRX_L1</name>
2494         <description>PAD_CDRX_L1.</description>
2495         <value>1</value>
2496        </enumeratedValue>
2497        <enumeratedValue>
2498         <name>PAD_CDRX_L2</name>
2499         <description>PAD_CDRX_L2.</description>
2500         <value>2</value>
2501        </enumeratedValue>
2502        <enumeratedValue>
2503         <name>PAD_CDRX_L3</name>
2504         <description>PAD_CDRX_L3.</description>
2505         <value>3</value>
2506        </enumeratedValue>
2507        <enumeratedValue>
2508         <name>PAD_CDRX_L4</name>
2509         <description>PAD_CDRX_L4.</description>
2510         <value>4</value>
2511        </enumeratedValue>
2512       </enumeratedValues>
2513      </field>
2514     </fields>
2515    </register>
2516    <register>
2517     <name>CFG_DPDN_SWAP</name>
2518     <description>CFG_DPDN_SWAP.</description>
2519     <addressOffset>0x418</addressOffset>
2520     <size>32</size>
2521     <fields>
2522      <field>
2523       <name>SWAP_DATA_LANE0</name>
2524       <description>SWAP_DATA_LANE0.</description>
2525       <bitOffset>0</bitOffset>
2526       <bitWidth>1</bitWidth>
2527      </field>
2528      <field>
2529       <name>SWAP_DATA_LANE1</name>
2530       <description>SWAP_DATA_LANE1.</description>
2531       <bitOffset>1</bitOffset>
2532       <bitWidth>1</bitWidth>
2533      </field>
2534      <field>
2535       <name>SWAP_DATA_LANE2</name>
2536       <description>SWAP_DATA_LANE2.</description>
2537       <bitOffset>2</bitOffset>
2538       <bitWidth>1</bitWidth>
2539      </field>
2540      <field>
2541       <name>SWAP_DATA_LANE3</name>
2542       <description>SWAP_DATA_LANE3.</description>
2543       <bitOffset>3</bitOffset>
2544       <bitWidth>1</bitWidth>
2545      </field>
2546      <field>
2547       <name>SWAP_CLK_LANE</name>
2548       <description>SWAP_CLK_LANE.</description>
2549       <bitOffset>4</bitOffset>
2550       <bitWidth>1</bitWidth>
2551      </field>
2552     </fields>
2553    </register>
2554    <register>
2555     <name>RG_CFGCLK_1US_CNT</name>
2556     <description>RG_CFGCLK_1US_CNT.</description>
2557     <addressOffset>0x41C</addressOffset>
2558     <size>32</size>
2559    </register>
2560    <register>
2561     <name>RG_HSRX_CLK_PRE_TIME_GRP0</name>
2562     <description>RG_HSRX_CLK_PRE_TIME_GRP0.</description>
2563     <addressOffset>0x420</addressOffset>
2564     <size>32</size>
2565    </register>
2566    <register>
2567     <name>RG_HSRX_DATA_PRE_TIME_GRP0</name>
2568     <description>RG_HSRX_DATA_PRE_TIME_GRP0.</description>
2569     <addressOffset>0x424</addressOffset>
2570     <size>32</size>
2571    </register>
2572    <register>
2573     <name>RESET_DESKEW</name>
2574     <description>RESET_DESKEW.</description>
2575     <addressOffset>0x428</addressOffset>
2576     <size>32</size>
2577     <fields>
2578      <field>
2579       <name>DATA_LANE0</name>
2580       <description>DATA_LANE0.</description>
2581       <bitOffset>0</bitOffset>
2582       <bitWidth>1</bitWidth>
2583      </field>
2584      <field>
2585       <name>DATA_LANE1</name>
2586       <description>DATA_LANE1.</description>
2587       <bitOffset>1</bitOffset>
2588       <bitWidth>1</bitWidth>
2589      </field>
2590      <field>
2591       <name>DATA_LANE2</name>
2592       <description>DATA_LANE2.</description>
2593       <bitOffset>2</bitOffset>
2594       <bitWidth>1</bitWidth>
2595      </field>
2596      <field>
2597       <name>DATA_LANE3</name>
2598       <description>DATA_LANE3.</description>
2599       <bitOffset>3</bitOffset>
2600       <bitWidth>1</bitWidth>
2601      </field>
2602     </fields>
2603    </register>
2604    <register>
2605     <name>PMA_RDY</name>
2606     <description>PMA_RDY.</description>
2607     <addressOffset>0x42C</addressOffset>
2608     <size>32</size>
2609    </register>
2610    <register>
2611     <name>XCFGI_DW00</name>
2612     <description>XCFGI_DW00.</description>
2613     <addressOffset>0x430</addressOffset>
2614     <size>32</size>
2615    </register>
2616    <register>
2617     <name>XCFGI_DW01</name>
2618     <description>XCFGI_DW01.</description>
2619     <addressOffset>0x434</addressOffset>
2620     <size>32</size>
2621    </register>
2622    <register>
2623     <name>XCFGI_DW02</name>
2624     <description>XCFGI_DW02.</description>
2625     <addressOffset>0x438</addressOffset>
2626     <size>32</size>
2627    </register>
2628    <register>
2629     <name>XCFGI_DW03</name>
2630     <description>XCFGI_DW03.</description>
2631     <addressOffset>0x43C</addressOffset>
2632     <size>32</size>
2633    </register>
2634    <register>
2635     <name>XCFGI_DW04</name>
2636     <description>XCFGI_DW04.</description>
2637     <addressOffset>0x440</addressOffset>
2638     <size>32</size>
2639    </register>
2640    <register>
2641     <name>XCFGI_DW05</name>
2642     <description>XCFGI_DW05.</description>
2643     <addressOffset>0x444</addressOffset>
2644     <size>32</size>
2645    </register>
2646    <register>
2647     <name>XCFGI_DW06</name>
2648     <description>XCFGI_DW06.</description>
2649     <addressOffset>0x448</addressOffset>
2650     <size>32</size>
2651    </register>
2652    <register>
2653     <name>XCFGI_DW07</name>
2654     <description>XCFGI_DW07.</description>
2655     <addressOffset>0x44C</addressOffset>
2656     <size>32</size>
2657    </register>
2658    <register>
2659     <name>XCFGI_DW08</name>
2660     <description>XCFGI_DW08.</description>
2661     <addressOffset>0x450</addressOffset>
2662     <size>32</size>
2663    </register>
2664    <register>
2665     <name>XCFGI_DW09</name>
2666     <description>XCFGI_DW09.</description>
2667     <addressOffset>0x454</addressOffset>
2668     <size>32</size>
2669    </register>
2670    <register>
2671     <name>XCFGI_DW0A</name>
2672     <description>XCFGI_DW0A.</description>
2673     <addressOffset>0x458</addressOffset>
2674     <size>32</size>
2675    </register>
2676    <register>
2677     <name>XCFGI_DW0B</name>
2678     <description>XCFGI_DW0B.</description>
2679     <addressOffset>0x45C</addressOffset>
2680     <size>32</size>
2681    </register>
2682    <register>
2683     <name>XCFGI_DW0C</name>
2684     <description>XCFGI_DW0C.</description>
2685     <addressOffset>0x460</addressOffset>
2686     <size>32</size>
2687    </register>
2688    <register>
2689     <name>XCFGI_DW0D</name>
2690     <description>XCFGI_DW0D.</description>
2691     <addressOffset>0x464</addressOffset>
2692     <size>32</size>
2693    </register>
2694    <register>
2695     <name>GPIO_MODE</name>
2696     <description>GPIO_MODE.</description>
2697     <addressOffset>0x468</addressOffset>
2698     <size>32</size>
2699    </register>
2700    <register>
2701     <name>GPIO_DP_IE</name>
2702     <description>GPIO_DP_IE.</description>
2703     <addressOffset>0x46C</addressOffset>
2704     <size>32</size>
2705    </register>
2706    <register>
2707     <name>GPIO_DN_IE</name>
2708     <description>GPIO_DN_IE.</description>
2709     <addressOffset>0x470</addressOffset>
2710     <size>32</size>
2711    </register>
2712    <register>
2713     <name>GPIO_DP_C</name>
2714     <description>GPIO_DP_C.</description>
2715     <addressOffset>0x474</addressOffset>
2716     <size>32</size>
2717    </register>
2718    <register>
2719     <name>GPIO_DN_C</name>
2720     <description>GPIO_DN_C.</description>
2721     <addressOffset>0x478</addressOffset>
2722     <size>32</size>
2723    </register>
2724    <register>
2725     <name>VCONTROL</name>
2726     <description>PMA_RDY.</description>
2727     <addressOffset>0x47C</addressOffset>
2728     <size>32</size>
2729     <fields>
2730      <field>
2731       <name>NORMAL_MODE</name>
2732       <description>NORMAL_MODE.</description>
2733       <bitOffset>0</bitOffset>
2734       <bitWidth>1</bitWidth>
2735      </field>
2736      <field>
2737       <name>LP_RX_DC_TEST</name>
2738       <description>LP_RX_DC_TEST.</description>
2739       <bitOffset>1</bitOffset>
2740       <bitWidth>1</bitWidth>
2741      </field>
2742      <field>
2743       <name>LP_RX_DC_1</name>
2744       <description>LP_RX_DC_1.</description>
2745       <bitOffset>2</bitOffset>
2746       <bitWidth>1</bitWidth>
2747      </field>
2748      <field>
2749       <name>LP_RX_DC_0</name>
2750       <description>LP_RX_DC_0.</description>
2751       <bitOffset>3</bitOffset>
2752       <bitWidth>1</bitWidth>
2753      </field>
2754      <field>
2755       <name>CAL_SEN_1</name>
2756       <description>CAL_SEN_1.</description>
2757       <bitOffset>4</bitOffset>
2758       <bitWidth>1</bitWidth>
2759      </field>
2760      <field>
2761       <name>CAL_SEN_0</name>
2762       <description>CAL_SEN_0.</description>
2763       <bitOffset>5</bitOffset>
2764       <bitWidth>1</bitWidth>
2765      </field>
2766      <field>
2767       <name>HSRT_0</name>
2768       <description>HSRT_0.</description>
2769       <bitOffset>7</bitOffset>
2770       <bitWidth>1</bitWidth>
2771      </field>
2772      <field>
2773       <name>HSRT_1</name>
2774       <description>HSRT_1.</description>
2775       <bitOffset>8</bitOffset>
2776       <bitWidth>1</bitWidth>
2777      </field>
2778      <field>
2779       <name>LP_RX_PARTBERT</name>
2780       <description>LP_RX_PARTBERT.</description>
2781       <bitOffset>10</bitOffset>
2782       <bitWidth>1</bitWidth>
2783      </field>
2784      <field>
2785       <name>HS_INT_LOOPBACK</name>
2786       <description>HS_INT_LOOPBACK.</description>
2787       <bitOffset>11</bitOffset>
2788       <bitWidth>1</bitWidth>
2789      </field>
2790      <field>
2791       <name>HS_RX_PARTBERT</name>
2792       <description>HS_RX_PARTBERT.</description>
2793       <bitOffset>27</bitOffset>
2794       <bitWidth>1</bitWidth>
2795      </field>
2796      <field>
2797       <name>HS_RX_PRBS9</name>
2798       <description>HS_RX_PRBS9.</description>
2799       <bitOffset>28</bitOffset>
2800       <bitWidth>1</bitWidth>
2801      </field>
2802      <field>
2803       <name>SUSPEND_MODE</name>
2804       <description>SUSPEND_MODE.</description>
2805       <bitOffset>31</bitOffset>
2806       <bitWidth>1</bitWidth>
2807      </field>
2808     </fields>
2809    </register>
2810    <register>
2811     <name>MPSOV1</name>
2812     <description>MPSOV1.</description>
2813     <addressOffset>0x480</addressOffset>
2814     <size>32</size>
2815    </register>
2816    <register>
2817     <name>MPSOV2</name>
2818     <description>MPSOV2.</description>
2819     <addressOffset>0x484</addressOffset>
2820     <size>32</size>
2821    </register>
2822    <register>
2823     <name>MPSOV3</name>
2824     <description>MPSOV3.</description>
2825     <addressOffset>0x488</addressOffset>
2826     <size>32</size>
2827    </register>
2828    <register>
2829     <name>RG_CDRX_DSIRX_EN</name>
2830     <description>RG_CDRX_DSIRX_EN.</description>
2831     <addressOffset>0x490</addressOffset>
2832     <size>32</size>
2833     <fields>
2834      <field>
2835       <name>RXMODE</name>
2836       <description>RXMODE.</description>
2837       <bitOffset>0</bitOffset>
2838       <bitWidth>1</bitWidth>
2839       <enumeratedValues>
2840        <enumeratedValue>
2841         <name>CSI</name>
2842         <description>CSI RX Mode.</description>
2843         <value>0</value>
2844        </enumeratedValue>
2845        <enumeratedValue>
2846         <name>DSI</name>
2847         <description>DSI RX Mode.</description>
2848         <value>1</value>
2849        </enumeratedValue>
2850       </enumeratedValues>
2851      </field>
2852     </fields>
2853    </register>
2854    <register>
2855     <name>RG_CDRX_L012_SUBLVDS_EN</name>
2856     <description>RG_CDRX_L012_SUBLVDS_EN.</description>
2857     <addressOffset>0x494</addressOffset>
2858     <size>32</size>
2859    </register>
2860    <register>
2861     <name>RG_CDRX_L012_HSRT_CTRL</name>
2862     <description>RG_CDRX_L012_HSRT_CTRL.</description>
2863     <addressOffset>0x498</addressOffset>
2864     <size>32</size>
2865    </register>
2866    <register>
2867     <name>RG_CDRX_BISTHS_PLL_EN</name>
2868     <description>RG_CDRX_BISTHS_PLL_EN.</description>
2869     <addressOffset>0x49C</addressOffset>
2870     <size>32</size>
2871    </register>
2872    <register>
2873     <name>RG_CDRX_BISTHS_PLL_PRE_DIV2</name>
2874     <description>RG_CDRX_BISTHS_PLL_PRE_DIV2.</description>
2875     <addressOffset>0x4A0</addressOffset>
2876     <size>32</size>
2877     <fields>
2878      <field>
2879       <name>RXMODE</name>
2880       <description>RXMODE.</description>
2881       <bitOffset>0</bitOffset>
2882       <bitWidth>1</bitWidth>
2883       <enumeratedValues>
2884        <enumeratedValue>
2885         <name>CSI</name>
2886         <description>CSI RX Mode.</description>
2887         <value>0</value>
2888        </enumeratedValue>
2889        <enumeratedValue>
2890         <name>DSI</name>
2891         <description>DSI RX Mode.</description>
2892         <value>1</value>
2893        </enumeratedValue>
2894       </enumeratedValues>
2895      </field>
2896     </fields>
2897    </register>
2898    <register>
2899     <name>RG_CDRX_BISTHS_PLL_FBK_INT</name>
2900     <description>RG_CDRX_BISTHS_PLL_FBK_INT.</description>
2901     <addressOffset>0x4A4</addressOffset>
2902     <size>32</size>
2903    </register>
2904    <register>
2905     <name>DBG1_MUX_SEL</name>
2906     <description>DBG1_MUX_SEL.</description>
2907     <addressOffset>0x4A8</addressOffset>
2908     <size>32</size>
2909    </register>
2910    <register>
2911     <name>DBG2_MUX_SEL</name>
2912     <description>DBG2_MUX_SEL.</description>
2913     <addressOffset>0x4AC</addressOffset>
2914     <size>32</size>
2915    </register>
2916    <register>
2917     <name>DBG1_MUX_DOUT</name>
2918     <description>DBG1_MUX_DOUT.</description>
2919     <addressOffset>0x4B0</addressOffset>
2920     <size>32</size>
2921    </register>
2922    <register>
2923     <name>DBG2_MUX_DOUT</name>
2924     <description>DBG2_MUX_DOUT.</description>
2925     <addressOffset>0x4B4</addressOffset>
2926     <size>32</size>
2927    </register>
2928    <register>
2929     <name>AON_POWER_READY_N</name>
2930     <description>AON_POWER_READY_N.</description>
2931     <addressOffset>0x4B8</addressOffset>
2932     <size>32</size>
2933    </register>
2934    <register>
2935     <name>DPHY_RST_N</name>
2936     <description>DPHY_RST_N.</description>
2937     <addressOffset>0x4BC</addressOffset>
2938     <size>32</size>
2939    </register>
2940    <register>
2941     <name>RXBYTECLKHS_INV</name>
2942     <description>RXBYTECLKHS_INV.</description>
2943     <addressOffset>0x4C0</addressOffset>
2944     <size>32</size>
2945    </register>
2946    <register>
2947     <name>VFIFO_CFG0</name>
2948     <description>Video FIFO Configuration Register 0.</description>
2949     <addressOffset>0x500</addressOffset>
2950     <size>32</size>
2951     <fields>
2952      <field>
2953       <name>VC</name>
2954       <description>CSI Virtual Channel.</description>
2955       <bitOffset>0</bitOffset>
2956       <bitWidth>2</bitWidth>
2957      </field>
2958      <field>
2959       <name>DMAMODE</name>
2960       <description>DMA Mode, the condition to trigger DMA request..</description>
2961       <bitOffset>6</bitOffset>
2962       <bitWidth>2</bitWidth>
2963       <enumeratedValues>
2964        <enumeratedValue>
2965         <name>NO_DMA</name>
2966         <description>No DMA.</description>
2967         <value>0</value>
2968        </enumeratedValue>
2969        <enumeratedValue>
2970         <name>DMA_REQ</name>
2971         <description>Immediately send DMA request.</description>
2972         <value>1</value>
2973        </enumeratedValue>
2974        <enumeratedValue>
2975         <name>FIFO_THD</name>
2976         <description>Wait for FIFO above threshold.</description>
2977         <value>2</value>
2978        </enumeratedValue>
2979        <enumeratedValue>
2980         <name>FIFO_FULL</name>
2981         <description>Wait for FIFO is full.</description>
2982         <value>3</value>
2983        </enumeratedValue>
2984       </enumeratedValues>
2985      </field>
2986      <field>
2987       <name>AHBWAIT</name>
2988       <description>AHB Wait Enable.</description>
2989       <bitOffset>8</bitOffset>
2990       <bitWidth>1</bitWidth>
2991      </field>
2992      <field>
2993       <name>FIFORM</name>
2994       <description>FIFO Read Mode.</description>
2995       <bitOffset>9</bitOffset>
2996       <bitWidth>1</bitWidth>
2997      </field>
2998      <field>
2999       <name>ERRDE</name>
3000       <description>Error Detection Enable.</description>
3001       <bitOffset>10</bitOffset>
3002       <bitWidth>1</bitWidth>
3003      </field>
3004      <field>
3005       <name>FBWM</name>
3006       <description>Full Band Width mode.</description>
3007       <bitOffset>11</bitOffset>
3008       <bitWidth>1</bitWidth>
3009      </field>
3010     </fields>
3011    </register>
3012    <register>
3013     <name>VFIFO_CFG1</name>
3014     <description>Video FIFO Configuration Register 1.</description>
3015     <addressOffset>0x504</addressOffset>
3016     <size>32</size>
3017     <fields>
3018      <field>
3019       <name>AHBWCYC</name>
3020       <description>Maximal AHB Wait Clock Cycles.</description>
3021       <bitOffset>0</bitOffset>
3022       <bitWidth>16</bitWidth>
3023      </field>
3024      <field>
3025       <name>WAIT_FIRST_FS</name>
3026       <description>WAIT_FIRST_FS.</description>
3027       <bitOffset>16</bitOffset>
3028       <bitWidth>1</bitWidth>
3029      </field>
3030      <field>
3031       <name>ACCU_FRAME_CTRL</name>
3032       <description>ACCU_FRAME_CTRL.</description>
3033       <bitOffset>17</bitOffset>
3034       <bitWidth>1</bitWidth>
3035      </field>
3036      <field>
3037       <name>ACCU_LINE_CTRL</name>
3038       <description>ACCU_LINE_CTRL.</description>
3039       <bitOffset>18</bitOffset>
3040       <bitWidth>1</bitWidth>
3041      </field>
3042      <field>
3043       <name>ACCU_LINE_CNT</name>
3044       <description>ACCU_LINE_CNT.</description>
3045       <bitOffset>19</bitOffset>
3046       <bitWidth>1</bitWidth>
3047      </field>
3048      <field>
3049       <name>ACCU_PIXEL_CNT</name>
3050       <description>ACCU_PIXEL_CNT.</description>
3051       <bitOffset>20</bitOffset>
3052       <bitWidth>1</bitWidth>
3053      </field>
3054      <field>
3055       <name>ACCU_PIXEL_ZERO</name>
3056       <description>ACCU_PIXEL_ZERO.</description>
3057       <bitOffset>21</bitOffset>
3058       <bitWidth>1</bitWidth>
3059      </field>
3060     </fields>
3061    </register>
3062    <register>
3063     <name>VFIFO_CTRL</name>
3064     <description>Video FIFO Control Register.</description>
3065     <addressOffset>0x508</addressOffset>
3066     <size>32</size>
3067     <fields>
3068      <field>
3069       <name>FIFOEN</name>
3070       <description>Video FIFO Enable.</description>
3071       <bitOffset>0</bitOffset>
3072       <bitWidth>1</bitWidth>
3073       <enumeratedValues>
3074        <enumeratedValue>
3075         <name>DIS</name>
3076         <description>Disable.</description>
3077         <value>0</value>
3078        </enumeratedValue>
3079        <enumeratedValue>
3080         <name>EN</name>
3081         <description>Enable.</description>
3082         <value>1</value>
3083        </enumeratedValue>
3084       </enumeratedValues>
3085      </field>
3086      <field>
3087       <name>FLUSH</name>
3088       <description>Write 1 to flush FIFO contents.</description>
3089       <bitOffset>4</bitOffset>
3090       <bitWidth>1</bitWidth>
3091      </field>
3092      <field>
3093       <name>THD</name>
3094       <description>FIFO Threshold.</description>
3095       <bitOffset>8</bitOffset>
3096       <bitWidth>7</bitWidth>
3097      </field>
3098     </fields>
3099    </register>
3100    <register>
3101     <name>VFIFO_STS</name>
3102     <description>Video FIFO Status Register.</description>
3103     <addressOffset>0x50C</addressOffset>
3104     <size>32</size>
3105     <fields>
3106      <field>
3107       <name>FEMPTY</name>
3108       <description>FIFO empty.</description>
3109       <bitOffset>0</bitOffset>
3110       <bitWidth>1</bitWidth>
3111      </field>
3112      <field>
3113       <name>FTHD</name>
3114       <description>FIFO above threshold.</description>
3115       <bitOffset>1</bitOffset>
3116       <bitWidth>1</bitWidth>
3117      </field>
3118      <field>
3119       <name>FFULL</name>
3120       <description>FIFO full.</description>
3121       <bitOffset>2</bitOffset>
3122       <bitWidth>1</bitWidth>
3123      </field>
3124      <field>
3125       <name>UNDERRUN</name>
3126       <description>FIFO underrun</description>
3127       <bitOffset>3</bitOffset>
3128       <bitWidth>1</bitWidth>
3129      </field>
3130      <field>
3131       <name>OVERRUN</name>
3132       <description>FIFO overrun</description>
3133       <bitOffset>4</bitOffset>
3134       <bitWidth>1</bitWidth>
3135      </field>
3136      <field>
3137       <name>OUTSYNC</name>
3138       <description>CSI out of sync</description>
3139       <bitOffset>5</bitOffset>
3140       <bitWidth>1</bitWidth>
3141      </field>
3142      <field>
3143       <name>FMTERR</name>
3144       <description>CSI Pixel Format Error</description>
3145       <bitOffset>6</bitOffset>
3146       <bitWidth>1</bitWidth>
3147      </field>
3148      <field>
3149       <name>AHBWTO</name>
3150       <description>AHB wait time out</description>
3151       <bitOffset>7</bitOffset>
3152       <bitWidth>1</bitWidth>
3153      </field>
3154      <field>
3155       <name>FS</name>
3156       <description>CSI Frame Start</description>
3157       <bitOffset>8</bitOffset>
3158       <bitWidth>1</bitWidth>
3159      </field>
3160      <field>
3161       <name>FE</name>
3162       <description>CSI Frame End</description>
3163       <bitOffset>9</bitOffset>
3164       <bitWidth>1</bitWidth>
3165      </field>
3166      <field>
3167       <name>LS</name>
3168       <description>CSI Line Start</description>
3169       <bitOffset>10</bitOffset>
3170       <bitWidth>1</bitWidth>
3171      </field>
3172      <field>
3173       <name>LE</name>
3174       <description>CSI Line End</description>
3175       <bitOffset>11</bitOffset>
3176       <bitWidth>1</bitWidth>
3177      </field>
3178      <field>
3179       <name>FELT</name>
3180       <description>FIFO remaining entity count</description>
3181       <bitOffset>16</bitOffset>
3182       <bitWidth>7</bitWidth>
3183      </field>
3184      <field>
3185       <name>FMT</name>
3186       <description>CSI pixel format of current transaction</description>
3187       <bitOffset>24</bitOffset>
3188       <bitWidth>6</bitWidth>
3189      </field>
3190     </fields>
3191    </register>
3192    <register>
3193     <name>VFIFO_LINE_NUM</name>
3194     <description>Video FIFO CSI Line Number Per Frame.</description>
3195     <addressOffset>0x510</addressOffset>
3196     <size>32</size>
3197     <fields>
3198      <field>
3199       <name>LINE_NUM</name>
3200       <description>Number of lines per frame.</description>
3201       <bitOffset>0</bitOffset>
3202       <bitWidth>13</bitWidth>
3203      </field>
3204     </fields>
3205    </register>
3206    <register>
3207     <name>VFIFO_PIXEL_NUM</name>
3208     <description>Video FIFO CSI Pixel Number Per Line.</description>
3209     <addressOffset>0x514</addressOffset>
3210     <size>32</size>
3211     <fields>
3212      <field>
3213       <name>PIXEL_NUM</name>
3214       <description>Number of pixels per line.</description>
3215       <bitOffset>0</bitOffset>
3216       <bitWidth>14</bitWidth>
3217      </field>
3218     </fields>
3219    </register>
3220    <register>
3221     <name>VFIFO_LINE_CNT</name>
3222     <description>Video FIFO CSI Line Count.</description>
3223     <addressOffset>0x518</addressOffset>
3224     <size>32</size>
3225     <fields>
3226      <field>
3227       <name>LINE_CNT</name>
3228       <description>Number of received lines in current frame.</description>
3229       <bitOffset>0</bitOffset>
3230       <bitWidth>12</bitWidth>
3231      </field>
3232     </fields>
3233    </register>
3234    <register>
3235     <name>VFIFO_PIXEL_CNT</name>
3236     <description>Video FIFO CSI Pixel Count.</description>
3237     <addressOffset>0x51C</addressOffset>
3238     <size>32</size>
3239     <fields>
3240      <field>
3241       <name>PIXEL_CNT</name>
3242       <description>Number of received pixels in current line in a frame.</description>
3243       <bitOffset>0</bitOffset>
3244       <bitWidth>13</bitWidth>
3245      </field>
3246     </fields>
3247    </register>
3248    <register>
3249     <name>VFIFO_FRAME_STS</name>
3250     <description>Video FIFO Frame Status Register.</description>
3251     <addressOffset>0x520</addressOffset>
3252     <size>32</size>
3253     <fields>
3254      <field>
3255       <name>FRAME_STATE</name>
3256       <description>Frame State.</description>
3257       <bitOffset>0</bitOffset>
3258       <bitWidth>3</bitWidth>
3259      </field>
3260      <field>
3261       <name>ERROR_CODE</name>
3262       <description>Error Codes.</description>
3263       <bitOffset>3</bitOffset>
3264       <bitWidth>3</bitWidth>
3265      </field>
3266     </fields>
3267    </register>
3268    <register>
3269     <name>VFIFO_RAW_CTRL</name>
3270     <description>Video FIFO RAW-to-RGB Control Register.</description>
3271     <addressOffset>0x524</addressOffset>
3272     <size>32</size>
3273     <fields>
3274      <field>
3275       <name>RAW_CEN</name>
3276       <description>RAW conversion enable.</description>
3277       <bitOffset>0</bitOffset>
3278       <bitWidth>1</bitWidth>
3279      </field>
3280      <field>
3281       <name>RAW_FF_AFO</name>
3282       <description>RAW conversion FIFO automatic flush-out.</description>
3283       <bitOffset>1</bitOffset>
3284       <bitWidth>1</bitWidth>
3285      </field>
3286      <field>
3287       <name>RAW_FF_FO</name>
3288       <description>RAW conversion FIFO flush-out trigger.</description>
3289       <bitOffset>4</bitOffset>
3290       <bitWidth>1</bitWidth>
3291      </field>
3292      <field>
3293       <name>RAW_FMT</name>
3294       <description>RAW format.</description>
3295       <bitOffset>8</bitOffset>
3296       <bitWidth>2</bitWidth>
3297       <enumeratedValues>
3298        <enumeratedValue>
3299         <name>RGRG_GBGB</name>
3300         <description>RGRG GBGB</description>
3301         <value>0</value>
3302        </enumeratedValue>
3303        <enumeratedValue>
3304         <name>GRGR_BGBG</name>
3305         <description>GRGR BGBG</description>
3306         <value>1</value>
3307        </enumeratedValue>
3308        <enumeratedValue>
3309         <name>GBGB_RGRG</name>
3310         <description>GBGB RGRG</description>
3311         <value>2</value>
3312        </enumeratedValue>
3313        <enumeratedValue>
3314         <name>BGBG_GRGR</name>
3315         <description>BGBG GRGR</description>
3316         <value>3</value>
3317        </enumeratedValue>
3318       </enumeratedValues>
3319      </field>
3320      <field>
3321       <name>RGB_TYP</name>
3322       <description>RGB type.</description>
3323       <bitOffset>12</bitOffset>
3324       <bitWidth>3</bitWidth>
3325       <enumeratedValues>
3326        <enumeratedValue>
3327         <name>RGB444</name>
3328         <description>RGB444.</description>
3329         <value>0</value>
3330        </enumeratedValue>
3331        <enumeratedValue>
3332         <name>RGB555</name>
3333         <description>RGB555.</description>
3334         <value>1</value>
3335        </enumeratedValue>
3336        <enumeratedValue>
3337         <name>RGB565</name>
3338         <description>RGB565.</description>
3339         <value>2</value>
3340        </enumeratedValue>
3341        <enumeratedValue>
3342         <name>RGB666</name>
3343         <description>RGB666.</description>
3344         <value>3</value>
3345        </enumeratedValue>
3346        <enumeratedValue>
3347         <name>RGG888</name>
3348         <description>RGG888.</description>
3349         <value>4</value>
3350        </enumeratedValue>
3351       </enumeratedValues>
3352      </field>
3353     </fields>
3354    </register>
3355    <register>
3356     <name>VFIFO_RAW_BUF0_ADDR</name>
3357     <description>Video FIFO RAW-to-RGB Line Buffer0 Address.</description>
3358     <addressOffset>0x528</addressOffset>
3359     <size>32</size>
3360     <fields>
3361      <field>
3362       <name>ADDR</name>
3363       <description>RAM address for RAW conversion buffer 0, word-aligned.</description>
3364       <bitOffset>2</bitOffset>
3365       <bitWidth>30</bitWidth>
3366      </field>
3367     </fields>
3368    </register>
3369    <register>
3370     <name>VFIFO_RAW_BUF1_ADDR</name>
3371     <description>Video FIFO RAW-to-RGB Line Buffer1 Address.</description>
3372     <addressOffset>0x52C</addressOffset>
3373     <size>32</size>
3374     <fields>
3375      <field>
3376       <name>ADDR</name>
3377       <description>RAM address for RAW conversion buffer 1, word-aligned.</description>
3378       <bitOffset>2</bitOffset>
3379       <bitWidth>30</bitWidth>
3380      </field>
3381     </fields>
3382    </register>
3383    <register>
3384     <name>VFIFO_AHBM_CTRL</name>
3385     <description>Video FIFO AHB Master Control Register.</description>
3386     <addressOffset>0x530</addressOffset>
3387     <size>32</size>
3388     <fields>
3389      <field>
3390       <name>AHBMEN</name>
3391       <description>AHB Master Enable.</description>
3392       <bitOffset>0</bitOffset>
3393       <bitWidth>1</bitWidth>
3394      </field>
3395      <field>
3396       <name>AHBMCLR</name>
3397       <description>AHB Master Status Clear.</description>
3398       <bitOffset>1</bitOffset>
3399       <bitWidth>1</bitWidth>
3400      </field>
3401      <field>
3402       <name>BSTLEN</name>
3403       <description>AHB Burst Length.</description>
3404       <bitOffset>4</bitOffset>
3405       <bitWidth>2</bitWidth>
3406       <enumeratedValues>
3407        <enumeratedValue>
3408         <name>VFIFO_THD</name>
3409         <description>Video FIFO THD.</description>
3410         <value>0</value>
3411        </enumeratedValue>
3412        <enumeratedValue>
3413         <name>ONE_WORD</name>
3414         <description>ONE_WORD.</description>
3415         <value>1</value>
3416        </enumeratedValue>
3417        <enumeratedValue>
3418         <name>FOUR_WORDS</name>
3419         <description>FOUR_WORDS.</description>
3420         <value>2</value>
3421        </enumeratedValue>
3422        <enumeratedValue>
3423         <name>EIGHT_WORDS</name>
3424         <description>EIGHT_WORDS.</description>
3425         <value>3</value>
3426        </enumeratedValue>
3427       </enumeratedValues>
3428      </field>
3429     </fields>
3430    </register>
3431    <register>
3432     <name>VFIFO_AHBM_STS</name>
3433     <description>Video FIFO AHB Master Status Register.</description>
3434     <addressOffset>0x534</addressOffset>
3435     <size>32</size>
3436     <fields>
3437      <field>
3438       <name>HRDY_TO</name>
3439       <description>AHB master HREADY time-out.</description>
3440       <bitOffset>0</bitOffset>
3441       <bitWidth>1</bitWidth>
3442      </field>
3443      <field>
3444       <name>IDLE_TO</name>
3445       <description>AHB master Idle time-out.</description>
3446       <bitOffset>1</bitOffset>
3447       <bitWidth>1</bitWidth>
3448      </field>
3449      <field>
3450       <name>TRANS_MAX</name>
3451       <description>AHB master maximal transfer count occurrence.</description>
3452       <bitOffset>2</bitOffset>
3453       <bitWidth>1</bitWidth>
3454      </field>
3455     </fields>
3456    </register>
3457    <register>
3458     <name>VFIFO_AHBM_START_ADDR</name>
3459     <description>Video FIFO AHB Master Start Address Register.</description>
3460     <addressOffset>0x538</addressOffset>
3461     <size>32</size>
3462     <fields>
3463      <field>
3464       <name>AHBM_START_ADDR</name>
3465       <description>AHB master transfer starting address, word-aligned.</description>
3466       <bitOffset>2</bitOffset>
3467       <bitWidth>30</bitWidth>
3468      </field>
3469     </fields>
3470    </register>
3471    <register>
3472     <name>VFIFO_AHBM_ADDR_RANGE</name>
3473     <description>Video FIFO AHB Master Address Range Register.</description>
3474     <addressOffset>0x53C</addressOffset>
3475     <size>32</size>
3476     <fields>
3477      <field>
3478       <name>AHBM_ADDR_RANGE</name>
3479       <description>AHB master address range.</description>
3480       <bitOffset>2</bitOffset>
3481       <bitWidth>14</bitWidth>
3482      </field>
3483     </fields>
3484    </register>
3485    <register>
3486     <name>VFIFO_AHBM_MAX_TRANS</name>
3487     <description>Video FIFO AHB Master Maximal Transfer Number Register.</description>
3488     <addressOffset>0x540</addressOffset>
3489     <size>32</size>
3490     <fields>
3491      <field>
3492       <name>AHBM_MAX_TRANS</name>
3493       <description>AHB master maximal number of transfer word count.</description>
3494       <bitOffset>0</bitOffset>
3495       <bitWidth>32</bitWidth>
3496      </field>
3497     </fields>
3498    </register>
3499    <register>
3500     <name>VFIFO_AHBM_TRANS_CNT</name>
3501     <description>Video FIFO AHB Master Transfer Count Register.</description>
3502     <addressOffset>0x544</addressOffset>
3503     <size>32</size>
3504     <fields>
3505      <field>
3506       <name>AHBM_TRANS_CNT</name>
3507       <description>AHB master number of words been transferred.</description>
3508       <bitOffset>0</bitOffset>
3509       <bitWidth>32</bitWidth>
3510      </field>
3511     </fields>
3512    </register>
3513    <register>
3514     <name>RX_EINT_VFF_IE</name>
3515     <description>RX Video FIFO Interrupt Enable Register.</description>
3516     <addressOffset>0x600</addressOffset>
3517     <size>32</size>
3518     <fields>
3519      <field>
3520       <name>FNEMPTY</name>
3521       <description>Video FIFO not empty interrupt enable.</description>
3522       <bitOffset>0</bitOffset>
3523       <bitWidth>1</bitWidth>
3524      </field>
3525      <field>
3526       <name>FTHD</name>
3527       <description>Video FIFO above threshold interrupt enable.</description>
3528       <bitOffset>1</bitOffset>
3529       <bitWidth>1</bitWidth>
3530      </field>
3531      <field>
3532       <name>FFULL</name>
3533       <description>Video FIFO full interrupt enable.</description>
3534       <bitOffset>2</bitOffset>
3535       <bitWidth>1</bitWidth>
3536      </field>
3537      <field>
3538       <name>UNDERRUN</name>
3539       <description>Video FIFO underrun interrupt enable</description>
3540       <bitOffset>3</bitOffset>
3541       <bitWidth>1</bitWidth>
3542      </field>
3543      <field>
3544       <name>OVERRUN</name>
3545       <description>Video FIFO overrun interrupt enable</description>
3546       <bitOffset>4</bitOffset>
3547       <bitWidth>1</bitWidth>
3548      </field>
3549      <field>
3550       <name>OUTSYNC</name>
3551       <description>CSI out of sync interrupt enable</description>
3552       <bitOffset>5</bitOffset>
3553       <bitWidth>1</bitWidth>
3554      </field>
3555      <field>
3556       <name>FMTERR</name>
3557       <description>CSI Pixel Format Error interrupt enable</description>
3558       <bitOffset>6</bitOffset>
3559       <bitWidth>1</bitWidth>
3560      </field>
3561      <field>
3562       <name>AHBWTO</name>
3563       <description>AHB wait time out interrupt enable</description>
3564       <bitOffset>7</bitOffset>
3565       <bitWidth>1</bitWidth>
3566      </field>
3567      <field>
3568       <name>FS</name>
3569       <description>CSI Frame Start interrupt enable</description>
3570       <bitOffset>8</bitOffset>
3571       <bitWidth>1</bitWidth>
3572      </field>
3573      <field>
3574       <name>FE</name>
3575       <description>CSI Frame End interrupt enable</description>
3576       <bitOffset>9</bitOffset>
3577       <bitWidth>1</bitWidth>
3578      </field>
3579      <field>
3580       <name>LS</name>
3581       <description>CSI Line Start interrupt enable</description>
3582       <bitOffset>10</bitOffset>
3583       <bitWidth>1</bitWidth>
3584      </field>
3585      <field>
3586       <name>LE</name>
3587       <description>CSI Line End interrupt enable</description>
3588       <bitOffset>11</bitOffset>
3589       <bitWidth>1</bitWidth>
3590      </field>
3591      <field>
3592       <name>RAW_OVR</name>
3593       <description>Raw FIFO Overrun Interrupt Enable</description>
3594       <bitOffset>12</bitOffset>
3595       <bitWidth>1</bitWidth>
3596      </field>
3597      <field>
3598       <name>RAW_AHBERR</name>
3599       <description>Raw AHB Error Interrupt Enable</description>
3600       <bitOffset>13</bitOffset>
3601       <bitWidth>1</bitWidth>
3602      </field>
3603      <field>
3604       <name>FNEMP_MD</name>
3605       <description>Video FIFO not empty detection mode</description>
3606       <bitOffset>16</bitOffset>
3607       <bitWidth>1</bitWidth>
3608      </field>
3609      <field>
3610       <name>FTHD_MD</name>
3611       <description>Video FIFO threshold detection mode</description>
3612       <bitOffset>17</bitOffset>
3613       <bitWidth>1</bitWidth>
3614      </field>
3615      <field>
3616       <name>FFUL_MD</name>
3617       <description>Video FIFO full detection mode</description>
3618       <bitOffset>18</bitOffset>
3619       <bitWidth>1</bitWidth>
3620      </field>
3621      <field>
3622       <name>AHBM_RDTO</name>
3623       <description>AHBM_RDTO</description>
3624       <bitOffset>24</bitOffset>
3625       <bitWidth>1</bitWidth>
3626      </field>
3627      <field>
3628       <name>AHBM_IDTO</name>
3629       <description>AHBM_IDTO</description>
3630       <bitOffset>25</bitOffset>
3631       <bitWidth>1</bitWidth>
3632      </field>
3633      <field>
3634       <name>AHBM_MAX</name>
3635       <description>AHBM_MAX</description>
3636       <bitOffset>26</bitOffset>
3637       <bitWidth>1</bitWidth>
3638      </field>
3639     </fields>
3640    </register>
3641    <register>
3642     <name>RX_EINT_VFF_IF</name>
3643     <description>RX Video FIFO Interrupt Flag Register.</description>
3644     <addressOffset>0x604</addressOffset>
3645     <size>32</size>
3646     <fields>
3647      <field>
3648       <name>FNEMPTY</name>
3649       <description>Video FIFO not empty interrupt flag.</description>
3650       <bitOffset>0</bitOffset>
3651       <bitWidth>1</bitWidth>
3652      </field>
3653      <field>
3654       <name>FTHD</name>
3655       <description>Video FIFO above threshold interrupt flag.</description>
3656       <bitOffset>1</bitOffset>
3657       <bitWidth>1</bitWidth>
3658      </field>
3659      <field>
3660       <name>FFULL</name>
3661       <description>Video FIFO full interrupt flag.</description>
3662       <bitOffset>2</bitOffset>
3663       <bitWidth>1</bitWidth>
3664      </field>
3665      <field>
3666       <name>UNDERRUN</name>
3667       <description>Video FIFO underrun interrupt flag</description>
3668       <bitOffset>3</bitOffset>
3669       <bitWidth>1</bitWidth>
3670      </field>
3671      <field>
3672       <name>OVERRUN</name>
3673       <description>Video FIFO overrun interrupt flag</description>
3674       <bitOffset>4</bitOffset>
3675       <bitWidth>1</bitWidth>
3676      </field>
3677      <field>
3678       <name>OUTSYNC</name>
3679       <description>CSI out of sync interrupt flag</description>
3680       <bitOffset>5</bitOffset>
3681       <bitWidth>1</bitWidth>
3682      </field>
3683      <field>
3684       <name>FMTERR</name>
3685       <description>CSI Pixel Format Error interrupt flag</description>
3686       <bitOffset>6</bitOffset>
3687       <bitWidth>1</bitWidth>
3688      </field>
3689      <field>
3690       <name>AHBWTO</name>
3691       <description>AHB wait time out interrupt flag</description>
3692       <bitOffset>7</bitOffset>
3693       <bitWidth>1</bitWidth>
3694      </field>
3695      <field>
3696       <name>FS</name>
3697       <description>CSI Frame Start interrupt flag</description>
3698       <bitOffset>8</bitOffset>
3699       <bitWidth>1</bitWidth>
3700      </field>
3701      <field>
3702       <name>FE</name>
3703       <description>CSI Frame End interrupt flag</description>
3704       <bitOffset>9</bitOffset>
3705       <bitWidth>1</bitWidth>
3706      </field>
3707      <field>
3708       <name>LS</name>
3709       <description>CSI Line Start interrupt flag</description>
3710       <bitOffset>10</bitOffset>
3711       <bitWidth>1</bitWidth>
3712      </field>
3713      <field>
3714       <name>LE</name>
3715       <description>CSI Line End interrupt flag</description>
3716       <bitOffset>11</bitOffset>
3717       <bitWidth>1</bitWidth>
3718      </field>
3719      <field>
3720       <name>RAW_OVR</name>
3721       <description>Raw FIFO Overrun Interrupt Enable</description>
3722       <bitOffset>12</bitOffset>
3723       <bitWidth>1</bitWidth>
3724      </field>
3725      <field>
3726       <name>RAW_AHBERR</name>
3727       <description>Raw AHB Error Interrupt Enable</description>
3728       <bitOffset>13</bitOffset>
3729       <bitWidth>1</bitWidth>
3730      </field>
3731      <field>
3732       <name>AHBM_RDTO</name>
3733       <description>AHBM_RDTO</description>
3734       <bitOffset>24</bitOffset>
3735       <bitWidth>1</bitWidth>
3736      </field>
3737      <field>
3738       <name>AHBM_IDTO</name>
3739       <description>AHBM_IDTO</description>
3740       <bitOffset>25</bitOffset>
3741       <bitWidth>1</bitWidth>
3742      </field>
3743      <field>
3744       <name>AHBM_MAX</name>
3745       <description>AHBM_MAX</description>
3746       <bitOffset>26</bitOffset>
3747       <bitWidth>1</bitWidth>
3748      </field>
3749     </fields>
3750    </register>
3751    <register>
3752     <name>RX_EINT_PPI_IE</name>
3753     <description>RX D-PHY Interrupt Enable Register.</description>
3754     <addressOffset>0x608</addressOffset>
3755     <size>32</size>
3756     <fields>
3757      <field>
3758       <name>DL0STOP</name>
3759       <description>DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt enable.</description>
3760       <bitOffset>0</bitOffset>
3761       <bitWidth>1</bitWidth>
3762      </field>
3763      <field>
3764       <name>DL1STOP</name>
3765       <description>DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt enable.</description>
3766       <bitOffset>1</bitOffset>
3767       <bitWidth>1</bitWidth>
3768      </field>
3769      <field>
3770       <name>CL0STOP</name>
3771       <description>DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt enable.</description>
3772       <bitOffset>4</bitOffset>
3773       <bitWidth>1</bitWidth>
3774      </field>
3775      <field>
3776       <name>DL0ECONT0</name>
3777       <description>DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt enable</description>
3778       <bitOffset>6</bitOffset>
3779       <bitWidth>1</bitWidth>
3780      </field>
3781      <field>
3782       <name>DL0ECONT1</name>
3783       <description>DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt enable</description>
3784       <bitOffset>7</bitOffset>
3785       <bitWidth>1</bitWidth>
3786      </field>
3787      <field>
3788       <name>DL0ESOT</name>
3789       <description>DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt enable</description>
3790       <bitOffset>8</bitOffset>
3791       <bitWidth>1</bitWidth>
3792      </field>
3793      <field>
3794       <name>DL1ESOT</name>
3795       <description>DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt enable</description>
3796       <bitOffset>9</bitOffset>
3797       <bitWidth>1</bitWidth>
3798      </field>
3799      <field>
3800       <name>DL0ESOTS</name>
3801       <description>DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt enable</description>
3802       <bitOffset>12</bitOffset>
3803       <bitWidth>1</bitWidth>
3804      </field>
3805      <field>
3806       <name>DL1ESOTS</name>
3807       <description>DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt enable</description>
3808       <bitOffset>13</bitOffset>
3809       <bitWidth>1</bitWidth>
3810      </field>
3811      <field>
3812       <name>DL0EESC</name>
3813       <description>DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt enable</description>
3814       <bitOffset>16</bitOffset>
3815       <bitWidth>1</bitWidth>
3816      </field>
3817      <field>
3818       <name>DL1EESC</name>
3819       <description>DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt enable</description>
3820       <bitOffset>17</bitOffset>
3821       <bitWidth>1</bitWidth>
3822      </field>
3823      <field>
3824       <name>DL0ESESC</name>
3825       <description>DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable</description>
3826       <bitOffset>20</bitOffset>
3827       <bitWidth>1</bitWidth>
3828      </field>
3829      <field>
3830       <name>DL1ESESC</name>
3831       <description>DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable</description>
3832       <bitOffset>21</bitOffset>
3833       <bitWidth>1</bitWidth>
3834      </field>
3835      <field>
3836       <name>DL0ECTL</name>
3837       <description>DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt enable</description>
3838       <bitOffset>24</bitOffset>
3839       <bitWidth>1</bitWidth>
3840      </field>
3841      <field>
3842       <name>DL1ECTL</name>
3843       <description>DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt enable</description>
3844       <bitOffset>25</bitOffset>
3845       <bitWidth>1</bitWidth>
3846      </field>
3847     </fields>
3848    </register>
3849    <register>
3850     <name>RX_EINT_PPI_IF</name>
3851     <description>RX D-PHY Interrupt Flag Register.</description>
3852     <addressOffset>0x60C</addressOffset>
3853     <size>32</size>
3854     <fields>
3855      <field>
3856       <name>DL0STOP</name>
3857       <description>DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt flag.</description>
3858       <bitOffset>0</bitOffset>
3859       <bitWidth>1</bitWidth>
3860      </field>
3861      <field>
3862       <name>DL1STOP</name>
3863       <description>DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt flag.</description>
3864       <bitOffset>1</bitOffset>
3865       <bitWidth>1</bitWidth>
3866      </field>
3867      <field>
3868       <name>CL0STOP</name>
3869       <description>DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt flag.</description>
3870       <bitOffset>4</bitOffset>
3871       <bitWidth>1</bitWidth>
3872      </field>
3873      <field>
3874       <name>DL0ECONT0</name>
3875       <description>DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt flag</description>
3876       <bitOffset>6</bitOffset>
3877       <bitWidth>1</bitWidth>
3878      </field>
3879      <field>
3880       <name>DL0ECONT1</name>
3881       <description>DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt flag</description>
3882       <bitOffset>7</bitOffset>
3883       <bitWidth>1</bitWidth>
3884      </field>
3885      <field>
3886       <name>DL0ESOT</name>
3887       <description>DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt flag</description>
3888       <bitOffset>8</bitOffset>
3889       <bitWidth>1</bitWidth>
3890      </field>
3891      <field>
3892       <name>DL1ESOT</name>
3893       <description>DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt flag</description>
3894       <bitOffset>9</bitOffset>
3895       <bitWidth>1</bitWidth>
3896      </field>
3897      <field>
3898       <name>DL0ESOTS</name>
3899       <description>DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt flag</description>
3900       <bitOffset>12</bitOffset>
3901       <bitWidth>1</bitWidth>
3902      </field>
3903      <field>
3904       <name>DL1ESOTS</name>
3905       <description>DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt flag</description>
3906       <bitOffset>13</bitOffset>
3907       <bitWidth>1</bitWidth>
3908      </field>
3909      <field>
3910       <name>DL0EESC</name>
3911       <description>DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt flag</description>
3912       <bitOffset>16</bitOffset>
3913       <bitWidth>1</bitWidth>
3914      </field>
3915      <field>
3916       <name>DL1EESC</name>
3917       <description>DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt flag</description>
3918       <bitOffset>17</bitOffset>
3919       <bitWidth>1</bitWidth>
3920      </field>
3921      <field>
3922       <name>DL0ESESC</name>
3923       <description>DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag</description>
3924       <bitOffset>20</bitOffset>
3925       <bitWidth>1</bitWidth>
3926      </field>
3927      <field>
3928       <name>DL1ESESC</name>
3929       <description>DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag</description>
3930       <bitOffset>21</bitOffset>
3931       <bitWidth>1</bitWidth>
3932      </field>
3933      <field>
3934       <name>DL0ECTL</name>
3935       <description>DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt flag</description>
3936       <bitOffset>24</bitOffset>
3937       <bitWidth>1</bitWidth>
3938      </field>
3939      <field>
3940       <name>DL1ECTL</name>
3941       <description>DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt flag</description>
3942       <bitOffset>25</bitOffset>
3943       <bitWidth>1</bitWidth>
3944      </field>
3945     </fields>
3946    </register>
3947    <register>
3948     <name>RX_EINT_CTRL_IE</name>
3949     <description>RX Controller Interrupt Enable Register.</description>
3950     <addressOffset>0x610</addressOffset>
3951     <size>32</size>
3952     <fields>
3953      <field>
3954       <name>EECC2</name>
3955       <description>CSI RX ECC 2-bit Error interrupt enable.</description>
3956       <bitOffset>0</bitOffset>
3957       <bitWidth>1</bitWidth>
3958      </field>
3959      <field>
3960       <name>EECC1</name>
3961       <description>CSI RX ECC 1-bit Error interrupt enable.</description>
3962       <bitOffset>1</bitOffset>
3963       <bitWidth>1</bitWidth>
3964      </field>
3965      <field>
3966       <name>ECRC</name>
3967       <description>CSI RX CRC Error interrupt enable.</description>
3968       <bitOffset>2</bitOffset>
3969       <bitWidth>1</bitWidth>
3970      </field>
3971      <field>
3972       <name>EID</name>
3973       <description>CSI RX Packet Header Data ID Error interrupt enable</description>
3974       <bitOffset>3</bitOffset>
3975       <bitWidth>1</bitWidth>
3976      </field>
3977      <field>
3978       <name>PKTFFOV</name>
3979       <description>CSI RX Packet FIFO Overrun interrupt enable</description>
3980       <bitOffset>4</bitOffset>
3981       <bitWidth>1</bitWidth>
3982      </field>
3983      <field>
3984       <name>DL0ULPSA</name>
3985       <description>CSI Data Lane0 ULPSS Active interrupt enable</description>
3986       <bitOffset>8</bitOffset>
3987       <bitWidth>1</bitWidth>
3988      </field>
3989      <field>
3990       <name>DL1ULPSA</name>
3991       <description>CSI Data Lane1 ULPSS Active interrupt enable</description>
3992       <bitOffset>9</bitOffset>
3993       <bitWidth>1</bitWidth>
3994      </field>
3995      <field>
3996       <name>DL0ULPSM</name>
3997       <description>CSI Data Lane0 ULPSS Mark interrupt enable</description>
3998       <bitOffset>12</bitOffset>
3999       <bitWidth>1</bitWidth>
4000      </field>
4001      <field>
4002       <name>DL1ULPSM</name>
4003       <description>CSI Data Lane1 ULPSS Mark interrupt enable</description>
4004       <bitOffset>13</bitOffset>
4005       <bitWidth>1</bitWidth>
4006      </field>
4007      <field>
4008       <name>CL0ULPSA</name>
4009       <description>CSI Clock Lane0 ULPSS Active interrupt enable</description>
4010       <bitOffset>16</bitOffset>
4011       <bitWidth>1</bitWidth>
4012      </field>
4013      <field>
4014       <name>CL0ULPSM</name>
4015       <description>CSI Data Lane0 ULPSS Mark interrupt enable</description>
4016       <bitOffset>17</bitOffset>
4017       <bitWidth>1</bitWidth>
4018      </field>
4019     </fields>
4020    </register>
4021    <register>
4022     <name>RX_EINT_CTRL_IF</name>
4023     <description>RX Controller Interrupt Flag Register.</description>
4024     <addressOffset>0x614</addressOffset>
4025     <size>32</size>
4026     <fields>
4027      <field>
4028       <name>EECC2</name>
4029       <description>CSI RX ECC 2-bit Error interrupt flag.</description>
4030       <bitOffset>0</bitOffset>
4031       <bitWidth>1</bitWidth>
4032      </field>
4033      <field>
4034       <name>EECC1</name>
4035       <description>CSI RX ECC 1-bit Error interrupt flag.</description>
4036       <bitOffset>1</bitOffset>
4037       <bitWidth>1</bitWidth>
4038      </field>
4039      <field>
4040       <name>ECRC</name>
4041       <description>CSI RX CRC Error interrupt flag.</description>
4042       <bitOffset>2</bitOffset>
4043       <bitWidth>1</bitWidth>
4044      </field>
4045      <field>
4046       <name>EID</name>
4047       <description>CSI RX Packet Header Data ID Error interrupt flag</description>
4048       <bitOffset>3</bitOffset>
4049       <bitWidth>1</bitWidth>
4050      </field>
4051      <field>
4052       <name>PKTFFOV</name>
4053       <description>CSI RX Packet FIFO Overrun interrupt flag</description>
4054       <bitOffset>4</bitOffset>
4055       <bitWidth>1</bitWidth>
4056      </field>
4057      <field>
4058       <name>DL0ULPSA</name>
4059       <description>CSI Data Lane0 ULPSS Active interrupt flag</description>
4060       <bitOffset>8</bitOffset>
4061       <bitWidth>1</bitWidth>
4062      </field>
4063      <field>
4064       <name>DL1ULPSA</name>
4065       <description>CSI Data Lane1 ULPSS Active interrupt flag</description>
4066       <bitOffset>9</bitOffset>
4067       <bitWidth>1</bitWidth>
4068      </field>
4069      <field>
4070       <name>DL0ULPSM</name>
4071       <description>CSI Data Lane0 ULPSS Mark interrupt flag</description>
4072       <bitOffset>12</bitOffset>
4073       <bitWidth>1</bitWidth>
4074      </field>
4075      <field>
4076       <name>DL1ULPSM</name>
4077       <description>CSI Data Lane1 ULPSS Mark interrupt flag</description>
4078       <bitOffset>13</bitOffset>
4079       <bitWidth>1</bitWidth>
4080      </field>
4081      <field>
4082       <name>CL0ULPSA</name>
4083       <description>CSI Clock Lane0 ULPSS Active interrupt flag</description>
4084       <bitOffset>16</bitOffset>
4085       <bitWidth>1</bitWidth>
4086      </field>
4087      <field>
4088       <name>CL0ULPSM</name>
4089       <description>CSI Data Lane0 ULPSS Mark interrupt flag</description>
4090       <bitOffset>17</bitOffset>
4091       <bitWidth>1</bitWidth>
4092      </field>
4093     </fields>
4094    </register>
4095    <register>
4096     <name>PPI_STOPSTATE</name>
4097     <description>DPHY PPI Stop State Register.</description>
4098     <addressOffset>0x700</addressOffset>
4099     <size>32</size>
4100     <fields>
4101      <field>
4102       <name>DL0STOP</name>
4103       <description>CSI Data Lane0 Stop State.</description>
4104       <bitOffset>0</bitOffset>
4105       <bitWidth>1</bitWidth>
4106      </field>
4107      <field>
4108       <name>DL1STOP</name>
4109       <description>CSI Data Lane1 Stop State.</description>
4110       <bitOffset>1</bitOffset>
4111       <bitWidth>1</bitWidth>
4112      </field>
4113      <field>
4114       <name>CL0STOP</name>
4115       <description>CSI Clock Lane0 Stop State.</description>
4116       <bitOffset>2</bitOffset>
4117       <bitWidth>1</bitWidth>
4118      </field>
4119     </fields>
4120    </register>
4121    <register>
4122     <name>PPI_TURNAROUND_CFG</name>
4123     <description>DPHY PPI Turn-Around Configuration Register.</description>
4124     <addressOffset>0x704</addressOffset>
4125     <size>32</size>
4126     <fields>
4127      <field>
4128       <name>DL0TAREQ</name>
4129       <description>CSI Data Lane0 turn around request.</description>
4130       <bitOffset>0</bitOffset>
4131       <bitWidth>1</bitWidth>
4132      </field>
4133      <field>
4134       <name>DL0TADIS</name>
4135       <description>CSI Data Lane0 turn around disable.</description>
4136       <bitOffset>1</bitOffset>
4137       <bitWidth>1</bitWidth>
4138      </field>
4139      <field>
4140       <name>DL0FRCRX</name>
4141       <description>CSI Data Lane0 force RX mode.</description>
4142       <bitOffset>2</bitOffset>
4143       <bitWidth>1</bitWidth>
4144      </field>
4145     </fields>
4146    </register>
4147   </registers>
4148  </peripheral>
4149<!--CSI2 Camera Serial Interface Registers.-->
4150  <peripheral>
4151   <name>DMA</name>
4152   <description>DMA Controller Fully programmable, chaining capable DMA channels.</description>
4153   <baseAddress>0x40028000</baseAddress>
4154   <size>32</size>
4155   <addressBlock>
4156    <offset>0x00</offset>
4157    <size>0x1000</size>
4158    <usage>registers</usage>
4159   </addressBlock>
4160   <interrupt>
4161    <name>DMA0</name>
4162    <value>28</value>
4163   </interrupt>
4164   <interrupt>
4165    <name>DMA1</name>
4166    <value>29</value>
4167   </interrupt>
4168   <interrupt>
4169    <name>DMA2</name>
4170    <value>30</value>
4171   </interrupt>
4172   <interrupt>
4173    <name>DMA3</name>
4174    <value>31</value>
4175   </interrupt>
4176   <interrupt>
4177    <name>DMA4</name>
4178    <value>68</value>
4179   </interrupt>
4180   <interrupt>
4181    <name>DMA5</name>
4182    <value>69</value>
4183   </interrupt>
4184   <interrupt>
4185    <name>DMA6</name>
4186    <value>70</value>
4187   </interrupt>
4188   <interrupt>
4189    <name>DMA7</name>
4190    <value>71</value>
4191   </interrupt>
4192   <interrupt>
4193    <name>DMA8</name>
4194    <value>72</value>
4195   </interrupt>
4196   <interrupt>
4197    <name>DMA9</name>
4198    <value>73</value>
4199   </interrupt>
4200   <interrupt>
4201    <name>DMA10</name>
4202    <value>74</value>
4203   </interrupt>
4204   <interrupt>
4205    <name>DMA11</name>
4206    <value>75</value>
4207   </interrupt>
4208   <interrupt>
4209    <name>DMA12</name>
4210    <value>76</value>
4211   </interrupt>
4212   <interrupt>
4213    <name>DMA13</name>
4214    <value>77</value>
4215   </interrupt>
4216   <interrupt>
4217    <name>DMA14</name>
4218    <value>78</value>
4219   </interrupt>
4220   <interrupt>
4221    <name>DMA15</name>
4222    <value>79</value>
4223   </interrupt>
4224   <registers>
4225    <register>
4226     <name>INTEN</name>
4227     <description>DMA Control Register.</description>
4228     <addressOffset>0x000</addressOffset>
4229     <fields>
4230      <field>
4231       <name>CH0</name>
4232       <description>Channel 0 Interrupt Enable.</description>
4233       <bitOffset>0</bitOffset>
4234       <bitWidth>1</bitWidth>
4235       <enumeratedValues>
4236        <enumeratedValue>
4237         <name>dis</name>
4238         <description>Disable.</description>
4239         <value>0</value>
4240        </enumeratedValue>
4241        <enumeratedValue>
4242         <name>en</name>
4243         <description>Enable.</description>
4244         <value>1</value>
4245        </enumeratedValue>
4246       </enumeratedValues>
4247      </field>
4248      <field derivedFrom="CH0">
4249       <name>CH1</name>
4250       <description>Channel 1 Interrupt Enable.</description>
4251       <bitOffset>1</bitOffset>
4252       <bitWidth>1</bitWidth>
4253      </field>
4254      <field derivedFrom="CH0">
4255       <name>CH2</name>
4256       <description>Channel 2 Interrupt Enable.</description>
4257       <bitOffset>2</bitOffset>
4258       <bitWidth>1</bitWidth>
4259      </field>
4260      <field derivedFrom="CH0">
4261       <name>CH3</name>
4262       <description>Channel 3 Interrupt Enable.</description>
4263       <bitOffset>3</bitOffset>
4264       <bitWidth>1</bitWidth>
4265      </field>
4266      <field derivedFrom="CH0">
4267       <name>CH4</name>
4268       <description>Channel 4 Interrupt Enable.</description>
4269       <bitOffset>4</bitOffset>
4270       <bitWidth>1</bitWidth>
4271      </field>
4272      <field derivedFrom="CH0">
4273       <name>CH5</name>
4274       <description>Channel 5 Interrupt Enable.</description>
4275       <bitOffset>5</bitOffset>
4276       <bitWidth>1</bitWidth>
4277      </field>
4278      <field derivedFrom="CH0">
4279       <name>CH6</name>
4280       <description>Channel 6 Interrupt Enable.</description>
4281       <bitOffset>6</bitOffset>
4282       <bitWidth>1</bitWidth>
4283      </field>
4284      <field derivedFrom="CH0">
4285       <name>CH7</name>
4286       <description>Channel 7 Interrupt Enable.</description>
4287       <bitOffset>7</bitOffset>
4288       <bitWidth>1</bitWidth>
4289      </field>
4290     </fields>
4291    </register>
4292    <register>
4293     <name>INTFL</name>
4294     <description>DMA Interrupt Register.</description>
4295     <addressOffset>0x004</addressOffset>
4296     <access>read-only</access>
4297     <fields>
4298      <field>
4299       <name>CH0</name>
4300       <description>Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.</description>
4301       <bitOffset>0</bitOffset>
4302       <bitWidth>1</bitWidth>
4303       <enumeratedValues>
4304        <enumeratedValue>
4305         <name>inactive</name>
4306         <description>No interrupt is pending.</description>
4307         <value>0</value>
4308        </enumeratedValue>
4309        <enumeratedValue>
4310         <name>pending</name>
4311         <description>An interrupt is pending.</description>
4312         <value>1</value>
4313        </enumeratedValue>
4314       </enumeratedValues>
4315      </field>
4316      <field derivedFrom="CH0">
4317       <name>CH1</name>
4318       <bitOffset>1</bitOffset>
4319       <bitWidth>1</bitWidth>
4320      </field>
4321      <field derivedFrom="CH0">
4322       <name>CH2</name>
4323       <bitOffset>2</bitOffset>
4324       <bitWidth>1</bitWidth>
4325      </field>
4326      <field derivedFrom="CH0">
4327       <name>CH3</name>
4328       <bitOffset>3</bitOffset>
4329       <bitWidth>1</bitWidth>
4330      </field>
4331      <field derivedFrom="CH0">
4332       <name>CH4</name>
4333       <bitOffset>4</bitOffset>
4334       <bitWidth>1</bitWidth>
4335      </field>
4336      <field derivedFrom="CH0">
4337       <name>CH5</name>
4338       <bitOffset>5</bitOffset>
4339       <bitWidth>1</bitWidth>
4340      </field>
4341      <field derivedFrom="CH0">
4342       <name>CH6</name>
4343       <bitOffset>6</bitOffset>
4344       <bitWidth>1</bitWidth>
4345      </field>
4346      <field derivedFrom="CH0">
4347       <name>CH7</name>
4348       <bitOffset>7</bitOffset>
4349       <bitWidth>1</bitWidth>
4350      </field>
4351     </fields>
4352    </register>
4353    <cluster>
4354     <dim>8</dim>
4355     <dimIncrement>0x20</dimIncrement>
4356     <name>CH[%s]</name>
4357     <description>DMA Channel registers.</description>
4358     <headerStructName>dma_ch</headerStructName>
4359     <addressOffset>0x100</addressOffset>
4360     <access>read-write</access>
4361     <register>
4362      <name>CTRL</name>
4363      <description>DMA Channel Control Register.</description>
4364      <addressOffset>0x000</addressOffset>
4365      <fields>
4366       <field>
4367        <name>EN</name>
4368        <description>Channel Enable.  This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.</description>
4369        <bitOffset>0</bitOffset>
4370        <bitWidth>1</bitWidth>
4371        <enumeratedValues>
4372         <enumeratedValue>
4373          <name>dis</name>
4374          <description>Disable.</description>
4375          <value>0</value>
4376         </enumeratedValue>
4377         <enumeratedValue>
4378          <name>en</name>
4379          <description>Enable.</description>
4380          <value>1</value>
4381         </enumeratedValue>
4382        </enumeratedValues>
4383       </field>
4384       <field>
4385        <name>RLDEN</name>
4386        <description>Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.</description>
4387        <bitOffset>1</bitOffset>
4388        <bitWidth>1</bitWidth>
4389        <enumeratedValues>
4390         <enumeratedValue>
4391          <name>dis</name>
4392          <description>Disable.</description>
4393          <value>0</value>
4394         </enumeratedValue>
4395         <enumeratedValue>
4396          <name>en</name>
4397          <description>Enable.</description>
4398          <value>1</value>
4399         </enumeratedValue>
4400        </enumeratedValues>
4401       </field>
4402       <field>
4403        <name>PRI</name>
4404        <description>DMA Priority.</description>
4405        <bitOffset>2</bitOffset>
4406        <bitWidth>2</bitWidth>
4407        <enumeratedValues>
4408         <enumeratedValue>
4409          <name>high</name>
4410          <description>Highest Priority.</description>
4411          <value>0</value>
4412         </enumeratedValue>
4413         <enumeratedValue>
4414          <name>medHigh</name>
4415          <description>Medium High Priority.</description>
4416          <value>1</value>
4417         </enumeratedValue>
4418         <enumeratedValue>
4419          <name>medLow</name>
4420          <description>Medium Low Priority.</description>
4421          <value>2</value>
4422         </enumeratedValue>
4423         <enumeratedValue>
4424          <name>low</name>
4425          <description>Lowest Priority.</description>
4426          <value>3</value>
4427         </enumeratedValue>
4428        </enumeratedValues>
4429       </field>
4430       <field>
4431        <name>REQUEST</name>
4432        <description>Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.</description>
4433        <bitOffset>4</bitOffset>
4434        <bitWidth>6</bitWidth>
4435        <enumeratedValues>
4436         <enumeratedValue>
4437          <name>MEMTOMEM</name>
4438          <description>Memory To Memory</description>
4439          <value>0x00</value>
4440         </enumeratedValue>
4441         <enumeratedValue>
4442          <name>SPI1RX</name>
4443          <description>SPI1 RX</description>
4444          <value>0x01</value>
4445         </enumeratedValue>
4446         <enumeratedValue>
4447          <name>UART0RX</name>
4448          <description>UART0 RX</description>
4449          <value>0x04</value>
4450         </enumeratedValue>
4451         <enumeratedValue>
4452          <name>UART1RX</name>
4453          <description>UART1 RX</description>
4454          <value>0x05</value>
4455         </enumeratedValue>
4456         <enumeratedValue>
4457          <name>I2C0RX</name>
4458          <description>I2C0 RX</description>
4459          <value>0x07</value>
4460         </enumeratedValue>
4461         <enumeratedValue>
4462          <name>I2C1RX</name>
4463          <description>I2C1 RX</description>
4464          <value>0x08</value>
4465         </enumeratedValue>
4466         <enumeratedValue>
4467          <name>ADC</name>
4468          <description>ADC</description>
4469          <value>0x09</value>
4470         </enumeratedValue>
4471         <enumeratedValue>
4472          <name>I2C2RX</name>
4473          <description>I2C2 RX</description>
4474          <value>0x0A</value>
4475         </enumeratedValue>
4476         <enumeratedValue>
4477          <name>CSI2RX</name>
4478          <description>CSI2 RX</description>
4479          <value>0x0C</value>
4480         </enumeratedValue>
4481         <enumeratedValue>
4482          <name>PCIFRX</name>
4483          <description>PCIF RX</description>
4484          <value>0x0D</value>
4485         </enumeratedValue>
4486         <enumeratedValue>
4487          <name>UART2RX</name>
4488          <description>UART2 RX</description>
4489          <value>0x0E</value>
4490         </enumeratedValue>
4491         <enumeratedValue>
4492          <name>SPI0RX</name>
4493          <description>SPI0 RX</description>
4494          <value>0x0F</value>
4495         </enumeratedValue>
4496         <enumeratedValue>
4497          <name>AESRX</name>
4498          <description>AES RX</description>
4499          <value>0x10</value>
4500         </enumeratedValue>
4501         <enumeratedValue>
4502          <name>I2SRX</name>
4503          <description>I2S RX</description>
4504          <value>0x1E</value>
4505         </enumeratedValue>
4506         <enumeratedValue>
4507          <name>SPI1TX</name>
4508          <description>SPI1 TX</description>
4509          <value>0x21</value>
4510         </enumeratedValue>
4511         <enumeratedValue>
4512          <name>UART0TX</name>
4513          <description>UART0 TX</description>
4514          <value>0x24</value>
4515         </enumeratedValue>
4516         <enumeratedValue>
4517          <name>UART1TX</name>
4518          <description>UART1 TX</description>
4519          <value>0x25</value>
4520         </enumeratedValue>
4521         <enumeratedValue>
4522          <name>I2C0TX</name>
4523          <description>I2C0 TX</description>
4524          <value>0x27</value>
4525         </enumeratedValue>
4526         <enumeratedValue>
4527          <name>I2C1TX</name>
4528          <description>I2C1 TX</description>
4529          <value>0x28</value>
4530         </enumeratedValue>
4531         <enumeratedValue>
4532          <name>I2C2TX</name>
4533          <description>I2C2 TX</description>
4534          <value>0x2A</value>
4535         </enumeratedValue>
4536         <enumeratedValue>
4537          <name>CRCTX</name>
4538          <description>CRC TX</description>
4539          <value>0x2C</value>
4540         </enumeratedValue>
4541         <enumeratedValue>
4542          <name>UART2TX</name>
4543          <description>UART2 TX</description>
4544          <value>0x2E</value>
4545         </enumeratedValue>
4546         <enumeratedValue>
4547          <name>SPI0TX</name>
4548          <description>SPI0 TX</description>
4549          <value>0x2F</value>
4550         </enumeratedValue>
4551         <enumeratedValue>
4552          <name>AESTX</name>
4553          <description>AES TX</description>
4554          <value>0x30</value>
4555         </enumeratedValue>
4556         <enumeratedValue>
4557          <name>I2STX</name>
4558          <description>I2S TX</description>
4559          <value>0x3E</value>
4560         </enumeratedValue>
4561        </enumeratedValues>
4562       </field>
4563       <field>
4564        <name>TO_WAIT</name>
4565        <description>Request Wait Enable.  When enabled, delay timer start until DMA request transitions from active to inactive.</description>
4566        <bitOffset>10</bitOffset>
4567        <bitWidth>1</bitWidth>
4568        <enumeratedValues>
4569         <enumeratedValue>
4570          <name>dis</name>
4571          <description>Disable.</description>
4572          <value>0</value>
4573         </enumeratedValue>
4574         <enumeratedValue>
4575          <name>en</name>
4576          <description>Enable.</description>
4577          <value>1</value>
4578         </enumeratedValue>
4579        </enumeratedValues>
4580       </field>
4581       <field>
4582        <name>TO_PER</name>
4583        <description>Timeout Period Select.</description>
4584        <bitOffset>11</bitOffset>
4585        <bitWidth>3</bitWidth>
4586        <enumeratedValues>
4587         <enumeratedValue>
4588          <name>to4</name>
4589          <description>Timeout of 3 to 4 prescale clocks.</description>
4590          <value>0</value>
4591         </enumeratedValue>
4592         <enumeratedValue>
4593          <name>to8</name>
4594          <description>Timeout of 7 to 8 prescale clocks.</description>
4595          <value>1</value>
4596         </enumeratedValue>
4597         <enumeratedValue>
4598          <name>to16</name>
4599          <description>Timeout of 15 to 16 prescale clocks.</description>
4600          <value>2</value>
4601         </enumeratedValue>
4602         <enumeratedValue>
4603          <name>to32</name>
4604          <description>Timeout of 31 to 32 prescale clocks.</description>
4605          <value>3</value>
4606         </enumeratedValue>
4607         <enumeratedValue>
4608          <name>to64</name>
4609          <description>Timeout of 63 to 64 prescale clocks.</description>
4610          <value>4</value>
4611         </enumeratedValue>
4612         <enumeratedValue>
4613          <name>to128</name>
4614          <description>Timeout of 127 to 128 prescale clocks.</description>
4615          <value>5</value>
4616         </enumeratedValue>
4617         <enumeratedValue>
4618          <name>to256</name>
4619          <description>Timeout of 255 to 256 prescale clocks.</description>
4620          <value>6</value>
4621         </enumeratedValue>
4622         <enumeratedValue>
4623          <name>to512</name>
4624          <description>Timeout of 511 to 512 prescale clocks.</description>
4625          <value>7</value>
4626         </enumeratedValue>
4627        </enumeratedValues>
4628       </field>
4629       <field>
4630        <name>TO_CLKDIV</name>
4631        <description>Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.</description>
4632        <bitOffset>14</bitOffset>
4633        <bitWidth>2</bitWidth>
4634        <enumeratedValues>
4635         <enumeratedValue>
4636          <name>dis</name>
4637          <description>Disable timer.</description>
4638          <value>0</value>
4639         </enumeratedValue>
4640         <enumeratedValue>
4641          <name>div256</name>
4642          <description>hclk / 256.</description>
4643          <value>1</value>
4644         </enumeratedValue>
4645         <enumeratedValue>
4646          <name>div64k</name>
4647          <description>hclk / 64k.</description>
4648          <value>2</value>
4649         </enumeratedValue>
4650         <enumeratedValue>
4651          <name>div16M</name>
4652          <description>hclk / 16M.</description>
4653          <value>3</value>
4654         </enumeratedValue>
4655        </enumeratedValues>
4656       </field>
4657       <field>
4658        <name>SRCWD</name>
4659        <description>Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.</description>
4660        <bitOffset>16</bitOffset>
4661        <bitWidth>2</bitWidth>
4662        <enumeratedValues>
4663         <enumeratedValue>
4664          <name>byte</name>
4665          <description>Byte.</description>
4666          <value>0</value>
4667         </enumeratedValue>
4668         <enumeratedValue>
4669          <name>halfWord</name>
4670          <description>Halfword.</description>
4671          <value>1</value>
4672         </enumeratedValue>
4673         <enumeratedValue>
4674          <name>word</name>
4675          <description>Word.</description>
4676          <value>2</value>
4677         </enumeratedValue>
4678        </enumeratedValues>
4679       </field>
4680       <field>
4681        <name>SRCINC</name>
4682        <description>Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.</description>
4683        <bitOffset>18</bitOffset>
4684        <bitWidth>1</bitWidth>
4685        <enumeratedValues>
4686         <enumeratedValue>
4687          <name>dis</name>
4688          <description>Disable.</description>
4689          <value>0</value>
4690         </enumeratedValue>
4691         <enumeratedValue>
4692          <name>en</name>
4693          <description>Enable.</description>
4694          <value>1</value>
4695         </enumeratedValue>
4696        </enumeratedValues>
4697       </field>
4698       <field>
4699        <name>DSTWD</name>
4700        <description>Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).</description>
4701        <bitOffset>20</bitOffset>
4702        <bitWidth>2</bitWidth>
4703        <enumeratedValues>
4704         <enumeratedValue>
4705          <name>byte</name>
4706          <description>Byte.</description>
4707          <value>0</value>
4708         </enumeratedValue>
4709         <enumeratedValue>
4710          <name>halfWord</name>
4711          <description>Halfword.</description>
4712          <value>1</value>
4713         </enumeratedValue>
4714         <enumeratedValue>
4715          <name>word</name>
4716          <description>Word.</description>
4717          <value>2</value>
4718         </enumeratedValue>
4719        </enumeratedValues>
4720       </field>
4721       <field>
4722        <name>DSTINC</name>
4723        <description>Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.</description>
4724        <bitOffset>22</bitOffset>
4725        <bitWidth>1</bitWidth>
4726        <enumeratedValues>
4727         <enumeratedValue>
4728          <name>dis</name>
4729          <description>Disable.</description>
4730          <value>0</value>
4731         </enumeratedValue>
4732         <enumeratedValue>
4733          <name>en</name>
4734          <description>Enable.</description>
4735          <value>1</value>
4736         </enumeratedValue>
4737        </enumeratedValues>
4738       </field>
4739       <field>
4740        <name>BURST_SIZE</name>
4741        <description>Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst.  Burst size equals 1 + value stored in this field.</description>
4742        <bitOffset>24</bitOffset>
4743        <bitWidth>5</bitWidth>
4744       </field>
4745       <field>
4746        <name>DIS_IE</name>
4747        <description>Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.</description>
4748        <bitOffset>30</bitOffset>
4749        <bitWidth>1</bitWidth>
4750        <enumeratedValues>
4751         <enumeratedValue>
4752          <name>dis</name>
4753          <description>Disable.</description>
4754          <value>0</value>
4755         </enumeratedValue>
4756         <enumeratedValue>
4757          <name>en</name>
4758          <description>Enable.</description>
4759          <value>1</value>
4760         </enumeratedValue>
4761        </enumeratedValues>
4762       </field>
4763       <field>
4764        <name>CTZ_IE</name>
4765        <description>Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.</description>
4766        <bitOffset>31</bitOffset>
4767        <bitWidth>1</bitWidth>
4768        <enumeratedValues>
4769         <enumeratedValue>
4770          <name>dis</name>
4771          <description>Disable.</description>
4772          <value>0</value>
4773         </enumeratedValue>
4774         <enumeratedValue>
4775          <name>en</name>
4776          <description>Enable.</description>
4777          <value>1</value>
4778         </enumeratedValue>
4779        </enumeratedValues>
4780       </field>
4781      </fields>
4782     </register>
4783     <register>
4784      <name>STATUS</name>
4785      <description>DMA Channel Status Register.</description>
4786      <addressOffset>0x004</addressOffset>
4787      <fields>
4788       <field>
4789        <name>STATUS</name>
4790        <description>Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware,  the DMA_CFG.CHEN bit is also cleared (if not cleared already).</description>
4791        <bitOffset>0</bitOffset>
4792        <bitWidth>1</bitWidth>
4793        <access>read-only</access>
4794        <enumeratedValues>
4795         <enumeratedValue>
4796          <name>dis</name>
4797          <description>Disable.</description>
4798          <value>0</value>
4799         </enumeratedValue>
4800         <enumeratedValue>
4801          <name>en</name>
4802          <description>Enable.</description>
4803          <value>1</value>
4804         </enumeratedValue>
4805        </enumeratedValues>
4806       </field>
4807       <field>
4808        <name>IPEND</name>
4809        <description>Channel Interrupt.</description>
4810        <bitOffset>1</bitOffset>
4811        <bitWidth>1</bitWidth>
4812        <access>read-only</access>
4813        <enumeratedValues>
4814         <enumeratedValue>
4815          <name>inactive</name>
4816          <description>No interrupt is pending.</description>
4817          <value>0</value>
4818         </enumeratedValue>
4819         <enumeratedValue>
4820          <name>pending</name>
4821          <description>An interrupt is pending.</description>
4822          <value>1</value>
4823         </enumeratedValue>
4824        </enumeratedValues>
4825       </field>
4826       <field>
4827        <name>CTZ_IF</name>
4828        <description>Count-to-Zero (CTZ) Interrupt Flag</description>
4829        <bitOffset>2</bitOffset>
4830        <bitWidth>1</bitWidth>
4831        <modifiedWriteValues>oneToClear</modifiedWriteValues>
4832       </field>
4833       <field>
4834        <name>RLD_IF</name>
4835        <description>Reload Event Interrupt Flag.</description>
4836        <bitOffset>3</bitOffset>
4837        <bitWidth>1</bitWidth>
4838        <modifiedWriteValues>oneToClear</modifiedWriteValues>
4839       </field>
4840       <field>
4841        <name>BUS_ERR</name>
4842        <description>Bus Error. Indicates that an AHB abort was received and the channel has been disabled.</description>
4843        <bitOffset>4</bitOffset>
4844        <bitWidth>1</bitWidth>
4845        <modifiedWriteValues>oneToClear</modifiedWriteValues>
4846       </field>
4847       <field>
4848        <name>TO_IF</name>
4849        <description>Time-Out Event Interrupt Flag.</description>
4850        <bitOffset>6</bitOffset>
4851        <bitWidth>1</bitWidth>
4852        <modifiedWriteValues>oneToClear</modifiedWriteValues>
4853       </field>
4854      </fields>
4855     </register>
4856     <register>
4857      <name>SRC</name>
4858      <description>Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.</description>
4859      <addressOffset>0x008</addressOffset>
4860      <fields>
4861       <field>
4862        <name>ADDR</name>
4863        <bitOffset>0</bitOffset>
4864        <bitWidth>32</bitWidth>
4865       </field>
4866      </fields>
4867     </register>
4868     <register>
4869      <name>DST</name>
4870      <description>Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.</description>
4871      <addressOffset>0x00C</addressOffset>
4872      <fields>
4873       <field>
4874        <name>ADDR</name>
4875        <bitOffset>0</bitOffset>
4876        <bitWidth>32</bitWidth>
4877       </field>
4878      </fields>
4879     </register>
4880     <register>
4881      <name>CNT</name>
4882      <description>DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.</description>
4883      <addressOffset>0x010</addressOffset>
4884      <fields>
4885       <field>
4886        <name>CNT</name>
4887        <description>DMA Counter.</description>
4888        <bitOffset>0</bitOffset>
4889        <bitWidth>24</bitWidth>
4890       </field>
4891      </fields>
4892     </register>
4893     <register>
4894      <name>SRCRLD</name>
4895      <description>Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.</description>
4896      <addressOffset>0x014</addressOffset>
4897      <fields>
4898       <field>
4899        <name>ADDR</name>
4900        <description>Source Address Reload Value.</description>
4901        <bitOffset>0</bitOffset>
4902        <bitWidth>31</bitWidth>
4903       </field>
4904      </fields>
4905     </register>
4906     <register>
4907      <name>DSTRLD</name>
4908      <description>Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.</description>
4909      <addressOffset>0x018</addressOffset>
4910      <fields>
4911       <field>
4912        <name>ADDR</name>
4913        <description>Destination Address Reload Value.</description>
4914        <bitOffset>0</bitOffset>
4915        <bitWidth>31</bitWidth>
4916       </field>
4917      </fields>
4918     </register>
4919     <register>
4920      <name>CNTRLD</name>
4921      <description>DMA Channel Count Reload Register.</description>
4922      <addressOffset>0x01C</addressOffset>
4923      <fields>
4924       <field>
4925        <name>CNT</name>
4926        <description>Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.</description>
4927        <bitOffset>0</bitOffset>
4928        <bitWidth>24</bitWidth>
4929       </field>
4930       <field>
4931        <name>EN</name>
4932        <description>Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.</description>
4933        <bitOffset>31</bitOffset>
4934        <bitWidth>1</bitWidth>
4935        <enumeratedValues>
4936         <enumeratedValue>
4937          <name>dis</name>
4938          <description>Disable.</description>
4939          <value>0</value>
4940         </enumeratedValue>
4941         <enumeratedValue>
4942          <name>en</name>
4943          <description>Enable.</description>
4944          <value>1</value>
4945         </enumeratedValue>
4946        </enumeratedValues>
4947       </field>
4948      </fields>
4949     </register>
4950    </cluster>
4951   </registers>
4952  </peripheral>
4953<!--DMA DMA Controller Fully programmable, chaining capable DMA channels.-->
4954  <peripheral>
4955   <name>DVS</name>
4956   <description>Dynamic Voltage Scaling</description>
4957   <prependToName>DVS_</prependToName>
4958   <baseAddress>0x40003C00</baseAddress>
4959   <addressBlock>
4960    <offset>0x00</offset>
4961    <size>0x0030</size>
4962    <usage>registers</usage>
4963   </addressBlock>
4964   <interrupt>
4965    <name>DVS</name>
4966    <description>Dynamic Voltage Scaling Interrupt</description>
4967    <value>83</value>
4968   </interrupt>
4969   <registers>
4970    <register>
4971     <name>CTL</name>
4972     <description>Control Register</description>
4973     <addressOffset>0x00</addressOffset>
4974     <fields>
4975      <field>
4976       <name>MON_ENA</name>
4977       <description>Enable the DVS monitoring circuit</description>
4978       <bitOffset>0</bitOffset>
4979       <bitWidth>1</bitWidth>
4980      </field>
4981      <field>
4982       <name>ADJ_ENA</name>
4983       <description>Enable the power supply adjustment based on measurements</description>
4984       <bitOffset>1</bitOffset>
4985       <bitWidth>1</bitWidth>
4986      </field>
4987      <field>
4988       <name>PS_FB_DIS</name>
4989       <description>Power Supply Feedback Disable</description>
4990       <bitOffset>2</bitOffset>
4991       <bitWidth>1</bitWidth>
4992      </field>
4993      <field>
4994       <name>CTRL_TAP_ENA</name>
4995       <description>Use the TAP Select for automatic adjustment or monitoring</description>
4996       <bitOffset>3</bitOffset>
4997       <bitWidth>1</bitWidth>
4998      </field>
4999      <field>
5000       <name>PROP_DLY</name>
5001       <description>Additional delay to monitor lines</description>
5002       <bitOffset>4</bitOffset>
5003       <bitWidth>2</bitWidth>
5004      </field>
5005      <field>
5006       <name>MON_ONESHOT</name>
5007       <description>Measure delay once</description>
5008       <bitOffset>6</bitOffset>
5009       <bitWidth>1</bitWidth>
5010      </field>
5011      <field>
5012       <name>GO_DIRECT</name>
5013       <description>Operate in automatic mode or move directly</description>
5014       <bitOffset>7</bitOffset>
5015       <bitWidth>1</bitWidth>
5016      </field>
5017      <field>
5018       <name>DIRECT_REG</name>
5019       <description>Step incrementally to target voltage</description>
5020       <bitOffset>8</bitOffset>
5021       <bitWidth>1</bitWidth>
5022      </field>
5023      <field>
5024       <name>PRIME_ENA</name>
5025       <description>Include a delay line priming signal before monitoring</description>
5026       <bitOffset>9</bitOffset>
5027       <bitWidth>1</bitWidth>
5028      </field>
5029      <field>
5030       <name>LIMIT_IE</name>
5031       <description>Enable Limit Error Interrupt</description>
5032       <bitOffset>10</bitOffset>
5033       <bitWidth>1</bitWidth>
5034      </field>
5035      <field>
5036       <name>RANGE_IE</name>
5037       <description>Enable Range Error Interrupt</description>
5038       <bitOffset>11</bitOffset>
5039       <bitWidth>1</bitWidth>
5040      </field>
5041      <field>
5042       <name>ADJ_IE</name>
5043       <description>Enable Adjustment Error Interrupt</description>
5044       <bitOffset>12</bitOffset>
5045       <bitWidth>1</bitWidth>
5046      </field>
5047      <field>
5048       <name>REF_SEL</name>
5049       <description>Select TAP used for voltage adjustment</description>
5050       <bitOffset>13</bitOffset>
5051       <bitWidth>4</bitWidth>
5052      </field>
5053      <field>
5054       <name>INC_VAL</name>
5055       <description>Step size to increment voltage when in automatic mode</description>
5056       <bitOffset>17</bitOffset>
5057       <bitWidth>3</bitWidth>
5058      </field>
5059      <field>
5060       <name>DVS_PS_APB_DIS</name>
5061       <description>Prevent the application code from adjusting Vcore</description>
5062       <bitOffset>20</bitOffset>
5063       <bitWidth>1</bitWidth>
5064      </field>
5065      <field>
5066       <name>DVS_HI_RANGE_ANY</name>
5067       <description>Any high range signal from a delay line will cause a voltage adjustment</description>
5068       <bitOffset>21</bitOffset>
5069       <bitWidth>1</bitWidth>
5070      </field>
5071      <field>
5072       <name>FB_TO_IE</name>
5073       <description>Enable Voltage Adjustment Timeout Interrupt</description>
5074       <bitOffset>22</bitOffset>
5075       <bitWidth>1</bitWidth>
5076      </field>
5077      <field>
5078       <name>FC_LV_IE</name>
5079       <description>Enable Low Voltage Interrupt</description>
5080       <bitOffset>23</bitOffset>
5081       <bitWidth>1</bitWidth>
5082      </field>
5083      <field>
5084       <name>PD_ACK_ENA</name>
5085       <description>Prevent DVS from ack'ing a request to enter a low power mode until in the idle state</description>
5086       <bitOffset>24</bitOffset>
5087       <bitWidth>1</bitWidth>
5088      </field>
5089      <field>
5090       <name>ADJ_ABORT</name>
5091       <description>Causes the DVS to enter the idle state immediately on a request to enter a low power mode</description>
5092       <bitOffset>25</bitOffset>
5093       <bitWidth>1</bitWidth>
5094      </field>
5095     </fields>
5096    </register>
5097    <register>
5098     <name>STAT</name>
5099     <description>Status Fields</description>
5100     <addressOffset>0x04</addressOffset>
5101     <resetValue>0x00000000</resetValue>
5102     <fields>
5103      <field>
5104       <name>DVS_STATE</name>
5105       <description>State machine state</description>
5106       <bitOffset>0</bitOffset>
5107       <bitWidth>4</bitWidth>
5108      </field>
5109      <field>
5110       <name>ADJ_UP_ENA</name>
5111       <description>DVS Raising voltage</description>
5112       <bitOffset>4</bitOffset>
5113       <bitWidth>1</bitWidth>
5114      </field>
5115      <field>
5116       <name>ADJ_DWN_ENA</name>
5117       <description>DVS Lowering voltage</description>
5118       <bitOffset>5</bitOffset>
5119       <bitWidth>1</bitWidth>
5120      </field>
5121      <field>
5122       <name>ADJ_ACTIVE</name>
5123       <description>Adjustment to a Direct Voltage</description>
5124       <bitOffset>6</bitOffset>
5125       <bitWidth>1</bitWidth>
5126      </field>
5127      <field>
5128       <name>CTR_TAP_OK</name>
5129       <description>Tap Enabled and the Tap is withing Hi/Low limits</description>
5130       <bitOffset>7</bitOffset>
5131       <bitWidth>1</bitWidth>
5132      </field>
5133      <field>
5134       <name>CTR_TAP_SEL</name>
5135       <description>Status of selected center tap delay line detect output</description>
5136       <bitOffset>8</bitOffset>
5137       <bitWidth>1</bitWidth>
5138      </field>
5139      <field>
5140       <name>SLOW_TRIP_DET</name>
5141       <description>Provides the current combined status of all selected Low Range delay lines</description>
5142       <bitOffset>9</bitOffset>
5143       <bitWidth>1</bitWidth>
5144      </field>
5145      <field>
5146       <name>FAST_TRIP_DET</name>
5147       <description>Provides the current combined status of all selected High Range delay lines</description>
5148       <bitOffset>10</bitOffset>
5149       <bitWidth>1</bitWidth>
5150      </field>
5151      <field>
5152       <name>PS_IN_RANGE</name>
5153       <description>Indicates if the power supply is in range</description>
5154       <bitOffset>11</bitOffset>
5155       <bitWidth>1</bitWidth>
5156      </field>
5157      <field>
5158       <name>PS_VCNTR</name>
5159       <description>Voltage Count value sent to the power supply</description>
5160       <bitOffset>12</bitOffset>
5161       <bitWidth>7</bitWidth>
5162      </field>
5163      <field>
5164       <name>MON_DLY_OK</name>
5165       <description>Indicates the monitor delay count is at 0</description>
5166       <bitOffset>19</bitOffset>
5167       <bitWidth>1</bitWidth>
5168      </field>
5169      <field>
5170       <name>ADJ_DLY_OK</name>
5171       <description>Indicates the adjustment delay count is at 0</description>
5172       <bitOffset>20</bitOffset>
5173       <bitWidth>1</bitWidth>
5174      </field>
5175      <field>
5176       <name>LO_LIMIT_DET</name>
5177       <description>Power supply voltage counter is at low limit</description>
5178       <bitOffset>21</bitOffset>
5179       <bitWidth>1</bitWidth>
5180      </field>
5181      <field>
5182       <name>HI_LIMIT_DET</name>
5183       <description>Power supply voltage counter is at high limit</description>
5184       <bitOffset>22</bitOffset>
5185       <bitWidth>1</bitWidth>
5186      </field>
5187      <field>
5188       <name>VALID_TAP</name>
5189       <description>At least one delay line has been enabled</description>
5190       <bitOffset>23</bitOffset>
5191       <bitWidth>1</bitWidth>
5192      </field>
5193      <field>
5194       <name>LIMIT_ERR</name>
5195       <description>Interrupt flag that indicates a voltage count is at/beyond manufacturer limits</description>
5196       <bitOffset>24</bitOffset>
5197       <bitWidth>1</bitWidth>
5198      </field>
5199      <field>
5200       <name>RANGE_ERR</name>
5201       <description>Interrupt flag that indicates a tap has an invalid value</description>
5202       <bitOffset>25</bitOffset>
5203       <bitWidth>1</bitWidth>
5204      </field>
5205      <field>
5206       <name>ADJ_ERR</name>
5207       <description>Interrupt flag that indicates up and down adjustment requested simultaneously</description>
5208       <bitOffset>26</bitOffset>
5209       <bitWidth>1</bitWidth>
5210      </field>
5211      <field>
5212       <name>REF_SEL_ERR</name>
5213       <description>Indicates the ref select register  bit is out of range</description>
5214       <bitOffset>27</bitOffset>
5215       <bitWidth>1</bitWidth>
5216      </field>
5217      <field>
5218       <name>FB_TO_ERR</name>
5219       <description>Interrupt flag that indicates a timeout while adjusting the voltage</description>
5220       <bitOffset>28</bitOffset>
5221       <bitWidth>1</bitWidth>
5222      </field>
5223      <field>
5224       <name>FB_TO_ERR_S</name>
5225       <description>Interrupt flag that mirror FB_TO_ERR and is write one clear</description>
5226       <bitOffset>29</bitOffset>
5227       <bitWidth>1</bitWidth>
5228      </field>
5229      <field>
5230       <name>FC_LV_DET_INT</name>
5231       <description>Interrupt flag that indicates the power supply voltage requested is below the low threshold</description>
5232       <bitOffset>30</bitOffset>
5233       <bitWidth>1</bitWidth>
5234      </field>
5235      <field>
5236       <name>FC_LV_DET_S</name>
5237       <description>Interrupt flag that mirrors FC_LV_DET_INT</description>
5238       <bitOffset>31</bitOffset>
5239       <bitWidth>1</bitWidth>
5240      </field>
5241     </fields>
5242    </register>
5243    <register>
5244     <name>DIRECT</name>
5245     <description>Direct control of target voltage</description>
5246     <addressOffset>0x08</addressOffset>
5247     <fields>
5248      <field>
5249       <name>VOLTAGE</name>
5250       <description>Sets the target power supply value</description>
5251       <bitOffset>0</bitOffset>
5252       <bitWidth>7</bitWidth>
5253      </field>
5254     </fields>
5255    </register>
5256    <register>
5257     <name>MON</name>
5258     <description>Monitor Delay</description>
5259     <addressOffset>0x00C</addressOffset>
5260     <fields>
5261      <field>
5262       <name>DLY</name>
5263       <description>Number of prescaled clocks between delay line samples</description>
5264       <bitOffset>0</bitOffset>
5265       <bitWidth>24</bitWidth>
5266      </field>
5267      <field>
5268       <name>PRE</name>
5269       <description>Number of clocks before DVS_MON_DLY is decremented</description>
5270       <bitOffset>24</bitOffset>
5271       <bitWidth>8</bitWidth>
5272      </field>
5273     </fields>
5274    </register>
5275    <register>
5276     <name>ADJ_UP</name>
5277     <description>Up Delay Register</description>
5278     <addressOffset>0x010</addressOffset>
5279     <fields>
5280      <field>
5281       <name>DLY</name>
5282       <description>Number of prescaled clocks between updates of the adjustment delay counter</description>
5283       <bitOffset>0</bitOffset>
5284       <bitWidth>16</bitWidth>
5285      </field>
5286      <field>
5287       <name>PRE</name>
5288       <description>Number of clocks before DVS_ADJ_UP_DLY is decremented</description>
5289       <bitOffset>16</bitOffset>
5290       <bitWidth>8</bitWidth>
5291      </field>
5292     </fields>
5293    </register>
5294    <register>
5295     <name>ADJ_DWN</name>
5296     <description>Down Delay Register</description>
5297     <addressOffset>0x014</addressOffset>
5298     <fields>
5299      <field>
5300       <name>DLY</name>
5301       <description>Number of prescaled clocks between updates of the adjustment delay counter</description>
5302       <bitOffset>0</bitOffset>
5303       <bitWidth>16</bitWidth>
5304      </field>
5305      <field>
5306       <name>PRE</name>
5307       <description>Number of clocks before DVS_ADJ_DWN_DLY is decremented</description>
5308       <bitOffset>16</bitOffset>
5309       <bitWidth>8</bitWidth>
5310      </field>
5311     </fields>
5312    </register>
5313    <register>
5314     <name>THRES_CMP</name>
5315     <description>Up Delay Register</description>
5316     <addressOffset>0x018</addressOffset>
5317     <fields>
5318      <field>
5319       <name>VCNTR_THRES_CNT</name>
5320       <description>Value used to determine 'low voltage' range</description>
5321       <bitOffset>0</bitOffset>
5322       <bitWidth>7</bitWidth>
5323      </field>
5324      <field>
5325       <name>VCNTR_THRES_MASK</name>
5326       <description>Mask applied to threshold and vcount to determine if the device is in a low voltage range</description>
5327       <bitOffset>8</bitOffset>
5328       <bitWidth>7</bitWidth>
5329      </field>
5330     </fields>
5331    </register>
5332    <register>
5333     <dim>5</dim>
5334     <dimIncrement>4</dimIncrement>
5335     <name>TAP_SEL[%s]</name>
5336     <description>DVS Tap Select Register</description>
5337     <addressOffset>0x1C</addressOffset>
5338     <fields>
5339      <field>
5340       <name>LO</name>
5341       <description>Select delay line tap for lower bound of auto adjustment</description>
5342       <bitOffset>0</bitOffset>
5343       <bitWidth>5</bitWidth>
5344      </field>
5345      <field>
5346       <name>LO_TAP_STAT</name>
5347       <description>Returns last delay line tap value</description>
5348       <bitOffset>5</bitOffset>
5349       <bitWidth>1</bitWidth>
5350      </field>
5351      <field>
5352       <name>CTR_TAP_STAT</name>
5353       <description>Returns last delay line tap value</description>
5354       <bitOffset>6</bitOffset>
5355       <bitWidth>1</bitWidth>
5356      </field>
5357      <field>
5358       <name>HI_TAP_STAT</name>
5359       <description>Returns last delay line tap value</description>
5360       <bitOffset>7</bitOffset>
5361       <bitWidth>1</bitWidth>
5362      </field>
5363      <field>
5364       <name>HI</name>
5365       <description>Selects delay line tap for high point of auto adjustment</description>
5366       <bitOffset>8</bitOffset>
5367       <bitWidth>5</bitWidth>
5368      </field>
5369      <field>
5370       <name>CTR</name>
5371       <description>Selects delay line tap for center point of auto adjustment</description>
5372       <bitOffset>16</bitOffset>
5373       <bitWidth>5</bitWidth>
5374      </field>
5375      <field>
5376       <name>COARSE</name>
5377       <description>Selects delay line tap for coarse or fixed delay portion of the line</description>
5378       <bitOffset>24</bitOffset>
5379       <bitWidth>3</bitWidth>
5380      </field>
5381      <field>
5382       <name>DET_DLY</name>
5383       <description>Number of HCLK between delay line launch and sampling</description>
5384       <bitOffset>29</bitOffset>
5385       <bitWidth>2</bitWidth>
5386      </field>
5387      <field>
5388       <name>DELAY_ACT</name>
5389       <description>Set if the delay is active</description>
5390       <bitOffset>31</bitOffset>
5391       <bitWidth>1</bitWidth>
5392      </field>
5393     </fields>
5394    </register>
5395   </registers>
5396  </peripheral>
5397<!--DVS Dynamic Voltage Scaling-->
5398  <peripheral>
5399   <name>FCR</name>
5400   <description>Function Control Register.</description>
5401   <baseAddress>0x40000800</baseAddress>
5402   <addressBlock>
5403    <offset>0x00</offset>
5404    <size>0x400</size>
5405    <usage>registers</usage>
5406   </addressBlock>
5407   <registers>
5408    <register>
5409     <name>FCTRL0</name>
5410     <description>Function Control 0.</description>
5411     <addressOffset>0x00</addressOffset>
5412     <access>read-write</access>
5413     <fields>
5414      <field>
5415       <name>USBCLKSEL</name>
5416       <description>USB Core Clock Select.</description>
5417       <bitOffset>16</bitOffset>
5418       <bitWidth>2</bitWidth>
5419      </field>
5420      <field>
5421       <name>I2C0DGEN0</name>
5422       <description>I2C0 SDA Pad Deglitcher enable.</description>
5423       <bitOffset>20</bitOffset>
5424       <bitWidth>1</bitWidth>
5425       <enumeratedValues>
5426        <enumeratedValue>
5427         <name>dis</name>
5428         <description>Deglitcher disabled.</description>
5429         <value>0</value>
5430        </enumeratedValue>
5431        <enumeratedValue>
5432         <name>en</name>
5433         <description>Deglitcher enabled.</description>
5434         <value>1</value>
5435        </enumeratedValue>
5436       </enumeratedValues>
5437      </field>
5438      <field>
5439       <name>I2C0DGEN1</name>
5440       <description>I2C0 SCL Pad Deglitcher enable.</description>
5441       <bitOffset>21</bitOffset>
5442       <bitWidth>1</bitWidth>
5443       <enumeratedValues>
5444        <enumeratedValue>
5445         <name>dis</name>
5446         <description>Deglitcher disabled.</description>
5447         <value>0</value>
5448        </enumeratedValue>
5449        <enumeratedValue>
5450         <name>en</name>
5451         <description>Deglitcher enabled.</description>
5452         <value>1</value>
5453        </enumeratedValue>
5454       </enumeratedValues>
5455      </field>
5456      <field>
5457       <name>I2C1DGEN0</name>
5458       <description>I2C1 SDA Pad Deglitcher enable.</description>
5459       <bitOffset>22</bitOffset>
5460       <bitWidth>1</bitWidth>
5461       <enumeratedValues>
5462        <enumeratedValue>
5463         <name>dis</name>
5464         <description>Deglitcher disabled.</description>
5465         <value>0</value>
5466        </enumeratedValue>
5467        <enumeratedValue>
5468         <name>en</name>
5469         <description>Deglitcher enabled.</description>
5470         <value>1</value>
5471        </enumeratedValue>
5472       </enumeratedValues>
5473      </field>
5474      <field>
5475       <name>I2C1DGEN1</name>
5476       <description>I2C1 SCL Pad Deglitcher enable.</description>
5477       <bitOffset>23</bitOffset>
5478       <bitWidth>1</bitWidth>
5479       <enumeratedValues>
5480        <enumeratedValue>
5481         <name>dis</name>
5482         <description>Deglitcher disabled.</description>
5483         <value>0</value>
5484        </enumeratedValue>
5485        <enumeratedValue>
5486         <name>en</name>
5487         <description>Deglitcher enabled.</description>
5488         <value>1</value>
5489        </enumeratedValue>
5490       </enumeratedValues>
5491      </field>
5492      <field>
5493       <name>I2C2DGEN0</name>
5494       <description>I2C2 SDA Pad Deglitcher enable.</description>
5495       <bitOffset>24</bitOffset>
5496       <bitWidth>1</bitWidth>
5497       <enumeratedValues>
5498        <enumeratedValue>
5499         <name>dis</name>
5500         <description>Deglitcher disabled.</description>
5501         <value>0</value>
5502        </enumeratedValue>
5503        <enumeratedValue>
5504         <name>en</name>
5505         <description>Deglitcher enabled.</description>
5506         <value>1</value>
5507        </enumeratedValue>
5508       </enumeratedValues>
5509      </field>
5510      <field>
5511       <name>I2C2DGEN1</name>
5512       <description>I2C2 SCL Pad Deglitcher enable.</description>
5513       <bitOffset>25</bitOffset>
5514       <bitWidth>1</bitWidth>
5515       <enumeratedValues>
5516        <enumeratedValue>
5517         <name>dis</name>
5518         <description>Deglitcher disabled.</description>
5519         <value>0</value>
5520        </enumeratedValue>
5521        <enumeratedValue>
5522         <name>en</name>
5523         <description>Deglitcher enabled.</description>
5524         <value>1</value>
5525        </enumeratedValue>
5526       </enumeratedValues>
5527      </field>
5528     </fields>
5529    </register>
5530    <register>
5531     <name>AUTOCAL0</name>
5532     <description>Automatic Calibration 0.</description>
5533     <addressOffset>0x04</addressOffset>
5534     <access>read-write</access>
5535     <fields>
5536      <field>
5537       <name>ACEN</name>
5538       <description>Auto-calibration Enable.</description>
5539       <bitOffset>0</bitOffset>
5540       <bitWidth>1</bitWidth>
5541       <enumeratedValues>
5542        <enumeratedValue>
5543         <name>dis</name>
5544         <description>Disabled.</description>
5545         <value>0</value>
5546        </enumeratedValue>
5547        <enumeratedValue>
5548         <name>en</name>
5549         <description>Enabled.</description>
5550         <value>1</value>
5551        </enumeratedValue>
5552       </enumeratedValues>
5553      </field>
5554      <field>
5555       <name>ACRUN</name>
5556       <description>Autocalibration Run.</description>
5557       <bitOffset>1</bitOffset>
5558       <bitWidth>1</bitWidth>
5559       <enumeratedValues>
5560        <enumeratedValue>
5561         <name>not</name>
5562         <description>Not Running.</description>
5563         <value>0</value>
5564        </enumeratedValue>
5565        <enumeratedValue>
5566         <name>run</name>
5567         <description>Running.</description>
5568         <value>1</value>
5569        </enumeratedValue>
5570       </enumeratedValues>
5571      </field>
5572      <field>
5573       <name>LDTRM</name>
5574       <description>Load Trim.</description>
5575       <bitOffset>2</bitOffset>
5576       <bitWidth>1</bitWidth>
5577      </field>
5578      <field>
5579       <name>GAININV</name>
5580       <description>Invert Gain.</description>
5581       <bitOffset>3</bitOffset>
5582       <bitWidth>1</bitWidth>
5583       <enumeratedValues>
5584        <enumeratedValue>
5585         <name>not</name>
5586         <description>Not Running.</description>
5587         <value>0</value>
5588        </enumeratedValue>
5589        <enumeratedValue>
5590         <name>run</name>
5591         <description>Running.</description>
5592         <value>1</value>
5593        </enumeratedValue>
5594       </enumeratedValues>
5595      </field>
5596      <field>
5597       <name>ATOMIC</name>
5598       <description>Atomic mode.</description>
5599       <bitOffset>4</bitOffset>
5600       <bitWidth>1</bitWidth>
5601       <enumeratedValues>
5602        <enumeratedValue>
5603         <name>not</name>
5604         <description>Not Running.</description>
5605         <value>0</value>
5606        </enumeratedValue>
5607        <enumeratedValue>
5608         <name>run</name>
5609         <description>Running.</description>
5610         <value>1</value>
5611        </enumeratedValue>
5612       </enumeratedValues>
5613      </field>
5614      <field>
5615       <name>MU</name>
5616       <description>MU value.</description>
5617       <bitOffset>8</bitOffset>
5618       <bitWidth>12</bitWidth>
5619      </field>
5620      <field>
5621       <name>HIRC96MACTMROUT</name>
5622       <description>HIRC96M Trim Value.</description>
5623       <bitOffset>23</bitOffset>
5624       <bitWidth>9</bitWidth>
5625      </field>
5626     </fields>
5627    </register>
5628    <register>
5629     <name>AUTOCAL1</name>
5630     <description>Automatic Calibration 1.</description>
5631     <addressOffset>0x08</addressOffset>
5632     <access>read-write</access>
5633     <fields>
5634      <field>
5635       <name>INITTRM</name>
5636       <description>Initial Trim Setting.</description>
5637       <bitOffset>0</bitOffset>
5638       <bitWidth>9</bitWidth>
5639      </field>
5640     </fields>
5641    </register>
5642    <register>
5643     <name>AUTOCAL2</name>
5644     <description>Automatic Calibration 2</description>
5645     <addressOffset>0x0C</addressOffset>
5646     <access>read-write</access>
5647     <fields>
5648      <field>
5649       <name>DONECNT</name>
5650       <description>Auto-callibration Done Counter Setting.</description>
5651       <bitOffset>0</bitOffset>
5652       <bitWidth>8</bitWidth>
5653      </field>
5654      <field>
5655       <name>ACDIV</name>
5656       <description>Auto-callibration Div Setting.</description>
5657       <bitOffset>8</bitOffset>
5658       <bitWidth>13</bitWidth>
5659      </field>
5660     </fields>
5661    </register>
5662    <register>
5663     <name>URVBOOTADDR</name>
5664     <description>RISC-V Boot Address.</description>
5665     <addressOffset>0x10</addressOffset>
5666     <access>read-write</access>
5667    </register>
5668    <register>
5669     <name>URVCTRL</name>
5670     <description>RISC-V Control Register.</description>
5671     <addressOffset>0x14</addressOffset>
5672     <access>read-write</access>
5673     <fields>
5674      <field>
5675       <name>MEMSEL</name>
5676       <description>RAM2, RAM3 exclusive ownership.</description>
5677       <bitOffset>0</bitOffset>
5678       <bitWidth>1</bitWidth>
5679      </field>
5680      <field>
5681       <name>IFLUSHEN</name>
5682       <description>URV instruction flush enable.</description>
5683       <bitOffset>1</bitOffset>
5684       <bitWidth>1</bitWidth>
5685      </field>
5686     </fields>
5687    </register>
5688    <register>
5689     <name>XO32MKS</name>
5690     <description>RISC-V Control Register.</description>
5691     <addressOffset>0x18</addressOffset>
5692     <access>read-write</access>
5693     <fields>
5694      <field>
5695       <name>CLK</name>
5696       <description>Kick Start XO Counter Setting</description>
5697       <bitOffset>0</bitOffset>
5698       <bitWidth>7</bitWidth>
5699      </field>
5700      <field>
5701       <name>EN</name>
5702       <description>Kick Start XO Enable</description>
5703       <bitOffset>7</bitOffset>
5704       <bitWidth>1</bitWidth>
5705      </field>
5706      <field>
5707       <name>DRIVER</name>
5708       <description>Kick Start XO Driver</description>
5709       <bitOffset>8</bitOffset>
5710       <bitWidth>3</bitWidth>
5711      </field>
5712      <field>
5713       <name>PULSE</name>
5714       <description>Kick Start XO 2X Pulse</description>
5715       <bitOffset>11</bitOffset>
5716       <bitWidth>1</bitWidth>
5717      </field>
5718      <field>
5719       <name>CLKSEL</name>
5720       <description>Kick Start XO Clock Select</description>
5721       <bitOffset>12</bitOffset>
5722       <bitWidth>2</bitWidth>
5723       <enumeratedValues>
5724        <enumeratedValue>
5725         <name>none</name>
5726         <description>No kick start clock.</description>
5727         <value>0</value>
5728        </enumeratedValue>
5729        <enumeratedValue>
5730         <name>test</name>
5731         <description>Test Clock in P1.2 (TMR3[22]=1).</description>
5732         <value>1</value>
5733        </enumeratedValue>
5734        <enumeratedValue>
5735         <name>ISO</name>
5736         <description>Internal secondary oscilator</description>
5737         <value>2</value>
5738        </enumeratedValue>
5739        <enumeratedValue>
5740         <name>IPO</name>
5741         <description>Internal Primary Oscilator</description>
5742         <value>3</value>
5743        </enumeratedValue>
5744       </enumeratedValues>
5745      </field>
5746     </fields>
5747    </register>
5748    <register>
5749     <name>TS0</name>
5750     <description>Temp Sensor trim0</description>
5751     <addressOffset>0x20</addressOffset>
5752     <access>read-write</access>
5753     <fields>
5754      <field>
5755       <name>GAIN</name>
5756       <description>Unsigned gain for temp sensor normalization Temp degrees C = (ADC result * TS_GAIN) + TS_OFFSET.</description>
5757       <bitOffset>0</bitOffset>
5758       <bitWidth>12</bitWidth>
5759      </field>
5760     </fields>
5761    </register>
5762    <register>
5763     <name>TS1</name>
5764     <description>Temp Sensor trim1</description>
5765     <addressOffset>0x24</addressOffset>
5766     <access>read-write</access>
5767     <fields>
5768      <field>
5769       <name>OFFSET</name>
5770       <description>Signed gain for temp sensor normalization Temp degrees C = (ADC result * TS_GAIN) + TS_OFFSET.</description>
5771       <bitOffset>0</bitOffset>
5772       <bitWidth>14</bitWidth>
5773      </field>
5774      <field>
5775       <name>TS_OFFSET_SIGN</name>
5776       <description>Sign extension of TS_OFFSET[13:0]</description>
5777       <bitOffset>14</bitOffset>
5778       <bitWidth>18</bitWidth>
5779      </field>
5780     </fields>
5781    </register>
5782    <register>
5783     <name>ADCREFTRIM0</name>
5784     <description>Temp Sensor trim1</description>
5785     <addressOffset>0x28</addressOffset>
5786     <access>read-write</access>
5787     <fields>
5788      <field>
5789       <name>VREFP</name>
5790       <description>Trimming code for VREFP output of reference buffer</description>
5791       <bitOffset>0</bitOffset>
5792       <bitWidth>7</bitWidth>
5793      </field>
5794      <field>
5795       <name>VREFM</name>
5796       <description>Trimming code for VREFM output of reference buffer</description>
5797       <bitOffset>8</bitOffset>
5798       <bitWidth>7</bitWidth>
5799      </field>
5800      <field>
5801       <name>VCM</name>
5802       <description>Trimming code for VCM output of reference buffer</description>
5803       <bitOffset>16</bitOffset>
5804       <bitWidth>2</bitWidth>
5805      </field>
5806      <field>
5807       <name>VX2_TUNE</name>
5808       <description>Controls tuning capacitor in fine DAC (offset binary)</description>
5809       <bitOffset>24</bitOffset>
5810       <bitWidth>6</bitWidth>
5811      </field>
5812     </fields>
5813    </register>
5814    <register>
5815     <name>ADCREFTRIM1</name>
5816     <description>Temp Sensor trim1</description>
5817     <addressOffset>0x2C</addressOffset>
5818     <access>read-write</access>
5819     <fields>
5820      <field>
5821       <name>VREFP</name>
5822       <description>Trimming code for VREFP output of reference buffer</description>
5823       <bitOffset>0</bitOffset>
5824       <bitWidth>7</bitWidth>
5825      </field>
5826      <field>
5827       <name>VREFM</name>
5828       <description>Trimming code for VREFM output of reference buffer</description>
5829       <bitOffset>8</bitOffset>
5830       <bitWidth>7</bitWidth>
5831      </field>
5832      <field>
5833       <name>VCM</name>
5834       <description>Trimming code for VCM output of reference buffer</description>
5835       <bitOffset>16</bitOffset>
5836       <bitWidth>2</bitWidth>
5837      </field>
5838      <field>
5839       <name>VX2_TUNE</name>
5840       <description>Controls tuning capacitor in fine DAC (offset binary)</description>
5841       <bitOffset>24</bitOffset>
5842       <bitWidth>6</bitWidth>
5843      </field>
5844     </fields>
5845    </register>
5846    <register>
5847     <name>ADCREFTRIM2</name>
5848     <description>Temp Sensor trim1</description>
5849     <addressOffset>0x30</addressOffset>
5850     <access>read-write</access>
5851     <fields>
5852      <field>
5853       <name>VREFP</name>
5854       <description>Trimming code for VREFP output of reference buffer</description>
5855       <bitOffset>0</bitOffset>
5856       <bitWidth>7</bitWidth>
5857      </field>
5858      <field>
5859       <name>VREFM</name>
5860       <description>Trimming code for VREFM output of reference buffer</description>
5861       <bitOffset>8</bitOffset>
5862       <bitWidth>7</bitWidth>
5863      </field>
5864      <field>
5865       <name>VCM</name>
5866       <description>Trimming code for VCM output of reference buffer</description>
5867       <bitOffset>16</bitOffset>
5868       <bitWidth>2</bitWidth>
5869      </field>
5870      <field>
5871       <name>VX2_TUNE</name>
5872       <description>Controls tuning capacitor in fine DAC (offset binary)</description>
5873       <bitOffset>24</bitOffset>
5874       <bitWidth>6</bitWidth>
5875      </field>
5876     </fields>
5877    </register>
5878   </registers>
5879  </peripheral>
5880<!--FCR Function Control Register.-->
5881  <peripheral>
5882   <name>FLC</name>
5883   <description>Flash Memory Control.</description>
5884   <prependToName>FLSH_</prependToName>
5885   <baseAddress>0x40029000</baseAddress>
5886   <addressBlock>
5887    <offset>0x00</offset>
5888    <size>0x1000</size>
5889    <usage>registers</usage>
5890   </addressBlock>
5891   <interrupt>
5892    <name>Flash_Controller</name>
5893    <description>Flash Controller interrupt.</description>
5894    <value>23</value>
5895   </interrupt>
5896   <registers>
5897    <register>
5898     <name>ADDR</name>
5899     <description>Flash Write Address.</description>
5900     <addressOffset>0x00</addressOffset>
5901     <fields>
5902      <field>
5903       <name>ADDR</name>
5904       <description>Address for next operation.</description>
5905       <bitOffset>0</bitOffset>
5906       <bitWidth>32</bitWidth>
5907      </field>
5908     </fields>
5909    </register>
5910    <register>
5911     <name>CLKDIV</name>
5912     <description>Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.</description>
5913     <addressOffset>0x04</addressOffset>
5914     <resetValue>0x00000064</resetValue>
5915     <fields>
5916      <field>
5917       <name>CLKDIV</name>
5918       <description>Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.</description>
5919       <bitOffset>0</bitOffset>
5920       <bitWidth>8</bitWidth>
5921      </field>
5922     </fields>
5923    </register>
5924    <register>
5925     <name>CTRL</name>
5926     <description>Flash Control Register.</description>
5927     <addressOffset>0x08</addressOffset>
5928     <fields>
5929      <field>
5930       <name>WR</name>
5931       <description>Write.  This bit is automatically cleared after the operation.</description>
5932       <bitOffset>0</bitOffset>
5933       <bitWidth>1</bitWidth>
5934       <enumeratedValues>
5935        <enumeratedValue>
5936         <name>complete</name>
5937         <description>No operation/complete.</description>
5938         <value>0</value>
5939        </enumeratedValue>
5940        <enumeratedValue>
5941         <name>start</name>
5942         <description>Start operation.</description>
5943         <value>1</value>
5944        </enumeratedValue>
5945       </enumeratedValues>
5946      </field>
5947      <field derivedFrom="WR">
5948       <name>ME</name>
5949       <description>Mass Erase.  This bit is automatically cleared after the operation.</description>
5950       <bitOffset>1</bitOffset>
5951       <bitWidth>1</bitWidth>
5952      </field>
5953      <field derivedFrom="WR">
5954       <name>PGE</name>
5955       <description>Page Erase.  This bit is automatically cleared after the operation.</description>
5956       <bitOffset>2</bitOffset>
5957       <bitWidth>1</bitWidth>
5958      </field>
5959      <field>
5960       <name>WDTH</name>
5961       <description>Data Width.  This bits selects write data width.</description>
5962       <bitOffset>4</bitOffset>
5963       <bitWidth>1</bitWidth>
5964       <enumeratedValues>
5965        <enumeratedValue>
5966         <name>size128</name>
5967         <description>128-bit.</description>
5968         <value>0</value>
5969        </enumeratedValue>
5970        <enumeratedValue>
5971         <name>size32</name>
5972         <description>32-bit.</description>
5973         <value>1</value>
5974        </enumeratedValue>
5975       </enumeratedValues>
5976      </field>
5977      <field>
5978       <name>ERASE_CODE</name>
5979       <description>Erase Code.  The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.</description>
5980       <bitOffset>8</bitOffset>
5981       <bitWidth>8</bitWidth>
5982       <enumeratedValues>
5983        <enumeratedValue>
5984         <name>nop</name>
5985         <description>No operation.</description>
5986         <value>0</value>
5987        </enumeratedValue>
5988        <enumeratedValue>
5989         <name>erasePage</name>
5990         <description>Enable Page Erase.</description>
5991         <value>0x55</value>
5992        </enumeratedValue>
5993        <enumeratedValue>
5994         <name>eraseAll</name>
5995         <description>Enable Mass Erase. The debug port must be enabled.</description>
5996         <value>0xAA</value>
5997        </enumeratedValue>
5998       </enumeratedValues>
5999      </field>
6000      <field>
6001       <name>PEND</name>
6002       <description>Flash Pending.  When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.</description>
6003       <bitOffset>24</bitOffset>
6004       <bitWidth>1</bitWidth>
6005       <access>read-only</access>
6006       <enumeratedValues>
6007        <enumeratedValue>
6008         <name>idle</name>
6009         <description>Idle.</description>
6010         <value>0</value>
6011        </enumeratedValue>
6012        <enumeratedValue>
6013         <name>busy</name>
6014         <description>Busy.</description>
6015         <value>1</value>
6016        </enumeratedValue>
6017       </enumeratedValues>
6018      </field>
6019      <field>
6020       <name>LVE</name>
6021       <description>Low Voltage enable.</description>
6022       <bitOffset>25</bitOffset>
6023       <bitWidth>1</bitWidth>
6024      </field>
6025      <field>
6026       <name>UNLOCK</name>
6027       <description>Flash Unlock.  The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.</description>
6028       <bitOffset>28</bitOffset>
6029       <bitWidth>4</bitWidth>
6030       <enumeratedValues>
6031        <enumeratedValue>
6032         <name>unlocked</name>
6033         <description>Flash Unlocked.</description>
6034         <value>2</value>
6035        </enumeratedValue>
6036        <enumeratedValue>
6037         <name>locked</name>
6038         <description>Flash Locked.</description>
6039         <value>3</value>
6040        </enumeratedValue>
6041       </enumeratedValues>
6042      </field>
6043     </fields>
6044    </register>
6045    <register>
6046     <name>INTR</name>
6047     <description>Flash Interrupt Register.</description>
6048     <addressOffset>0x24</addressOffset>
6049     <fields>
6050      <field>
6051       <name>DONE</name>
6052       <description>Flash Done Interrupt.  This bit is set to 1 upon Flash write or erase completion.</description>
6053       <bitOffset>0</bitOffset>
6054       <bitWidth>1</bitWidth>
6055       <enumeratedValues>
6056        <enumeratedValue>
6057         <name>inactive</name>
6058         <description>No interrupt is pending.</description>
6059         <value>0</value>
6060        </enumeratedValue>
6061        <enumeratedValue>
6062         <name>pending</name>
6063         <description>An interrupt is pending.</description>
6064         <value>1</value>
6065        </enumeratedValue>
6066       </enumeratedValues>
6067      </field>
6068      <field>
6069       <name>AF</name>
6070       <description>Flash Access Fail.  This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.</description>
6071       <bitOffset>1</bitOffset>
6072       <bitWidth>1</bitWidth>
6073       <enumeratedValues>
6074        <enumeratedValue>
6075         <name>noError</name>
6076         <description>No Failure.</description>
6077         <value>0</value>
6078        </enumeratedValue>
6079        <enumeratedValue>
6080         <name>error</name>
6081         <description>Failure occurs.</description>
6082         <value>1</value>
6083        </enumeratedValue>
6084       </enumeratedValues>
6085      </field>
6086      <field>
6087       <name>DONEIE</name>
6088       <description>Flash Done Interrupt Enable.</description>
6089       <bitOffset>8</bitOffset>
6090       <bitWidth>1</bitWidth>
6091       <enumeratedValues>
6092        <enumeratedValue>
6093         <name>disable</name>
6094         <description>Disable.</description>
6095         <value>0</value>
6096        </enumeratedValue>
6097        <enumeratedValue>
6098         <name>enable</name>
6099         <description>Enable.</description>
6100         <value>1</value>
6101        </enumeratedValue>
6102       </enumeratedValues>
6103      </field>
6104      <field derivedFrom="DONEIE">
6105       <name>AFIE</name>
6106       <bitOffset>9</bitOffset>
6107       <bitWidth>1</bitWidth>
6108      </field>
6109     </fields>
6110    </register>
6111    <register>
6112     <dim>4</dim>
6113     <dimIncrement>4</dimIncrement>
6114     <name>DATA[%s]</name>
6115     <description>Flash Write Data.</description>
6116     <addressOffset>0x30</addressOffset>
6117     <fields>
6118      <field>
6119       <name>DATA</name>
6120       <description>Data next operation.</description>
6121       <bitOffset>0</bitOffset>
6122       <bitWidth>32</bitWidth>
6123      </field>
6124     </fields>
6125    </register>
6126    <register>
6127     <name>ACTRL</name>
6128     <description>Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block:
6129    pflc-actrl = 0x3a7f5ca3;
6130    pflc-actrl = 0xa1e34f20;
6131    pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.</description>
6132     <addressOffset>0x40</addressOffset>
6133     <access>write-only</access>
6134     <fields>
6135      <field>
6136       <name>ACTRL</name>
6137       <description>Access control.</description>
6138       <bitOffset>0</bitOffset>
6139       <bitWidth>32</bitWidth>
6140      </field>
6141     </fields>
6142    </register>
6143    <register>
6144     <name>WELR0</name>
6145     <description>WELR0</description>
6146     <addressOffset>0x80</addressOffset>
6147     <fields>
6148      <field>
6149       <name>WELR0</name>
6150       <description>Access control.</description>
6151       <bitOffset>0</bitOffset>
6152       <bitWidth>32</bitWidth>
6153      </field>
6154     </fields>
6155    </register>
6156    <register>
6157     <name>RLR0</name>
6158     <description>RLR0</description>
6159     <addressOffset>0x84</addressOffset>
6160     <fields>
6161      <field>
6162       <name>RLR0</name>
6163       <description>Access control.</description>
6164       <bitOffset>0</bitOffset>
6165       <bitWidth>32</bitWidth>
6166      </field>
6167     </fields>
6168    </register>
6169    <register>
6170     <name>WELR1</name>
6171     <description>WELR1</description>
6172     <addressOffset>0x88</addressOffset>
6173     <fields>
6174      <field>
6175       <name>WELR1</name>
6176       <description>Access control.</description>
6177       <bitOffset>0</bitOffset>
6178       <bitWidth>32</bitWidth>
6179      </field>
6180     </fields>
6181    </register>
6182    <register>
6183     <name>RLR1</name>
6184     <description>RLR1</description>
6185     <addressOffset>0x8C</addressOffset>
6186     <fields>
6187      <field>
6188       <name>RLR1</name>
6189       <description>Access control.</description>
6190       <bitOffset>0</bitOffset>
6191       <bitWidth>32</bitWidth>
6192      </field>
6193     </fields>
6194    </register>
6195    <register>
6196     <name>WELR2</name>
6197     <description>WELR2</description>
6198     <addressOffset>90</addressOffset>
6199     <fields>
6200      <field>
6201       <name>WELR2</name>
6202       <description>Access control.</description>
6203       <bitOffset>0</bitOffset>
6204       <bitWidth>32</bitWidth>
6205      </field>
6206     </fields>
6207    </register>
6208    <register>
6209     <name>RLR2</name>
6210     <description>RLR2</description>
6211     <addressOffset>0x94</addressOffset>
6212     <fields>
6213      <field>
6214       <name>RLR2</name>
6215       <description>Access control.</description>
6216       <bitOffset>0</bitOffset>
6217       <bitWidth>32</bitWidth>
6218      </field>
6219     </fields>
6220    </register>
6221    <register>
6222     <name>WELR3</name>
6223     <description>WELR3</description>
6224     <addressOffset>0x98</addressOffset>
6225     <fields>
6226      <field>
6227       <name>WELR3</name>
6228       <description>Access control.</description>
6229       <bitOffset>0</bitOffset>
6230       <bitWidth>32</bitWidth>
6231      </field>
6232     </fields>
6233    </register>
6234    <register>
6235     <name>RLR3</name>
6236     <description>RLR3</description>
6237     <addressOffset>0x9C</addressOffset>
6238     <fields>
6239      <field>
6240       <name>RLR3</name>
6241       <description>Access control.</description>
6242       <bitOffset>0</bitOffset>
6243       <bitWidth>32</bitWidth>
6244      </field>
6245     </fields>
6246    </register>
6247    <register>
6248     <name>WELR4</name>
6249     <description>WELR4</description>
6250     <addressOffset>0xA0</addressOffset>
6251     <fields>
6252      <field>
6253       <name>WELR4</name>
6254       <description>Access control.</description>
6255       <bitOffset>0</bitOffset>
6256       <bitWidth>32</bitWidth>
6257      </field>
6258     </fields>
6259    </register>
6260    <register>
6261     <name>RLR4</name>
6262     <description>RLR4</description>
6263     <addressOffset>0xA4</addressOffset>
6264     <fields>
6265      <field>
6266       <name>RLR4</name>
6267       <description>Access control.</description>
6268       <bitOffset>0</bitOffset>
6269       <bitWidth>32</bitWidth>
6270      </field>
6271     </fields>
6272    </register>
6273   </registers>
6274  </peripheral>
6275<!--FLC Flash Memory Control.-->
6276  <peripheral>
6277   <name>GCR</name>
6278   <description>Global Control Registers.</description>
6279   <baseAddress>0x40000000</baseAddress>
6280   <addressBlock>
6281    <offset>0</offset>
6282    <size>0x400</size>
6283    <usage>registers</usage>
6284   </addressBlock>
6285   <registers>
6286    <register>
6287     <name>SYSCTRL</name>
6288     <description>System Control.</description>
6289     <addressOffset>0x00</addressOffset>
6290     <resetMask>0xFFFFFFFE</resetMask>
6291     <fields>
6292      <field>
6293       <name>BSTAPEN</name>
6294       <description>Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE.</description>
6295       <bitOffset>0</bitOffset>
6296       <bitWidth>1</bitWidth>
6297      </field>
6298      <field>
6299       <name>FLASH_PAGE_FLIP</name>
6300       <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description>
6301       <bitOffset>4</bitOffset>
6302       <bitWidth>1</bitWidth>
6303       <enumeratedValues>
6304        <enumeratedValue>
6305         <name>normal</name>
6306         <description>Physical layout matches logical layout.</description>
6307         <value>0</value>
6308        </enumeratedValue>
6309        <enumeratedValue>
6310         <name>swapped</name>
6311         <description>Bottom half mapped to logical top half and vice versa.</description>
6312         <value>1</value>
6313        </enumeratedValue>
6314       </enumeratedValues>
6315      </field>
6316      <field>
6317       <name>ICC0_FLUSH</name>
6318       <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description>
6319       <bitOffset>6</bitOffset>
6320       <bitWidth>1</bitWidth>
6321       <enumeratedValues>
6322        <enumeratedValue>
6323         <name>normal</name>
6324         <description>Normal Code Cache Operation</description>
6325         <value>0</value>
6326        </enumeratedValue>
6327        <enumeratedValue>
6328         <name>flush</name>
6329         <description>Code Caches and CPU instruction buffer are flushed </description>
6330         <value>1</value>
6331        </enumeratedValue>
6332       </enumeratedValues>
6333      </field>
6334      <field>
6335       <name>ROMDONE</name>
6336       <description>ROM_DONE status. Used to disable SWD interface during system initialization procedure</description>
6337       <bitOffset>12</bitOffset>
6338       <bitWidth>1</bitWidth>
6339      </field>
6340      <field>
6341       <name>CCHK</name>
6342       <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description>
6343       <bitOffset>13</bitOffset>
6344       <bitWidth>1</bitWidth>
6345       <enumeratedValues>
6346        <enumeratedValue>
6347         <name>complete</name>
6348         <description>No operation/complete.</description>
6349         <value>0</value>
6350        </enumeratedValue>
6351        <enumeratedValue>
6352         <name>start</name>
6353         <description>Start operation.</description>
6354         <value>1</value>
6355        </enumeratedValue>
6356       </enumeratedValues>
6357      </field>
6358      <field>
6359       <name>SWD_DIS</name>
6360       <description> Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set).</description>
6361       <bitOffset>14</bitOffset>
6362       <bitWidth>1</bitWidth>
6363      </field>
6364      <field>
6365       <name>CHKRES</name>
6366       <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description>
6367       <bitOffset>15</bitOffset>
6368       <bitWidth>1</bitWidth>
6369       <enumeratedValues>
6370        <enumeratedValue>
6371         <name>pass</name>
6372         <description>ROM Checksum Correct.</description>
6373         <value>0</value>
6374        </enumeratedValue>
6375        <enumeratedValue>
6376         <name>fail</name>
6377         <description>ROM Checksum Fail.</description>
6378         <value>1</value>
6379        </enumeratedValue>
6380       </enumeratedValues>
6381      </field>
6382      <field>
6383       <name>OVR</name>
6384       <description>Operating Voltage Range.</description>
6385       <bitOffset>16</bitOffset>
6386       <bitWidth>2</bitWidth>
6387       <enumeratedValues>
6388        <enumeratedValue>
6389         <name>V0_9</name>
6390         <description>0.9V</description>
6391         <value>0</value>
6392        </enumeratedValue>
6393        <enumeratedValue>
6394         <name>V1_0</name>
6395         <description>1.0V</description>
6396         <value>1</value>
6397        </enumeratedValue>
6398        <enumeratedValue>
6399         <name>V1_1</name>
6400         <description>1.1V</description>
6401         <value>2</value>
6402        </enumeratedValue>
6403       </enumeratedValues>
6404      </field>
6405     </fields>
6406    </register>
6407    <register>
6408     <name>RST0</name>
6409     <description>Reset.</description>
6410     <addressOffset>0x04</addressOffset>
6411     <fields>
6412      <field>
6413       <name>DMA</name>
6414       <description>DMA Reset.</description>
6415       <bitOffset>0</bitOffset>
6416       <bitWidth>1</bitWidth>
6417       <enumeratedValues>
6418        <name>reset</name>
6419        <usage>read-write</usage>
6420        <enumeratedValue>
6421         <name>reset_done</name>
6422         <description>Reset complete.</description>
6423         <value>0</value>
6424        </enumeratedValue>
6425        <enumeratedValue>
6426         <name>busy</name>
6427         <description>Starts Reset or indicates reset in progress.</description>
6428         <value>1</value>
6429        </enumeratedValue>
6430       </enumeratedValues>
6431      </field>
6432      <field derivedFrom="DMA">
6433       <name>WDT0</name>
6434       <description>Watchdog Timer 0 Reset.</description>
6435       <bitOffset>1</bitOffset>
6436       <bitWidth>1</bitWidth>
6437      </field>
6438      <field derivedFrom="DMA">
6439       <name>GPIO0</name>
6440       <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description>
6441       <bitOffset>2</bitOffset>
6442       <bitWidth>1</bitWidth>
6443      </field>
6444      <field derivedFrom="DMA">
6445       <name>GPIO1</name>
6446       <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description>
6447       <bitOffset>3</bitOffset>
6448       <bitWidth>1</bitWidth>
6449      </field>
6450      <field derivedFrom="DMA">
6451       <name>TMR0</name>
6452       <description>Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description>
6453       <bitOffset>5</bitOffset>
6454       <bitWidth>1</bitWidth>
6455      </field>
6456      <field derivedFrom="DMA">
6457       <name>TMR1</name>
6458       <description>Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description>
6459       <bitOffset>6</bitOffset>
6460       <bitWidth>1</bitWidth>
6461      </field>
6462      <field derivedFrom="DMA">
6463       <name>TMR2</name>
6464       <description>Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description>
6465       <bitOffset>7</bitOffset>
6466       <bitWidth>1</bitWidth>
6467      </field>
6468      <field derivedFrom="DMA">
6469       <name>TMR3</name>
6470       <description>Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description>
6471       <bitOffset>8</bitOffset>
6472       <bitWidth>1</bitWidth>
6473      </field>
6474      <field derivedFrom="DMA">
6475       <name>UART0</name>
6476       <description>UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description>
6477       <bitOffset>11</bitOffset>
6478       <bitWidth>1</bitWidth>
6479      </field>
6480      <field derivedFrom="DMA">
6481       <name>UART1</name>
6482       <description>UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description>
6483       <bitOffset>12</bitOffset>
6484       <bitWidth>1</bitWidth>
6485      </field>
6486      <field derivedFrom="DMA">
6487       <name>SPI1</name>
6488       <description>SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description>
6489       <bitOffset>13</bitOffset>
6490       <bitWidth>1</bitWidth>
6491      </field>
6492      <field derivedFrom="DMA">
6493       <name>I2C0</name>
6494       <description>I2C 0 Reset.</description>
6495       <bitOffset>16</bitOffset>
6496       <bitWidth>1</bitWidth>
6497      </field>
6498      <field derivedFrom="DMA">
6499       <name>RTC</name>
6500       <description>Real Time Clock Reset.</description>
6501       <bitOffset>17</bitOffset>
6502       <bitWidth>1</bitWidth>
6503      </field>
6504      <field derivedFrom="DMA">
6505       <name>SMPHR</name>
6506       <description>Semaphore Reset.</description>
6507       <bitOffset>22</bitOffset>
6508       <bitWidth>1</bitWidth>
6509      </field>
6510      <field derivedFrom="DMA">
6511       <name>USB</name>
6512       <description>USB Reset.</description>
6513       <bitOffset>23</bitOffset>
6514       <bitWidth>1</bitWidth>
6515      </field>
6516      <field derivedFrom="DMA">
6517       <name>TRNG</name>
6518       <description>TRNG Reset. This reset is only available during the manufacture testing phase.</description>
6519       <bitOffset>24</bitOffset>
6520       <bitWidth>1</bitWidth>
6521      </field>
6522      <field derivedFrom="DMA">
6523       <name>CNN</name>
6524       <description>CNN Reset.</description>
6525       <bitOffset>25</bitOffset>
6526       <bitWidth>1</bitWidth>
6527      </field>
6528      <field derivedFrom="DMA">
6529       <name>ADC</name>
6530       <description>ADC Reset.</description>
6531       <bitOffset>26</bitOffset>
6532       <bitWidth>1</bitWidth>
6533      </field>
6534      <field derivedFrom="DMA">
6535       <name>UART2</name>
6536       <description>UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.</description>
6537       <bitOffset>28</bitOffset>
6538       <bitWidth>1</bitWidth>
6539      </field>
6540      <field derivedFrom="DMA">
6541       <name>SOFT</name>
6542       <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description>
6543       <bitOffset>29</bitOffset>
6544       <bitWidth>1</bitWidth>
6545      </field>
6546      <field derivedFrom="DMA">
6547       <name>PERIPH</name>
6548       <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description>
6549       <bitOffset>30</bitOffset>
6550       <bitWidth>1</bitWidth>
6551      </field>
6552      <field derivedFrom="DMA">
6553       <name>SYS</name>
6554       <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description>
6555       <bitOffset>31</bitOffset>
6556       <bitWidth>1</bitWidth>
6557      </field>
6558     </fields>
6559    </register>
6560    <register>
6561     <name>CLKCTRL</name>
6562     <description>Clock Control.</description>
6563     <addressOffset>0x08</addressOffset>
6564     <resetValue>0x00000008</resetValue>
6565     <fields>
6566      <field>
6567       <name>SYSCLK_DIV</name>
6568       <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the IPLL0.</description>
6569       <bitOffset>6</bitOffset>
6570       <bitWidth>3</bitWidth>
6571       <enumeratedValues>
6572        <enumeratedValue>
6573         <name>div1</name>
6574         <description>Divide by 1.</description>
6575         <value>0</value>
6576        </enumeratedValue>
6577        <enumeratedValue>
6578         <name>div2</name>
6579         <description>Divide by 2.</description>
6580         <value>1</value>
6581        </enumeratedValue>
6582        <enumeratedValue>
6583         <name>div4</name>
6584         <description>Divide by 4.</description>
6585         <value>2</value>
6586        </enumeratedValue>
6587        <enumeratedValue>
6588         <name>div8</name>
6589         <description>Divide by 8.</description>
6590         <value>3</value>
6591        </enumeratedValue>
6592        <enumeratedValue>
6593         <name>div16</name>
6594         <description>Divide by 16.</description>
6595         <value>4</value>
6596        </enumeratedValue>
6597        <enumeratedValue>
6598         <name>div32</name>
6599         <description>Divide by 32.</description>
6600         <value>5</value>
6601        </enumeratedValue>
6602        <enumeratedValue>
6603         <name>div64</name>
6604         <description>Divide by 64.</description>
6605         <value>6</value>
6606        </enumeratedValue>
6607        <enumeratedValue>
6608         <name>div128</name>
6609         <description>Divide by 128.</description>
6610         <value>7</value>
6611        </enumeratedValue>
6612       </enumeratedValues>
6613      </field>
6614      <field>
6615       <name>SYSCLK_SEL</name>
6616       <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description>
6617       <bitOffset>9</bitOffset>
6618       <bitWidth>3</bitWidth>
6619       <enumeratedValues>
6620        <enumeratedValue>
6621         <name>ISO</name>
6622         <description>The internal 60 MHz oscillator is used for the system clock.</description>
6623         <value>0</value>
6624        </enumeratedValue>
6625        <enumeratedValue>
6626         <name>IPLL</name>
6627         <description>The internal 120 MHz IPLL is used for the system clock.</description>
6628         <value>1</value>
6629        </enumeratedValue>
6630        <enumeratedValue>
6631         <name>EBO</name>
6632         <description>The external 25 MHz input is used for the system clock.</description>
6633         <value>2</value>
6634        </enumeratedValue>
6635        <enumeratedValue>
6636         <name>INRO</name>
6637         <description>8 kHz LIRC is used for the system clock.</description>
6638         <value>3</value>
6639        </enumeratedValue>
6640        <enumeratedValue>
6641         <name>IPO</name>
6642         <description>The internal 100 MHz oscillator is used for the system clock.</description>
6643         <value>4</value>
6644        </enumeratedValue>
6645        <enumeratedValue>
6646         <name>IBRO</name>
6647         <description>The internal 7.3725 MHz oscillator is used for the system clock.</description>
6648         <value>5</value>
6649        </enumeratedValue>
6650        <enumeratedValue>
6651         <name>ERTCO</name>
6652         <description>External 32 kHz input is used for the system clock.</description>
6653         <value>6</value>
6654        </enumeratedValue>
6655        <enumeratedValue>
6656         <name>EXTCLK</name>
6657         <description>External clock input is used for the system clock.</description>
6658         <value>7</value>
6659        </enumeratedValue>
6660       </enumeratedValues>
6661      </field>
6662      <field>
6663       <name>SYSCLK_RDY</name>
6664       <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description>
6665       <bitOffset>13</bitOffset>
6666       <bitWidth>1</bitWidth>
6667       <access>read-only</access>
6668       <enumeratedValues>
6669        <enumeratedValue>
6670         <name>busy</name>
6671         <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description>
6672         <value>0</value>
6673        </enumeratedValue>
6674        <enumeratedValue>
6675         <name>ready</name>
6676         <description>System clock running from CLKSEL clock source.</description>
6677         <value>1</value>
6678        </enumeratedValue>
6679       </enumeratedValues>
6680      </field>
6681      <field>
6682       <name>EBO_EN</name>
6683       <description>External Base Oscillator</description>
6684       <bitOffset>16</bitOffset>
6685       <bitWidth>1</bitWidth>
6686       <enumeratedValues>
6687        <enumeratedValue>
6688         <name>dis</name>
6689         <description>Is Disabled.</description>
6690         <value>0</value>
6691        </enumeratedValue>
6692        <enumeratedValue>
6693         <name>en</name>
6694         <description>Is Enabled.</description>
6695         <value>1</value>
6696        </enumeratedValue>
6697       </enumeratedValues>
6698      </field>
6699      <field derivedFrom="EBO_EN">
6700       <name>ERTCO_EN</name>
6701       <description>32 kHz Oscillator Enable.</description>
6702       <bitOffset>17</bitOffset>
6703       <bitWidth>1</bitWidth>
6704      </field>
6705      <field derivedFrom="EBO_EN">
6706       <name>ISO_EN</name>
6707       <description>60 MHz Internal Oscillator Enable.</description>
6708       <bitOffset>18</bitOffset>
6709       <bitWidth>1</bitWidth>
6710      </field>
6711      <field derivedFrom="EBO_EN">
6712       <name>IPO_EN</name>
6713       <description>100 MHz Clock Enable.</description>
6714       <bitOffset>19</bitOffset>
6715       <bitWidth>1</bitWidth>
6716      </field>
6717      <field derivedFrom="EBO_EN">
6718       <name>IBRO_EN</name>
6719       <description>7.3725 MHz Clock Enable.</description>
6720       <bitOffset>20</bitOffset>
6721       <bitWidth>1</bitWidth>
6722      </field>
6723      <field>
6724       <name>IBRO_VS</name>
6725       <description>7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO.</description>
6726       <bitOffset>21</bitOffset>
6727       <bitWidth>1</bitWidth>
6728       <enumeratedValues>
6729        <enumeratedValue>
6730         <name>Vcor</name>
6731         <description>VCore Supply</description>
6732         <value>0</value>
6733        </enumeratedValue>
6734        <enumeratedValue>
6735         <name>1V</name>
6736         <description>Dedicated 1V regulated supply.</description>
6737         <value>1</value>
6738        </enumeratedValue>
6739       </enumeratedValues>
6740      </field>
6741      <field>
6742       <name>EBO_RDY</name>
6743       <description>External Base Oscillator Ready.</description>
6744       <bitOffset>24</bitOffset>
6745       <bitWidth>1</bitWidth>
6746       <access>read-only</access>
6747       <enumeratedValues>
6748        <enumeratedValue>
6749         <name>not</name>
6750         <description>Is not Ready.</description>
6751         <value>0</value>
6752        </enumeratedValue>
6753        <enumeratedValue>
6754         <name>ready</name>
6755         <description>Is Ready.</description>
6756         <value>1</value>
6757        </enumeratedValue>
6758       </enumeratedValues>
6759      </field>
6760      <field derivedFrom="EBO_RDY">
6761       <name>ERTCO_RDY</name>
6762       <description>32 kHz Crystal Oscillator Ready.</description>
6763       <bitOffset>25</bitOffset>
6764       <bitWidth>1</bitWidth>
6765      </field>
6766      <field derivedFrom="EBO_RDY">
6767       <name>ISO_RDY</name>
6768       <description>60 MHz Oscillator Ready.</description>
6769       <bitOffset>26</bitOffset>
6770       <bitWidth>1</bitWidth>
6771      </field>
6772      <field derivedFrom="EBO_RDY">
6773       <name>IPO_RDY</name>
6774       <description>100 MHz Clock Ready.</description>
6775       <bitOffset>27</bitOffset>
6776       <bitWidth>1</bitWidth>
6777      </field>
6778      <field derivedFrom="EBO_RDY">
6779       <name>IBRO_RDY</name>
6780       <description>7.3725 MHz HIRC Ready.</description>
6781       <bitOffset>28</bitOffset>
6782       <bitWidth>1</bitWidth>
6783      </field>
6784      <field derivedFrom="EBO_RDY">
6785       <name>INRO_RDY</name>
6786       <description>8 kHz Low Frequency Reference Clock Ready.</description>
6787       <bitOffset>29</bitOffset>
6788       <bitWidth>1</bitWidth>
6789      </field>
6790     </fields>
6791    </register>
6792    <register>
6793     <name>PM</name>
6794     <description>Power Management.</description>
6795     <addressOffset>0x0C</addressOffset>
6796     <fields>
6797      <field>
6798       <name>MODE</name>
6799       <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description>
6800       <bitOffset>0</bitOffset>
6801       <bitWidth>4</bitWidth>
6802       <enumeratedValues>
6803        <enumeratedValue>
6804         <name>active</name>
6805         <description>Active Mode.</description>
6806         <value>0</value>
6807        </enumeratedValue>
6808        <enumeratedValue>
6809         <name>sleep</name>
6810         <description>Cortex-M4 Active, RISC-V Sleep Mode.</description>
6811         <value>1</value>
6812        </enumeratedValue>
6813        <enumeratedValue>
6814         <name>standby</name>
6815         <description>Standby Mode.</description>
6816         <value>2</value>
6817        </enumeratedValue>
6818        <enumeratedValue>
6819         <name>backup</name>
6820         <description>Backup Mode.</description>
6821         <value>4</value>
6822        </enumeratedValue>
6823        <enumeratedValue>
6824         <name>lpm</name>
6825         <description>LPM or CM4 Deep Sleep Mode.</description>
6826         <value>8</value>
6827        </enumeratedValue>
6828        <enumeratedValue>
6829         <name>upm</name>
6830         <description>UPM.</description>
6831         <value>9</value>
6832        </enumeratedValue>
6833        <enumeratedValue>
6834         <name>powerdown</name>
6835         <description>Power Down Mode.</description>
6836         <value>10</value>
6837        </enumeratedValue>
6838       </enumeratedValues>
6839      </field>
6840      <field>
6841       <name>GPIO_WE</name>
6842       <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description>
6843       <bitOffset>4</bitOffset>
6844       <bitWidth>1</bitWidth>
6845       <enumeratedValues>
6846        <enumeratedValue>
6847         <name>dis</name>
6848         <description>Wake Up Disable.</description>
6849         <value>0</value>
6850        </enumeratedValue>
6851        <enumeratedValue>
6852         <name>en</name>
6853         <description>Wake Up Enable.</description>
6854         <value>1</value>
6855        </enumeratedValue>
6856       </enumeratedValues>
6857      </field>
6858      <field derivedFrom="GPIO_WE">
6859       <name>RTC_WE</name>
6860       <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description>
6861       <bitOffset>5</bitOffset>
6862       <bitWidth>1</bitWidth>
6863      </field>
6864      <field derivedFrom="GPIO_WE">
6865       <name>USB_WE</name>
6866       <description>USB Wake Up Enable. This bit enables USB IRQ as wakeup source</description>
6867       <bitOffset>6</bitOffset>
6868       <bitWidth>1</bitWidth>
6869      </field>
6870      <field derivedFrom="GPIO_WE">
6871       <name>WUT_WE</name>
6872       <description>WUT Wake Up Enable. This bit enables the Wake-Up Timer as wakeup source. </description>
6873       <bitOffset>7</bitOffset>
6874       <bitWidth>1</bitWidth>
6875      </field>
6876      <field derivedFrom="GPIO_WE">
6877       <name>AINCOMP_WE</name>
6878       <description>AIN COMP Wake Up Enable. This bit enables AIN COMP as wakeup source. </description>
6879       <bitOffset>9</bitOffset>
6880       <bitWidth>1</bitWidth>
6881      </field>
6882      <field>
6883       <name>ISO_PD</name>
6884       <description>60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode.</description>
6885       <bitOffset>15</bitOffset>
6886       <bitWidth>1</bitWidth>
6887       <enumeratedValues>
6888        <enumeratedValue>
6889         <name>active</name>
6890         <description>Mode is Active.</description>
6891         <value>0</value>
6892        </enumeratedValue>
6893        <enumeratedValue>
6894         <name>deepsleep</name>
6895         <description>Powered down in DEEPSLEEP.</description>
6896         <value>1</value>
6897        </enumeratedValue>
6898       </enumeratedValues>
6899      </field>
6900      <field derivedFrom="ISO_PD">
6901       <name>IPO_PD</name>
6902       <description>100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. </description>
6903       <bitOffset>16</bitOffset>
6904       <bitWidth>1</bitWidth>
6905      </field>
6906      <field derivedFrom="ISO_PD">
6907       <name>IBRO_PD</name>
6908       <description>7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. </description>
6909       <bitOffset>17</bitOffset>
6910       <bitWidth>1</bitWidth>
6911      </field>
6912      <field>
6913       <name>EBO_BP</name>
6914       <description>EBO Bypass</description>
6915       <bitOffset>20</bitOffset>
6916       <bitWidth>1</bitWidth>
6917      </field>
6918     </fields>
6919    </register>
6920    <register>
6921     <name>IPLL_CTRL</name>
6922     <description>IPLL Control</description>
6923     <addressOffset>0x10</addressOffset>
6924     <fields>
6925      <field>
6926       <name>EN</name>
6927       <bitOffset>0</bitOffset>
6928       <bitWidth>1</bitWidth>
6929      </field>
6930      <field>
6931       <name>RDY</name>
6932       <bitOffset>1</bitOffset>
6933       <bitWidth>1</bitWidth>
6934      </field>
6935     </fields>
6936    </register>
6937    <register>
6938     <name>PCLKDIV</name>
6939     <description>Peripheral Clock Divider.</description>
6940     <addressOffset>0x18</addressOffset>
6941     <resetValue>0x00000001</resetValue>
6942     <fields>
6943      <field>
6944       <name>SDIOCLKDIV</name>
6945       <bitOffset>7</bitOffset>
6946       <bitWidth>1</bitWidth>
6947       <enumeratedValues>
6948        <enumeratedValue>
6949         <name>IPO_DIV2</name>
6950         <description>48 MHz</description>
6951         <value>0</value>
6952        </enumeratedValue>
6953        <enumeratedValue>
6954         <name>IPO_DIV4</name>
6955         <description>24 MHz</description>
6956         <value>1</value>
6957        </enumeratedValue>
6958       </enumeratedValues>
6959      </field>
6960      <field>
6961       <name>CNNCLKDIV</name>
6962       <description>CNN Clock Divider.</description>
6963       <bitOffset>14</bitOffset>
6964       <bitWidth>3</bitWidth>
6965       <enumeratedValues>
6966        <enumeratedValue>
6967         <name>div2</name>
6968         <value>0</value>
6969        </enumeratedValue>
6970        <enumeratedValue>
6971         <name>div4</name>
6972         <value>1</value>
6973        </enumeratedValue>
6974        <enumeratedValue>
6975         <name>div8</name>
6976         <value>2</value>
6977        </enumeratedValue>
6978        <enumeratedValue>
6979         <name>div16</name>
6980         <value>3</value>
6981        </enumeratedValue>
6982        <enumeratedValue>
6983         <name>div1</name>
6984         <value>4</value>
6985        </enumeratedValue>
6986       </enumeratedValues>
6987      </field>
6988      <field>
6989       <name>CNNCLKSEL</name>
6990       <description>CNN Clock Select.</description>
6991       <bitOffset>17</bitOffset>
6992       <bitWidth>2</bitWidth>
6993       <enumeratedValues>
6994        <enumeratedValue>
6995         <name>PCLK</name>
6996         <value>0</value>
6997        </enumeratedValue>
6998        <enumeratedValue>
6999         <name>ISO</name>
7000         <value>1</value>
7001        </enumeratedValue>
7002        <enumeratedValue>
7003         <name>IPLL</name>
7004         <value>3</value>
7005        </enumeratedValue>
7006       </enumeratedValues>
7007      </field>
7008     </fields>
7009    </register>
7010    <register>
7011     <name>PCLKDIS0</name>
7012     <description>Peripheral Clock Disable.</description>
7013     <addressOffset>0x24</addressOffset>
7014     <fields>
7015      <field>
7016       <name>GPIO0</name>
7017       <description>GPIO0 Clock Disable.</description>
7018       <bitOffset>0</bitOffset>
7019       <bitWidth>1</bitWidth>
7020       <enumeratedValues>
7021        <enumeratedValue>
7022         <name>en</name>
7023         <description>enable it.</description>
7024         <value>0</value>
7025        </enumeratedValue>
7026        <enumeratedValue>
7027         <name>dis</name>
7028         <description>disable it.</description>
7029         <value>1</value>
7030        </enumeratedValue>
7031       </enumeratedValues>
7032      </field>
7033      <field derivedFrom="GPIO0">
7034       <name>GPIO1</name>
7035       <description>GPIO1 Clock Disable.</description>
7036       <bitOffset>1</bitOffset>
7037       <bitWidth>1</bitWidth>
7038      </field>
7039      <field derivedFrom="GPIO0">
7040       <name>USB</name>
7041       <description>USB Clock Disable.</description>
7042       <bitOffset>3</bitOffset>
7043       <bitWidth>1</bitWidth>
7044      </field>
7045      <field derivedFrom="GPIO0">
7046       <name>DMA</name>
7047       <description>DMA Clock Disable.</description>
7048       <bitOffset>5</bitOffset>
7049       <bitWidth>1</bitWidth>
7050      </field>
7051      <field derivedFrom="GPIO0">
7052       <name>SPI1</name>
7053       <description>SPI 1 Clock Disable.</description>
7054       <bitOffset>6</bitOffset>
7055       <bitWidth>1</bitWidth>
7056      </field>
7057      <field derivedFrom="GPIO0">
7058       <name>UART0</name>
7059       <description>UART 0 Clock Disable.</description>
7060       <bitOffset>9</bitOffset>
7061       <bitWidth>1</bitWidth>
7062      </field>
7063      <field derivedFrom="GPIO0">
7064       <name>UART1</name>
7065       <description>UART 1 Clock Disable.</description>
7066       <bitOffset>10</bitOffset>
7067       <bitWidth>1</bitWidth>
7068      </field>
7069      <field derivedFrom="GPIO0">
7070       <name>I2C0</name>
7071       <description>I2C 0 Clock Disable.</description>
7072       <bitOffset>13</bitOffset>
7073       <bitWidth>1</bitWidth>
7074      </field>
7075      <field derivedFrom="GPIO0">
7076       <name>TMR0</name>
7077       <description>Timer 0 Clock Disable.</description>
7078       <bitOffset>15</bitOffset>
7079       <bitWidth>1</bitWidth>
7080      </field>
7081      <field derivedFrom="GPIO0">
7082       <name>TMR1</name>
7083       <description>Timer 1 Clock Disable.</description>
7084       <bitOffset>16</bitOffset>
7085       <bitWidth>1</bitWidth>
7086      </field>
7087      <field derivedFrom="GPIO0">
7088       <name>TMR2</name>
7089       <description>Timer 2 Clock Disable.</description>
7090       <bitOffset>17</bitOffset>
7091       <bitWidth>1</bitWidth>
7092      </field>
7093      <field derivedFrom="GPIO0">
7094       <name>TMR3</name>
7095       <description>Timer 3 Clock Disable.</description>
7096       <bitOffset>18</bitOffset>
7097       <bitWidth>1</bitWidth>
7098      </field>
7099      <field derivedFrom="GPIO0">
7100       <name>ADC</name>
7101       <description>ADC Clock Disable.</description>
7102       <bitOffset>23</bitOffset>
7103       <bitWidth>1</bitWidth>
7104      </field>
7105      <field derivedFrom="GPIO0">
7106       <name>CNN</name>
7107       <description>CNN Clock Disable.</description>
7108       <bitOffset>25</bitOffset>
7109       <bitWidth>1</bitWidth>
7110      </field>
7111      <field derivedFrom="GPIO0">
7112       <name>I2C1</name>
7113       <description>I2C 1 Clock Disable.</description>
7114       <bitOffset>28</bitOffset>
7115       <bitWidth>1</bitWidth>
7116      </field>
7117      <field derivedFrom="GPIO0">
7118       <name>PT</name>
7119       <description>Pluse Train Clock Disable.</description>
7120       <bitOffset>29</bitOffset>
7121       <bitWidth>1</bitWidth>
7122      </field>
7123     </fields>
7124    </register>
7125    <register>
7126     <name>MEMCTRL</name>
7127     <description>Memory Clock Control Register.</description>
7128     <addressOffset>0x28</addressOffset>
7129     <fields>
7130      <field>
7131       <name>FWS</name>
7132       <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description>
7133       <bitOffset>0</bitOffset>
7134       <bitWidth>3</bitWidth>
7135      </field>
7136      <field>
7137       <name>SYSRAM0ECC</name>
7138       <description>SYSRAM0 ECC Select.</description>
7139       <bitOffset>16</bitOffset>
7140       <bitWidth>1</bitWidth>
7141      </field>
7142     </fields>
7143    </register>
7144    <register>
7145     <name>MEMZ</name>
7146     <description>Memory Zeroize Control.</description>
7147     <addressOffset>0x2C</addressOffset>
7148     <fields>
7149      <field>
7150       <name>RAM0</name>
7151       <description>System RAM Block 0 Zeroization.</description>
7152       <bitOffset>0</bitOffset>
7153       <bitWidth>1</bitWidth>
7154       <enumeratedValues>
7155        <enumeratedValue>
7156         <name>nop</name>
7157         <description>No operation/complete.</description>
7158         <value>0</value>
7159        </enumeratedValue>
7160        <enumeratedValue>
7161         <name>start</name>
7162         <description>Start operation.</description>
7163         <value>1</value>
7164        </enumeratedValue>
7165       </enumeratedValues>
7166      </field>
7167      <field derivedFrom="RAM0">
7168       <name>RAM1</name>
7169       <description>System RAM Block 1 Zeroization.</description>
7170       <bitOffset>1</bitOffset>
7171       <bitWidth>1</bitWidth>
7172      </field>
7173      <field derivedFrom="RAM0">
7174       <name>RAM2</name>
7175       <description>System RAM Block 2 Zeroization.</description>
7176       <bitOffset>2</bitOffset>
7177       <bitWidth>1</bitWidth>
7178      </field>
7179      <field derivedFrom="RAM0">
7180       <name>RAM3</name>
7181       <description>System RAM Block 3 Zeroization.</description>
7182       <bitOffset>3</bitOffset>
7183       <bitWidth>1</bitWidth>
7184      </field>
7185      <field derivedFrom="RAM0">
7186       <name>RAM4</name>
7187       <description>System RAM Block 4 Zeroization.</description>
7188       <bitOffset>4</bitOffset>
7189       <bitWidth>1</bitWidth>
7190      </field>
7191      <field derivedFrom="RAM0">
7192       <name>RAM5</name>
7193       <description>System RAM Block 5 Zeroization.</description>
7194       <bitOffset>5</bitOffset>
7195       <bitWidth>1</bitWidth>
7196      </field>
7197      <field derivedFrom="RAM0">
7198       <name>RAM6</name>
7199       <description>System RAM Block 6 Zeroization.</description>
7200       <bitOffset>6</bitOffset>
7201       <bitWidth>1</bitWidth>
7202      </field>
7203      <field derivedFrom="RAM0">
7204       <name>RAM7</name>
7205       <description>System RAM Block 7 Zeroization.</description>
7206       <bitOffset>7</bitOffset>
7207       <bitWidth>1</bitWidth>
7208      </field>
7209      <field derivedFrom="RAM0">
7210       <name>RAM0ECC</name>
7211       <description>System RAM Block 0 ECC Zeroization.</description>
7212       <bitOffset>8</bitOffset>
7213       <bitWidth>1</bitWidth>
7214      </field>
7215      <field derivedFrom="RAM0">
7216       <name>ICC0</name>
7217       <description>Instruction Cache 0 Zeroization.</description>
7218       <bitOffset>9</bitOffset>
7219       <bitWidth>1</bitWidth>
7220      </field>
7221      <field derivedFrom="RAM0">
7222       <name>ICC1</name>
7223       <description>Instruction Cache 1 Zeroization.</description>
7224       <bitOffset>10</bitOffset>
7225       <bitWidth>1</bitWidth>
7226      </field>
7227      <field derivedFrom="RAM0">
7228       <name>USBFIFO</name>
7229       <description>USB FIFO Zeroization.</description>
7230       <bitOffset>11</bitOffset>
7231       <bitWidth>1</bitWidth>
7232      </field>
7233     </fields>
7234    </register>
7235    <register>
7236     <name>SYSST</name>
7237     <description>System Status Register.</description>
7238     <addressOffset>0x40</addressOffset>
7239     <fields>
7240      <field>
7241       <name>ICELOCK</name>
7242       <description>ARM ICE Lock Status.</description>
7243       <bitOffset>0</bitOffset>
7244       <bitWidth>1</bitWidth>
7245       <enumeratedValues>
7246        <enumeratedValue>
7247         <name>unlocked</name>
7248         <description>ICE is unlocked.</description>
7249         <value>0</value>
7250        </enumeratedValue>
7251        <enumeratedValue>
7252         <name>locked</name>
7253         <description>ICE is locked.</description>
7254         <value>1</value>
7255        </enumeratedValue>
7256       </enumeratedValues>
7257      </field>
7258     </fields>
7259    </register>
7260    <register>
7261     <name>RST1</name>
7262     <description>Reset 1.</description>
7263     <addressOffset>0x44</addressOffset>
7264     <fields>
7265      <field>
7266       <name>I2C1</name>
7267       <description>I2C1 Reset.</description>
7268       <bitOffset>0</bitOffset>
7269       <bitWidth>1</bitWidth>
7270       <enumeratedValues>
7271        <name>reset_read</name>
7272        <usage>read</usage>
7273        <enumeratedValue>
7274         <name>reset_done</name>
7275         <description>Reset complete.</description>
7276         <value>0</value>
7277        </enumeratedValue>
7278        <enumeratedValue>
7279         <name>busy</name>
7280         <description>Starts reset or indicates reset in progress.</description>
7281         <value>1</value>
7282        </enumeratedValue>
7283       </enumeratedValues>
7284      </field>
7285      <field derivedFrom="I2C1">
7286       <name>PT</name>
7287       <description>PT Reset.</description>
7288       <bitOffset>1</bitOffset>
7289       <bitWidth>1</bitWidth>
7290      </field>
7291      <field derivedFrom="I2C1">
7292       <name>SDHC</name>
7293       <description>SDHC Reset.</description>
7294       <bitOffset>6</bitOffset>
7295       <bitWidth>1</bitWidth>
7296      </field>
7297      <field derivedFrom="I2C1">
7298       <name>OWM</name>
7299       <description>OWM Reset.</description>
7300       <bitOffset>7</bitOffset>
7301       <bitWidth>1</bitWidth>
7302      </field>
7303      <field derivedFrom="I2C1">
7304       <name>CRC</name>
7305       <description>CRC Reset.</description>
7306       <bitOffset>9</bitOffset>
7307       <bitWidth>1</bitWidth>
7308      </field>
7309      <field derivedFrom="I2C1">
7310       <name>AES</name>
7311       <description>AES Reset.</description>
7312       <bitOffset>10</bitOffset>
7313       <bitWidth>1</bitWidth>
7314      </field>
7315      <field derivedFrom="I2C1">
7316       <name>SPI0</name>
7317       <description>SPI 0 Reset.</description>
7318       <bitOffset>11</bitOffset>
7319       <bitWidth>1</bitWidth>
7320      </field>
7321      <field derivedFrom="I2C1">
7322       <name>CSI2PHY</name>
7323       <description>CSI2 PHY Reset.</description>
7324       <bitOffset>14</bitOffset>
7325       <bitWidth>1</bitWidth>
7326      </field>
7327      <field derivedFrom="I2C1">
7328       <name>SMPHR</name>
7329       <description>SMPHR Reset.</description>
7330       <bitOffset>16</bitOffset>
7331       <bitWidth>1</bitWidth>
7332      </field>
7333      <field derivedFrom="I2C1">
7334       <name>I2S</name>
7335       <description>I2S Reset.</description>
7336       <bitOffset>19</bitOffset>
7337       <bitWidth>1</bitWidth>
7338      </field>
7339      <field derivedFrom="I2C1">
7340       <name>I2C2</name>
7341       <description>I2C2 Reset.</description>
7342       <bitOffset>20</bitOffset>
7343       <bitWidth>1</bitWidth>
7344      </field>
7345      <field derivedFrom="I2C1">
7346       <name>DVS</name>
7347       <description>DVS Reset.</description>
7348       <bitOffset>24</bitOffset>
7349       <bitWidth>1</bitWidth>
7350      </field>
7351      <field derivedFrom="I2C1">
7352       <name>SIMO</name>
7353       <description>SIMO Reset.</description>
7354       <bitOffset>25</bitOffset>
7355       <bitWidth>1</bitWidth>
7356      </field>
7357      <field derivedFrom="I2C1">
7358       <name>PCIF</name>
7359       <description>PCIF Reset.</description>
7360       <bitOffset>26</bitOffset>
7361       <bitWidth>1</bitWidth>
7362      </field>
7363      <field derivedFrom="I2C1">
7364       <name>CSI2</name>
7365       <description>CSI2 Reset.</description>
7366       <bitOffset>27</bitOffset>
7367       <bitWidth>1</bitWidth>
7368      </field>
7369      <field derivedFrom="I2C1">
7370       <name>CPU1</name>
7371       <description>CPU1 Reset.</description>
7372       <bitOffset>31</bitOffset>
7373       <bitWidth>1</bitWidth>
7374      </field>
7375     </fields>
7376    </register>
7377    <register>
7378     <name>PCLKDIS1</name>
7379     <description>Peripheral Clock Disable.</description>
7380     <addressOffset>0x48</addressOffset>
7381     <fields>
7382      <field>
7383       <name>UART2</name>
7384       <description>UART2 Clock Disable.</description>
7385       <bitOffset>1</bitOffset>
7386       <bitWidth>1</bitWidth>
7387       <enumeratedValues>
7388        <enumeratedValue>
7389         <name>en</name>
7390         <description>Enable.</description>
7391         <value>0</value>
7392        </enumeratedValue>
7393        <enumeratedValue>
7394         <name>dis</name>
7395         <description>Disable.</description>
7396         <value>1</value>
7397        </enumeratedValue>
7398       </enumeratedValues>
7399      </field>
7400      <field derivedFrom="UART2">
7401       <name>TRNG</name>
7402       <description>TRNG Clock Disable.</description>
7403       <bitOffset>2</bitOffset>
7404       <bitWidth>1</bitWidth>
7405      </field>
7406      <field derivedFrom="UART2">
7407       <name>SMPHR</name>
7408       <description>SMPHR Clock Disable.</description>
7409       <bitOffset>9</bitOffset>
7410       <bitWidth>1</bitWidth>
7411      </field>
7412      <field derivedFrom="UART2">
7413       <name>SDHC</name>
7414       <description>SDHC Clock Disable.</description>
7415       <bitOffset>10</bitOffset>
7416       <bitWidth>1</bitWidth>
7417      </field>
7418      <field derivedFrom="UART2">
7419       <name>OWM</name>
7420       <description>One-Wire Clock Disable.</description>
7421       <bitOffset>13</bitOffset>
7422       <bitWidth>1</bitWidth>
7423      </field>
7424      <field derivedFrom="UART2">
7425       <name>CRC</name>
7426       <description>CRC Clock Disable.</description>
7427       <bitOffset>14</bitOffset>
7428       <bitWidth>1</bitWidth>
7429      </field>
7430      <field derivedFrom="UART2">
7431       <name>AES</name>
7432       <description>AES Clock Disable.</description>
7433       <bitOffset>15</bitOffset>
7434       <bitWidth>1</bitWidth>
7435      </field>
7436      <field derivedFrom="UART2">
7437       <name>SPI0</name>
7438       <description>SPI0 AHB.</description>
7439       <bitOffset>16</bitOffset>
7440       <bitWidth>1</bitWidth>
7441      </field>
7442      <field derivedFrom="UART2">
7443       <name>PCIF</name>
7444       <description>Parallel Camera Interface Clock Disable.</description>
7445       <bitOffset>18</bitOffset>
7446       <bitWidth>1</bitWidth>
7447      </field>
7448      <field derivedFrom="UART2">
7449       <name>I2S</name>
7450       <description>I2S Clock Disable.</description>
7451       <bitOffset>23</bitOffset>
7452       <bitWidth>1</bitWidth>
7453      </field>
7454      <field derivedFrom="UART2">
7455       <name>I2C2</name>
7456       <description>I2C2 Clock Disable.</description>
7457       <bitOffset>24</bitOffset>
7458       <bitWidth>1</bitWidth>
7459      </field>
7460      <field derivedFrom="UART2">
7461       <name>WDT0</name>
7462       <description>Watch Dog Timer 0 Clock Disable.</description>
7463       <bitOffset>27</bitOffset>
7464       <bitWidth>1</bitWidth>
7465      </field>
7466      <field derivedFrom="UART2">
7467       <name>CSI2</name>
7468       <description>CSI2 Clock Disable.</description>
7469       <bitOffset>30</bitOffset>
7470       <bitWidth>1</bitWidth>
7471      </field>
7472      <field derivedFrom="UART2">
7473       <name>CPU1</name>
7474       <description>CPU1 Clock Disable.</description>
7475       <bitOffset>31</bitOffset>
7476       <bitWidth>1</bitWidth>
7477      </field>
7478     </fields>
7479    </register>
7480    <register>
7481     <name>EVENTEN</name>
7482     <description>Event Enable Register.</description>
7483     <addressOffset>0x4C</addressOffset>
7484     <fields>
7485      <field>
7486       <name>DMA</name>
7487       <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description>
7488       <bitOffset>0</bitOffset>
7489       <bitWidth>1</bitWidth>
7490      </field>
7491      <field>
7492       <name>TX</name>
7493       <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9.</description>
7494       <bitOffset>2</bitOffset>
7495       <bitWidth>1</bitWidth>
7496      </field>
7497     </fields>
7498    </register>
7499    <register>
7500     <name>REVISION</name>
7501     <description>Revision Register.</description>
7502     <addressOffset>0x50</addressOffset>
7503     <access>read-only</access>
7504     <fields>
7505      <field>
7506       <name>REVISION</name>
7507       <description>Manufacturer Chip Revision.</description>
7508       <bitOffset>0</bitOffset>
7509       <bitWidth>16</bitWidth>
7510      </field>
7511     </fields>
7512    </register>
7513    <register>
7514     <name>SYSIE</name>
7515     <description>System Status Interrupt Enable Register.</description>
7516     <addressOffset>0x54</addressOffset>
7517     <fields>
7518      <field>
7519       <name>ICEUNLOCK</name>
7520       <description>ARM ICE Unlock Interrupt Enable.</description>
7521       <bitOffset>0</bitOffset>
7522       <bitWidth>1</bitWidth>
7523       <enumeratedValues>
7524        <enumeratedValue>
7525         <name>dis</name>
7526         <description>disabled.</description>
7527         <value>0</value>
7528        </enumeratedValue>
7529        <enumeratedValue>
7530         <name>en</name>
7531         <description>enabled.</description>
7532         <value>1</value>
7533        </enumeratedValue>
7534       </enumeratedValues>
7535      </field>
7536     </fields>
7537    </register>
7538    <register>
7539     <name>ECCERR</name>
7540     <description>ECC Error Register</description>
7541     <addressOffset>0x64</addressOffset>
7542     <fields>
7543      <field>
7544       <name>RAM</name>
7545       <description>ECC System RAM0 Error Flag. Write 1 to clear.</description>
7546       <bitOffset>0</bitOffset>
7547       <bitWidth>1</bitWidth>
7548      </field>
7549     </fields>
7550    </register>
7551    <register>
7552     <name>ECCCED</name>
7553     <description>ECC Not Double Error Detect Register</description>
7554     <addressOffset>0x68</addressOffset>
7555     <fields>
7556      <field>
7557       <name>RAM</name>
7558       <description>ECC System RAM0 Error Flag. Write 1 to clear.</description>
7559       <bitOffset>0</bitOffset>
7560       <bitWidth>1</bitWidth>
7561      </field>
7562     </fields>
7563    </register>
7564    <register>
7565     <name>ECCIE</name>
7566     <description>ECC IRQ Enable Register</description>
7567     <addressOffset>0x6C</addressOffset>
7568     <fields>
7569      <field>
7570       <name>RAM</name>
7571       <description>ECC System RAM0 Error Interrup Enable</description>
7572       <bitOffset>0</bitOffset>
7573       <bitWidth>1</bitWidth>
7574      </field>
7575     </fields>
7576    </register>
7577    <register>
7578     <name>ECCADDR</name>
7579     <description>ECC Error Address Register</description>
7580     <addressOffset>0x70</addressOffset>
7581     <fields>
7582      <field>
7583       <name>ECCERRAD</name>
7584       <description>ECC Error Address.</description>
7585       <bitOffset>0</bitOffset>
7586       <bitWidth>32</bitWidth>
7587      </field>
7588     </fields>
7589    </register>
7590    <register>
7591     <name>GPR0</name>
7592     <description>General Purpose Register 0</description>
7593     <addressOffset>0x80</addressOffset>
7594    </register>
7595   </registers>
7596  </peripheral>
7597<!--GCR Global Control Registers.-->
7598  <peripheral>
7599   <name>GCFR</name>
7600   <description>Global Control Function Register.</description>
7601   <baseAddress>0x40005800</baseAddress>
7602   <addressBlock>
7603    <offset>0x00</offset>
7604    <size>0x400</size>
7605    <usage>registers</usage>
7606   </addressBlock>
7607   <registers>
7608    <register>
7609     <name>REG0</name>
7610     <description>Register 0.</description>
7611     <addressOffset>0x00</addressOffset>
7612     <access>read-write</access>
7613     <fields>
7614      <field>
7615       <name>cnnx16_0_pwr_en</name>
7616       <description>CNNx16_0 Power Domain Enable</description>
7617       <bitOffset>0</bitOffset>
7618       <bitWidth>1</bitWidth>
7619      </field>
7620      <field>
7621       <name>cnnx16_1_pwr_en</name>
7622       <description>CNNx16_1 Power Domain Enable</description>
7623       <bitOffset>1</bitOffset>
7624       <bitWidth>1</bitWidth>
7625      </field>
7626      <field>
7627       <name>cnnx16_2_pwr_en</name>
7628       <description>CNNx16_2 Power Domain Enable</description>
7629       <bitOffset>2</bitOffset>
7630       <bitWidth>1</bitWidth>
7631      </field>
7632      <field>
7633       <name>cnnx16_3_pwr_en</name>
7634       <description>CNNx16_3 Power Domain Enable</description>
7635       <bitOffset>3</bitOffset>
7636       <bitWidth>1</bitWidth>
7637      </field>
7638     </fields>
7639    </register>
7640    <register>
7641     <name>REG1</name>
7642     <description>Register 1.</description>
7643     <addressOffset>0x04</addressOffset>
7644     <access>read-write</access>
7645     <fields>
7646      <field>
7647       <name>cnnx16_0_ram_en</name>
7648       <description>CNNx16_0 RAM Power Enable</description>
7649       <bitOffset>0</bitOffset>
7650       <bitWidth>1</bitWidth>
7651      </field>
7652      <field>
7653       <name>cnnx16_1_ram_en</name>
7654       <description>CNNx16_1 RAM Power Enable</description>
7655       <bitOffset>1</bitOffset>
7656       <bitWidth>1</bitWidth>
7657      </field>
7658      <field>
7659       <name>cnnx16_2_ram_en</name>
7660       <description>CNNx16_2 RAM Power Enable</description>
7661       <bitOffset>2</bitOffset>
7662       <bitWidth>1</bitWidth>
7663      </field>
7664      <field>
7665       <name>cnnx16_3_ram_en</name>
7666       <description>CNNx16_3 RAM Power Enable</description>
7667       <bitOffset>3</bitOffset>
7668       <bitWidth>1</bitWidth>
7669      </field>
7670     </fields>
7671    </register>
7672    <register>
7673     <name>REG2</name>
7674     <description>Register 2.</description>
7675     <addressOffset>0x08</addressOffset>
7676     <access>read-write</access>
7677     <fields>
7678      <field>
7679       <name>cnnx16_0_iso</name>
7680       <description>CNNx16_0 Power Domain Isolation</description>
7681       <bitOffset>0</bitOffset>
7682       <bitWidth>1</bitWidth>
7683      </field>
7684      <field>
7685       <name>cnnx16_1_iso</name>
7686       <description>CNNx16_1 Power Domain Isolation</description>
7687       <bitOffset>1</bitOffset>
7688       <bitWidth>1</bitWidth>
7689      </field>
7690      <field>
7691       <name>cnnx16_2_iso</name>
7692       <description>CNNx16_2 Power Domain Isolation</description>
7693       <bitOffset>2</bitOffset>
7694       <bitWidth>1</bitWidth>
7695      </field>
7696      <field>
7697       <name>cnnx16_3_iso</name>
7698       <description>CNNx16_3 Power Domain Isolation</description>
7699       <bitOffset>3</bitOffset>
7700       <bitWidth>1</bitWidth>
7701      </field>
7702      <field>
7703       <name>cnnx16_0_data_ret_en</name>
7704       <description>CNNx16_0 Pad Retention Control</description>
7705       <bitOffset>16</bitOffset>
7706       <bitWidth>1</bitWidth>
7707      </field>
7708      <field>
7709       <name>cnnx16_1_data_ret_en</name>
7710       <description>CNNx16_1 Pad Retention Control</description>
7711       <bitOffset>17</bitOffset>
7712       <bitWidth>1</bitWidth>
7713      </field>
7714      <field>
7715       <name>cnnx16_2_data_ret_en</name>
7716       <description>CNNx16_2 Pad Retention Control</description>
7717       <bitOffset>18</bitOffset>
7718       <bitWidth>1</bitWidth>
7719      </field>
7720      <field>
7721       <name>cnnx16_3_data_ret_en</name>
7722       <description>CNNx16_3 Pad Retention Control</description>
7723       <bitOffset>19</bitOffset>
7724       <bitWidth>1</bitWidth>
7725      </field>
7726      <field>
7727       <name>cnnx16_0_ram_data_ret_en</name>
7728       <description>CNNx16_0 RAM Pad Retention Control</description>
7729       <bitOffset>20</bitOffset>
7730       <bitWidth>1</bitWidth>
7731      </field>
7732      <field>
7733       <name>cnnx16_1_ram_data_ret_en</name>
7734       <description>CNNx16_1 RAM Pad Retention Control</description>
7735       <bitOffset>21</bitOffset>
7736       <bitWidth>1</bitWidth>
7737      </field>
7738      <field>
7739       <name>cnnx16_2_ram_data_ret_en</name>
7740       <description>CNNx16_2 RAM Pad Retention Control</description>
7741       <bitOffset>22</bitOffset>
7742       <bitWidth>1</bitWidth>
7743      </field>
7744      <field>
7745       <name>cnnx16_3_ram_data_ret_en</name>
7746       <description>CNNx16_3 RAM Pad Retention Control</description>
7747       <bitOffset>23</bitOffset>
7748       <bitWidth>1</bitWidth>
7749      </field>
7750     </fields>
7751    </register>
7752    <register>
7753     <name>REG3</name>
7754     <description>Register 3.</description>
7755     <addressOffset>0x0C</addressOffset>
7756     <access>read-write</access>
7757     <fields>
7758      <field>
7759       <name>cnnx16_0_rst</name>
7760       <description>CNNx16_0 Power Domain Reset</description>
7761       <bitOffset>0</bitOffset>
7762       <bitWidth>1</bitWidth>
7763      </field>
7764      <field>
7765       <name>cnnx16_1_rst</name>
7766       <description>CNNx16_1 Power Domain Reset</description>
7767       <bitOffset>1</bitOffset>
7768       <bitWidth>1</bitWidth>
7769      </field>
7770      <field>
7771       <name>cnnx16_2_rst</name>
7772       <description>CNNx16_2 Power Domain Reset</description>
7773       <bitOffset>2</bitOffset>
7774       <bitWidth>1</bitWidth>
7775      </field>
7776      <field>
7777       <name>cnnx16_3_rst</name>
7778       <description>CNNx16_3 Power Domain Reset</description>
7779       <bitOffset>3</bitOffset>
7780       <bitWidth>1</bitWidth>
7781      </field>
7782     </fields>
7783    </register>
7784   </registers>
7785  </peripheral>
7786<!--GCFR Global Control Function Register.-->
7787  <peripheral>
7788   <name>GPIO0</name>
7789   <description>Individual I/O for each GPIO</description>
7790   <groupName>GPIO</groupName>
7791   <baseAddress>0x40008000</baseAddress>
7792   <addressBlock>
7793    <offset>0x00</offset>
7794    <size>0x1000</size>
7795    <usage>registers</usage>
7796   </addressBlock>
7797   <interrupt>
7798    <name>GPIO0</name>
7799    <description>GPIO0 interrupt.</description>
7800    <value>24</value>
7801   </interrupt>
7802   <registers>
7803    <register>
7804     <name>EN0</name>
7805     <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description>
7806     <addressOffset>0x00</addressOffset>
7807     <fields>
7808      <field>
7809       <name>GPIO_EN</name>
7810       <description>Mask of all of the pins on the port.</description>
7811       <bitOffset>0</bitOffset>
7812       <bitWidth>32</bitWidth>
7813       <enumeratedValues>
7814        <enumeratedValue>
7815         <name>ALTERNATE</name>
7816         <description>Alternate function enabled.</description>
7817         <value>0</value>
7818        </enumeratedValue>
7819        <enumeratedValue>
7820         <name>GPIO</name>
7821         <description>GPIO function is enabled.</description>
7822         <value>1</value>
7823        </enumeratedValue>
7824       </enumeratedValues>
7825      </field>
7826     </fields>
7827    </register>
7828    <register>
7829     <name>EN0_SET</name>
7830     <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description>
7831     <addressOffset>0x04</addressOffset>
7832     <fields>
7833      <field>
7834       <name>ALL</name>
7835       <description>Mask of all of the pins on the port.</description>
7836       <bitOffset>0</bitOffset>
7837       <bitWidth>32</bitWidth>
7838      </field>
7839     </fields>
7840    </register>
7841    <register>
7842     <name>EN0_CLR</name>
7843     <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description>
7844     <addressOffset>0x08</addressOffset>
7845     <fields>
7846      <field>
7847       <name>ALL</name>
7848       <description>Mask of all of the pins on the port.</description>
7849       <bitOffset>0</bitOffset>
7850       <bitWidth>32</bitWidth>
7851      </field>
7852     </fields>
7853    </register>
7854    <register>
7855     <name>OUTEN</name>
7856     <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description>
7857     <addressOffset>0x0C</addressOffset>
7858     <fields>
7859      <field>
7860       <name>EN</name>
7861       <description>Mask of all of the pins on the port.</description>
7862       <bitOffset>0</bitOffset>
7863       <bitWidth>32</bitWidth>
7864       <enumeratedValues>
7865        <enumeratedValue>
7866         <name>dis</name>
7867         <description>GPIO Output Disable</description>
7868         <value>0</value>
7869        </enumeratedValue>
7870        <enumeratedValue>
7871         <name>en</name>
7872         <description>GPIO Output Enable</description>
7873         <value>1</value>
7874        </enumeratedValue>
7875       </enumeratedValues>
7876      </field>
7877     </fields>
7878    </register>
7879    <register>
7880     <name>OUTEN_SET</name>
7881     <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description>
7882     <addressOffset>0x10</addressOffset>
7883     <fields>
7884      <field>
7885       <name>ALL</name>
7886       <description>Mask of all of the pins on the port.</description>
7887       <bitOffset>0</bitOffset>
7888       <bitWidth>32</bitWidth>
7889      </field>
7890     </fields>
7891    </register>
7892    <register>
7893     <name>OUTEN_CLR</name>
7894     <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description>
7895     <addressOffset>0x14</addressOffset>
7896     <fields>
7897      <field>
7898       <name>ALL</name>
7899       <description>Mask of all of the pins on the port.</description>
7900       <bitOffset>0</bitOffset>
7901       <bitWidth>32</bitWidth>
7902      </field>
7903     </fields>
7904    </register>
7905    <register>
7906     <name>OUT</name>
7907     <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port.  This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description>
7908     <addressOffset>0x18</addressOffset>
7909     <fields>
7910      <field>
7911       <name>GPIO_OUT</name>
7912       <description>Mask of all of the pins on the port.</description>
7913       <bitOffset>0</bitOffset>
7914       <bitWidth>32</bitWidth>
7915       <enumeratedValues>
7916        <enumeratedValue>
7917         <name>low</name>
7918         <description>Drive Logic 0 (low) on GPIO output.</description>
7919         <value>0</value>
7920        </enumeratedValue>
7921        <enumeratedValue>
7922         <name>high</name>
7923         <description>Drive logic 1 (high) on GPIO output.</description>
7924         <value>1</value>
7925        </enumeratedValue>
7926       </enumeratedValues>
7927      </field>
7928     </fields>
7929    </register>
7930    <register>
7931     <name>OUT_SET</name>
7932     <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description>
7933     <addressOffset>0x1C</addressOffset>
7934     <access>write-only</access>
7935     <fields>
7936      <field>
7937       <name>GPIO_OUT_SET</name>
7938       <description>Mask of all of the pins on the port.</description>
7939       <bitOffset>0</bitOffset>
7940       <bitWidth>32</bitWidth>
7941       <enumeratedValues>
7942        <enumeratedValue>
7943         <name>no</name>
7944         <description>No Effect.</description>
7945         <value>0</value>
7946        </enumeratedValue>
7947        <enumeratedValue>
7948         <name>set</name>
7949         <description>Set GPIO_OUT bit in this position to '1'</description>
7950         <value>1</value>
7951        </enumeratedValue>
7952       </enumeratedValues>
7953      </field>
7954     </fields>
7955    </register>
7956    <register>
7957     <name>OUT_CLR</name>
7958     <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description>
7959     <addressOffset>0x20</addressOffset>
7960     <access>write-only</access>
7961     <fields>
7962      <field>
7963       <name>GPIO_OUT_CLR</name>
7964       <description>Mask of all of the pins on the port.</description>
7965       <bitOffset>0</bitOffset>
7966       <bitWidth>32</bitWidth>
7967      </field>
7968     </fields>
7969    </register>
7970    <register>
7971     <name>IN</name>
7972     <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description>
7973     <addressOffset>0x24</addressOffset>
7974     <access>read-only</access>
7975     <fields>
7976      <field>
7977       <name>GPIO_IN</name>
7978       <description>Mask of all of the pins on the port.</description>
7979       <bitOffset>0</bitOffset>
7980       <bitWidth>32</bitWidth>
7981      </field>
7982     </fields>
7983    </register>
7984    <register>
7985     <name>INTMODE</name>
7986     <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description>
7987     <addressOffset>0x28</addressOffset>
7988     <fields>
7989      <field>
7990       <name>GPIO_INTMODE</name>
7991       <description>Mask of all of the pins on the port.</description>
7992       <bitOffset>0</bitOffset>
7993       <bitWidth>32</bitWidth>
7994       <enumeratedValues>
7995        <enumeratedValue>
7996         <name>level</name>
7997         <description>Interrupts for this pin are level triggered.</description>
7998         <value>0</value>
7999        </enumeratedValue>
8000        <enumeratedValue>
8001         <name>edge</name>
8002         <description>Interrupts for this pin are edge triggered.</description>
8003         <value>1</value>
8004        </enumeratedValue>
8005       </enumeratedValues>
8006      </field>
8007     </fields>
8008    </register>
8009    <register>
8010     <name>INTPOL</name>
8011     <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description>
8012     <addressOffset>0x2C</addressOffset>
8013     <fields>
8014      <field>
8015       <name>GPIO_INTPOL</name>
8016       <description>Mask of all of the pins on the port.</description>
8017       <bitOffset>0</bitOffset>
8018       <bitWidth>32</bitWidth>
8019       <enumeratedValues>
8020        <enumeratedValue>
8021         <name>falling</name>
8022         <description>Interrupts are latched on a falling edge or low level condition for this pin.</description>
8023         <value>0</value>
8024        </enumeratedValue>
8025        <enumeratedValue>
8026         <name>rising</name>
8027         <description>Interrupts are latched on a rising edge or high condition for this pin.</description>
8028         <value>1</value>
8029        </enumeratedValue>
8030       </enumeratedValues>
8031      </field>
8032     </fields>
8033    </register>
8034    <register>
8035     <name>INEN</name>
8036     <description>GPIO Input Enable</description>
8037     <addressOffset>0x30</addressOffset>
8038    </register>
8039    <register>
8040     <name>INTEN</name>
8041     <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description>
8042     <addressOffset>0x34</addressOffset>
8043     <fields>
8044      <field>
8045       <name>GPIO_INTEN</name>
8046       <description>Mask of all of the pins on the port.</description>
8047       <bitOffset>0</bitOffset>
8048       <bitWidth>32</bitWidth>
8049       <enumeratedValues>
8050        <enumeratedValue>
8051         <name>dis</name>
8052         <description>Interrupts are disabled for this GPIO pin.</description>
8053         <value>0</value>
8054        </enumeratedValue>
8055        <enumeratedValue>
8056         <name>en</name>
8057         <description>Interrupts are enabled for this GPIO pin.</description>
8058         <value>1</value>
8059        </enumeratedValue>
8060       </enumeratedValues>
8061      </field>
8062     </fields>
8063    </register>
8064    <register>
8065     <name>INTEN_SET</name>
8066     <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description>
8067     <addressOffset>0x38</addressOffset>
8068     <fields>
8069      <field>
8070       <name>GPIO_INTEN_SET</name>
8071       <description>Mask of all of the pins on the port.</description>
8072       <bitOffset>0</bitOffset>
8073       <bitWidth>32</bitWidth>
8074       <enumeratedValues>
8075        <enumeratedValue>
8076         <name>no</name>
8077         <description>No effect.</description>
8078         <value>0</value>
8079        </enumeratedValue>
8080        <enumeratedValue>
8081         <name>set</name>
8082         <description>Set GPIO_INT_EN bit in this position to '1'</description>
8083         <value>1</value>
8084        </enumeratedValue>
8085       </enumeratedValues>
8086      </field>
8087     </fields>
8088    </register>
8089    <register>
8090     <name>INTEN_CLR</name>
8091     <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description>
8092     <addressOffset>0x3C</addressOffset>
8093     <fields>
8094      <field>
8095       <name>GPIO_INTEN_CLR</name>
8096       <description>Mask of all of the pins on the port.</description>
8097       <bitOffset>0</bitOffset>
8098       <bitWidth>32</bitWidth>
8099       <enumeratedValues>
8100        <enumeratedValue>
8101         <name>no</name>
8102         <description>No Effect.</description>
8103         <value>0</value>
8104        </enumeratedValue>
8105        <enumeratedValue>
8106         <name>clear</name>
8107         <description>Clear GPIO_INT_EN bit in this position to '0'</description>
8108         <value>1</value>
8109        </enumeratedValue>
8110       </enumeratedValues>
8111      </field>
8112     </fields>
8113    </register>
8114    <register>
8115     <name>INTFL</name>
8116     <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description>
8117     <addressOffset>0x40</addressOffset>
8118     <access>read-only</access>
8119     <fields>
8120      <field>
8121       <name>GPIO_INTFL</name>
8122       <description>Mask of all of the pins on the port.</description>
8123       <bitOffset>0</bitOffset>
8124       <bitWidth>32</bitWidth>
8125       <enumeratedValues>
8126        <enumeratedValue>
8127         <name>no</name>
8128         <description>No Interrupt is pending on this GPIO pin.</description>
8129         <value>0</value>
8130        </enumeratedValue>
8131        <enumeratedValue>
8132         <name>pending</name>
8133         <description>An Interrupt is pending on this GPIO pin.</description>
8134         <value>1</value>
8135        </enumeratedValue>
8136       </enumeratedValues>
8137      </field>
8138     </fields>
8139    </register>
8140    <register>
8141     <name>INTFL_CLR</name>
8142     <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description>
8143     <addressOffset>0x48</addressOffset>
8144     <fields>
8145      <field>
8146       <name>ALL</name>
8147       <description>Mask of all of the pins on the port.</description>
8148       <bitOffset>0</bitOffset>
8149       <bitWidth>32</bitWidth>
8150      </field>
8151     </fields>
8152    </register>
8153    <register>
8154     <name>WKEN</name>
8155     <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description>
8156     <addressOffset>0x4C</addressOffset>
8157     <fields>
8158      <field>
8159       <name>GPIO_WKEN</name>
8160       <description>Mask of all of the pins on the port.</description>
8161       <bitOffset>0</bitOffset>
8162       <bitWidth>32</bitWidth>
8163       <enumeratedValues>
8164        <enumeratedValue>
8165         <name>dis</name>
8166         <description>PMU wakeup for this GPIO is disabled.</description>
8167         <value>0</value>
8168        </enumeratedValue>
8169        <enumeratedValue>
8170         <name>en</name>
8171         <description>PMU wakeup for this GPIO is enabled.</description>
8172         <value>1</value>
8173        </enumeratedValue>
8174       </enumeratedValues>
8175      </field>
8176     </fields>
8177    </register>
8178    <register>
8179     <name>WKEN_SET</name>
8180     <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description>
8181     <addressOffset>0x50</addressOffset>
8182     <fields>
8183      <field>
8184       <name>ALL</name>
8185       <description>Mask of all of the pins on the port.</description>
8186       <bitOffset>0</bitOffset>
8187       <bitWidth>32</bitWidth>
8188      </field>
8189     </fields>
8190    </register>
8191    <register>
8192     <name>WKEN_CLR</name>
8193     <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description>
8194     <addressOffset>0x54</addressOffset>
8195     <fields>
8196      <field>
8197       <name>ALL</name>
8198       <description>Mask of all of the pins on the port.</description>
8199       <bitOffset>0</bitOffset>
8200       <bitWidth>32</bitWidth>
8201      </field>
8202     </fields>
8203    </register>
8204    <register>
8205     <name>DUALEDGE</name>
8206     <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description>
8207     <addressOffset>0x5C</addressOffset>
8208     <fields>
8209      <field>
8210       <name>GPIO_DUALEDGE</name>
8211       <description>Mask of all of the pins on the port.</description>
8212       <bitOffset>0</bitOffset>
8213       <bitWidth>32</bitWidth>
8214       <enumeratedValues>
8215        <enumeratedValue>
8216         <name>no</name>
8217         <description>No Effect.</description>
8218         <value>0</value>
8219        </enumeratedValue>
8220        <enumeratedValue>
8221         <name>en</name>
8222         <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description>
8223         <value>1</value>
8224        </enumeratedValue>
8225       </enumeratedValues>
8226      </field>
8227     </fields>
8228    </register>
8229    <register>
8230     <name>PADCTRL0</name>
8231     <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description>
8232     <addressOffset>0x60</addressOffset>
8233     <fields>
8234      <field>
8235       <name>GPIO_PADCTRL0</name>
8236       <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description>
8237       <bitOffset>0</bitOffset>
8238       <bitWidth>32</bitWidth>
8239       <enumeratedValues>
8240        <enumeratedValue>
8241         <name>impedance</name>
8242         <description>High Impedance.</description>
8243         <value>0</value>
8244        </enumeratedValue>
8245        <enumeratedValue>
8246         <name>pu</name>
8247         <description>Weak pull-up mode.</description>
8248         <value>1</value>
8249        </enumeratedValue>
8250        <enumeratedValue>
8251         <name>pd</name>
8252         <description>weak pull-down mode.</description>
8253         <value>2</value>
8254        </enumeratedValue>
8255       </enumeratedValues>
8256      </field>
8257     </fields>
8258    </register>
8259    <register>
8260     <name>PADCTRL1</name>
8261     <description>GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description>
8262     <addressOffset>0x64</addressOffset>
8263     <fields>
8264      <field>
8265       <name>GPIO_PADCTRL1</name>
8266       <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description>
8267       <bitOffset>0</bitOffset>
8268       <bitWidth>32</bitWidth>
8269       <enumeratedValues>
8270        <enumeratedValue>
8271         <name>impedance</name>
8272         <description>High Impedance.</description>
8273         <value>0</value>
8274        </enumeratedValue>
8275        <enumeratedValue>
8276         <name>pu</name>
8277         <description>Weak pull-up mode.</description>
8278         <value>1</value>
8279        </enumeratedValue>
8280        <enumeratedValue>
8281         <name>pd</name>
8282         <description>weak pull-down mode.</description>
8283         <value>2</value>
8284        </enumeratedValue>
8285       </enumeratedValues>
8286      </field>
8287     </fields>
8288    </register>
8289    <register>
8290     <name>EN1</name>
8291     <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description>
8292     <addressOffset>0x68</addressOffset>
8293     <fields>
8294      <field>
8295       <name>GPIO_EN1</name>
8296       <description>Mask of all of the pins on the port.</description>
8297       <bitOffset>0</bitOffset>
8298       <bitWidth>32</bitWidth>
8299       <enumeratedValues>
8300        <enumeratedValue>
8301         <name>primary</name>
8302         <description>Primary function selected.</description>
8303         <value>0</value>
8304        </enumeratedValue>
8305        <enumeratedValue>
8306         <name>secondary</name>
8307         <description>Secondary function selected.</description>
8308         <value>1</value>
8309        </enumeratedValue>
8310       </enumeratedValues>
8311      </field>
8312     </fields>
8313    </register>
8314    <register>
8315     <name>EN1_SET</name>
8316     <description>GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description>
8317     <addressOffset>0x6C</addressOffset>
8318     <fields>
8319      <field>
8320       <name>ALL</name>
8321       <description>Mask of all of the pins on the port.</description>
8322       <bitOffset>0</bitOffset>
8323       <bitWidth>32</bitWidth>
8324      </field>
8325     </fields>
8326    </register>
8327    <register>
8328     <name>EN1_CLR</name>
8329     <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description>
8330     <addressOffset>0x70</addressOffset>
8331     <fields>
8332      <field>
8333       <name>ALL</name>
8334       <description>Mask of all of the pins on the port.</description>
8335       <bitOffset>0</bitOffset>
8336       <bitWidth>32</bitWidth>
8337      </field>
8338     </fields>
8339    </register>
8340    <register>
8341     <name>EN2</name>
8342     <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description>
8343     <addressOffset>0x74</addressOffset>
8344     <fields>
8345      <field>
8346       <name>GPIO_EN2</name>
8347       <description>Mask of all of the pins on the port.</description>
8348       <bitOffset>0</bitOffset>
8349       <bitWidth>32</bitWidth>
8350       <enumeratedValues>
8351        <enumeratedValue>
8352         <name>primary</name>
8353         <description>Primary function selected.</description>
8354         <value>0</value>
8355        </enumeratedValue>
8356        <enumeratedValue>
8357         <name>secondary</name>
8358         <description>Secondary function selected.</description>
8359         <value>1</value>
8360        </enumeratedValue>
8361       </enumeratedValues>
8362      </field>
8363     </fields>
8364    </register>
8365    <register>
8366     <name>EN2_SET</name>
8367     <description>GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.</description>
8368     <addressOffset>0x78</addressOffset>
8369     <fields>
8370      <field>
8371       <name>ALL</name>
8372       <description>Mask of all of the pins on the port.</description>
8373       <bitOffset>0</bitOffset>
8374       <bitWidth>32</bitWidth>
8375      </field>
8376     </fields>
8377    </register>
8378    <register>
8379     <name>EN2_CLR</name>
8380     <description>GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.</description>
8381     <addressOffset>0x7C</addressOffset>
8382     <fields>
8383      <field>
8384       <name>ALL</name>
8385       <description>Mask of all of the pins on the port.</description>
8386       <bitOffset>0</bitOffset>
8387       <bitWidth>32</bitWidth>
8388      </field>
8389     </fields>
8390    </register>
8391    <register>
8392     <name>HYSEN</name>
8393     <description>GPIO Input Hysteresis Enable.</description>
8394     <addressOffset>0xA8</addressOffset>
8395     <fields>
8396      <field>
8397       <name>GPIO_HYSEN</name>
8398       <description>Mask of all of the pins on the port.</description>
8399       <bitOffset>0</bitOffset>
8400       <bitWidth>32</bitWidth>
8401      </field>
8402     </fields>
8403    </register>
8404    <register>
8405     <name>SRSEL</name>
8406     <description>GPIO Slew Rate Enable Register.</description>
8407     <addressOffset>0xAC</addressOffset>
8408     <fields>
8409      <field>
8410       <name>GPIO_SRSEL</name>
8411       <description>Mask of all of the pins on the port.</description>
8412       <bitOffset>0</bitOffset>
8413       <bitWidth>32</bitWidth>
8414       <enumeratedValues>
8415        <enumeratedValue>
8416         <name>FAST</name>
8417         <description>Fast Slew Rate selected.</description>
8418         <value>0</value>
8419        </enumeratedValue>
8420        <enumeratedValue>
8421         <name>SLOW</name>
8422         <description>Slow Slew Rate selected.</description>
8423         <value>1</value>
8424        </enumeratedValue>
8425       </enumeratedValues>
8426      </field>
8427     </fields>
8428    </register>
8429    <register>
8430     <name>DS0</name>
8431     <description>GPIO Drive Strength  Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description>
8432     <addressOffset>0xB0</addressOffset>
8433     <fields>
8434      <field>
8435       <name>GPIO_DS0</name>
8436       <description>Mask of all of the pins on the port.</description>
8437       <bitOffset>0</bitOffset>
8438       <bitWidth>32</bitWidth>
8439       <enumeratedValues>
8440        <enumeratedValue>
8441         <name>ld</name>
8442         <description>GPIO port pin is in low-drive mode.</description>
8443         <value>0</value>
8444        </enumeratedValue>
8445        <enumeratedValue>
8446         <name>hd</name>
8447         <description>GPIO port pin is in high-drive mode.</description>
8448         <value>1</value>
8449        </enumeratedValue>
8450       </enumeratedValues>
8451      </field>
8452     </fields>
8453    </register>
8454    <register>
8455     <name>DS1</name>
8456     <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description>
8457     <addressOffset>0xB4</addressOffset>
8458     <fields>
8459      <field>
8460       <name>GPIO_DS1</name>
8461       <description>Mask of all of the pins on the port.</description>
8462       <bitOffset>0</bitOffset>
8463       <bitWidth>32</bitWidth>
8464      </field>
8465     </fields>
8466    </register>
8467    <register>
8468     <name>PS</name>
8469     <description>GPIO Pull Select Mode.</description>
8470     <addressOffset>0xB8</addressOffset>
8471     <fields>
8472      <field>
8473       <name>ALL</name>
8474       <description>Mask of all of the pins on the port.</description>
8475       <bitOffset>0</bitOffset>
8476       <bitWidth>32</bitWidth>
8477      </field>
8478     </fields>
8479    </register>
8480    <register>
8481     <name>VSSEL</name>
8482     <description>GPIO Voltage Select.</description>
8483     <addressOffset>0xC0</addressOffset>
8484     <fields>
8485      <field>
8486       <name>ALL</name>
8487       <description>Mask of all of the pins on the port.</description>
8488       <bitOffset>0</bitOffset>
8489       <bitWidth>32</bitWidth>
8490      </field>
8491     </fields>
8492    </register>
8493   </registers>
8494  </peripheral>
8495<!--GPIO0 Individual I/O for each GPIO-->
8496  <peripheral derivedFrom="GPIO0">
8497   <name>GPIO1</name>
8498   <description>Individual I/O for each GPIO 1</description>
8499   <baseAddress>0x40009000</baseAddress>
8500   <interrupt>
8501    <name>GPIO1</name>
8502    <description>GPIO1 IRQ</description>
8503    <value>25</value>
8504   </interrupt>
8505  </peripheral>
8506<!--GPIO1 Individual I/O for each GPIO 1-->
8507  <peripheral derivedFrom="GPIO0">
8508   <name>GPIO2</name>
8509   <description>Individual I/O for each GPIO 2</description>
8510   <baseAddress>0x40080400</baseAddress>
8511   <interrupt>
8512    <name>GPIO2</name>
8513    <description>GPIO2 IRQ</description>
8514    <value>26</value>
8515   </interrupt>
8516  </peripheral>
8517<!--GPIO2 Individual I/O for each GPIO 2-->
8518  <peripheral>
8519   <name>I2C0</name>
8520   <description>Inter-Integrated Circuit.</description>
8521   <groupName>I2C</groupName>
8522   <baseAddress>0x4001D000</baseAddress>
8523   <size>32</size>
8524   <addressBlock>
8525    <offset>0x00</offset>
8526    <size>0x1000</size>
8527    <usage>registers</usage>
8528   </addressBlock>
8529   <interrupt>
8530    <name>I2C0</name>
8531    <description>I2C0 IRQ</description>
8532    <value>13</value>
8533   </interrupt>
8534   <registers>
8535    <register>
8536     <name>CTRL</name>
8537     <description>Control Register0.</description>
8538     <addressOffset>0x00</addressOffset>
8539     <fields>
8540      <field>
8541       <name>EN</name>
8542       <description>I2C Enable.</description>
8543       <bitRange>[0:0]</bitRange>
8544       <access>read-write</access>
8545       <enumeratedValues>
8546        <enumeratedValue>
8547         <name>dis</name>
8548         <description>Disable I2C.</description>
8549         <value>0</value>
8550        </enumeratedValue>
8551        <enumeratedValue>
8552         <name>en</name>
8553         <description>enable I2C.</description>
8554         <value>1</value>
8555        </enumeratedValue>
8556       </enumeratedValues>
8557      </field>
8558      <field>
8559       <name>MST_MODE</name>
8560       <description>Master Mode Enable.</description>
8561       <bitRange>[1:1]</bitRange>
8562       <access>read-write</access>
8563       <enumeratedValues>
8564        <enumeratedValue>
8565         <name>slave_mode</name>
8566         <description>Slave Mode.</description>
8567         <value>0</value>
8568        </enumeratedValue>
8569        <enumeratedValue>
8570         <name>master_mode</name>
8571         <description>Master Mode.</description>
8572         <value>1</value>
8573        </enumeratedValue>
8574       </enumeratedValues>
8575      </field>
8576      <field>
8577       <name>GC_ADDR_EN</name>
8578       <description>General Call Address Enable.</description>
8579       <bitRange>[2:2]</bitRange>
8580       <access>read-write</access>
8581       <enumeratedValues>
8582        <enumeratedValue>
8583         <name>dis</name>
8584         <description>Ignore Gneral Call Address.</description>
8585         <value>0</value>
8586        </enumeratedValue>
8587        <enumeratedValue>
8588         <name>en</name>
8589         <description>Acknowledge general call address.</description>
8590         <value>1</value>
8591        </enumeratedValue>
8592       </enumeratedValues>
8593      </field>
8594      <field>
8595       <name>IRXM_EN</name>
8596       <description>Interactive Receive Mode.</description>
8597       <bitRange>[3:3]</bitRange>
8598       <access>read-write</access>
8599       <enumeratedValues>
8600        <enumeratedValue>
8601         <name>dis</name>
8602         <description>Disable Interactive Receive Mode.</description>
8603         <value>0</value>
8604        </enumeratedValue>
8605        <enumeratedValue>
8606         <name>en</name>
8607         <description>Enable Interactive Receive Mode.</description>
8608         <value>1</value>
8609        </enumeratedValue>
8610       </enumeratedValues>
8611      </field>
8612      <field>
8613       <name>IRXM_ACK</name>
8614       <description>Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.</description>
8615       <bitRange>[4:4]</bitRange>
8616       <access>read-write</access>
8617       <enumeratedValues>
8618        <enumeratedValue>
8619         <name>ack</name>
8620         <description>return ACK (pulling SDA LOW).</description>
8621         <value>0</value>
8622        </enumeratedValue>
8623        <enumeratedValue>
8624         <name>nack</name>
8625         <description>return NACK (leaving SDA HIGH).</description>
8626         <value>1</value>
8627        </enumeratedValue>
8628       </enumeratedValues>
8629      </field>
8630      <field>
8631       <name>SCL_OUT</name>
8632       <description>SCL Output. This bits control SCL output when SWOE =1.</description>
8633       <bitRange>[6:6]</bitRange>
8634       <access>read-write</access>
8635       <enumeratedValues>
8636        <enumeratedValue>
8637         <name>drive_scl_low</name>
8638         <description>Drive SCL low. </description>
8639         <value>0</value>
8640        </enumeratedValue>
8641        <enumeratedValue>
8642         <name>release_scl</name>
8643         <description>Release SCL.</description>
8644         <value>1</value>
8645        </enumeratedValue>
8646       </enumeratedValues>
8647      </field>
8648      <field>
8649       <name>SDA_OUT</name>
8650       <description>SDA Output. This bits control SDA output when SWOE = 1. </description>
8651       <bitRange>[7:7]</bitRange>
8652       <access>read-write</access>
8653       <enumeratedValues>
8654        <enumeratedValue>
8655         <name>drive_sda_low</name>
8656         <description>Drive SDA low. </description>
8657         <value>0</value>
8658        </enumeratedValue>
8659        <enumeratedValue>
8660         <name>release_sda</name>
8661         <description>Release SDA.</description>
8662         <value>1</value>
8663        </enumeratedValue>
8664       </enumeratedValues>
8665      </field>
8666      <field>
8667       <name>SCL</name>
8668       <description>SCL status. This bit reflects the logic gate of SCL signal. </description>
8669       <bitRange>[8:8]</bitRange>
8670       <access>read-only</access>
8671      </field>
8672      <field>
8673       <name>SDA</name>
8674       <description>SDA status. THis bit reflects the logic gate of SDA signal.</description>
8675       <bitRange>[9:9]</bitRange>
8676       <access>read-only</access>
8677      </field>
8678      <field>
8679       <name>BB_MODE</name>
8680       <description>Software Output Enable.</description>
8681       <bitRange>[10:10]</bitRange>
8682       <access>read-write</access>
8683       <enumeratedValues>
8684        <enumeratedValue>
8685         <name>outputs_disable</name>
8686         <description>I2C Outputs SCLO and SDAO disabled. </description>
8687         <value>0</value>
8688        </enumeratedValue>
8689        <enumeratedValue>
8690         <name>outputs_enable</name>
8691         <description>I2C Outputs SCLO and SDAO enabled.</description>
8692         <value>1</value>
8693        </enumeratedValue>
8694       </enumeratedValues>
8695      </field>
8696      <field>
8697       <name>READ</name>
8698       <description>Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.</description>
8699       <bitRange>[11:11]</bitRange>
8700       <access>read-only</access>
8701       <enumeratedValues>
8702        <enumeratedValue>
8703         <name>write</name>
8704         <description>Write.</description>
8705         <value>0</value>
8706        </enumeratedValue>
8707        <enumeratedValue>
8708         <name>read</name>
8709         <description>Read.</description>
8710         <value>1</value>
8711        </enumeratedValue>
8712       </enumeratedValues>
8713      </field>
8714      <field>
8715       <name>CLKSTR_DIS</name>
8716       <description>This bit will disable slave clock stretching when set.</description>
8717       <bitRange>[12:12]</bitRange>
8718       <access>read-write</access>
8719       <enumeratedValues>
8720        <enumeratedValue>
8721         <name>en</name>
8722         <description>Slave clock stretching enabled.</description>
8723         <value>0</value>
8724        </enumeratedValue>
8725        <enumeratedValue>
8726         <name>dis</name>
8727         <description>Slave clock stretching disabled.</description>
8728         <value>1</value>
8729        </enumeratedValue>
8730       </enumeratedValues>
8731      </field>
8732      <field>
8733       <name>ONE_MST_MODE</name>
8734       <description>SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. </description>
8735       <bitRange>[13:13]</bitRange>
8736       <access>read-write</access>
8737       <enumeratedValues>
8738        <enumeratedValue>
8739         <name>dis</name>
8740         <description>Standard open-drain operation:
8741					drive low for 0, Hi-Z for 1</description>
8742         <value>0</value>
8743        </enumeratedValue>
8744        <enumeratedValue>
8745         <name>en</name>
8746         <description>Non-standard push-pull operation:
8747					drive low for 0, drive high for 1</description>
8748         <value>1</value>
8749        </enumeratedValue>
8750       </enumeratedValues>
8751      </field>
8752      <field>
8753       <name>HS_EN</name>
8754       <description>High speed mode enable</description>
8755       <bitRange>[15:15]</bitRange>
8756       <access>read-write</access>
8757      </field>
8758     </fields>
8759    </register>
8760    <register>
8761     <name>STATUS</name>
8762     <description>Status Register.</description>
8763     <addressOffset>0x04</addressOffset>
8764     <fields>
8765      <field>
8766       <name>BUSY</name>
8767       <description>Bus Status.</description>
8768       <bitRange>[0:0]</bitRange>
8769       <access>read-only</access>
8770       <enumeratedValues>
8771        <enumeratedValue>
8772         <name>idle</name>
8773         <description>I2C Bus Idle.</description>
8774         <value>0</value>
8775        </enumeratedValue>
8776        <enumeratedValue>
8777         <name>busy</name>
8778         <description>I2C Bus Busy.</description>
8779         <value>1</value>
8780        </enumeratedValue>
8781       </enumeratedValues>
8782      </field>
8783      <field>
8784       <name>RX_EM</name>
8785       <description>RX empty.</description>
8786       <bitRange>[1:1]</bitRange>
8787       <access>read-only</access>
8788       <enumeratedValues>
8789        <enumeratedValue>
8790         <name>not_empty</name>
8791         <description>Not Empty.</description>
8792         <value>0</value>
8793        </enumeratedValue>
8794        <enumeratedValue>
8795         <name>empty</name>
8796         <description>Empty.</description>
8797         <value>1</value>
8798        </enumeratedValue>
8799       </enumeratedValues>
8800      </field>
8801      <field>
8802       <name>RX_FULL</name>
8803       <description>RX Full.</description>
8804       <bitRange>[2:2]</bitRange>
8805       <access>read-only</access>
8806       <enumeratedValues>
8807        <enumeratedValue>
8808         <name>not_full</name>
8809         <description>Not Full.</description>
8810         <value>0</value>
8811        </enumeratedValue>
8812        <enumeratedValue>
8813         <name>full</name>
8814         <description>Full.</description>
8815         <value>1</value>
8816        </enumeratedValue>
8817       </enumeratedValues>
8818      </field>
8819      <field>
8820       <name>TX_EM</name>
8821       <description>TX Empty.</description>
8822       <bitRange>[3:3]</bitRange>
8823       <enumeratedValues>
8824        <enumeratedValue>
8825         <name>not_empty</name>
8826         <description>Not Empty.</description>
8827         <value>0</value>
8828        </enumeratedValue>
8829        <enumeratedValue>
8830         <name>empty</name>
8831         <description>Empty.</description>
8832         <value>1</value>
8833        </enumeratedValue>
8834       </enumeratedValues>
8835      </field>
8836      <field>
8837       <name>TX_FULL</name>
8838       <description>TX Full.</description>
8839       <bitRange>[4:4]</bitRange>
8840       <enumeratedValues>
8841        <enumeratedValue>
8842         <name>not_empty</name>
8843         <description>Not Empty.</description>
8844         <value>0</value>
8845        </enumeratedValue>
8846        <enumeratedValue>
8847         <name>empty</name>
8848         <description>Empty.</description>
8849         <value>1</value>
8850        </enumeratedValue>
8851       </enumeratedValues>
8852      </field>
8853      <field>
8854       <name>MST_BUSY</name>
8855       <description>Clock Mode.</description>
8856       <bitRange>[5:5]</bitRange>
8857       <access>read-only</access>
8858       <enumeratedValues>
8859        <enumeratedValue>
8860         <name>not_actively_driving_scl_clock</name>
8861         <description>Device not actively driving SCL clock cycles.</description>
8862         <value>0</value>
8863        </enumeratedValue>
8864        <enumeratedValue>
8865         <name>actively_driving_scl_clock</name>
8866         <description>Device operating as master and actively driving SCL clock cycles.</description>
8867         <value>1</value>
8868        </enumeratedValue>
8869       </enumeratedValues>
8870      </field>
8871     </fields>
8872    </register>
8873    <register>
8874     <name>INTFL0</name>
8875     <description>Interrupt Status Register.</description>
8876     <addressOffset>0x08</addressOffset>
8877     <fields>
8878      <field>
8879       <name>DONE</name>
8880       <description>Transfer Done Interrupt.</description>
8881       <bitRange>[0:0]</bitRange>
8882       <enumeratedValues>
8883        <name>INT_FL0_Done</name>
8884        <enumeratedValue>
8885         <name>inactive</name>
8886         <description>No Interrupt is Pending.</description>
8887         <value>0</value>
8888        </enumeratedValue>
8889        <enumeratedValue>
8890         <name>pending</name>
8891         <description>An interrupt is pending.</description>
8892         <value>1</value>
8893        </enumeratedValue>
8894       </enumeratedValues>
8895      </field>
8896      <field>
8897       <name>IRXM</name>
8898       <description>Interactive Receive Interrupt.</description>
8899       <bitRange>[1:1]</bitRange>
8900       <enumeratedValues>
8901        <enumeratedValue>
8902         <name>inactive</name>
8903         <description>No Interrupt is Pending.</description>
8904         <value>0</value>
8905        </enumeratedValue>
8906        <enumeratedValue>
8907         <name>pending</name>
8908         <description>An interrupt is pending.</description>
8909         <value>1</value>
8910        </enumeratedValue>
8911       </enumeratedValues>
8912      </field>
8913      <field>
8914       <name>GC_ADDR_MATCH</name>
8915       <description>Slave General Call Address Match Interrupt.</description>
8916       <bitRange>[2:2]</bitRange>
8917       <enumeratedValues>
8918        <enumeratedValue>
8919         <name>inactive</name>
8920         <description>No Interrupt is Pending.</description>
8921         <value>0</value>
8922        </enumeratedValue>
8923        <enumeratedValue>
8924         <name>pending</name>
8925         <description>An interrupt is pending.</description>
8926         <value>1</value>
8927        </enumeratedValue>
8928       </enumeratedValues>
8929      </field>
8930      <field>
8931       <name>ADDR_MATCH</name>
8932       <description>Slave Address Match Interrupt.</description>
8933       <bitRange>[3:3]</bitRange>
8934       <enumeratedValues>
8935        <enumeratedValue>
8936         <name>inactive</name>
8937         <description>No Interrupt is Pending.</description>
8938         <value>0</value>
8939        </enumeratedValue>
8940        <enumeratedValue>
8941         <name>pending</name>
8942         <description>An interrupt is pending.</description>
8943         <value>1</value>
8944        </enumeratedValue>
8945       </enumeratedValues>
8946      </field>
8947      <field>
8948       <name>RX_THD</name>
8949       <description>Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.</description>
8950       <bitRange>[4:4]</bitRange>
8951       <enumeratedValues>
8952        <enumeratedValue>
8953         <name>inactive</name>
8954         <description>No interrupt is pending.</description>
8955         <value>0</value>
8956        </enumeratedValue>
8957        <enumeratedValue>
8958         <name>pending</name>
8959         <description>An interrupt is pending. RX_FIFO equal or more bytes than the threshold.</description>
8960         <value>1</value>
8961        </enumeratedValue>
8962       </enumeratedValues>
8963      </field>
8964      <field>
8965       <name>TX_THD</name>
8966       <description>Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.</description>
8967       <bitRange>[5:5]</bitRange>
8968       <enumeratedValues>
8969        <enumeratedValue>
8970         <name>inactive</name>
8971         <description>No interrupt is pending.</description>
8972         <value>0</value>
8973        </enumeratedValue>
8974        <enumeratedValue>
8975         <name>pending</name>
8976         <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description>
8977         <value>1</value>
8978        </enumeratedValue>
8979       </enumeratedValues>
8980      </field>
8981      <field>
8982       <name>STOP</name>
8983       <description>STOP Interrupt.</description>
8984       <bitRange>[6:6]</bitRange>
8985       <enumeratedValues>
8986        <enumeratedValue>
8987         <name>inactive</name>
8988         <description>No interrupt is pending.</description>
8989         <value>0</value>
8990        </enumeratedValue>
8991        <enumeratedValue>
8992         <name>pending</name>
8993         <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description>
8994         <value>1</value>
8995        </enumeratedValue>
8996       </enumeratedValues>
8997      </field>
8998      <field>
8999       <name>ADDR_ACK</name>
9000       <description>Address Acknowledge Interrupt.</description>
9001       <bitRange>[7:7]</bitRange>
9002       <enumeratedValues>
9003        <enumeratedValue>
9004         <name>inactive</name>
9005         <description>No Interrupt is Pending.</description>
9006         <value>0</value>
9007        </enumeratedValue>
9008        <enumeratedValue>
9009         <name>pending</name>
9010         <description>An interrupt is pending.</description>
9011         <value>1</value>
9012        </enumeratedValue>
9013       </enumeratedValues>
9014      </field>
9015      <field>
9016       <name>ARB_ERR</name>
9017       <description>Arbritation error Interrupt.</description>
9018       <bitRange>[8:8]</bitRange>
9019       <enumeratedValues>
9020        <enumeratedValue>
9021         <name>inactive</name>
9022         <description>No Interrupt is Pending.</description>
9023         <value>0</value>
9024        </enumeratedValue>
9025        <enumeratedValue>
9026         <name>pending</name>
9027         <description>An interrupt is pending.</description>
9028         <value>1</value>
9029        </enumeratedValue>
9030       </enumeratedValues>
9031      </field>
9032      <field>
9033       <name>TO_ERR</name>
9034       <description>timeout Error Interrupt.</description>
9035       <bitRange>[9:9]</bitRange>
9036       <enumeratedValues>
9037        <enumeratedValue>
9038         <name>inactive</name>
9039         <description>No Interrupt is Pending.</description>
9040         <value>0</value>
9041        </enumeratedValue>
9042        <enumeratedValue>
9043         <name>pending</name>
9044         <description>An interrupt is pending.</description>
9045         <value>1</value>
9046        </enumeratedValue>
9047       </enumeratedValues>
9048      </field>
9049      <field>
9050       <name>ADDR_NACK_ERR</name>
9051       <description>Address NACK Error Interrupt.</description>
9052       <bitRange>[10:10]</bitRange>
9053       <enumeratedValues>
9054        <enumeratedValue>
9055         <name>inactive</name>
9056         <description>No Interrupt is Pending.</description>
9057         <value>0</value>
9058        </enumeratedValue>
9059        <enumeratedValue>
9060         <name>pending</name>
9061         <description>An interrupt is pending.</description>
9062         <value>1</value>
9063        </enumeratedValue>
9064       </enumeratedValues>
9065      </field>
9066      <field>
9067       <name>DATA_ERR</name>
9068       <description>Data NACK Error Interrupt.</description>
9069       <bitRange>[11:11]</bitRange>
9070       <enumeratedValues>
9071        <enumeratedValue>
9072         <name>inactive</name>
9073         <description>No Interrupt is Pending.</description>
9074         <value>0</value>
9075        </enumeratedValue>
9076        <enumeratedValue>
9077         <name>pending</name>
9078         <description>An interrupt is pending.</description>
9079         <value>1</value>
9080        </enumeratedValue>
9081       </enumeratedValues>
9082      </field>
9083      <field>
9084       <name>DNR_ERR</name>
9085       <description>Do Not Respond Error Interrupt.</description>
9086       <bitRange>[12:12]</bitRange>
9087       <enumeratedValues>
9088        <enumeratedValue>
9089         <name>inactive</name>
9090         <description>No Interrupt is Pending.</description>
9091         <value>0</value>
9092        </enumeratedValue>
9093        <enumeratedValue>
9094         <name>pending</name>
9095         <description>An interrupt is pending.</description>
9096         <value>1</value>
9097        </enumeratedValue>
9098       </enumeratedValues>
9099      </field>
9100      <field>
9101       <name>START_ERR</name>
9102       <description>Start Error Interrupt.</description>
9103       <bitRange>[13:13]</bitRange>
9104       <enumeratedValues>
9105        <enumeratedValue>
9106         <name>inactive</name>
9107         <description>No Interrupt is Pending.</description>
9108         <value>0</value>
9109        </enumeratedValue>
9110        <enumeratedValue>
9111         <name>pending</name>
9112         <description>An interrupt is pending.</description>
9113         <value>1</value>
9114        </enumeratedValue>
9115       </enumeratedValues>
9116      </field>
9117      <field>
9118       <name>STOP_ERR</name>
9119       <description>Stop Error Interrupt.</description>
9120       <bitRange>[14:14]</bitRange>
9121       <enumeratedValues>
9122        <enumeratedValue>
9123         <name>inactive</name>
9124         <description>No Interrupt is Pending.</description>
9125         <value>0</value>
9126        </enumeratedValue>
9127        <enumeratedValue>
9128         <name>pending</name>
9129         <description>An interrupt is pending.</description>
9130         <value>1</value>
9131        </enumeratedValue>
9132       </enumeratedValues>
9133      </field>
9134      <field>
9135       <name>TX_LOCKOUT</name>
9136       <description>Transmit Lock Out Interrupt.</description>
9137       <bitRange>[15:15]</bitRange>
9138      </field>
9139      <field>
9140       <name>MAMI</name>
9141       <description>Multiple Address Match Interrupt</description>
9142       <bitRange>[21:16]</bitRange>
9143      </field>
9144      <field>
9145       <name>RD_ADDR_MATCH</name>
9146       <description>Slave Read Address Match Interrupt</description>
9147       <bitRange>[22:22]</bitRange>
9148      </field>
9149      <field>
9150       <name>WR_ADDR_MATCH</name>
9151       <description>Slave Write Address Match Interrupt</description>
9152       <bitRange>[23:23]</bitRange>
9153      </field>
9154     </fields>
9155    </register>
9156    <register>
9157     <name>INTEN0</name>
9158     <description>Interrupt Enable Register.</description>
9159     <addressOffset>0x0C</addressOffset>
9160     <access>read-write</access>
9161     <fields>
9162      <field>
9163       <name>DONE</name>
9164       <description>Transfer Done Interrupt Enable.</description>
9165       <bitRange>[0:0]</bitRange>
9166       <access>read-write</access>
9167       <enumeratedValues>
9168        <enumeratedValue>
9169         <name>dis</name>
9170         <description>Interrupt disabled.</description>
9171         <value>0</value>
9172        </enumeratedValue>
9173        <enumeratedValue>
9174         <name>en</name>
9175         <description>Interrupt enabled when DONE = 1.</description>
9176         <value>1</value>
9177        </enumeratedValue>
9178       </enumeratedValues>
9179      </field>
9180      <field>
9181       <name>IRXM</name>
9182       <description>Description not available.</description>
9183       <bitRange>[1:1]</bitRange>
9184       <access>read-write</access>
9185       <enumeratedValues>
9186        <enumeratedValue>
9187         <name>dis</name>
9188         <description>Interrupt disabled.</description>
9189         <value>0</value>
9190        </enumeratedValue>
9191        <enumeratedValue>
9192         <name>en</name>
9193         <description>Interrupt enabled when RX_MODE = 1.</description>
9194         <value>1</value>
9195        </enumeratedValue>
9196       </enumeratedValues>
9197      </field>
9198      <field>
9199       <name>GC_ADDR_MATCH</name>
9200       <description>Slave mode general call address match received input enable.</description>
9201       <bitRange>[2:2]</bitRange>
9202       <access>read-write</access>
9203       <enumeratedValues>
9204        <enumeratedValue>
9205         <name>dis</name>
9206         <description>Interrupt disabled.</description>
9207         <value>0</value>
9208        </enumeratedValue>
9209        <enumeratedValue>
9210         <name>en</name>
9211         <description>Interrupt enabled when GEN_CTRL_ADDR = 1.</description>
9212         <value>1</value>
9213        </enumeratedValue>
9214       </enumeratedValues>
9215      </field>
9216      <field>
9217       <name>ADDR_MATCH</name>
9218       <description>Slave mode incoming address match interrupt.</description>
9219       <bitRange>[3:3]</bitRange>
9220       <access>read-write</access>
9221       <enumeratedValues>
9222        <enumeratedValue>
9223         <name>dis</name>
9224         <description>Interrupt disabled.</description>
9225         <value>0</value>
9226        </enumeratedValue>
9227        <enumeratedValue>
9228         <name>en</name>
9229         <description>Interrupt enabled when ADDR_MATCH = 1.</description>
9230         <value>1</value>
9231        </enumeratedValue>
9232       </enumeratedValues>
9233      </field>
9234      <field>
9235       <name>RX_THD</name>
9236       <description>RX FIFO Above Treshold Level Interrupt Enable.</description>
9237       <bitRange>[4:4]</bitRange>
9238       <access>read-write</access>
9239       <enumeratedValues>
9240        <enumeratedValue>
9241         <name>dis</name>
9242         <description>Interrupt disabled.</description>
9243         <value>0</value>
9244        </enumeratedValue>
9245        <enumeratedValue>
9246         <name>en</name>
9247         <description>Interrupt enabled.</description>
9248         <value>1</value>
9249        </enumeratedValue>
9250       </enumeratedValues>
9251      </field>
9252      <field>
9253       <name>TX_THD</name>
9254       <description>TX FIFO Below Treshold Level Interrupt Enable.</description>
9255       <bitRange>[5:5]</bitRange>
9256       <enumeratedValues>
9257        <enumeratedValue>
9258         <name>dis</name>
9259         <description>Interrupt disabled.</description>
9260         <value>0</value>
9261        </enumeratedValue>
9262        <enumeratedValue>
9263         <name>en</name>
9264         <description>Interrupt enabled.</description>
9265         <value>1</value>
9266        </enumeratedValue>
9267       </enumeratedValues>
9268      </field>
9269      <field>
9270       <name>STOP</name>
9271       <description>Stop Interrupt Enable</description>
9272       <bitRange>[6:6]</bitRange>
9273       <access>read-write</access>
9274       <enumeratedValues>
9275        <enumeratedValue>
9276         <name>dis</name>
9277         <description>Interrupt disabled.</description>
9278         <value>0</value>
9279        </enumeratedValue>
9280        <enumeratedValue>
9281         <name>en</name>
9282         <description>Interrupt enabled when STOP = 1.</description>
9283         <value>1</value>
9284        </enumeratedValue>
9285       </enumeratedValues>
9286      </field>
9287      <field>
9288       <name>ADDR_ACK</name>
9289       <description>Received Address ACK from Slave Interrupt.</description>
9290       <bitRange>[7:7]</bitRange>
9291       <enumeratedValues>
9292        <enumeratedValue>
9293         <name>dis</name>
9294         <description>Interrupt disabled.</description>
9295         <value>0</value>
9296        </enumeratedValue>
9297        <enumeratedValue>
9298         <name>en</name>
9299         <description>Interrupt enabled.</description>
9300         <value>1</value>
9301        </enumeratedValue>
9302       </enumeratedValues>
9303      </field>
9304      <field>
9305       <name>ARB_ERR</name>
9306       <description>Master Mode Arbitration Lost Interrupt.</description>
9307       <bitRange>[8:8]</bitRange>
9308       <enumeratedValues>
9309        <enumeratedValue>
9310         <name>dis</name>
9311         <description>Interrupt disabled.</description>
9312         <value>0</value>
9313        </enumeratedValue>
9314        <enumeratedValue>
9315         <name>en</name>
9316         <description>Interrupt enabled.</description>
9317         <value>1</value>
9318        </enumeratedValue>
9319       </enumeratedValues>
9320      </field>
9321      <field>
9322       <name>TO_ERR</name>
9323       <description>Timeout Error Interrupt Enable.</description>
9324       <bitRange>[9:9]</bitRange>
9325       <enumeratedValues>
9326        <enumeratedValue>
9327         <name>dis</name>
9328         <description>Interrupt disabled.</description>
9329         <value>0</value>
9330        </enumeratedValue>
9331        <enumeratedValue>
9332         <name>en</name>
9333         <description>Interrupt enabled.</description>
9334         <value>1</value>
9335        </enumeratedValue>
9336       </enumeratedValues>
9337      </field>
9338      <field>
9339       <name>ADDR_NACK_ERR</name>
9340       <description>Master Mode Address NACK Received Interrupt.</description>
9341       <bitRange>[10:10]</bitRange>
9342       <enumeratedValues>
9343        <enumeratedValue>
9344         <name>dis</name>
9345         <description>Interrupt disabled.</description>
9346         <value>0</value>
9347        </enumeratedValue>
9348        <enumeratedValue>
9349         <name>en</name>
9350         <description>Interrupt enabled.</description>
9351         <value>1</value>
9352        </enumeratedValue>
9353       </enumeratedValues>
9354      </field>
9355      <field>
9356       <name>DATA_ERR</name>
9357       <description>Master Mode Data NACK Received Interrupt.</description>
9358       <bitRange>[11:11]</bitRange>
9359       <enumeratedValues>
9360        <enumeratedValue>
9361         <name>dis</name>
9362         <description>Interrupt disabled.</description>
9363         <value>0</value>
9364        </enumeratedValue>
9365        <enumeratedValue>
9366         <name>en</name>
9367         <description>Interrupt enabled.</description>
9368         <value>1</value>
9369        </enumeratedValue>
9370       </enumeratedValues>
9371      </field>
9372      <field>
9373       <name>DNR_ERR</name>
9374       <description>Slave Mode Do Not Respond Interrupt.</description>
9375       <bitRange>[12:12]</bitRange>
9376       <enumeratedValues>
9377        <enumeratedValue>
9378         <name>dis</name>
9379         <description>Interrupt disabled.</description>
9380         <value>0</value>
9381        </enumeratedValue>
9382        <enumeratedValue>
9383         <name>en</name>
9384         <description>Interrupt enabled.</description>
9385         <value>1</value>
9386        </enumeratedValue>
9387       </enumeratedValues>
9388      </field>
9389      <field>
9390       <name>START_ERR</name>
9391       <description>Out of Sequence START condition detected interrupt.</description>
9392       <bitRange>[13:13]</bitRange>
9393       <enumeratedValues>
9394        <enumeratedValue>
9395         <name>dis</name>
9396         <description>Interrupt disabled.</description>
9397         <value>0</value>
9398        </enumeratedValue>
9399        <enumeratedValue>
9400         <name>en</name>
9401         <description>Interrupt enabled.</description>
9402         <value>1</value>
9403        </enumeratedValue>
9404       </enumeratedValues>
9405      </field>
9406      <field>
9407       <name>STOP_ERR</name>
9408       <description>Out of Sequence STOP condition detected interrupt.</description>
9409       <bitRange>[14:14]</bitRange>
9410       <enumeratedValues>
9411        <enumeratedValue>
9412         <name>dis</name>
9413         <description>Interrupt disabled.</description>
9414         <value>0</value>
9415        </enumeratedValue>
9416        <enumeratedValue>
9417         <name>en</name>
9418         <description>Interrupt enabled.</description>
9419         <value>1</value>
9420        </enumeratedValue>
9421       </enumeratedValues>
9422      </field>
9423      <field>
9424       <name>TX_LOCKOUT</name>
9425       <description>TX FIFO Locked Out Interrupt.</description>
9426       <bitRange>[15:15]</bitRange>
9427      </field>
9428      <field>
9429       <name>MAMI</name>
9430       <description>Multiple Address Match Interrupt</description>
9431       <bitRange>[21:16]</bitRange>
9432      </field>
9433      <field>
9434       <name>RD_ADDR_MATCH</name>
9435       <description>Slave Read Address Match Interrupt</description>
9436       <bitRange>[22:22]</bitRange>
9437      </field>
9438      <field>
9439       <name>WR_ADDR_MATCH</name>
9440       <description>Slave Write Address Match Interrupt</description>
9441       <bitRange>[23:23]</bitRange>
9442      </field>
9443     </fields>
9444    </register>
9445    <register>
9446     <name>INTFL1</name>
9447     <description>Interrupt Status Register 1.</description>
9448     <addressOffset>0x10</addressOffset>
9449     <fields>
9450      <field>
9451       <name>RX_OV</name>
9452       <description>Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.</description>
9453       <bitRange>[0:0]</bitRange>
9454       <enumeratedValues>
9455        <enumeratedValue>
9456         <name>inactive</name>
9457         <description>No Interrupt is Pending.</description>
9458         <value>0</value>
9459        </enumeratedValue>
9460        <enumeratedValue>
9461         <name>pending</name>
9462         <description>An interrupt is pending.</description>
9463         <value>1</value>
9464        </enumeratedValue>
9465       </enumeratedValues>
9466      </field>
9467      <field>
9468       <name>TX_UN</name>
9469       <description>Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).</description>
9470       <bitRange>[1:1]</bitRange>
9471       <enumeratedValues>
9472        <enumeratedValue>
9473         <name>inactive</name>
9474         <description>No Interrupt is Pending.</description>
9475         <value>0</value>
9476        </enumeratedValue>
9477        <enumeratedValue>
9478         <name>pending</name>
9479         <description>An interrupt is pending.</description>
9480         <value>1</value>
9481        </enumeratedValue>
9482       </enumeratedValues>
9483      </field>
9484      <field>
9485       <name>START</name>
9486       <description>START Condition Status Flag.</description>
9487       <bitRange>[2:2]</bitRange>
9488      </field>
9489     </fields>
9490    </register>
9491    <register>
9492     <name>INTEN1</name>
9493     <description>Interrupt Staus Register 1.</description>
9494     <addressOffset>0x14</addressOffset>
9495     <access>read-write</access>
9496     <fields>
9497      <field>
9498       <name>RX_OV</name>
9499       <description>Receiver Overflow Interrupt Enable.</description>
9500       <bitRange>[0:0]</bitRange>
9501       <enumeratedValues>
9502        <enumeratedValue>
9503         <name>dis</name>
9504         <description>No Interrupt is Pending.</description>
9505         <value>0</value>
9506        </enumeratedValue>
9507        <enumeratedValue>
9508         <name>en</name>
9509         <description>An interrupt is pending.</description>
9510         <value>1</value>
9511        </enumeratedValue>
9512       </enumeratedValues>
9513      </field>
9514      <field>
9515       <name>TX_UN</name>
9516       <description>Transmit Underflow Interrupt Enable.</description>
9517       <bitRange>[1:1]</bitRange>
9518       <enumeratedValues>
9519        <enumeratedValue>
9520         <name>dis</name>
9521         <description>No Interrupt is Pending.</description>
9522         <value>0</value>
9523        </enumeratedValue>
9524        <enumeratedValue>
9525         <name>en</name>
9526         <description>An interrupt is pending.</description>
9527         <value>1</value>
9528        </enumeratedValue>
9529       </enumeratedValues>
9530      </field>
9531      <field>
9532       <name>START</name>
9533       <description>START Condition Interrupt Enable.</description>
9534       <bitRange>[2:2]</bitRange>
9535      </field>
9536     </fields>
9537    </register>
9538    <register>
9539     <name>FIFOLEN</name>
9540     <description>FIFO Configuration Register.</description>
9541     <addressOffset>0x18</addressOffset>
9542     <fields>
9543      <field>
9544       <name>RX_DEPTH</name>
9545       <description>Receive FIFO Length.</description>
9546       <bitRange>[7:0]</bitRange>
9547       <access>read-only</access>
9548      </field>
9549      <field>
9550       <name>TX_DEPTH</name>
9551       <description>Transmit FIFO Length.</description>
9552       <bitRange>[15:8]</bitRange>
9553       <access>read-only</access>
9554      </field>
9555     </fields>
9556    </register>
9557    <register>
9558     <name>RXCTRL0</name>
9559     <description>Receive Control Register 0.</description>
9560     <addressOffset>0x1C</addressOffset>
9561     <fields>
9562      <field>
9563       <name>DNR</name>
9564       <description>Do Not Respond.</description>
9565       <bitRange>[0:0]</bitRange>
9566       <enumeratedValues>
9567        <enumeratedValue>
9568         <name>respond</name>
9569         <description>Always respond to address match.</description>
9570         <value>0</value>
9571        </enumeratedValue>
9572        <enumeratedValue>
9573         <name>not_respond_rx_fifo_empty</name>
9574         <description>Do not respond to address match when RX_FIFO is not empty.</description>
9575         <value>1</value>
9576        </enumeratedValue>
9577       </enumeratedValues>
9578      </field>
9579      <field>
9580       <name>FLUSH</name>
9581       <description>Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.</description>
9582       <bitRange>[7:7]</bitRange>
9583       <enumeratedValues>
9584        <enumeratedValue>
9585         <name>not_flushed</name>
9586         <description>FIFO not flushed.</description>
9587         <value>0</value>
9588        </enumeratedValue>
9589        <enumeratedValue>
9590         <name>flush</name>
9591         <description>Flush RX_FIFO.</description>
9592         <value>1</value>
9593        </enumeratedValue>
9594       </enumeratedValues>
9595      </field>
9596      <field>
9597       <name>THD_LVL</name>
9598       <description>Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.</description>
9599       <bitRange>[11:8]</bitRange>
9600      </field>
9601     </fields>
9602    </register>
9603    <register>
9604     <name>RXCTRL1</name>
9605     <description>Receive Control Register 1.</description>
9606     <addressOffset>0x20</addressOffset>
9607     <fields>
9608      <field>
9609       <name>CNT</name>
9610       <description>Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.</description>
9611       <bitRange>[7:0]</bitRange>
9612      </field>
9613      <field>
9614       <name>LVL</name>
9615       <description>Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.</description>
9616       <bitRange>[11:8]</bitRange>
9617       <access>read-only</access>
9618      </field>
9619     </fields>
9620    </register>
9621    <register>
9622     <name>TXCTRL0</name>
9623     <description>Transmit Control Register 0.</description>
9624     <addressOffset>0x24</addressOffset>
9625     <fields>
9626      <field>
9627       <name>PRELOAD_MODE</name>
9628       <description>Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.</description>
9629       <bitRange>[0:0]</bitRange>
9630      </field>
9631      <field>
9632       <name>TX_READY_MODE</name>
9633       <description>Transmit FIFO Ready Manual Mode.</description>
9634       <bitRange>[1:1]</bitRange>
9635       <enumeratedValues>
9636        <enumeratedValue>
9637         <name>en</name>
9638         <description>HW control of I2CTXRDY enabled.</description>
9639         <value>0</value>
9640        </enumeratedValue>
9641        <enumeratedValue>
9642         <name>dis</name>
9643         <description>HW control of I2CTXRDY disabled.</description>
9644         <value>1</value>
9645        </enumeratedValue>
9646       </enumeratedValues>
9647      </field>
9648      <field>
9649       <name>GC_ADDR_FLUSH_DIS</name>
9650       <description>TX FIFO General Call Address Match Auto Flush Disable.</description>
9651       <bitRange>[2:2]</bitRange>
9652       <enumeratedValues>
9653        <enumeratedValue>
9654         <name>en</name>
9655         <description>Enabled.</description>
9656         <value>0</value>
9657        </enumeratedValue>
9658        <enumeratedValue>
9659         <name>dis</name>
9660         <description>Disabled.</description>
9661         <value>1</value>
9662        </enumeratedValue>
9663       </enumeratedValues>
9664      </field>
9665      <field>
9666       <name>WR_ADDR_FLUSH_DIS</name>
9667       <description>TX FIFO Slave Address Match Write Auto Flush Disable.</description>
9668       <bitRange>[3:3]</bitRange>
9669       <enumeratedValues>
9670        <enumeratedValue>
9671         <name>en</name>
9672         <description>Enabled.</description>
9673         <value>0</value>
9674        </enumeratedValue>
9675        <enumeratedValue>
9676         <name>dis</name>
9677         <description>Disabled.</description>
9678         <value>1</value>
9679        </enumeratedValue>
9680       </enumeratedValues>
9681      </field>
9682      <field>
9683       <name>RD_ADDR_FLUSH_DIS</name>
9684       <description>TX FIFO Slave Address Match Read Auto Flush Disable.</description>
9685       <bitRange>[4:4]</bitRange>
9686       <enumeratedValues>
9687        <enumeratedValue>
9688         <name>en</name>
9689         <description>Enabled.</description>
9690         <value>0</value>
9691        </enumeratedValue>
9692        <enumeratedValue>
9693         <name>dis</name>
9694         <description>Disabled.</description>
9695         <value>1</value>
9696        </enumeratedValue>
9697       </enumeratedValues>
9698      </field>
9699      <field>
9700       <name>NACK_FLUSH_DIS</name>
9701       <description>TX FIFO received NACK Auto Flush Disable.</description>
9702       <bitRange>[5:5]</bitRange>
9703       <enumeratedValues>
9704        <enumeratedValue>
9705         <name>en</name>
9706         <description>Enabled.</description>
9707         <value>0</value>
9708        </enumeratedValue>
9709        <enumeratedValue>
9710         <name>dis</name>
9711         <description>Disabled.</description>
9712         <value>1</value>
9713        </enumeratedValue>
9714       </enumeratedValues>
9715      </field>
9716      <field>
9717       <name>FLUSH</name>
9718       <description>Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.</description>
9719       <bitRange>[7:7]</bitRange>
9720       <enumeratedValues>
9721        <enumeratedValue>
9722         <name>not_flushed</name>
9723         <description>FIFO not flushed.</description>
9724         <value>0</value>
9725        </enumeratedValue>
9726        <enumeratedValue>
9727         <name>flush</name>
9728         <description>Flush TX_FIFO.</description>
9729         <value>1</value>
9730        </enumeratedValue>
9731       </enumeratedValues>
9732      </field>
9733      <field>
9734       <name>THD_VAL</name>
9735       <description>Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.</description>
9736       <bitRange>[11:8]</bitRange>
9737      </field>
9738     </fields>
9739    </register>
9740    <register>
9741     <name>TXCTRL1</name>
9742     <description>Transmit Control Register 1.</description>
9743     <addressOffset>0x28</addressOffset>
9744     <fields>
9745      <field>
9746       <name>PRELOAD_RDY</name>
9747       <description>Transmit FIFO Preload Ready.</description>
9748       <bitRange>[0:0]</bitRange>
9749      </field>
9750      <field>
9751       <name>LVL</name>
9752       <description>Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.</description>
9753       <bitRange>[11:8]</bitRange>
9754       <access>read-only</access>
9755      </field>
9756     </fields>
9757    </register>
9758    <register>
9759     <name>FIFO</name>
9760     <description>Data Register.</description>
9761     <addressOffset>0x2C</addressOffset>
9762     <fields>
9763      <field>
9764       <name>DATA</name>
9765       <description>Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.</description>
9766       <bitOffset>0</bitOffset>
9767       <bitWidth>8</bitWidth>
9768      </field>
9769     </fields>
9770    </register>
9771    <register>
9772     <name>MSTCTRL</name>
9773     <description>Master Control Register.</description>
9774     <addressOffset>0x30</addressOffset>
9775     <fields>
9776      <field>
9777       <name>START</name>
9778       <description>Setting this bit to 1 will start a master transfer.</description>
9779       <bitRange>[0:0]</bitRange>
9780      </field>
9781      <field>
9782       <name>RESTART</name>
9783       <description>Setting this bit to 1 will generate a repeated START.</description>
9784       <bitRange>[1:1]</bitRange>
9785      </field>
9786      <field>
9787       <name>STOP</name>
9788       <description>Setting this bit to 1 will generate a STOP condition.</description>
9789       <bitRange>[2:2]</bitRange>
9790      </field>
9791      <field>
9792       <name>EX_ADDR_EN</name>
9793       <description>Slave Extend Address Select.</description>
9794       <bitRange>[7:7]</bitRange>
9795       <enumeratedValues>
9796        <enumeratedValue>
9797         <name>7_bits_address</name>
9798         <description>7-bit address.</description>
9799         <value>0</value>
9800        </enumeratedValue>
9801        <enumeratedValue>
9802         <name>10_bits_address</name>
9803         <description>10-bit address.</description>
9804         <value>1</value>
9805        </enumeratedValue>
9806       </enumeratedValues>
9807      </field>
9808     </fields>
9809    </register>
9810    <register>
9811     <name>CLKLO</name>
9812     <description>Clock Low Register.</description>
9813     <addressOffset>0x34</addressOffset>
9814     <fields>
9815      <field>
9816       <name>LO</name>
9817       <description>Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.</description>
9818       <bitRange>[8:0]</bitRange>
9819      </field>
9820     </fields>
9821    </register>
9822    <register>
9823     <name>CLKHI</name>
9824     <description>Clock high Register.</description>
9825     <addressOffset>0x38</addressOffset>
9826     <fields>
9827      <field>
9828       <name>HI</name>
9829       <description>Clock High. In master mode, these bits define the SCL high period.</description>
9830       <bitRange>[8:0]</bitRange>
9831      </field>
9832     </fields>
9833    </register>
9834    <register>
9835     <name>HSCLK</name>
9836     <description>Clock high Register.</description>
9837     <addressOffset>0x3C</addressOffset>
9838     <fields>
9839      <field>
9840       <name>LO</name>
9841       <description>Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA.</description>
9842       <bitRange>[7:0]</bitRange>
9843      </field>
9844      <field>
9845       <name>HI</name>
9846       <description>Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA</description>
9847       <bitRange>[15:8]</bitRange>
9848      </field>
9849     </fields>
9850    </register>
9851    <register>
9852     <name>TIMEOUT</name>
9853     <description>Timeout Register</description>
9854     <addressOffset>0x40</addressOffset>
9855     <fields>
9856      <field>
9857       <name>SCL_TO_VAL</name>
9858       <description>Timeout</description>
9859       <bitRange>[15:0]</bitRange>
9860      </field>
9861     </fields>
9862    </register>
9863    <register>
9864     <name>DMA</name>
9865     <description>DMA Register.</description>
9866     <addressOffset>0x48</addressOffset>
9867     <fields>
9868      <field>
9869       <name>TX_EN</name>
9870       <description>TX channel enable.</description>
9871       <bitRange>[0:0]</bitRange>
9872       <enumeratedValues>
9873        <enumeratedValue>
9874         <name>dis</name>
9875         <description>Disable.</description>
9876         <value>0</value>
9877        </enumeratedValue>
9878        <enumeratedValue>
9879         <name>en</name>
9880         <description>Enable.</description>
9881         <value>1</value>
9882        </enumeratedValue>
9883       </enumeratedValues>
9884      </field>
9885      <field>
9886       <name>RX_EN</name>
9887       <description>RX channel enable.</description>
9888       <bitRange>[1:1]</bitRange>
9889       <enumeratedValues>
9890        <enumeratedValue>
9891         <name>dis</name>
9892         <description>Disable.</description>
9893         <value>0</value>
9894        </enumeratedValue>
9895        <enumeratedValue>
9896         <name>en</name>
9897         <description>Enable.</description>
9898         <value>1</value>
9899        </enumeratedValue>
9900       </enumeratedValues>
9901      </field>
9902     </fields>
9903    </register>
9904    <register>
9905     <dim>4</dim>
9906     <dimIncrement>4</dimIncrement>
9907     <name>SLAVE_MULTI[%s]</name>
9908     <description>Slave Address Register.</description>
9909     <alternateRegister>SLAVE0</alternateRegister>
9910     <addressOffset>0x4C</addressOffset>
9911     <size>32</size>
9912     <access>read-write</access>
9913     <fields>
9914      <field>
9915       <name>ADDR</name>
9916       <description>Slave Address.</description>
9917       <bitRange>[9:0]</bitRange>
9918      </field>
9919      <field>
9920       <name>DIS</name>
9921       <description>Slave Disable.</description>
9922       <bitRange>[10:10]</bitRange>
9923      </field>
9924      <field>
9925       <name>EXT_ADDR_EN</name>
9926       <description>Extended Address Select.</description>
9927       <bitRange>[15:15]</bitRange>
9928       <enumeratedValues>
9929        <enumeratedValue>
9930         <name>7_bits_address</name>
9931         <description>7-bit address.</description>
9932         <value>0</value>
9933        </enumeratedValue>
9934        <enumeratedValue>
9935         <name>10_bits_address</name>
9936         <description>10-bit address.</description>
9937         <value>1</value>
9938        </enumeratedValue>
9939       </enumeratedValues>
9940      </field>
9941     </fields>
9942    </register>
9943    <register>
9944     <name>SLAVE0</name>
9945     <description>Slave Address Register.</description>
9946     <addressOffset>0x4C</addressOffset>
9947    </register>
9948    <register>
9949     <name>SLAVE1</name>
9950     <description>Slave Address Register.</description>
9951     <addressOffset>0x50</addressOffset>
9952    </register>
9953    <register>
9954     <name>SLAVE2</name>
9955     <description>Slave Address Register.</description>
9956     <addressOffset>0x54</addressOffset>
9957    </register>
9958    <register>
9959     <name>SLAVE3</name>
9960     <description>Slave Address Register.</description>
9961     <addressOffset>0x58</addressOffset>
9962    </register>
9963   </registers>
9964  </peripheral>
9965<!--I2C0 Inter-Integrated Circuit.-->
9966  <peripheral derivedFrom="I2C0">
9967   <name>I2C1</name>
9968   <description>Inter-Integrated Circuit. 1</description>
9969   <baseAddress>0x4001E000</baseAddress>
9970   <interrupt>
9971    <name>I2C1</name>
9972    <description>I2C1 IRQ</description>
9973    <value>36</value>
9974   </interrupt>
9975  </peripheral>
9976<!--I2C1 Inter-Integrated Circuit. 1-->
9977  <peripheral derivedFrom="I2C0">
9978   <name>I2C2</name>
9979   <description>Inter-Integrated Circuit. 2</description>
9980   <baseAddress>0x4001F000</baseAddress>
9981   <interrupt>
9982    <name>I2C2</name>
9983    <description>I2C2 IRQ</description>
9984    <value>62</value>
9985   </interrupt>
9986  </peripheral>
9987<!--I2C2 Inter-Integrated Circuit. 2-->
9988  <peripheral>
9989   <name>I2S</name>
9990   <description>Inter-IC Sound Interface.</description>
9991   <groupName>I2S</groupName>
9992   <baseAddress>0x40060000</baseAddress>
9993   <size>32</size>
9994   <addressBlock>
9995    <offset>0x00</offset>
9996    <size>0x1000</size>
9997    <usage>registers</usage>
9998   </addressBlock>
9999   <interrupt>
10000    <name>I2S</name>
10001    <description>I2S IRQ</description>
10002    <value>99</value>
10003   </interrupt>
10004   <registers>
10005    <register>
10006     <name>CTRL0CH0</name>
10007     <description>Global mode channel.</description>
10008     <addressOffset>0x00</addressOffset>
10009     <fields>
10010      <field>
10011       <name>LSB_FIRST</name>
10012       <description>LSB Transmit Receive First.</description>
10013       <bitRange>[1:1]</bitRange>
10014       <access>read-write</access>
10015      </field>
10016      <field>
10017       <name>PDM_FILT</name>
10018       <description>PDM Filter.</description>
10019       <bitRange>[2:2]</bitRange>
10020       <access>read-write</access>
10021      </field>
10022      <field>
10023       <name>PDM_EN</name>
10024       <description>PDM Enable.</description>
10025       <bitRange>[3:3]</bitRange>
10026       <access>read-write</access>
10027      </field>
10028      <field>
10029       <name>USEDDR</name>
10030       <description>DDR.</description>
10031       <bitRange>[4:4]</bitRange>
10032       <access>read-write</access>
10033      </field>
10034      <field>
10035       <name>PDM_INV</name>
10036       <description>Invert PDM.</description>
10037       <bitRange>[5:5]</bitRange>
10038       <access>read-write</access>
10039      </field>
10040      <field>
10041       <name>CH_MODE</name>
10042       <description>SCK Select.</description>
10043       <bitRange>[7:6]</bitRange>
10044       <access>read-write</access>
10045      </field>
10046      <field>
10047       <name>WS_POL</name>
10048       <description>WS polarity select. </description>
10049       <bitRange>[8:8]</bitRange>
10050       <access>read-write</access>
10051      </field>
10052      <field>
10053       <name>MSB_LOC</name>
10054       <description>MSB location. </description>
10055       <bitRange>[9:9]</bitRange>
10056       <access>read-only</access>
10057      </field>
10058      <field>
10059       <name>ALIGN</name>
10060       <description>Align to MSB or LSB.</description>
10061       <bitRange>[10:10]</bitRange>
10062       <access>read-only</access>
10063      </field>
10064      <field>
10065       <name>EXT_SEL</name>
10066       <description>External SCK/WS selection.</description>
10067       <bitRange>[11:11]</bitRange>
10068       <access>read-write</access>
10069      </field>
10070      <field>
10071       <name>STEREO</name>
10072       <description>Stereo mode of I2S.</description>
10073       <bitRange>[13:12]</bitRange>
10074       <access>read-only</access>
10075      </field>
10076      <field>
10077       <name>WSIZE</name>
10078       <description>Data size when write to FIFO.</description>
10079       <bitRange>[15:14]</bitRange>
10080       <access>read-write</access>
10081      </field>
10082      <field>
10083       <name>TX_EN</name>
10084       <description>TX channel enable. </description>
10085       <bitRange>[16:16]</bitRange>
10086       <access>read-write</access>
10087      </field>
10088      <field>
10089       <name>RX_EN</name>
10090       <description>RX channel enable. </description>
10091       <bitRange>[17:17]</bitRange>
10092       <access>read-write</access>
10093      </field>
10094      <field>
10095       <name>FLUSH</name>
10096       <description>Flushes the TX/RX FIFO buffer. </description>
10097       <bitRange>[18:18]</bitRange>
10098       <access>read-write</access>
10099      </field>
10100      <field>
10101       <name>RST</name>
10102       <description>Write 1 to reset channel. </description>
10103       <bitRange>[19:19]</bitRange>
10104       <access>read-write</access>
10105      </field>
10106      <field>
10107       <name>FIFO_LSB</name>
10108       <description>Bit Field Control. </description>
10109       <bitRange>[20:20]</bitRange>
10110       <access>read-write</access>
10111      </field>
10112      <field>
10113       <name>RX_THD_VAL</name>
10114       <description>depth of receive FIFO for threshold interrupt generation. </description>
10115       <bitRange>[31:24]</bitRange>
10116       <access>read-write</access>
10117      </field>
10118     </fields>
10119    </register>
10120    <register>
10121     <name>CTRL1CH0</name>
10122     <description>Local channel Setup.</description>
10123     <addressOffset>0x10</addressOffset>
10124     <fields>
10125      <field>
10126       <name>BITS_WORD</name>
10127       <description>I2S word length.</description>
10128       <bitRange>[4:0]</bitRange>
10129       <access>read-write</access>
10130      </field>
10131      <field>
10132       <name>EN</name>
10133       <description>I2S clock enable.</description>
10134       <bitRange>[8:8]</bitRange>
10135       <access>read-write</access>
10136      </field>
10137      <field>
10138       <name>SMP_SIZE</name>
10139       <description>I2S sample size length.</description>
10140       <bitRange>[13:9]</bitRange>
10141       <access>read-write</access>
10142      </field>
10143      <field>
10144       <name>CLKSEL</name>
10145       <description>I2S clock select.</description>
10146       <bitRange>[14:14]</bitRange>
10147       <access>read-write</access>
10148      </field>
10149      <field>
10150       <name>ADJUST</name>
10151       <description>LSB/MSB Justify.</description>
10152       <bitRange>[15:15]</bitRange>
10153       <access>read-write</access>
10154      </field>
10155      <field>
10156       <name>CLKDIV</name>
10157       <description>I2S clock frequency divisor.</description>
10158       <bitRange>[31:16]</bitRange>
10159       <access>read-write</access>
10160      </field>
10161     </fields>
10162    </register>
10163    <register>
10164     <name>FILTCH0</name>
10165     <description>Filter.</description>
10166     <addressOffset>0x20</addressOffset>
10167    </register>
10168    <register>
10169     <name>DMACH0</name>
10170     <description>DMA Control.</description>
10171     <addressOffset>0x30</addressOffset>
10172     <fields>
10173      <field>
10174       <name>DMA_TX_THD_VAL</name>
10175       <description>TX FIFO Level DMA Trigger.</description>
10176       <bitRange>[6:0]</bitRange>
10177       <access>read-write</access>
10178      </field>
10179      <field>
10180       <name>DMA_TX_EN</name>
10181       <description>TX DMA channel enable.</description>
10182       <bitRange>[7:7]</bitRange>
10183       <access>read-write</access>
10184      </field>
10185      <field>
10186       <name>DMA_RX_THD_VAL</name>
10187       <description>RX FIFO Level DMA Trigger.</description>
10188       <bitRange>[14:8]</bitRange>
10189       <access>read-write</access>
10190      </field>
10191      <field>
10192       <name>DMA_RX_EN</name>
10193       <description>RX DMA channel enable.</description>
10194       <bitRange>[15:15]</bitRange>
10195       <access>read-write</access>
10196      </field>
10197      <field>
10198       <name>TX_LVL</name>
10199       <description>Number of data word in the TX FIFO.</description>
10200       <bitRange>[23:16]</bitRange>
10201       <access>read-write</access>
10202      </field>
10203      <field>
10204       <name>RX_LVL</name>
10205       <description>Number of data word in the RX FIFO.</description>
10206       <bitRange>[31:24]</bitRange>
10207       <access>read-write</access>
10208      </field>
10209     </fields>
10210    </register>
10211    <register>
10212     <name>FIFOCH0</name>
10213     <description>I2S Fifo.</description>
10214     <addressOffset>0x40</addressOffset>
10215     <fields>
10216      <field>
10217       <name>DATA</name>
10218       <description>Load/unload location for TX and RX FIFO buffers.</description>
10219       <bitRange>[31:0]</bitRange>
10220       <access>read-write</access>
10221      </field>
10222     </fields>
10223    </register>
10224    <register>
10225     <name>INTFL</name>
10226     <description>ISR Status.</description>
10227     <addressOffset>0x50</addressOffset>
10228     <fields>
10229      <field>
10230       <name>RX_OV_CH0</name>
10231       <description>Status for RX FIFO Overrun interrupt.</description>
10232       <bitRange>[0:0]</bitRange>
10233       <access>read-write</access>
10234      </field>
10235      <field>
10236       <name>RX_THD_CH0</name>
10237       <description>Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
10238       <bitRange>[1:1]</bitRange>
10239       <access>read-write</access>
10240      </field>
10241      <field>
10242       <name>TX_OB_CH0</name>
10243       <description>Status for interrupt when TX FIFO has only one byte remaining.</description>
10244       <bitRange>[2:2]</bitRange>
10245       <access>read-write</access>
10246      </field>
10247      <field>
10248       <name>TX_HE_CH0</name>
10249       <description>Status for interrupt when TX FIFO is half empty.</description>
10250       <bitRange>[3:3]</bitRange>
10251       <access>read-write</access>
10252      </field>
10253     </fields>
10254    </register>
10255    <register>
10256     <name>INTEN</name>
10257     <description>Interrupt Enable.</description>
10258     <addressOffset>0x54</addressOffset>
10259     <fields>
10260      <field>
10261       <name>RX_OV_CH0</name>
10262       <description>Enable for RX FIFO Overrun interrupt.</description>
10263       <bitRange>[0:0]</bitRange>
10264       <access>read-write</access>
10265      </field>
10266      <field>
10267       <name>RX_THD_CH0</name>
10268       <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
10269       <bitRange>[1:1]</bitRange>
10270       <access>read-write</access>
10271      </field>
10272      <field>
10273       <name>TX_OB_CH0</name>
10274       <description>Enable for interrupt when TX FIFO has only one byte remaining.</description>
10275       <bitRange>[2:2]</bitRange>
10276       <access>read-write</access>
10277      </field>
10278      <field>
10279       <name>TX_HE_CH0</name>
10280       <description>Enable for interrupt when TX FIFO is half empty.</description>
10281       <bitRange>[3:3]</bitRange>
10282       <access>read-write</access>
10283      </field>
10284     </fields>
10285    </register>
10286    <register>
10287     <name>EXTSETUP</name>
10288     <description>Ext Control.</description>
10289     <addressOffset>0x58</addressOffset>
10290     <fields>
10291      <field>
10292       <name>EXT_BITS_WORD</name>
10293       <description>Word Length for ch_mode.</description>
10294       <bitRange>[4:0]</bitRange>
10295       <access>read-write</access>
10296      </field>
10297     </fields>
10298    </register>
10299    <register>
10300     <name>WKEN</name>
10301     <description>Wakeup Enable.</description>
10302     <addressOffset>0x5C</addressOffset>
10303    </register>
10304    <register>
10305     <name>WKFL</name>
10306     <description>Wakeup Flags.</description>
10307     <addressOffset>0x60</addressOffset>
10308    </register>
10309   </registers>
10310  </peripheral>
10311<!--I2S Inter-IC Sound Interface.-->
10312  <peripheral>
10313   <name>ICC0</name>
10314   <description>Instruction Cache Controller Registers</description>
10315   <baseAddress>0x4002A000</baseAddress>
10316   <addressBlock>
10317    <offset>0x00</offset>
10318    <size>0x800</size>
10319    <usage>registers</usage>
10320   </addressBlock>
10321   <registers>
10322    <register>
10323     <name>INFO</name>
10324     <description>Cache ID Register.</description>
10325     <addressOffset>0x0000</addressOffset>
10326     <access>read-only</access>
10327     <fields>
10328      <field>
10329       <name>RELNUM</name>
10330       <description>Release Number. Identifies the RTL release version.</description>
10331       <bitOffset>0</bitOffset>
10332       <bitWidth>6</bitWidth>
10333      </field>
10334      <field>
10335       <name>PARTNUM</name>
10336       <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description>
10337       <bitOffset>6</bitOffset>
10338       <bitWidth>4</bitWidth>
10339      </field>
10340      <field>
10341       <name>ID</name>
10342       <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description>
10343       <bitOffset>10</bitOffset>
10344       <bitWidth>6</bitWidth>
10345      </field>
10346     </fields>
10347    </register>
10348    <register>
10349     <name>SZ</name>
10350     <description>Memory Configuration Register.</description>
10351     <addressOffset>0x0004</addressOffset>
10352     <access>read-only</access>
10353     <resetValue>0x00080008</resetValue>
10354     <fields>
10355      <field>
10356       <name>CCH</name>
10357       <description>Cache Size. Indicates total size in Kbytes of cache.</description>
10358       <bitOffset>0</bitOffset>
10359       <bitWidth>16</bitWidth>
10360      </field>
10361      <field>
10362       <name>MEM</name>
10363       <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description>
10364       <bitOffset>16</bitOffset>
10365       <bitWidth>16</bitWidth>
10366      </field>
10367     </fields>
10368    </register>
10369    <register>
10370     <name>CTRL</name>
10371     <description>Cache Control and Status Register.</description>
10372     <addressOffset>0x0100</addressOffset>
10373     <fields>
10374      <field>
10375       <name>EN</name>
10376       <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description>
10377       <bitOffset>0</bitOffset>
10378       <bitWidth>1</bitWidth>
10379       <enumeratedValues>
10380        <enumeratedValue>
10381         <name>dis</name>
10382         <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description>
10383         <value>0</value>
10384        </enumeratedValue>
10385        <enumeratedValue>
10386         <name>en</name>
10387         <description>Cache Enabled.</description>
10388         <value>1</value>
10389        </enumeratedValue>
10390       </enumeratedValues>
10391      </field>
10392      <field>
10393       <name>RDY</name>
10394       <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description>
10395       <bitOffset>16</bitOffset>
10396       <bitWidth>1</bitWidth>
10397       <access>read-only</access>
10398       <enumeratedValues>
10399        <enumeratedValue>
10400         <name>notReady</name>
10401         <description>Not Ready.</description>
10402         <value>0</value>
10403        </enumeratedValue>
10404        <enumeratedValue>
10405         <name>ready</name>
10406         <description>Ready.</description>
10407         <value>1</value>
10408        </enumeratedValue>
10409       </enumeratedValues>
10410      </field>
10411     </fields>
10412    </register>
10413    <register>
10414     <name>INVALIDATE</name>
10415     <description>Invalidate All Registers.</description>
10416     <addressOffset>0x0700</addressOffset>
10417     <access>read-write</access>
10418     <fields>
10419      <field>
10420       <name>INVALID</name>
10421       <description>Invalidate.</description>
10422       <bitOffset>0</bitOffset>
10423       <bitWidth>32</bitWidth>
10424      </field>
10425     </fields>
10426    </register>
10427   </registers>
10428  </peripheral>
10429<!--ICC0 Instruction Cache Controller Registers-->
10430  <peripheral derivedFrom="ICC0">
10431   <name>ICC1</name>
10432   <description>Instruction Cache Controller Registers 1</description>
10433   <baseAddress>0x4002AC00</baseAddress>
10434  </peripheral>
10435<!--ICC1 Instruction Cache Controller Registers 1-->
10436  <peripheral>
10437   <name>LPCMP</name>
10438   <description>Low Power Comparator</description>
10439   <baseAddress>0x40088000</baseAddress>
10440   <addressBlock>
10441    <offset>0x00</offset>
10442    <size>0x400</size>
10443    <usage>registers</usage>
10444   </addressBlock>
10445   <interrupt>
10446    <name>LPCMP</name>
10447    <description>Low Power Comparato</description>
10448    <value>103</value>
10449   </interrupt>
10450   <registers>
10451    <register>
10452     <dim>3</dim>
10453     <dimIncrement>4</dimIncrement>
10454     <name>CTRL[%s]</name>
10455     <description>Comparator Control Register.</description>
10456     <addressOffset>0x00</addressOffset>
10457     <fields>
10458      <field>
10459       <name>EN</name>
10460       <description>Comparator Enable.</description>
10461       <bitOffset>0</bitOffset>
10462       <bitWidth>1</bitWidth>
10463      </field>
10464      <field>
10465       <name>POL</name>
10466       <description>Polarity Select</description>
10467       <bitOffset>5</bitOffset>
10468       <bitWidth>1</bitWidth>
10469      </field>
10470      <field>
10471       <name>INT_EN</name>
10472       <description>IRQ Enable.</description>
10473       <bitOffset>6</bitOffset>
10474       <bitWidth>1</bitWidth>
10475      </field>
10476      <field>
10477       <name>OUT</name>
10478       <description>Raw Compartor Input.</description>
10479       <bitOffset>14</bitOffset>
10480       <bitWidth>1</bitWidth>
10481      </field>
10482      <field>
10483       <name>INT_FL</name>
10484       <description>IRQ Flag</description>
10485       <bitOffset>15</bitOffset>
10486       <bitWidth>1</bitWidth>
10487      </field>
10488     </fields>
10489    </register>
10490   </registers>
10491  </peripheral>
10492<!--LPCMP Low Power Comparator-->
10493  <peripheral>
10494   <name>LPGCR</name>
10495   <description>Low Power Global Control.</description>
10496   <baseAddress>0x40080000</baseAddress>
10497   <addressBlock>
10498    <offset>0x00</offset>
10499    <size>0x400</size>
10500    <usage>registers</usage>
10501   </addressBlock>
10502   <registers>
10503    <register>
10504     <name>RST</name>
10505     <description>Low Power Reset Register.</description>
10506     <addressOffset>0x08</addressOffset>
10507     <fields>
10508      <field>
10509       <name>GPIO2</name>
10510       <description>Low Power GPIO 2 Reset.</description>
10511       <bitOffset>0</bitOffset>
10512       <bitWidth>1</bitWidth>
10513       <enumeratedValues>
10514        <name>reset</name>
10515        <usage>read-write</usage>
10516        <enumeratedValue>
10517         <name>reset_done</name>
10518         <description>Reset complete.</description>
10519         <value>0</value>
10520        </enumeratedValue>
10521        <enumeratedValue>
10522         <name>busy</name>
10523         <description>Starts Reset or indicates reset in progress.</description>
10524         <value>1</value>
10525        </enumeratedValue>
10526       </enumeratedValues>
10527      </field>
10528      <field derivedFrom="GPIO2">
10529       <name>WDT1</name>
10530       <description>Low Power Watchdog Timer 1 Reset.</description>
10531       <bitOffset>1</bitOffset>
10532       <bitWidth>1</bitWidth>
10533      </field>
10534      <field derivedFrom="GPIO2">
10535       <name>TMR4</name>
10536       <description>Low Power Timer 4 Reset.</description>
10537       <bitOffset>2</bitOffset>
10538       <bitWidth>1</bitWidth>
10539      </field>
10540      <field derivedFrom="GPIO2">
10541       <name>TMR5</name>
10542       <description>Low Power Timer 5 Reset.</description>
10543       <bitOffset>3</bitOffset>
10544       <bitWidth>1</bitWidth>
10545      </field>
10546      <field derivedFrom="GPIO2">
10547       <name>UART3</name>
10548       <description>Low Power UART 3 Reset.</description>
10549       <bitOffset>4</bitOffset>
10550       <bitWidth>1</bitWidth>
10551      </field>
10552      <field derivedFrom="GPIO2">
10553       <name>LPCOMP</name>
10554       <description>Low Power Comparator Reset.</description>
10555       <bitOffset>6</bitOffset>
10556       <bitWidth>1</bitWidth>
10557      </field>
10558     </fields>
10559    </register>
10560    <register>
10561     <name>PCLKDIS</name>
10562     <description>Low Power Peripheral Clock Disable Register.</description>
10563     <addressOffset>0x0C</addressOffset>
10564     <fields>
10565      <field>
10566       <name>GPIO2</name>
10567       <description>Low Power GPIO 2 Clock Disable.</description>
10568       <bitOffset>0</bitOffset>
10569       <bitWidth>1</bitWidth>
10570       <enumeratedValues>
10571        <enumeratedValue>
10572         <name>en</name>
10573         <description>enable it.</description>
10574         <value>0</value>
10575        </enumeratedValue>
10576        <enumeratedValue>
10577         <name>dis</name>
10578         <description>disable it.</description>
10579         <value>1</value>
10580        </enumeratedValue>
10581       </enumeratedValues>
10582      </field>
10583      <field derivedFrom="GPIO2">
10584       <name>WDT1</name>
10585       <description>Low Power Watchdog 1 Clock Disable.</description>
10586       <bitOffset>1</bitOffset>
10587       <bitWidth>1</bitWidth>
10588      </field>
10589      <field derivedFrom="GPIO2">
10590       <name>TMR4</name>
10591       <description>Low Power Timer 4 Clock Disable.</description>
10592       <bitOffset>2</bitOffset>
10593       <bitWidth>1</bitWidth>
10594      </field>
10595      <field derivedFrom="GPIO2">
10596       <name>TMR5</name>
10597       <description>Low Power Timer 5 Clock Disable.</description>
10598       <bitOffset>3</bitOffset>
10599       <bitWidth>1</bitWidth>
10600      </field>
10601      <field derivedFrom="GPIO2">
10602       <name>UART3</name>
10603       <description>Low Power UART 3 Clock Disable.</description>
10604       <bitOffset>4</bitOffset>
10605       <bitWidth>1</bitWidth>
10606      </field>
10607      <field derivedFrom="GPIO2">
10608       <name>LPCOMP</name>
10609       <description>Low Power Comparator Clock Disable.</description>
10610       <bitOffset>6</bitOffset>
10611       <bitWidth>1</bitWidth>
10612      </field>
10613     </fields>
10614    </register>
10615   </registers>
10616  </peripheral>
10617<!--LPGCR Low Power Global Control.-->
10618  <peripheral>
10619   <name>MCR</name>
10620   <description>Misc Control.</description>
10621   <baseAddress>0x40006C00</baseAddress>
10622   <addressBlock>
10623    <offset>0x00</offset>
10624    <size>0x400</size>
10625    <usage>registers</usage>
10626   </addressBlock>
10627   <registers>
10628    <register>
10629     <name>ECCEN</name>
10630     <description>ECC Enable Register</description>
10631     <addressOffset>0x00</addressOffset>
10632     <fields>
10633      <field>
10634       <name>RAM0</name>
10635       <description>ECC System RAM0 Enable.</description>
10636       <bitOffset>0</bitOffset>
10637       <bitWidth>1</bitWidth>
10638       <enumeratedValues>
10639        <enumeratedValue>
10640         <name>dis</name>
10641         <description>disabled.</description>
10642         <value>0</value>
10643        </enumeratedValue>
10644        <enumeratedValue>
10645         <name>en</name>
10646         <description>enabled.</description>
10647         <value>1</value>
10648        </enumeratedValue>
10649       </enumeratedValues>
10650      </field>
10651     </fields>
10652    </register>
10653    <register>
10654     <name>IPO_MTRIM</name>
10655     <description>IPO Manual Register</description>
10656     <addressOffset>0x04</addressOffset>
10657     <fields>
10658      <field>
10659       <name>MTRIM</name>
10660       <description>Manual Trim Value.</description>
10661       <bitOffset>0</bitOffset>
10662       <bitWidth>8</bitWidth>
10663      </field>
10664      <field>
10665       <name>TRIM_RANGE</name>
10666       <description>Trim Range Select.</description>
10667       <bitOffset>8</bitOffset>
10668       <bitWidth>1</bitWidth>
10669      </field>
10670     </fields>
10671    </register>
10672    <register>
10673     <name>OUTEN</name>
10674     <description>Output Enable Register</description>
10675     <addressOffset>0x08</addressOffset>
10676     <fields>
10677      <field>
10678       <name>SQWOUT_EN</name>
10679       <description>Square Wave Output Enable.</description>
10680       <bitOffset>0</bitOffset>
10681       <bitWidth>1</bitWidth>
10682      </field>
10683      <field>
10684       <name>PDOWN_OUT_EN</name>
10685       <description>Power Down Output Enable.</description>
10686       <bitOffset>1</bitOffset>
10687       <bitWidth>1</bitWidth>
10688      </field>
10689     </fields>
10690    </register>
10691    <register>
10692     <name>CMP_CTRL</name>
10693     <description>Comparator Control Register.</description>
10694     <addressOffset>0x0C</addressOffset>
10695     <fields>
10696      <field>
10697       <name>EN</name>
10698       <description>Comparator Enable.</description>
10699       <bitOffset>0</bitOffset>
10700       <bitWidth>1</bitWidth>
10701      </field>
10702      <field>
10703       <name>POL</name>
10704       <description>Polarity Select</description>
10705       <bitOffset>5</bitOffset>
10706       <bitWidth>1</bitWidth>
10707      </field>
10708      <field>
10709       <name>INT_EN</name>
10710       <description>IRQ Enable.</description>
10711       <bitOffset>6</bitOffset>
10712       <bitWidth>1</bitWidth>
10713      </field>
10714      <field>
10715       <name>OUT</name>
10716       <description>Comparator Output State.</description>
10717       <bitOffset>14</bitOffset>
10718       <bitWidth>1</bitWidth>
10719      </field>
10720      <field>
10721       <name>INT_FL</name>
10722       <description>IRQ Flag</description>
10723       <bitOffset>15</bitOffset>
10724       <bitWidth>1</bitWidth>
10725      </field>
10726     </fields>
10727    </register>
10728    <register>
10729     <name>CTRL</name>
10730     <description>Miscellaneous Control Register.</description>
10731     <addressOffset>0x10</addressOffset>
10732     <fields>
10733      <field>
10734       <name>CMPHYST</name>
10735       <description>Comparator HYST.</description>
10736       <bitOffset>0</bitOffset>
10737       <bitWidth>2</bitWidth>
10738      </field>
10739      <field>
10740       <name>INRO_EN</name>
10741       <description>INRO Enable.</description>
10742       <bitOffset>2</bitOffset>
10743       <bitWidth>1</bitWidth>
10744      </field>
10745      <field>
10746       <name>ERTCO_EN</name>
10747       <description>ERTCO Enable.</description>
10748       <bitOffset>3</bitOffset>
10749       <bitWidth>1</bitWidth>
10750      </field>
10751      <field>
10752       <name>IBRO_EN</name>
10753       <description>IBRO Enable.</description>
10754       <bitOffset>4</bitOffset>
10755       <bitWidth>1</bitWidth>
10756      </field>
10757      <field>
10758       <name>SIMO_CLKSCL_EN</name>
10759       <description>SIMO Clock Scaling Enable.</description>
10760       <bitOffset>8</bitOffset>
10761       <bitWidth>1</bitWidth>
10762      </field>
10763      <field>
10764       <name>SIMO_RSTD</name>
10765       <description>SIMO System Reset Disable.</description>
10766       <bitOffset>9</bitOffset>
10767       <bitWidth>1</bitWidth>
10768      </field>
10769     </fields>
10770    </register>
10771    <register>
10772     <name>GPIO3_CTRL</name>
10773     <description>GPIO3 Pin Control Register.</description>
10774     <addressOffset>0x20</addressOffset>
10775     <fields>
10776      <field>
10777       <name>P30_DO</name>
10778       <description>GPIO3 Pin 0 Data Output.</description>
10779       <bitOffset>0</bitOffset>
10780       <bitWidth>1</bitWidth>
10781      </field>
10782      <field>
10783       <name>P30_OE</name>
10784       <description>GPIO3 Pin 0 Output Enable.</description>
10785       <bitOffset>1</bitOffset>
10786       <bitWidth>1</bitWidth>
10787      </field>
10788      <field>
10789       <name>P30_PE</name>
10790       <description>GPIO3 Pin 0 Pull-up Enable.</description>
10791       <bitOffset>2</bitOffset>
10792       <bitWidth>1</bitWidth>
10793      </field>
10794      <field>
10795       <name>P30_IN</name>
10796       <description>GPIO3 Pin 0 Input Status.</description>
10797       <bitOffset>3</bitOffset>
10798       <bitWidth>1</bitWidth>
10799      </field>
10800      <field>
10801       <name>P31_DO</name>
10802       <description>GPIO3 Pin 1 Data Output.</description>
10803       <bitOffset>4</bitOffset>
10804       <bitWidth>1</bitWidth>
10805      </field>
10806      <field>
10807       <name>P31_OE</name>
10808       <description>GPIO3 Pin 1 Output Enable.</description>
10809       <bitOffset>5</bitOffset>
10810       <bitWidth>1</bitWidth>
10811      </field>
10812      <field>
10813       <name>P31_PE</name>
10814       <description>GPIO3 Pin 1 Pull-up Enable.</description>
10815       <bitOffset>6</bitOffset>
10816       <bitWidth>1</bitWidth>
10817      </field>
10818      <field>
10819       <name>P31_IN</name>
10820       <description>GPIO3 Pin 1 Input Status.</description>
10821       <bitOffset>7</bitOffset>
10822       <bitWidth>1</bitWidth>
10823      </field>
10824     </fields>
10825    </register>
10826    <register>
10827     <name>CWD0</name>
10828     <description>Code Word Data0</description>
10829     <addressOffset>0x40</addressOffset>
10830     <fields>
10831      <field>
10832       <name>data</name>
10833       <description>Code word Data0 the register retains its value while vregi supply present</description>
10834       <bitOffset>0</bitOffset>
10835       <bitWidth>32</bitWidth>
10836      </field>
10837     </fields>
10838    </register>
10839    <register>
10840     <name>CWD1</name>
10841     <description>Code Word Data1</description>
10842     <addressOffset>0x44</addressOffset>
10843     <fields>
10844      <field>
10845       <name>data</name>
10846       <description>Code word Data0 the register retains its value while vregi supply present</description>
10847       <bitOffset>0</bitOffset>
10848       <bitWidth>32</bitWidth>
10849      </field>
10850     </fields>
10851    </register>
10852    <register>
10853     <name>ADCCFG0</name>
10854     <description>ADC Config 0</description>
10855     <addressOffset>0x50</addressOffset>
10856     <fields>
10857      <field>
10858       <name>LP_5K_DIS</name>
10859       <description>Disable 5K divider optionin low power modes</description>
10860       <bitOffset>0</bitOffset>
10861       <bitWidth>1</bitWidth>
10862      </field>
10863      <field>
10864       <name>LP_50K_DIS</name>
10865       <description>Disable 50K divider optionin low power modes</description>
10866       <bitOffset>1</bitOffset>
10867       <bitWidth>1</bitWidth>
10868      </field>
10869      <field>
10870       <name>EXT_REF</name>
10871       <description>External Reference Select Option</description>
10872       <bitOffset>2</bitOffset>
10873       <bitWidth>1</bitWidth>
10874      </field>
10875      <field>
10876       <name>REF_SEL</name>
10877       <description>Internal Reference Select Option</description>
10878       <bitOffset>3</bitOffset>
10879       <bitWidth>1</bitWidth>
10880      </field>
10881     </fields>
10882    </register>
10883    <register>
10884     <name>ADCCFG1</name>
10885     <description>ADC Config 1</description>
10886     <addressOffset>0x54</addressOffset>
10887     <fields>
10888      <field>
10889       <name>CHX_PU_DYN</name>
10890       <description>ADC PU dynamic control</description>
10891       <bitOffset>0</bitOffset>
10892       <bitWidth>13</bitWidth>
10893      </field>
10894     </fields>
10895    </register>
10896    <register>
10897     <name>ADCCFG2</name>
10898     <description>ADC Config 2</description>
10899     <addressOffset>0x58</addressOffset>
10900     <fields>
10901      <field>
10902       <name>CH0</name>
10903       <description>Divider option for ADC input channel 0</description>
10904       <bitOffset>0</bitOffset>
10905       <bitWidth>2</bitWidth>
10906       <enumeratedValues>
10907        <enumeratedValue>
10908         <name>div1</name>
10909         <description>div1</description>
10910         <value>0</value>
10911        </enumeratedValue>
10912        <enumeratedValue>
10913         <name>div2_5k</name>
10914         <description>5k ohom</description>
10915         <value>1</value>
10916        </enumeratedValue>
10917        <enumeratedValue>
10918         <name>div2_50k</name>
10919         <description>50k ohom</description>
10920         <value>2</value>
10921        </enumeratedValue>
10922       </enumeratedValues>
10923      </field>
10924      <field derivedFrom="CH0">
10925       <name>CH1</name>
10926       <description>Divider option for ADC input channel 1</description>
10927       <bitOffset>2</bitOffset>
10928       <bitWidth>2</bitWidth>
10929      </field>
10930      <field derivedFrom="CH0">
10931       <name>CH2</name>
10932       <description>Divider option for ADC input channel 2</description>
10933       <bitOffset>4</bitOffset>
10934       <bitWidth>2</bitWidth>
10935      </field>
10936      <field derivedFrom="CH0">
10937       <name>CH3</name>
10938       <description>Divider option for ADC input channel 3</description>
10939       <bitOffset>6</bitOffset>
10940       <bitWidth>2</bitWidth>
10941      </field>
10942      <field derivedFrom="CH0">
10943       <name>CH4</name>
10944       <description>Divider option for ADC input channel 4</description>
10945       <bitOffset>8</bitOffset>
10946       <bitWidth>2</bitWidth>
10947      </field>
10948      <field derivedFrom="CH0">
10949       <name>CH5</name>
10950       <description>Divider option for ADC input channel 5</description>
10951       <bitOffset>10</bitOffset>
10952       <bitWidth>2</bitWidth>
10953      </field>
10954      <field derivedFrom="CH0">
10955       <name>CH6</name>
10956       <description>Divider option for ADC input channel 6</description>
10957       <bitOffset>12</bitOffset>
10958       <bitWidth>2</bitWidth>
10959      </field>
10960      <field derivedFrom="CH0">
10961       <name>CH7</name>
10962       <description>Divider option for ADC input channel 7</description>
10963       <bitOffset>14</bitOffset>
10964       <bitWidth>2</bitWidth>
10965      </field>
10966     </fields>
10967    </register>
10968    <register>
10969     <name>LDOCTRL</name>
10970     <description>LDO Control</description>
10971     <addressOffset>0x60</addressOffset>
10972     <fields>
10973      <field>
10974       <name>0P9EN</name>
10975       <description>LDO 0.9V Enable</description>
10976       <bitOffset>0</bitOffset>
10977       <bitWidth>1</bitWidth>
10978      </field>
10979      <field>
10980       <name>2P5EN</name>
10981       <description>LDO 2.5V Enable</description>
10982       <bitOffset>1</bitOffset>
10983       <bitWidth>1</bitWidth>
10984      </field>
10985     </fields>
10986    </register>
10987   </registers>
10988  </peripheral>
10989<!--MCR Misc Control.-->
10990  <peripheral>
10991   <name>OWM</name>
10992   <description>1-Wire Master Interface.</description>
10993   <baseAddress>0x4003D000</baseAddress>
10994   <size>32</size>
10995   <access>read-write</access>
10996   <addressBlock>
10997    <offset>0</offset>
10998    <size>0x1000</size>
10999    <usage>registers</usage>
11000   </addressBlock>
11001   <interrupt>
11002    <name>OneWire</name>
11003    <value>67</value>
11004   </interrupt>
11005   <registers>
11006    <register>
11007     <name>CFG</name>
11008     <description>1-Wire Master Configuration.</description>
11009     <addressOffset>0x0000</addressOffset>
11010     <access>read-write</access>
11011     <fields>
11012      <field>
11013       <name>long_line_mode</name>
11014       <description>Long Line Mode.</description>
11015       <bitRange>[0:0]</bitRange>
11016       <access>read-write</access>
11017      </field>
11018      <field>
11019       <name>force_pres_det</name>
11020       <description>Force Line During Presence Detect.</description>
11021       <bitRange>[1:1]</bitRange>
11022       <access>read-write</access>
11023      </field>
11024      <field>
11025       <name>bit_bang_en</name>
11026       <description>Bit Bang Enable.</description>
11027       <bitRange>[2:2]</bitRange>
11028       <access>read-write</access>
11029      </field>
11030      <field>
11031       <name>ext_pullup_mode</name>
11032       <description>Provide an extra output control to control an external pullup.</description>
11033       <bitRange>[3:3]</bitRange>
11034       <access>read-write</access>
11035      </field>
11036      <field>
11037       <name>ext_pullup_enable</name>
11038       <description>Enable External Pullup.</description>
11039       <bitRange>[4:4]</bitRange>
11040       <access>read-write</access>
11041      </field>
11042      <field>
11043       <name>single_bit_mode</name>
11044       <description>Enable Single Bit TX/RX Mode.</description>
11045       <bitRange>[5:5]</bitRange>
11046       <access>read-write</access>
11047      </field>
11048      <field>
11049       <name>overdrive</name>
11050       <description>Enables overdrive speed for 1-Wire operations.</description>
11051       <bitRange>[6:6]</bitRange>
11052       <access>read-write</access>
11053      </field>
11054      <field>
11055       <name>int_pullup_enable</name>
11056       <description>Enable intenral pullup.</description>
11057       <bitRange>[7:7]</bitRange>
11058       <access>read-write</access>
11059      </field>
11060     </fields>
11061    </register>
11062    <register>
11063     <name>CLK_DIV_1US</name>
11064     <description>1-Wire Master Clock Divisor.</description>
11065     <addressOffset>0x0004</addressOffset>
11066     <access>read-write</access>
11067     <fields>
11068      <field>
11069       <name>divisor</name>
11070       <description>Clock Divisor for 1Mhz.</description>
11071       <bitRange>[7:0]</bitRange>
11072       <access>read-write</access>
11073      </field>
11074     </fields>
11075    </register>
11076    <register>
11077     <name>CTRL_STAT</name>
11078     <description>1-Wire Master Control/Status.</description>
11079     <addressOffset>0x0008</addressOffset>
11080     <access>read-write</access>
11081     <fields>
11082      <field>
11083       <name>start_ow_reset</name>
11084       <description>Start OW Reset.</description>
11085       <bitRange>[0:0]</bitRange>
11086       <access>read-write</access>
11087      </field>
11088      <field>
11089       <name>sra_mode</name>
11090       <description>SRA Mode.</description>
11091       <bitRange>[1:1]</bitRange>
11092       <access>read-write</access>
11093      </field>
11094      <field>
11095       <name>bit_bang_oe</name>
11096       <description>Bit Bang Output Enable.</description>
11097       <bitRange>[2:2]</bitRange>
11098       <access>read-write</access>
11099      </field>
11100      <field>
11101       <name>ow_input</name>
11102       <description>OW Input State.</description>
11103       <bitRange>[3:3]</bitRange>
11104       <access>read-only</access>
11105      </field>
11106      <field>
11107       <name>od_spec_mode</name>
11108       <description>Overdrive Spec Mode.</description>
11109       <bitRange>[4:4]</bitRange>
11110       <access>read-only</access>
11111      </field>
11112      <field>
11113       <name>presence_detect</name>
11114       <description>Presence Pulse Detected.</description>
11115       <bitRange>[7:7]</bitRange>
11116       <access>read-only</access>
11117      </field>
11118     </fields>
11119    </register>
11120    <register>
11121     <name>DATA</name>
11122     <description>1-Wire Master Data Buffer.</description>
11123     <addressOffset>0x000C</addressOffset>
11124     <access>read-write</access>
11125     <fields>
11126      <field>
11127       <name>tx_rx</name>
11128       <description>TX/RX Buffer.</description>
11129       <bitRange>[7:0]</bitRange>
11130       <access>read-write</access>
11131      </field>
11132     </fields>
11133    </register>
11134    <register>
11135     <name>INTFL</name>
11136     <description>1-Wire Master Interrupt Flags.</description>
11137     <addressOffset>0x0010</addressOffset>
11138     <access>read-write</access>
11139     <fields>
11140      <field>
11141       <name>ow_reset_done</name>
11142       <description>OW Reset Sequence Completed.</description>
11143       <bitRange>[0:0]</bitRange>
11144       <access>read-write</access>
11145      </field>
11146      <field>
11147       <name>tx_data_empty</name>
11148       <description>TX Data Empty Interrupt Flag.</description>
11149       <bitRange>[1:1]</bitRange>
11150       <access>read-write</access>
11151      </field>
11152      <field>
11153       <name>rx_data_ready</name>
11154       <description>RX Data Ready Interrupt Flag</description>
11155       <bitRange>[2:2]</bitRange>
11156       <access>read-write</access>
11157      </field>
11158      <field>
11159       <name>line_short</name>
11160       <description>OW Line Short Detected Interrupt Flag.</description>
11161       <bitRange>[3:3]</bitRange>
11162       <access>read-write</access>
11163      </field>
11164      <field>
11165       <name>line_low</name>
11166       <description>OW Line Low Detected Interrupt Flag.</description>
11167       <bitRange>[4:4]</bitRange>
11168       <access>read-write</access>
11169      </field>
11170     </fields>
11171    </register>
11172    <register>
11173     <name>INTEN</name>
11174     <description>1-Wire Master Interrupt Enables.</description>
11175     <addressOffset>0x0014</addressOffset>
11176     <access>read-write</access>
11177     <fields>
11178      <field>
11179       <name>ow_reset_done</name>
11180       <description>OW Reset Sequence Completed.</description>
11181       <bitRange>[0:0]</bitRange>
11182       <access>read-write</access>
11183       <modifiedWriteValues>oneToClear</modifiedWriteValues>
11184      </field>
11185      <field>
11186       <name>tx_data_empty</name>
11187       <description>Tx Data Empty Interrupt Enable.</description>
11188       <bitRange>[1:1]</bitRange>
11189       <access>read-write</access>
11190       <modifiedWriteValues>oneToClear</modifiedWriteValues>
11191      </field>
11192      <field>
11193       <name>rx_data_ready</name>
11194       <description>Rx Data Ready Interrupt Enable.</description>
11195       <bitRange>[2:2]</bitRange>
11196       <access>read-write</access>
11197       <modifiedWriteValues>oneToClear</modifiedWriteValues>
11198      </field>
11199      <field>
11200       <name>line_short</name>
11201       <description>OW Line Short Detected Interrupt Enable.</description>
11202       <bitRange>[3:3]</bitRange>
11203       <access>read-write</access>
11204       <modifiedWriteValues>oneToClear</modifiedWriteValues>
11205      </field>
11206      <field>
11207       <name>line_low</name>
11208       <description>OW Line Low Detected Interrupt Enable.</description>
11209       <bitRange>[4:4]</bitRange>
11210       <access>read-write</access>
11211       <modifiedWriteValues>oneToClear</modifiedWriteValues>
11212      </field>
11213     </fields>
11214    </register>
11215   </registers>
11216  </peripheral>
11217<!--OWM 1-Wire Master Interface.-->
11218  <peripheral>
11219   <name>PT</name>
11220   <description>Pulse Train</description>
11221   <groupName>Pulse_Train</groupName>
11222   <baseAddress>0x4003C020</baseAddress>
11223   <size>32</size>
11224   <access>read-write</access>
11225   <addressBlock>
11226    <offset>0</offset>
11227    <size>0x0010</size>
11228    <usage>registers</usage>
11229   </addressBlock>
11230   <registers>
11231    <register>
11232     <name>RATE_LENGTH</name>
11233     <description>Pulse Train Configuration</description>
11234     <addressOffset>0x0000</addressOffset>
11235     <access>read-write</access>
11236     <fields>
11237      <field>
11238       <name>rate_control</name>
11239       <description>Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.</description>
11240       <bitOffset>0</bitOffset>
11241       <bitWidth>27</bitWidth>
11242       <access>read-write</access>
11243      </field>
11244      <field>
11245       <name>mode</name>
11246       <description>Pulse Train Output Mode/Train Length</description>
11247       <bitOffset>27</bitOffset>
11248       <bitWidth>5</bitWidth>
11249       <access>read-write</access>
11250       <enumeratedValues>
11251        <enumeratedValue>
11252         <name>32_BIT</name>
11253         <description>Pulse train, 32 bit pattern.</description>
11254         <value>0</value>
11255        </enumeratedValue>
11256        <enumeratedValue>
11257         <name>SQUARE_WAVE</name>
11258         <description>Square wave mode.</description>
11259         <value>1</value>
11260        </enumeratedValue>
11261        <enumeratedValue>
11262         <name>2_BIT</name>
11263         <description>Pulse train, 2 bit pattern.</description>
11264         <value>2</value>
11265        </enumeratedValue>
11266        <enumeratedValue>
11267         <name>3_BIT</name>
11268         <description>Pulse train, 3 bit pattern.</description>
11269         <value>3</value>
11270        </enumeratedValue>
11271        <enumeratedValue>
11272         <name>4_BIT</name>
11273         <description>Pulse train, 4 bit pattern.</description>
11274         <value>4</value>
11275        </enumeratedValue>
11276        <enumeratedValue>
11277         <name>5_BIT</name>
11278         <description>Pulse train, 5 bit pattern.</description>
11279         <value>5</value>
11280        </enumeratedValue>
11281        <enumeratedValue>
11282         <name>6_BIT</name>
11283         <description>Pulse train, 6 bit pattern.</description>
11284         <value>6</value>
11285        </enumeratedValue>
11286        <enumeratedValue>
11287         <name>7_BIT</name>
11288         <description>Pulse train, 7 bit pattern.</description>
11289         <value>7</value>
11290        </enumeratedValue>
11291        <enumeratedValue>
11292         <name>8_BIT</name>
11293         <description>Pulse train, 8 bit pattern.</description>
11294         <value>8</value>
11295        </enumeratedValue>
11296        <enumeratedValue>
11297         <name>9_BIT</name>
11298         <description>Pulse train, 9 bit pattern.</description>
11299         <value>9</value>
11300        </enumeratedValue>
11301        <enumeratedValue>
11302         <name>10_BIT</name>
11303         <description>Pulse train, 10 bit pattern.</description>
11304         <value>10</value>
11305        </enumeratedValue>
11306        <enumeratedValue>
11307         <name>11_BIT</name>
11308         <description>Pulse train, 11 bit pattern.</description>
11309         <value>11</value>
11310        </enumeratedValue>
11311        <enumeratedValue>
11312         <name>12_BIT</name>
11313         <description>Pulse train, 12 bit pattern.</description>
11314         <value>12</value>
11315        </enumeratedValue>
11316        <enumeratedValue>
11317         <name>13_BIT</name>
11318         <description>Pulse train, 13 bit pattern.</description>
11319         <value>13</value>
11320        </enumeratedValue>
11321        <enumeratedValue>
11322         <name>14_BIT</name>
11323         <description>Pulse train, 14 bit pattern.</description>
11324         <value>14</value>
11325        </enumeratedValue>
11326        <enumeratedValue>
11327         <name>15_BIT</name>
11328         <description>Pulse train, 15 bit pattern.</description>
11329         <value>15</value>
11330        </enumeratedValue>
11331        <enumeratedValue>
11332         <name>16_BIT</name>
11333         <description>Pulse train, 16 bit pattern.</description>
11334         <value>16</value>
11335        </enumeratedValue>
11336        <enumeratedValue>
11337         <name>17_BIT</name>
11338         <description>Pulse train, 17 bit pattern.</description>
11339         <value>17</value>
11340        </enumeratedValue>
11341        <enumeratedValue>
11342         <name>18_BIT</name>
11343         <description>Pulse train, 18 bit pattern.</description>
11344         <value>18</value>
11345        </enumeratedValue>
11346        <enumeratedValue>
11347         <name>19_BIT</name>
11348         <description>Pulse train, 19 bit pattern.</description>
11349         <value>19</value>
11350        </enumeratedValue>
11351        <enumeratedValue>
11352         <name>20_BIT</name>
11353         <description>Pulse train, 20 bit pattern.</description>
11354         <value>20</value>
11355        </enumeratedValue>
11356        <enumeratedValue>
11357         <name>21_BIT</name>
11358         <description>Pulse train, 21 bit pattern.</description>
11359         <value>21</value>
11360        </enumeratedValue>
11361        <enumeratedValue>
11362         <name>22_BIT</name>
11363         <description>Pulse train, 22 bit pattern.</description>
11364         <value>22</value>
11365        </enumeratedValue>
11366        <enumeratedValue>
11367         <name>23_BIT</name>
11368         <description>Pulse train, 23 bit pattern.</description>
11369         <value>23</value>
11370        </enumeratedValue>
11371        <enumeratedValue>
11372         <name>24_BIT</name>
11373         <description>Pulse train, 24 bit pattern.</description>
11374         <value>24</value>
11375        </enumeratedValue>
11376        <enumeratedValue>
11377         <name>25_BIT</name>
11378         <description>Pulse train, 25 bit pattern.</description>
11379         <value>25</value>
11380        </enumeratedValue>
11381        <enumeratedValue>
11382         <name>26_BIT</name>
11383         <description>Pulse train, 26 bit pattern.</description>
11384         <value>26</value>
11385        </enumeratedValue>
11386        <enumeratedValue>
11387         <name>27_BIT</name>
11388         <description>Pulse train, 27 bit pattern.</description>
11389         <value>27</value>
11390        </enumeratedValue>
11391        <enumeratedValue>
11392         <name>28_BIT</name>
11393         <description>Pulse train, 28 bit pattern.</description>
11394         <value>28</value>
11395        </enumeratedValue>
11396        <enumeratedValue>
11397         <name>29_BIT</name>
11398         <description>Pulse train, 29 bit pattern.</description>
11399         <value>29</value>
11400        </enumeratedValue>
11401        <enumeratedValue>
11402         <name>30_BIT</name>
11403         <description>Pulse train, 30 bit pattern.</description>
11404         <value>30</value>
11405        </enumeratedValue>
11406        <enumeratedValue>
11407         <name>31_BIT</name>
11408         <description>Pulse train, 31 bit pattern.</description>
11409         <value>31</value>
11410        </enumeratedValue>
11411       </enumeratedValues>
11412      </field>
11413     </fields>
11414    </register>
11415    <register>
11416     <name>TRAIN</name>
11417     <description>Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.</description>
11418     <addressOffset>0x0004</addressOffset>
11419     <access>read-write</access>
11420    </register>
11421    <register>
11422     <name>LOOP</name>
11423     <description>Pulse Train Loop Count</description>
11424     <addressOffset>0x0008</addressOffset>
11425     <access>read-write</access>
11426     <fields>
11427      <field>
11428       <name>count</name>
11429       <description>Number of loops for this pulse train to repeat.</description>
11430       <bitOffset>0</bitOffset>
11431       <bitWidth>16</bitWidth>
11432       <access>read-write</access>
11433      </field>
11434      <field>
11435       <name>delay</name>
11436       <description>Delay between loops of the Pulse Train in PT Peripheral Clock cycles</description>
11437       <bitOffset>16</bitOffset>
11438       <bitWidth>12</bitWidth>
11439       <access>read-write</access>
11440      </field>
11441     </fields>
11442    </register>
11443    <register>
11444     <name>RESTART</name>
11445     <description> Pulse Train Auto-Restart Configuration.</description>
11446     <addressOffset>0x000C</addressOffset>
11447     <access>read-write</access>
11448     <fields>
11449      <field>
11450       <name>pt_x_select</name>
11451       <description>Auto-Restart PT X Select</description>
11452       <bitOffset>0</bitOffset>
11453       <bitWidth>5</bitWidth>
11454       <access>read-write</access>
11455      </field>
11456      <field>
11457       <name>on_pt_x_loop_exit</name>
11458       <description>Enable Auto-Restart on PT X Loop Exit</description>
11459       <bitOffset>7</bitOffset>
11460       <bitWidth>1</bitWidth>
11461       <access>read-write</access>
11462      </field>
11463      <field>
11464       <name>pt_y_select</name>
11465       <description>Auto-Restart PT Y Select</description>
11466       <bitOffset>8</bitOffset>
11467       <bitWidth>5</bitWidth>
11468       <access>read-write</access>
11469      </field>
11470      <field>
11471       <name>on_pt_y_loop_exit</name>
11472       <description>Enable Auto-Restart on PT Y Loop Exit</description>
11473       <bitOffset>15</bitOffset>
11474       <bitWidth>1</bitWidth>
11475       <access>read-write</access>
11476      </field>
11477     </fields>
11478    </register>
11479   </registers>
11480  </peripheral>
11481<!--PT Pulse Train-->
11482  <peripheral derivedFrom="PT">
11483   <name>PT1</name>
11484   <description>Pulse Train 1</description>
11485   <baseAddress>0x4003C030</baseAddress>
11486  </peripheral>
11487<!--PT1 Pulse Train 1-->
11488  <peripheral derivedFrom="PT">
11489   <name>PT2</name>
11490   <description>Pulse Train 2</description>
11491   <baseAddress>0x4003C040</baseAddress>
11492  </peripheral>
11493<!--PT2 Pulse Train 2-->
11494  <peripheral derivedFrom="PT">
11495   <name>PT3</name>
11496   <description>Pulse Train 3</description>
11497   <baseAddress>0x4003C050</baseAddress>
11498  </peripheral>
11499<!--PT3 Pulse Train 3-->
11500  <peripheral>
11501   <name>PTG</name>
11502   <description>Pulse Train Generation</description>
11503   <groupName>Pulse_Train</groupName>
11504   <baseAddress>0x4003C000</baseAddress>
11505   <size>32</size>
11506   <access>read-write</access>
11507   <addressBlock>
11508    <offset>0</offset>
11509    <size>0x0020</size>
11510    <usage>registers</usage>
11511   </addressBlock>
11512   <interrupt>
11513    <name>PT</name>
11514    <description>Pulse Train IRQ</description>
11515    <value>59</value>
11516   </interrupt>
11517   <registers>
11518    <register>
11519     <name>ENABLE</name>
11520     <description>Global Enable/Disable Controls for All Pulse Trains</description>
11521     <addressOffset>0x0000</addressOffset>
11522     <access>read-write</access>
11523     <fields>
11524      <field>
11525       <name>pt0</name>
11526       <description>Enable/Disable control for PT0</description>
11527       <bitOffset>0</bitOffset>
11528       <bitWidth>1</bitWidth>
11529       <access>read-write</access>
11530      </field>
11531      <field>
11532       <name>pt1</name>
11533       <description>Enable/Disable control for PT1</description>
11534       <bitOffset>1</bitOffset>
11535       <bitWidth>1</bitWidth>
11536       <access>read-write</access>
11537      </field>
11538      <field>
11539       <name>pt2</name>
11540       <description>Enable/Disable control for PT2</description>
11541       <bitOffset>2</bitOffset>
11542       <bitWidth>1</bitWidth>
11543       <access>read-write</access>
11544      </field>
11545      <field>
11546       <name>pt3</name>
11547       <description>Enable/Disable control for PT3</description>
11548       <bitOffset>3</bitOffset>
11549       <bitWidth>1</bitWidth>
11550       <access>read-write</access>
11551      </field>
11552     </fields>
11553    </register>
11554    <register>
11555     <name>RESYNC</name>
11556     <description>Global Resync (All Pulse Trains) Control</description>
11557     <addressOffset>0x0004</addressOffset>
11558     <access>read-write</access>
11559     <fields>
11560      <field>
11561       <name>pt0</name>
11562       <description>Resync control for PT0</description>
11563       <bitOffset>0</bitOffset>
11564       <bitWidth>1</bitWidth>
11565       <access>read-write</access>
11566      </field>
11567      <field>
11568       <name>pt1</name>
11569       <description>Resync control for PT1</description>
11570       <bitOffset>1</bitOffset>
11571       <bitWidth>1</bitWidth>
11572       <access>read-write</access>
11573      </field>
11574      <field>
11575       <name>pt2</name>
11576       <description>Resync control for PT2</description>
11577       <bitOffset>2</bitOffset>
11578       <bitWidth>1</bitWidth>
11579       <access>read-write</access>
11580      </field>
11581      <field>
11582       <name>pt3</name>
11583       <description>Resync control for PT3</description>
11584       <bitOffset>3</bitOffset>
11585       <bitWidth>1</bitWidth>
11586       <access>read-write</access>
11587      </field>
11588     </fields>
11589    </register>
11590    <register>
11591     <name>INTFL</name>
11592     <description>Pulse Train Interrupt Flags</description>
11593     <addressOffset>0x0008</addressOffset>
11594     <access>read-write</access>
11595     <fields>
11596      <field>
11597       <name>pt0</name>
11598       <description>Pulse Train 0 Stopped Interrupt Flag</description>
11599       <bitOffset>0</bitOffset>
11600       <bitWidth>1</bitWidth>
11601       <access>read-write</access>
11602      </field>
11603      <field>
11604       <name>pt1</name>
11605       <description>Pulse Train 1 Stopped Interrupt Flag</description>
11606       <bitOffset>1</bitOffset>
11607       <bitWidth>1</bitWidth>
11608       <access>read-write</access>
11609      </field>
11610      <field>
11611       <name>pt2</name>
11612       <description>Pulse Train 2 Stopped Interrupt Flag</description>
11613       <bitOffset>2</bitOffset>
11614       <bitWidth>1</bitWidth>
11615       <access>read-write</access>
11616      </field>
11617      <field>
11618       <name>pt3</name>
11619       <description>Pulse Train 3 Stopped Interrupt Flag</description>
11620       <bitOffset>3</bitOffset>
11621       <bitWidth>1</bitWidth>
11622       <access>read-write</access>
11623      </field>
11624     </fields>
11625    </register>
11626    <register>
11627     <name>INTEN</name>
11628     <description>Pulse Train Interrupt Enable/Disable</description>
11629     <addressOffset>0x000C</addressOffset>
11630     <access>read-write</access>
11631     <fields>
11632      <field>
11633       <name>pt0</name>
11634       <description>Pulse Train 0 Stopped Interrupt Enable/Disable</description>
11635       <bitOffset>0</bitOffset>
11636       <bitWidth>1</bitWidth>
11637       <access>read-write</access>
11638      </field>
11639      <field>
11640       <name>pt1</name>
11641       <description>Pulse Train 1 Stopped Interrupt Enable/Disable</description>
11642       <bitOffset>1</bitOffset>
11643       <bitWidth>1</bitWidth>
11644       <access>read-write</access>
11645      </field>
11646      <field>
11647       <name>pt2</name>
11648       <description>Pulse Train 2 Stopped Interrupt Enable/Disable</description>
11649       <bitOffset>2</bitOffset>
11650       <bitWidth>1</bitWidth>
11651       <access>read-write</access>
11652      </field>
11653      <field>
11654       <name>pt3</name>
11655       <description>Pulse Train 3 Stopped Interrupt Enable/Disable</description>
11656       <bitOffset>3</bitOffset>
11657       <bitWidth>1</bitWidth>
11658       <access>read-write</access>
11659      </field>
11660     </fields>
11661    </register>
11662    <register>
11663     <name>SAFE_EN</name>
11664     <description>Pulse Train Global Safe Enable.</description>
11665     <addressOffset>0x0010</addressOffset>
11666     <access>write-only</access>
11667     <fields>
11668      <field>
11669       <name>PT0</name>
11670       <bitOffset>0</bitOffset>
11671       <bitWidth>1</bitWidth>
11672       <access>write-only</access>
11673      </field>
11674      <field>
11675       <name>PT1</name>
11676       <bitOffset>1</bitOffset>
11677       <bitWidth>1</bitWidth>
11678       <access>write-only</access>
11679      </field>
11680      <field>
11681       <name>PT2</name>
11682       <bitOffset>2</bitOffset>
11683       <bitWidth>1</bitWidth>
11684       <access>write-only</access>
11685      </field>
11686      <field>
11687       <name>PT3</name>
11688       <bitOffset>3</bitOffset>
11689       <bitWidth>1</bitWidth>
11690       <access>write-only</access>
11691      </field>
11692     </fields>
11693    </register>
11694    <register>
11695     <name>SAFE_DIS</name>
11696     <description>Pulse Train Global Safe Disable.</description>
11697     <addressOffset>0x0014</addressOffset>
11698     <access>write-only</access>
11699     <fields>
11700      <field>
11701       <name>PT0</name>
11702       <bitOffset>0</bitOffset>
11703       <bitWidth>1</bitWidth>
11704       <access>write-only</access>
11705      </field>
11706      <field>
11707       <name>PT1</name>
11708       <bitOffset>1</bitOffset>
11709       <bitWidth>1</bitWidth>
11710       <access>write-only</access>
11711      </field>
11712      <field>
11713       <name>PT2</name>
11714       <bitOffset>2</bitOffset>
11715       <bitWidth>1</bitWidth>
11716       <access>write-only</access>
11717      </field>
11718      <field>
11719       <name>PT3</name>
11720       <bitOffset>3</bitOffset>
11721       <bitWidth>1</bitWidth>
11722       <access>write-only</access>
11723      </field>
11724     </fields>
11725    </register>
11726   </registers>
11727  </peripheral>
11728<!--PTG Pulse Train Generation-->
11729  <peripheral>
11730   <name>PWRSEQ</name>
11731   <description>Power Sequencer / Low Power Control Register.</description>
11732   <baseAddress>0x40006800</baseAddress>
11733   <addressBlock>
11734    <offset>0x00</offset>
11735    <size>0x400</size>
11736    <usage>registers</usage>
11737   </addressBlock>
11738   <registers>
11739    <register>
11740     <name>LPCN</name>
11741     <description>Low Power Control Register.</description>
11742     <addressOffset>0x00</addressOffset>
11743     <fields>
11744      <field>
11745       <name>RAMRET0</name>
11746       <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
11747       <bitOffset>0</bitOffset>
11748       <bitWidth>1</bitWidth>
11749       <enumeratedValues>
11750        <enumeratedValue>
11751         <name>dis</name>
11752         <description>Disable Ram Retention.</description>
11753         <value>0</value>
11754        </enumeratedValue>
11755        <enumeratedValue>
11756         <name>en</name>
11757         <description>Enable System RAM 0 retention.</description>
11758         <value>1</value>
11759        </enumeratedValue>
11760       </enumeratedValues>
11761      </field>
11762      <field>
11763       <name>RAMRET1</name>
11764       <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
11765       <bitOffset>1</bitOffset>
11766       <bitWidth>1</bitWidth>
11767       <enumeratedValues>
11768        <enumeratedValue>
11769         <name>dis</name>
11770         <description>Disable Ram Retention.</description>
11771         <value>0</value>
11772        </enumeratedValue>
11773        <enumeratedValue>
11774         <name>en</name>
11775         <description>Enable System RAM 1 retention.</description>
11776         <value>1</value>
11777        </enumeratedValue>
11778       </enumeratedValues>
11779      </field>
11780      <field>
11781       <name>RAMRET2</name>
11782       <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
11783       <bitOffset>2</bitOffset>
11784       <bitWidth>1</bitWidth>
11785       <enumeratedValues>
11786        <enumeratedValue>
11787         <name>dis</name>
11788         <description>Disable Ram Retention.</description>
11789         <value>0</value>
11790        </enumeratedValue>
11791        <enumeratedValue>
11792         <name>en</name>
11793         <description>Enable System RAM 2 retention.</description>
11794         <value>1</value>
11795        </enumeratedValue>
11796       </enumeratedValues>
11797      </field>
11798      <field>
11799       <name>RAMRET3</name>
11800       <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
11801       <bitOffset>3</bitOffset>
11802       <bitWidth>1</bitWidth>
11803       <enumeratedValues>
11804        <enumeratedValue>
11805         <name>dis</name>
11806         <description>Disable Ram Retention.</description>
11807         <value>0</value>
11808        </enumeratedValue>
11809        <enumeratedValue>
11810         <name>en</name>
11811         <description>Enable System RAM 3 retention.</description>
11812         <value>1</value>
11813        </enumeratedValue>
11814       </enumeratedValues>
11815      </field>
11816      <field>
11817       <name>RAMRET4</name>
11818       <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
11819       <bitOffset>4</bitOffset>
11820       <bitWidth>1</bitWidth>
11821       <enumeratedValues>
11822        <enumeratedValue>
11823         <name>dis</name>
11824         <description>Disable Ram Retention.</description>
11825         <value>0</value>
11826        </enumeratedValue>
11827        <enumeratedValue>
11828         <name>en</name>
11829         <description>Enable System RAM 3 retention.</description>
11830         <value>1</value>
11831        </enumeratedValue>
11832       </enumeratedValues>
11833      </field>
11834      <field>
11835       <name>RAMRET5</name>
11836       <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
11837       <bitOffset>5</bitOffset>
11838       <bitWidth>1</bitWidth>
11839       <enumeratedValues>
11840        <enumeratedValue>
11841         <name>dis</name>
11842         <description>Disable Ram Retention.</description>
11843         <value>0</value>
11844        </enumeratedValue>
11845        <enumeratedValue>
11846         <name>en</name>
11847         <description>Enable System RAM 3 retention.</description>
11848         <value>1</value>
11849        </enumeratedValue>
11850       </enumeratedValues>
11851      </field>
11852      <field>
11853       <name>RAMRET6</name>
11854       <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
11855       <bitOffset>6</bitOffset>
11856       <bitWidth>1</bitWidth>
11857       <enumeratedValues>
11858        <enumeratedValue>
11859         <name>dis</name>
11860         <description>Disable Ram Retention.</description>
11861         <value>0</value>
11862        </enumeratedValue>
11863        <enumeratedValue>
11864         <name>en</name>
11865         <description>Enable System RAM 3 retention.</description>
11866         <value>1</value>
11867        </enumeratedValue>
11868       </enumeratedValues>
11869      </field>
11870      <field>
11871       <name>RAMRET7</name>
11872       <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description>
11873       <bitOffset>7</bitOffset>
11874       <bitWidth>1</bitWidth>
11875       <enumeratedValues>
11876        <enumeratedValue>
11877         <name>dis</name>
11878         <description>Disable Ram Retention.</description>
11879         <value>0</value>
11880        </enumeratedValue>
11881        <enumeratedValue>
11882         <name>en</name>
11883         <description>Enable System RAM 3 retention.</description>
11884         <value>1</value>
11885        </enumeratedValue>
11886       </enumeratedValues>
11887      </field>
11888      <field>
11889       <name>ISOCLK_SELECT</name>
11890       <description>0 = PCLK 1= ISO CLK use for RISV in Low power mode  </description>
11891       <bitOffset>8</bitOffset>
11892       <bitWidth>1</bitWidth>
11893      </field>
11894      <field>
11895       <name>FAST_ENTRY_DIS</name>
11896       <description>Fast Low Power mode entry disable</description>
11897       <bitOffset>9</bitOffset>
11898       <bitWidth>1</bitWidth>
11899      </field>
11900      <field>
11901       <name>BGOFF</name>
11902       <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description>
11903       <bitOffset>11</bitOffset>
11904       <bitWidth>1</bitWidth>
11905       <enumeratedValues>
11906        <enumeratedValue>
11907         <name>on</name>
11908         <description>Bandgap is always ON.</description>
11909         <value>0</value>
11910        </enumeratedValue>
11911        <enumeratedValue>
11912         <name>off</name>
11913         <description>Bandgap is OFF in DeepSleep mode (default).</description>
11914         <value>1</value>
11915        </enumeratedValue>
11916       </enumeratedValues>
11917      </field>
11918      <field>
11919       <name>WKRST</name>
11920       <description>Reset wakeup status registers</description>
11921       <bitOffset>31</bitOffset>
11922       <bitWidth>1</bitWidth>
11923      </field>
11924     </fields>
11925    </register>
11926    <register>
11927     <name>LPWKST0</name>
11928     <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description>
11929     <addressOffset>0x04</addressOffset>
11930     <fields>
11931      <field>
11932       <name>WAKEST</name>
11933       <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description>
11934       <bitOffset>0</bitOffset>
11935       <bitWidth>1</bitWidth>
11936      </field>
11937     </fields>
11938    </register>
11939    <register>
11940     <name>LPWKEN0</name>
11941     <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description>
11942     <addressOffset>0x08</addressOffset>
11943     <fields>
11944      <field>
11945       <name>WAKEEN</name>
11946       <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description>
11947       <bitOffset>0</bitOffset>
11948       <bitWidth>31</bitWidth>
11949      </field>
11950     </fields>
11951    </register>
11952    <register>
11953     <name>LPWKST1</name>
11954     <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description>
11955     <addressOffset>0x0C</addressOffset>
11956     <fields>
11957      <field>
11958       <name>WAKEST</name>
11959       <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description>
11960       <bitOffset>0</bitOffset>
11961       <bitWidth>10</bitWidth>
11962      </field>
11963     </fields>
11964    </register>
11965    <register>
11966     <name>LPWKEN1</name>
11967     <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description>
11968     <addressOffset>0x10</addressOffset>
11969     <fields>
11970      <field>
11971       <name>WAKEEN</name>
11972       <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description>
11973       <bitOffset>0</bitOffset>
11974       <bitWidth>10</bitWidth>
11975      </field>
11976     </fields>
11977    </register>
11978    <register>
11979     <name>LPWKST2</name>
11980     <description>Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.</description>
11981     <addressOffset>0x14</addressOffset>
11982     <fields>
11983      <field>
11984       <name>WAKEST</name>
11985       <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description>
11986       <bitOffset>0</bitOffset>
11987       <bitWidth>8</bitWidth>
11988      </field>
11989     </fields>
11990    </register>
11991    <register>
11992     <name>LPWKEN2</name>
11993     <description>Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.</description>
11994     <addressOffset>0x18</addressOffset>
11995     <fields>
11996      <field>
11997       <name>WAKEEN</name>
11998       <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description>
11999       <bitOffset>0</bitOffset>
12000       <bitWidth>8</bitWidth>
12001      </field>
12002     </fields>
12003    </register>
12004    <register>
12005     <name>LPWKST3</name>
12006     <description>Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.</description>
12007     <addressOffset>0x1C</addressOffset>
12008     <fields>
12009      <field>
12010       <name>WAKEST</name>
12011       <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description>
12012       <bitOffset>0</bitOffset>
12013       <bitWidth>2</bitWidth>
12014      </field>
12015     </fields>
12016    </register>
12017    <register>
12018     <name>LPWKEN3</name>
12019     <description>Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.</description>
12020     <addressOffset>0x20</addressOffset>
12021     <fields>
12022      <field>
12023       <name>WAKEEN</name>
12024       <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description>
12025       <bitOffset>0</bitOffset>
12026       <bitWidth>2</bitWidth>
12027      </field>
12028     </fields>
12029    </register>
12030    <register>
12031     <name>LPPWST</name>
12032     <description>Low Power Peripheral Wakeup Status Register.</description>
12033     <addressOffset>0x30</addressOffset>
12034     <fields>
12035      <field>
12036       <name>AINCOMP0</name>
12037       <description>Analog Input Comparator Wakeup Flag.</description>
12038       <bitOffset>4</bitOffset>
12039       <bitWidth>1</bitWidth>
12040      </field>
12041      <field>
12042       <name>BACKUP</name>
12043       <description>Backup Mode Wakeup Flag.</description>
12044       <bitOffset>16</bitOffset>
12045       <bitWidth>1</bitWidth>
12046      </field>
12047      <field>
12048       <name>RESET</name>
12049       <description>Reset Detected Wakeup Flag.</description>
12050       <bitOffset>17</bitOffset>
12051       <bitWidth>1</bitWidth>
12052      </field>
12053     </fields>
12054    </register>
12055    <register>
12056     <name>LPPWEN</name>
12057     <description>Low Power Peripheral Wakeup Enable Register.</description>
12058     <addressOffset>0x34</addressOffset>
12059     <fields>
12060      <field>
12061       <name>USBLS</name>
12062       <description> USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate
12063signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set.</description>
12064       <bitOffset>0</bitOffset>
12065       <bitWidth>2</bitWidth>
12066      </field>
12067      <field>
12068       <name>USBVBUS</name>
12069       <description> USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status.</description>
12070       <bitOffset>2</bitOffset>
12071       <bitWidth>1</bitWidth>
12072      </field>
12073      <field>
12074       <name>AINCOMP0</name>
12075       <description> AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0.</description>
12076       <bitOffset>4</bitOffset>
12077       <bitWidth>1</bitWidth>
12078      </field>
12079      <field>
12080       <name>WDT0</name>
12081       <description> WDT0 Wakeup Enable. This bit allows wakeup from the WDT0.</description>
12082       <bitOffset>8</bitOffset>
12083       <bitWidth>1</bitWidth>
12084      </field>
12085      <field>
12086       <name>WDT1</name>
12087       <description> WDT1 Wakeup Enable. This bit allows wakeup from the WDT1.</description>
12088       <bitOffset>9</bitOffset>
12089       <bitWidth>1</bitWidth>
12090      </field>
12091      <field>
12092       <name>CPU1</name>
12093       <description> CPU1 Wakeup Enable. This bit allows wakeup from the CPU1.</description>
12094       <bitOffset>10</bitOffset>
12095       <bitWidth>1</bitWidth>
12096      </field>
12097      <field>
12098       <name>TMR0</name>
12099       <description> TMR0 Wakeup Enable. This bit allows wakeup from the TMR0.</description>
12100       <bitOffset>11</bitOffset>
12101       <bitWidth>1</bitWidth>
12102      </field>
12103      <field>
12104       <name>TMR1</name>
12105       <description> TMR1 Wakeup Enable. This bit allows wakeup from the TMR1.</description>
12106       <bitOffset>12</bitOffset>
12107       <bitWidth>1</bitWidth>
12108      </field>
12109      <field>
12110       <name>TMR2</name>
12111       <description> TMR2 Wakeup Enable. This bit allows wakeup from the TMR2.</description>
12112       <bitOffset>13</bitOffset>
12113       <bitWidth>1</bitWidth>
12114      </field>
12115      <field>
12116       <name>TMR3</name>
12117       <description> TMR3 Wakeup Enable. This bit allows wakeup from the TMR3.</description>
12118       <bitOffset>14</bitOffset>
12119       <bitWidth>1</bitWidth>
12120      </field>
12121      <field>
12122       <name>TMR4</name>
12123       <description> TMR4 Wakeup Enable. This bit allows wakeup from the TMR4.</description>
12124       <bitOffset>15</bitOffset>
12125       <bitWidth>1</bitWidth>
12126      </field>
12127      <field>
12128       <name>TMR5</name>
12129       <description> TMR5 Wakeup Enable. This bit allows wakeup from the TMR5.</description>
12130       <bitOffset>16</bitOffset>
12131       <bitWidth>1</bitWidth>
12132      </field>
12133      <field>
12134       <name>UART0</name>
12135       <description> UART0 Wakeup Enable. This bit allows wakeup from the UART0.</description>
12136       <bitOffset>17</bitOffset>
12137       <bitWidth>1</bitWidth>
12138      </field>
12139      <field>
12140       <name>UART1</name>
12141       <description> UART1 Wakeup Enable. This bit allows wakeup from the UART1.</description>
12142       <bitOffset>18</bitOffset>
12143       <bitWidth>1</bitWidth>
12144      </field>
12145      <field>
12146       <name>UART2</name>
12147       <description> UART2 Wakeup Enable. This bit allows wakeup from the UART2.</description>
12148       <bitOffset>19</bitOffset>
12149       <bitWidth>1</bitWidth>
12150      </field>
12151      <field>
12152       <name>UART3</name>
12153       <description> UART3 Wakeup Enable. This bit allows wakeup from the UART3.</description>
12154       <bitOffset>20</bitOffset>
12155       <bitWidth>1</bitWidth>
12156      </field>
12157      <field>
12158       <name>I2C0</name>
12159       <description> I2C0 Wakeup Enable. This bit allows wakeup from the I2C0.</description>
12160       <bitOffset>21</bitOffset>
12161       <bitWidth>1</bitWidth>
12162      </field>
12163      <field>
12164       <name>I2C1</name>
12165       <description> I2C1 Wakeup Enable. This bit allows wakeup from the I2C1.</description>
12166       <bitOffset>22</bitOffset>
12167       <bitWidth>1</bitWidth>
12168      </field>
12169      <field>
12170       <name>I2C2</name>
12171       <description> I2C2 Wakeup Enable. This bit allows wakeup from the I2C2.</description>
12172       <bitOffset>23</bitOffset>
12173       <bitWidth>1</bitWidth>
12174      </field>
12175      <field>
12176       <name>I2S</name>
12177       <description> I2S Wakeup Enable. This bit allows wakeup from the I2S.</description>
12178       <bitOffset>24</bitOffset>
12179       <bitWidth>1</bitWidth>
12180      </field>
12181      <field>
12182       <name>SPI1</name>
12183       <description> SPI1 Wakeup Enable. This bit allows wakeup from the SPI0.</description>
12184       <bitOffset>25</bitOffset>
12185       <bitWidth>1</bitWidth>
12186      </field>
12187      <field>
12188       <name>LPCMP</name>
12189       <description> LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP.</description>
12190       <bitOffset>26</bitOffset>
12191       <bitWidth>1</bitWidth>
12192      </field>
12193     </fields>
12194    </register>
12195    <register>
12196     <name>GP0</name>
12197     <description>General Purpose Register 0</description>
12198     <addressOffset>0x48</addressOffset>
12199    </register>
12200    <register>
12201     <name>GP1</name>
12202     <description>General Purpose Register 1</description>
12203     <addressOffset>0x4C</addressOffset>
12204    </register>
12205   </registers>
12206  </peripheral>
12207<!--PWRSEQ Power Sequencer / Low Power Control Register.-->
12208  <peripheral>
12209   <name>RTC</name>
12210   <description>Real Time Clock and Alarm.</description>
12211   <baseAddress>0x40006000</baseAddress>
12212   <addressBlock>
12213    <offset>0x00</offset>
12214    <size>0x400</size>
12215    <usage>registers</usage>
12216   </addressBlock>
12217   <interrupt>
12218    <name>RTC</name>
12219    <description>RTC interrupt.</description>
12220    <value>3</value>
12221   </interrupt>
12222   <registers>
12223    <register>
12224     <name>SEC</name>
12225     <description>RTC Second Counter. This register contains the 32-bit second counter.</description>
12226     <addressOffset>0x00</addressOffset>
12227     <resetMask>0x00000000</resetMask>
12228     <fields>
12229      <field>
12230       <name>SEC</name>
12231       <description>Seconds Counter.</description>
12232       <bitOffset>0</bitOffset>
12233       <bitWidth>32</bitWidth>
12234      </field>
12235     </fields>
12236    </register>
12237    <register>
12238     <name>SSEC</name>
12239     <description>RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.</description>
12240     <addressOffset>0x04</addressOffset>
12241     <resetMask>0x00000000</resetMask>
12242     <fields>
12243      <field>
12244       <name>SSEC</name>
12245       <description>Sub-Seconds Counter (12-bit).</description>
12246       <bitOffset>0</bitOffset>
12247       <bitWidth>12</bitWidth>
12248      </field>
12249     </fields>
12250    </register>
12251    <register>
12252     <name>TODA</name>
12253     <description>Time-of-day Alarm.</description>
12254     <addressOffset>0x08</addressOffset>
12255     <resetMask>0x00000000</resetMask>
12256     <fields>
12257      <field>
12258       <name>TOD_ALARM</name>
12259       <description>Time-of-day Alarm.</description>
12260       <bitOffset>0</bitOffset>
12261       <bitWidth>20</bitWidth>
12262      </field>
12263     </fields>
12264    </register>
12265    <register>
12266     <name>SSECA</name>
12267     <description>RTC sub-second alarm.  This register contains the reload value for the sub-second alarm.</description>
12268     <addressOffset>0x0C</addressOffset>
12269     <resetMask>0x00000000</resetMask>
12270     <fields>
12271      <field>
12272       <name>SSEC_ALARM</name>
12273       <description>This register contains the reload value for the sub-second alarm.</description>
12274       <bitOffset>0</bitOffset>
12275       <bitWidth>32</bitWidth>
12276      </field>
12277     </fields>
12278    </register>
12279    <register>
12280     <name>CTRL</name>
12281     <description>RTC Control Register.</description>
12282     <addressOffset>0x10</addressOffset>
12283     <resetValue>0x00000008</resetValue>
12284     <resetMask>0xFFFFFF38</resetMask>
12285     <fields>
12286      <field>
12287       <name>EN</name>
12288       <description>Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description>
12289       <bitOffset>0</bitOffset>
12290       <bitWidth>1</bitWidth>
12291       <enumeratedValues>
12292        <enumeratedValue>
12293         <name>dis</name>
12294         <description>Disable.</description>
12295         <value>0</value>
12296        </enumeratedValue>
12297        <enumeratedValue>
12298         <name>en</name>
12299         <description>Enable.</description>
12300         <value>1</value>
12301        </enumeratedValue>
12302       </enumeratedValues>
12303      </field>
12304      <field>
12305       <name>TOD_ALARM_IE</name>
12306       <description>Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description>
12307       <bitOffset>1</bitOffset>
12308       <bitWidth>1</bitWidth>
12309       <enumeratedValues>
12310        <enumeratedValue>
12311         <name>dis</name>
12312         <description>Disable.</description>
12313         <value>0</value>
12314        </enumeratedValue>
12315        <enumeratedValue>
12316         <name>en</name>
12317         <description>Enable.</description>
12318         <value>1</value>
12319        </enumeratedValue>
12320       </enumeratedValues>
12321      </field>
12322      <field>
12323       <name>SSEC_ALARM_IE</name>
12324       <description>Alarm Sub-second Interrupt Enable.  Change to this bit is effective only after BUSY is cleared from 1 to 0.</description>
12325       <bitOffset>2</bitOffset>
12326       <bitWidth>1</bitWidth>
12327       <enumeratedValues>
12328        <enumeratedValue>
12329         <name>dis</name>
12330         <description>Disable.</description>
12331         <value>0</value>
12332        </enumeratedValue>
12333        <enumeratedValue>
12334         <name>en</name>
12335         <description>Enable.</description>
12336         <value>1</value>
12337        </enumeratedValue>
12338       </enumeratedValues>
12339      </field>
12340      <field>
12341       <name>BUSY</name>
12342       <description>RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place.  This bit is automatically cleared by hardware.</description>
12343       <bitOffset>3</bitOffset>
12344       <bitWidth>1</bitWidth>
12345       <access>read-only</access>
12346       <enumeratedValues>
12347        <enumeratedValue>
12348         <name>idle</name>
12349         <description>Idle.</description>
12350         <value>0</value>
12351        </enumeratedValue>
12352        <enumeratedValue>
12353         <name>busy</name>
12354         <description>Busy.</description>
12355         <value>1</value>
12356        </enumeratedValue>
12357       </enumeratedValues>
12358      </field>
12359      <field>
12360       <name>RDY</name>
12361       <description>RTC Ready. This bit is set to 1 by hardware when the RTC count registers update.  It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.</description>
12362       <bitOffset>4</bitOffset>
12363       <bitWidth>1</bitWidth>
12364       <enumeratedValues>
12365        <enumeratedValue>
12366         <name>busy</name>
12367         <description>Register has not updated.</description>
12368         <value>0</value>
12369        </enumeratedValue>
12370        <enumeratedValue>
12371         <name>ready</name>
12372         <description>Ready.</description>
12373         <value>1</value>
12374        </enumeratedValue>
12375       </enumeratedValues>
12376      </field>
12377      <field>
12378       <name>RDY_IE</name>
12379       <description>RTC Ready Interrupt Enable.</description>
12380       <bitOffset>5</bitOffset>
12381       <bitWidth>1</bitWidth>
12382       <enumeratedValues>
12383        <enumeratedValue>
12384         <name>dis</name>
12385         <description>Disable.</description>
12386         <value>0</value>
12387        </enumeratedValue>
12388        <enumeratedValue>
12389         <name>en</name>
12390         <description>Enable.</description>
12391         <value>1</value>
12392        </enumeratedValue>
12393       </enumeratedValues>
12394      </field>
12395      <field>
12396       <name>TOD_ALARM</name>
12397       <description>Time-of-Day Alarm Interrupt Flag.  This alarm is qualified as wake-up source to the processor.</description>
12398       <bitOffset>6</bitOffset>
12399       <bitWidth>1</bitWidth>
12400       <access>read-only</access>
12401       <enumeratedValues>
12402        <enumeratedValue>
12403         <name>inactive</name>
12404         <description>Not active</description>
12405         <value>0</value>
12406        </enumeratedValue>
12407        <enumeratedValue>
12408         <name>Pending</name>
12409         <description>Active</description>
12410         <value>1</value>
12411        </enumeratedValue>
12412       </enumeratedValues>
12413      </field>
12414      <field>
12415       <name>SSEC_ALARM</name>
12416       <description>Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description>
12417       <bitOffset>7</bitOffset>
12418       <bitWidth>1</bitWidth>
12419       <access>read-only</access>
12420       <enumeratedValues>
12421        <enumeratedValue>
12422         <name>inactive</name>
12423         <description>Not active</description>
12424         <value>0</value>
12425        </enumeratedValue>
12426        <enumeratedValue>
12427         <name>Pending</name>
12428         <description>Active</description>
12429         <value>1</value>
12430        </enumeratedValue>
12431       </enumeratedValues>
12432      </field>
12433      <field>
12434       <name>SQW_EN</name>
12435       <description>Square Wave Output Enable.</description>
12436       <bitOffset>8</bitOffset>
12437       <bitWidth>1</bitWidth>
12438       <enumeratedValues>
12439        <enumeratedValue>
12440         <name>inactive</name>
12441         <description>Not active</description>
12442         <value>0</value>
12443        </enumeratedValue>
12444        <enumeratedValue>
12445         <name>Pending</name>
12446         <description>Active</description>
12447         <value>1</value>
12448        </enumeratedValue>
12449       </enumeratedValues>
12450      </field>
12451      <field>
12452       <name>SQW_SEL</name>
12453       <description>Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.</description>
12454       <bitOffset>9</bitOffset>
12455       <bitWidth>2</bitWidth>
12456       <enumeratedValues>
12457        <enumeratedValue>
12458         <name>freq1Hz</name>
12459         <description>1 Hz (Compensated).</description>
12460         <value>0</value>
12461        </enumeratedValue>
12462        <enumeratedValue>
12463         <name>freq512Hz</name>
12464         <description>512 Hz (Compensated).</description>
12465         <value>1</value>
12466        </enumeratedValue>
12467        <enumeratedValue>
12468         <name>freq4KHz</name>
12469         <description>4 KHz.</description>
12470         <value>2</value>
12471        </enumeratedValue>
12472        <enumeratedValue>
12473         <name>clkDiv8</name>
12474         <description>RTC Input Clock / 8.</description>
12475         <value>3</value>
12476        </enumeratedValue>
12477       </enumeratedValues>
12478      </field>
12479      <field>
12480       <name>RD_EN</name>
12481       <description>Asynchronous Counter Read Enable.</description>
12482       <bitOffset>14</bitOffset>
12483       <bitWidth>1</bitWidth>
12484      </field>
12485      <field>
12486       <name>WR_EN</name>
12487       <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.</description>
12488       <bitOffset>15</bitOffset>
12489       <bitWidth>1</bitWidth>
12490       <enumeratedValues>
12491        <enumeratedValue>
12492         <name>inactive</name>
12493         <description>Not active</description>
12494         <value>0</value>
12495        </enumeratedValue>
12496        <enumeratedValue>
12497         <name>Pending</name>
12498         <description>Active</description>
12499         <value>1</value>
12500        </enumeratedValue>
12501       </enumeratedValues>
12502      </field>
12503     </fields>
12504    </register>
12505    <register>
12506     <name>TRIM</name>
12507     <description>RTC Trim Register.</description>
12508     <addressOffset>0x14</addressOffset>
12509     <resetMask>0x00000000</resetMask>
12510     <fields>
12511      <field>
12512       <name>TRIM</name>
12513       <description>RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.</description>
12514       <bitOffset>0</bitOffset>
12515       <bitWidth>8</bitWidth>
12516      </field>
12517      <field>
12518       <name>VRTC_TMR</name>
12519       <description>VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.</description>
12520       <bitOffset>8</bitOffset>
12521       <bitWidth>24</bitWidth>
12522      </field>
12523     </fields>
12524    </register>
12525    <register>
12526     <name>OSCCTRL</name>
12527     <description>RTC Oscillator Control Register.</description>
12528     <addressOffset>0x18</addressOffset>
12529     <resetMask>0x00000000</resetMask>
12530     <fields>
12531      <field>
12532       <name>FILTER_EN</name>
12533       <description>Enables analog deglitch filter.</description>
12534       <bitOffset>0</bitOffset>
12535       <bitWidth>1</bitWidth>
12536      </field>
12537      <field>
12538       <name>IBIAS_SEL</name>
12539       <description>If IBIAS_EN is 1, selects 4x,2x mode.</description>
12540       <bitOffset>1</bitOffset>
12541       <bitWidth>1</bitWidth>
12542      </field>
12543      <field>
12544       <name>HYST_EN</name>
12545       <description>Enables high current hysteresis buffer.</description>
12546       <bitOffset>2</bitOffset>
12547       <bitWidth>1</bitWidth>
12548      </field>
12549      <field>
12550       <name>IBIAS_EN</name>
12551       <description>Enables higher 4x,2x current modes.</description>
12552       <bitOffset>3</bitOffset>
12553       <bitWidth>1</bitWidth>
12554      </field>
12555      <field>
12556       <name>BYPASS</name>
12557       <description>RTC Crystal Bypass</description>
12558       <bitOffset>4</bitOffset>
12559       <bitWidth>1</bitWidth>
12560      </field>
12561      <field>
12562       <name>SQW_32K</name>
12563       <description>RTC 32kHz Square Wave Output</description>
12564       <bitOffset>5</bitOffset>
12565       <bitWidth>1</bitWidth>
12566      </field>
12567     </fields>
12568    </register>
12569   </registers>
12570  </peripheral>
12571<!--RTC Real Time Clock and Alarm.-->
12572  <peripheral>
12573   <name>SDHC</name>
12574   <description>SDHC/SDIO Controller</description>
12575   <baseAddress>0x40037000</baseAddress>
12576   <addressBlock>
12577    <offset>0</offset>
12578    <size>0x1000</size>
12579    <usage>registers</usage>
12580   </addressBlock>
12581   <interrupt>
12582    <name>SDHC</name>
12583    <value>66</value>
12584   </interrupt>
12585   <registers>
12586    <register>
12587     <name>SDMA</name>
12588     <description>SDMA System Address / Argument 2.</description>
12589     <addressOffset>0x00</addressOffset>
12590     <size>32</size>
12591     <fields>
12592      <field>
12593       <name>ADDR</name>
12594       <description>SDMA System Address / Argument 2  of Auto CMD23.</description>
12595       <bitOffset>0</bitOffset>
12596       <bitWidth>32</bitWidth>
12597      </field>
12598     </fields>
12599    </register>
12600    <register>
12601     <name>BLK_SIZE</name>
12602     <description>Block Size.</description>
12603     <addressOffset>0x04</addressOffset>
12604     <size>16</size>
12605     <fields>
12606      <field>
12607       <name>TRANS</name>
12608       <description>Transfer Block Size.</description>
12609       <bitOffset>0</bitOffset>
12610       <bitWidth>12</bitWidth>
12611      </field>
12612      <field>
12613       <name>HOST_BUFF</name>
12614       <description>Host SDMA Buffer Boundary.</description>
12615       <bitOffset>12</bitOffset>
12616       <bitWidth>3</bitWidth>
12617      </field>
12618     </fields>
12619    </register>
12620    <register>
12621     <name>BLK_CNT</name>
12622     <description>Block Count.</description>
12623     <addressOffset>0x06</addressOffset>
12624     <size>16</size>
12625     <fields>
12626      <field>
12627       <name>COUNT</name>
12628       <description>Blocks Count For Current Transfer.</description>
12629       <bitOffset>0</bitOffset>
12630       <bitWidth>16</bitWidth>
12631      </field>
12632     </fields>
12633    </register>
12634    <register>
12635     <name>ARG_1</name>
12636     <description>Argument 1.</description>
12637     <addressOffset>0x08</addressOffset>
12638     <size>32</size>
12639     <fields>
12640      <field>
12641       <name>CMD</name>
12642       <description>Command Argument 1.</description>
12643       <bitOffset>0</bitOffset>
12644       <bitWidth>32</bitWidth>
12645      </field>
12646     </fields>
12647    </register>
12648    <register>
12649     <name>TRANS</name>
12650     <description>Transfer Mode.</description>
12651     <addressOffset>0x0C</addressOffset>
12652     <size>16</size>
12653     <fields>
12654      <field>
12655       <name>DMA_EN</name>
12656       <description>DMA Enable.</description>
12657       <bitOffset>0</bitOffset>
12658       <bitWidth>1</bitWidth>
12659       <enumeratedValues>
12660        <name>enable</name>
12661        <enumeratedValue>
12662         <name>dma_transfer</name>
12663         <value>1</value>
12664        </enumeratedValue>
12665        <enumeratedValue>
12666         <name>non_dma_transfer</name>
12667         <value>0</value>
12668        </enumeratedValue>
12669       </enumeratedValues>
12670      </field>
12671      <field>
12672       <name>BLK_CNT_EN</name>
12673       <description>Block Count Enable.</description>
12674       <bitOffset>1</bitOffset>
12675       <bitWidth>1</bitWidth>
12676       <enumeratedValues>
12677        <name>count</name>
12678        <enumeratedValue>
12679         <name>enable</name>
12680         <value>1</value>
12681        </enumeratedValue>
12682        <enumeratedValue>
12683         <name>disable</name>
12684         <value>0</value>
12685        </enumeratedValue>
12686       </enumeratedValues>
12687      </field>
12688      <field>
12689       <name>AUTO_CMD_EN</name>
12690       <description>Auto CMD Enable.</description>
12691       <bitOffset>2</bitOffset>
12692       <bitWidth>2</bitWidth>
12693       <enumeratedValues>
12694        <name>CMD</name>
12695        <enumeratedValue>
12696         <name>disable</name>
12697         <value>0</value>
12698        </enumeratedValue>
12699        <enumeratedValue>
12700         <name>cmd12</name>
12701         <value>1</value>
12702        </enumeratedValue>
12703        <enumeratedValue>
12704         <name>cmd23</name>
12705         <value>2</value>
12706        </enumeratedValue>
12707       </enumeratedValues>
12708      </field>
12709      <field>
12710       <name>READ_WRITE</name>
12711       <description>Data Transfer Direction Select.</description>
12712       <bitOffset>4</bitOffset>
12713       <bitWidth>1</bitWidth>
12714       <enumeratedValues>
12715        <name>read</name>
12716        <enumeratedValue>
12717         <name>read</name>
12718         <value>1</value>
12719        </enumeratedValue>
12720        <enumeratedValue>
12721         <name>write</name>
12722         <value>0</value>
12723        </enumeratedValue>
12724       </enumeratedValues>
12725      </field>
12726      <field>
12727       <name>MULTI</name>
12728       <description>Multi / Single Block Select.</description>
12729       <bitOffset>5</bitOffset>
12730       <bitWidth>1</bitWidth>
12731       <enumeratedValues>
12732        <name>multi</name>
12733        <enumeratedValue>
12734         <name>enable</name>
12735         <value>1</value>
12736        </enumeratedValue>
12737        <enumeratedValue>
12738         <name>disable</name>
12739         <value>0</value>
12740        </enumeratedValue>
12741       </enumeratedValues>
12742      </field>
12743     </fields>
12744    </register>
12745    <register>
12746     <name>CMD</name>
12747     <description>Command.</description>
12748     <addressOffset>0x0E</addressOffset>
12749     <size>16</size>
12750     <fields>
12751      <field>
12752       <name>RESP_TYPE</name>
12753       <description>Response Type Select.</description>
12754       <bitOffset>0</bitOffset>
12755       <bitWidth>2</bitWidth>
12756      </field>
12757      <field>
12758       <name>CRC_CHK_EN</name>
12759       <description>Command CRC Check Enable.</description>
12760       <bitOffset>3</bitOffset>
12761       <bitWidth>1</bitWidth>
12762      </field>
12763      <field>
12764       <name>IDX_CHK_EN</name>
12765       <description>Command Index Check Enable.</description>
12766       <bitOffset>4</bitOffset>
12767       <bitWidth>1</bitWidth>
12768      </field>
12769      <field>
12770       <name>DATA_PRES_SEL</name>
12771       <description>Data Present Select.</description>
12772       <bitOffset>5</bitOffset>
12773       <bitWidth>1</bitWidth>
12774      </field>
12775      <field>
12776       <name>TYPE</name>
12777       <description>Command Type.</description>
12778       <bitOffset>6</bitOffset>
12779       <bitWidth>2</bitWidth>
12780      </field>
12781      <field>
12782       <name>IDX</name>
12783       <description>Command Index.</description>
12784       <bitOffset>8</bitOffset>
12785       <bitWidth>6</bitWidth>
12786      </field>
12787     </fields>
12788    </register>
12789    <register>
12790     <dim>4</dim>
12791     <dimIncrement>4</dimIncrement>
12792     <name>RESP[%s]</name>
12793     <description>Response 0 Register 0-15.</description>
12794     <addressOffset>0x010</addressOffset>
12795     <size>32</size>
12796     <fields>
12797      <field>
12798       <name>CMD_RESP</name>
12799       <description>Command Response.</description>
12800       <bitOffset>0</bitOffset>
12801       <bitWidth>32</bitWidth>
12802      </field>
12803     </fields>
12804    </register>
12805    <register>
12806     <name>BUFFER</name>
12807     <description>Buffer Data Port.</description>
12808     <addressOffset>0x20</addressOffset>
12809     <size>32</size>
12810     <fields>
12811      <field>
12812       <name>DATA</name>
12813       <description>Buffer Data.</description>
12814       <bitOffset>0</bitOffset>
12815       <bitWidth>32</bitWidth>
12816      </field>
12817     </fields>
12818    </register>
12819    <register>
12820     <name>PRESENT</name>
12821     <description>Present State.</description>
12822     <addressOffset>0x024</addressOffset>
12823     <size>32</size>
12824     <access>read-only</access>
12825     <fields>
12826      <field>
12827       <name>CMD</name>
12828       <description>Command Inhibit (CMD).</description>
12829       <bitOffset>0</bitOffset>
12830       <bitWidth>1</bitWidth>
12831       <access>read-only</access>
12832      </field>
12833      <field>
12834       <name>DAT</name>
12835       <description>Command Inhibit (DAT).</description>
12836       <bitOffset>1</bitOffset>
12837       <bitWidth>1</bitWidth>
12838       <access>read-only</access>
12839      </field>
12840      <field>
12841       <name>DAT_LINE_ACTIVE</name>
12842       <description>DAT Line Active.</description>
12843       <bitOffset>2</bitOffset>
12844       <bitWidth>1</bitWidth>
12845       <access>read-only</access>
12846      </field>
12847      <field>
12848       <name>RETUNING</name>
12849       <description>Re-Tuning Request.</description>
12850       <bitOffset>3</bitOffset>
12851       <bitWidth>1</bitWidth>
12852       <access>read-only</access>
12853      </field>
12854      <field>
12855       <name>WRITE_TRANSFER</name>
12856       <description>Write Transfer Active.</description>
12857       <bitOffset>8</bitOffset>
12858       <bitWidth>1</bitWidth>
12859       <access>read-only</access>
12860      </field>
12861      <field>
12862       <name>READ_TRANSFER</name>
12863       <description>Read Transfer Active.</description>
12864       <bitOffset>9</bitOffset>
12865       <bitWidth>1</bitWidth>
12866       <access>read-only</access>
12867      </field>
12868      <field>
12869       <name>BUFFER_WRITE</name>
12870       <description>Buffer Write Enable.</description>
12871       <bitOffset>10</bitOffset>
12872       <bitWidth>1</bitWidth>
12873       <access>read-only</access>
12874      </field>
12875      <field>
12876       <name>BUFFER_READ</name>
12877       <description>Buffer Read Enable.</description>
12878       <bitOffset>11</bitOffset>
12879       <bitWidth>1</bitWidth>
12880       <access>read-only</access>
12881      </field>
12882      <field>
12883       <name>CARD_INSERTED</name>
12884       <description>Card Inserted.</description>
12885       <bitOffset>16</bitOffset>
12886       <bitWidth>1</bitWidth>
12887       <access>read-only</access>
12888      </field>
12889      <field>
12890       <name>CARD_STATE</name>
12891       <description>Card State Stable.</description>
12892       <bitOffset>17</bitOffset>
12893       <bitWidth>1</bitWidth>
12894       <access>read-only</access>
12895      </field>
12896      <field>
12897       <name>CARD_DETECT</name>
12898       <description>Card Detect Pin Level.</description>
12899       <bitOffset>18</bitOffset>
12900       <bitWidth>1</bitWidth>
12901       <access>read-only</access>
12902      </field>
12903      <field>
12904       <name>WP</name>
12905       <description>Write Protect Switch Pin Level.</description>
12906       <bitOffset>19</bitOffset>
12907       <bitWidth>1</bitWidth>
12908       <access>read-only</access>
12909      </field>
12910      <field>
12911       <name>DAT_SIGNAL_LEVEL</name>
12912       <description>DAT[3:0] Line Signal Level.</description>
12913       <bitOffset>20</bitOffset>
12914       <bitWidth>4</bitWidth>
12915      </field>
12916      <field>
12917       <name>CMD_SIGNAL_LEVEL</name>
12918       <description>CMD Line Signal Level.</description>
12919       <bitOffset>24</bitOffset>
12920       <bitWidth>1</bitWidth>
12921      </field>
12922     </fields>
12923    </register>
12924    <register>
12925     <name>HOST_CN_1</name>
12926     <description>Host Control 1.</description>
12927     <addressOffset>0x028</addressOffset>
12928     <size>8</size>
12929     <fields>
12930      <field>
12931       <name>LED_CN</name>
12932       <description>LED Control.</description>
12933       <bitOffset>0</bitOffset>
12934       <bitWidth>1</bitWidth>
12935      </field>
12936      <field>
12937       <name>DATA_TRANSFER_WIDTH</name>
12938       <description>Data Transfer Width.</description>
12939       <bitOffset>1</bitOffset>
12940       <bitWidth>1</bitWidth>
12941      </field>
12942      <field>
12943       <name>HS_EN</name>
12944       <description>High Speed Enable.</description>
12945       <bitOffset>2</bitOffset>
12946       <bitWidth>1</bitWidth>
12947      </field>
12948      <field>
12949       <name>DMA_SELECT</name>
12950       <description>DMA Select.</description>
12951       <bitOffset>3</bitOffset>
12952       <bitWidth>2</bitWidth>
12953      </field>
12954      <field>
12955       <name>EXT_DATA_TRANSFER_WIDTH</name>
12956       <description>Extended Data Transfer Width.</description>
12957       <bitOffset>5</bitOffset>
12958       <bitWidth>1</bitWidth>
12959      </field>
12960      <field>
12961       <name>CARD_DETECT_TEST</name>
12962       <description>Card Detect Test Level.</description>
12963       <bitOffset>6</bitOffset>
12964       <bitWidth>1</bitWidth>
12965      </field>
12966      <field>
12967       <name>CARD_DETECT_SIGNAL</name>
12968       <description>Card Detect Signal Selection.</description>
12969       <bitOffset>7</bitOffset>
12970       <bitWidth>1</bitWidth>
12971      </field>
12972     </fields>
12973    </register>
12974    <register>
12975     <name>PWR</name>
12976     <description>Power Control.</description>
12977     <addressOffset>0x029</addressOffset>
12978     <size>8</size>
12979     <fields>
12980      <field>
12981       <name>BUS_POWER</name>
12982       <description>SD Bus Power.</description>
12983       <bitOffset>0</bitOffset>
12984       <bitWidth>1</bitWidth>
12985      </field>
12986      <field>
12987       <name>BUS_VOLT_SEL</name>
12988       <description>SD Bus Voltage Select.</description>
12989       <bitOffset>1</bitOffset>
12990       <bitWidth>3</bitWidth>
12991      </field>
12992     </fields>
12993    </register>
12994    <register>
12995     <name>BLK_GAP</name>
12996     <description>Block Gap Control.</description>
12997     <addressOffset>0x02A</addressOffset>
12998     <size>8</size>
12999     <fields>
13000      <field>
13001       <name>STOP</name>
13002       <description>Stop At Block Gap Request.</description>
13003       <bitOffset>0</bitOffset>
13004       <bitWidth>1</bitWidth>
13005      </field>
13006      <field>
13007       <name>CONT</name>
13008       <description>Continue Request.</description>
13009       <bitOffset>1</bitOffset>
13010       <bitWidth>1</bitWidth>
13011      </field>
13012      <field>
13013       <name>READ_WAIT</name>
13014       <description>Read Wait Control.</description>
13015       <bitOffset>2</bitOffset>
13016       <bitWidth>1</bitWidth>
13017      </field>
13018      <field>
13019       <name>INTR</name>
13020       <description>Interrupt At Block Gap.</description>
13021       <bitOffset>3</bitOffset>
13022       <bitWidth>1</bitWidth>
13023      </field>
13024     </fields>
13025    </register>
13026    <register>
13027     <name>WAKEUP</name>
13028     <description>Wakeup Control.</description>
13029     <addressOffset>0x02B</addressOffset>
13030     <size>8</size>
13031     <fields>
13032      <field>
13033       <name>CARD_INT</name>
13034       <description>Wakeup Event Enable On Card Interrupt.</description>
13035       <bitOffset>0</bitOffset>
13036       <bitWidth>1</bitWidth>
13037      </field>
13038      <field>
13039       <name>CARD_INS</name>
13040       <description>Wakeup Event Enable On SD Card Insertion.</description>
13041       <bitOffset>1</bitOffset>
13042       <bitWidth>1</bitWidth>
13043      </field>
13044      <field>
13045       <name>CARD_REM</name>
13046       <description>Wakeup Event Enable On SD Card Removal.</description>
13047       <bitOffset>2</bitOffset>
13048       <bitWidth>1</bitWidth>
13049      </field>
13050     </fields>
13051    </register>
13052    <register>
13053     <name>CLK_CN</name>
13054     <description>Clock Control.</description>
13055     <addressOffset>0x02C</addressOffset>
13056     <size>16</size>
13057     <fields>
13058      <field>
13059       <name>INTERNAL_CLK_EN</name>
13060       <description>Internal Clock Enable.</description>
13061       <bitOffset>0</bitOffset>
13062       <bitWidth>1</bitWidth>
13063      </field>
13064      <field>
13065       <name>INTERNAL_CLK_STABLE</name>
13066       <description>Internal Clock Stable.</description>
13067       <bitOffset>1</bitOffset>
13068       <bitWidth>1</bitWidth>
13069       <access>read-only</access>
13070      </field>
13071      <field>
13072       <name>SD_CLK_EN</name>
13073       <description>SD Clock Enable.</description>
13074       <bitOffset>2</bitOffset>
13075       <bitWidth>1</bitWidth>
13076      </field>
13077      <field>
13078       <name>CLK_GEN_SEL</name>
13079       <description>Clock Generator Select.</description>
13080       <bitOffset>5</bitOffset>
13081       <bitWidth>1</bitWidth>
13082       <access>read-only</access>
13083      </field>
13084      <field>
13085       <name>UPPER_SDCLK_FREQ_SEL</name>
13086       <description>Upper Bits of SDCLK Frequency Select.</description>
13087       <bitOffset>6</bitOffset>
13088       <bitWidth>2</bitWidth>
13089      </field>
13090      <field>
13091       <name>SDCLK_FREQ_SEL</name>
13092       <description>SDCLK Frequency Select.</description>
13093       <bitOffset>8</bitOffset>
13094       <bitWidth>8</bitWidth>
13095      </field>
13096     </fields>
13097    </register>
13098    <register>
13099     <name>TO</name>
13100     <description>Timeout Control.</description>
13101     <addressOffset>0x02E</addressOffset>
13102     <size>8</size>
13103     <fields>
13104      <field>
13105       <name>DATA_COUNT_VALUE</name>
13106       <description>Data Timeout Counter Value.</description>
13107       <bitOffset>0</bitOffset>
13108       <bitWidth>3</bitWidth>
13109      </field>
13110     </fields>
13111    </register>
13112    <register>
13113     <name>SW_RESET</name>
13114     <description>Software Reset.</description>
13115     <addressOffset>0x02F</addressOffset>
13116     <size>8</size>
13117     <fields>
13118      <field>
13119       <name>RESET_ALL</name>
13120       <description>Software Reset For All.</description>
13121       <bitOffset>0</bitOffset>
13122       <bitWidth>1</bitWidth>
13123      </field>
13124      <field>
13125       <name>RESET_CMD</name>
13126       <description>Software Reset For CMD Line.</description>
13127       <bitOffset>1</bitOffset>
13128       <bitWidth>1</bitWidth>
13129      </field>
13130      <field>
13131       <name>RESET_DAT</name>
13132       <description>Software Reset For DAT Line.</description>
13133       <bitOffset>2</bitOffset>
13134       <bitWidth>1</bitWidth>
13135      </field>
13136     </fields>
13137    </register>
13138    <register>
13139     <name>INT_STAT</name>
13140     <description>Normal Interrupt Status.</description>
13141     <addressOffset>0x030</addressOffset>
13142     <size>16</size>
13143     <fields>
13144      <field>
13145       <name>CMD_COMP</name>
13146       <description>Command Complete.</description>
13147       <bitOffset>0</bitOffset>
13148       <bitWidth>1</bitWidth>
13149      </field>
13150      <field>
13151       <name>TRANS_COMP</name>
13152       <description>Transfer Complete.</description>
13153       <bitOffset>1</bitOffset>
13154       <bitWidth>1</bitWidth>
13155      </field>
13156      <field>
13157       <name>BLK_GAP_EVENT</name>
13158       <description>Block Gap Event.</description>
13159       <bitOffset>2</bitOffset>
13160       <bitWidth>1</bitWidth>
13161      </field>
13162      <field>
13163       <name>DMA</name>
13164       <description>DMA Interrupt.</description>
13165       <bitOffset>3</bitOffset>
13166       <bitWidth>1</bitWidth>
13167      </field>
13168      <field>
13169       <name>BUFF_WR_READY</name>
13170       <description>Buffer Write Ready.</description>
13171       <bitOffset>4</bitOffset>
13172       <bitWidth>1</bitWidth>
13173      </field>
13174      <field>
13175       <name>BUFF_RD_READY</name>
13176       <description>Buffer Read Ready.</description>
13177       <bitOffset>5</bitOffset>
13178       <bitWidth>1</bitWidth>
13179      </field>
13180      <field>
13181       <name>CARD_INSERTION</name>
13182       <description>Card Insertion.</description>
13183       <bitOffset>6</bitOffset>
13184       <bitWidth>1</bitWidth>
13185      </field>
13186      <field>
13187       <name>CARD_REMOVAL</name>
13188       <description>Card Removal.</description>
13189       <bitOffset>7</bitOffset>
13190       <bitWidth>1</bitWidth>
13191      </field>
13192      <field>
13193       <name>CARD_INTR</name>
13194       <description>Card Interrupt.</description>
13195       <bitOffset>8</bitOffset>
13196       <bitWidth>1</bitWidth>
13197      </field>
13198      <field>
13199       <name>RETUNING</name>
13200       <description>Re-Tuning Event.</description>
13201       <bitOffset>12</bitOffset>
13202       <bitWidth>1</bitWidth>
13203      </field>
13204      <field>
13205       <name>ERR_INTR</name>
13206       <description>Error Interrupt.</description>
13207       <bitOffset>15</bitOffset>
13208       <bitWidth>1</bitWidth>
13209      </field>
13210     </fields>
13211    </register>
13212    <register>
13213     <name>ER_INT_STAT</name>
13214     <description>Error Interrupt Status.</description>
13215     <addressOffset>0x032</addressOffset>
13216     <size>16</size>
13217     <fields>
13218      <field>
13219       <name>CMD_TO</name>
13220       <description>Command Timeout Error.</description>
13221       <bitOffset>0</bitOffset>
13222       <bitWidth>1</bitWidth>
13223      </field>
13224      <field>
13225       <name>CMD_CRC</name>
13226       <description>Command CRC Error.</description>
13227       <bitOffset>1</bitOffset>
13228       <bitWidth>1</bitWidth>
13229      </field>
13230      <field>
13231       <name>CMD_END_BIT</name>
13232       <description>Command End Bit Error.</description>
13233       <bitOffset>2</bitOffset>
13234       <bitWidth>1</bitWidth>
13235      </field>
13236      <field>
13237       <name>CMD_IDX</name>
13238       <description>Command Index Error.</description>
13239       <bitOffset>3</bitOffset>
13240       <bitWidth>1</bitWidth>
13241      </field>
13242      <field>
13243       <name>DATA_TO</name>
13244       <description>Data Timeout Error.</description>
13245       <bitOffset>4</bitOffset>
13246       <bitWidth>1</bitWidth>
13247      </field>
13248      <field>
13249       <name>DATA_CRC</name>
13250       <description>Data CRC Error.</description>
13251       <bitOffset>5</bitOffset>
13252       <bitWidth>1</bitWidth>
13253      </field>
13254      <field>
13255       <name>DATA_END_BIT</name>
13256       <description>Data End Bit Error.</description>
13257       <bitOffset>6</bitOffset>
13258       <bitWidth>1</bitWidth>
13259      </field>
13260      <field>
13261       <name>CURRENT_LIMIT</name>
13262       <description>Current Limit Error.</description>
13263       <bitOffset>7</bitOffset>
13264       <bitWidth>1</bitWidth>
13265      </field>
13266      <field>
13267       <name>AUTO_CMD_12</name>
13268       <description>Auto CMD Error.</description>
13269       <bitOffset>8</bitOffset>
13270       <bitWidth>1</bitWidth>
13271      </field>
13272      <field>
13273       <name>ADMA</name>
13274       <description>ADMA Error.</description>
13275       <bitOffset>9</bitOffset>
13276       <bitWidth>1</bitWidth>
13277      </field>
13278      <field>
13279       <name>DMA</name>
13280       <description>DMA Error.</description>
13281       <bitOffset>12</bitOffset>
13282       <bitWidth>1</bitWidth>
13283      </field>
13284     </fields>
13285    </register>
13286    <register>
13287     <name>INT_EN</name>
13288     <description>Normal Interrupt Status Enable.</description>
13289     <addressOffset>0x034</addressOffset>
13290     <size>16</size>
13291     <fields>
13292      <field>
13293       <name>CMD_COMP</name>
13294       <description>Command Complete Status Enable.</description>
13295       <bitOffset>0</bitOffset>
13296       <bitWidth>1</bitWidth>
13297      </field>
13298      <field>
13299       <name>TRANS_COMP</name>
13300       <description>Transfer Complete Status Enable.</description>
13301       <bitOffset>1</bitOffset>
13302       <bitWidth>1</bitWidth>
13303      </field>
13304      <field>
13305       <name>BLK_GAP</name>
13306       <description>Block Gap Event Status Enable.</description>
13307       <bitOffset>2</bitOffset>
13308       <bitWidth>1</bitWidth>
13309      </field>
13310      <field>
13311       <name>DMA</name>
13312       <description>DMA Interrupt Status Enable.</description>
13313       <bitOffset>3</bitOffset>
13314       <bitWidth>1</bitWidth>
13315      </field>
13316      <field>
13317       <name>BUFFER_WR</name>
13318       <description>Buffer Write Ready Status Enable.</description>
13319       <bitOffset>4</bitOffset>
13320       <bitWidth>1</bitWidth>
13321      </field>
13322      <field>
13323       <name>BUFFER_RD</name>
13324       <description>Buffer Read Ready Status Enable.</description>
13325       <bitOffset>5</bitOffset>
13326       <bitWidth>1</bitWidth>
13327      </field>
13328      <field>
13329       <name>CARD_INSERT</name>
13330       <description>Card Insertion Status Enable.</description>
13331       <bitOffset>6</bitOffset>
13332       <bitWidth>1</bitWidth>
13333      </field>
13334      <field>
13335       <name>CARD_REMOVAL</name>
13336       <description>Card Removal Status Enable.</description>
13337       <bitOffset>7</bitOffset>
13338       <bitWidth>1</bitWidth>
13339      </field>
13340      <field>
13341       <name>CARD_INT</name>
13342       <description>Card Interrupt Status Enable.</description>
13343       <bitOffset>8</bitOffset>
13344       <bitWidth>1</bitWidth>
13345      </field>
13346      <field>
13347       <name>RETUNING</name>
13348       <description>Re-Tuning Event Status Enable.</description>
13349       <bitOffset>12</bitOffset>
13350       <bitWidth>1</bitWidth>
13351      </field>
13352     </fields>
13353    </register>
13354    <register>
13355     <name>ER_INT_EN</name>
13356     <description>Error Interrupt Status Enable.</description>
13357     <addressOffset>0x36</addressOffset>
13358     <size>16</size>
13359     <fields>
13360      <field>
13361       <name>CMD_TO</name>
13362       <description>Command Timeout Error Status Enable.</description>
13363       <bitOffset>0</bitOffset>
13364       <bitWidth>1</bitWidth>
13365      </field>
13366      <field>
13367       <name>CMD_CRC</name>
13368       <description>Command CRC Error Status Enable.</description>
13369       <bitOffset>1</bitOffset>
13370       <bitWidth>1</bitWidth>
13371      </field>
13372      <field>
13373       <name>CMD_END_BIT</name>
13374       <description>Command End Bit Error Status Enable.</description>
13375       <bitOffset>2</bitOffset>
13376       <bitWidth>1</bitWidth>
13377      </field>
13378      <field>
13379       <name>CMD_IDX</name>
13380       <description>Command Index Error Status Enable.</description>
13381       <bitOffset>3</bitOffset>
13382       <bitWidth>1</bitWidth>
13383      </field>
13384      <field>
13385       <name>DATA_TO</name>
13386       <description>Data Timeout Error Status Enable.</description>
13387       <bitOffset>4</bitOffset>
13388       <bitWidth>1</bitWidth>
13389      </field>
13390      <field>
13391       <name>DATA_CRC</name>
13392       <description>Data CRC Error Status Enable.</description>
13393       <bitOffset>5</bitOffset>
13394       <bitWidth>1</bitWidth>
13395      </field>
13396      <field>
13397       <name>DATA_END_BIT</name>
13398       <description>Data End Bit Error Status Enable.</description>
13399       <bitOffset>6</bitOffset>
13400       <bitWidth>1</bitWidth>
13401      </field>
13402      <field>
13403       <name>AUTO_CMD</name>
13404       <description>Auto CMD Error Status Enable.</description>
13405       <bitOffset>8</bitOffset>
13406       <bitWidth>1</bitWidth>
13407      </field>
13408      <field>
13409       <name>ADMA</name>
13410       <description>ADMA Error Status Enable.</description>
13411       <bitOffset>9</bitOffset>
13412       <bitWidth>1</bitWidth>
13413      </field>
13414      <field>
13415       <name>TUNING</name>
13416       <description>Tuning Error Status Enable.</description>
13417       <bitOffset>10</bitOffset>
13418       <bitWidth>1</bitWidth>
13419      </field>
13420      <field>
13421       <name>VENDOR</name>
13422       <description>Vendor Specific Error Status Enable.</description>
13423       <bitOffset>12</bitOffset>
13424       <bitWidth>1</bitWidth>
13425      </field>
13426     </fields>
13427    </register>
13428    <register>
13429     <name>INT_SIGNAL</name>
13430     <description>Normal Interrupt Signal Enable.</description>
13431     <addressOffset>0x038</addressOffset>
13432     <size>16</size>
13433     <fields>
13434      <field>
13435       <name>CMD_COMP</name>
13436       <description>Command Complete Signal Enable.</description>
13437       <bitOffset>0</bitOffset>
13438       <bitWidth>1</bitWidth>
13439      </field>
13440      <field>
13441       <name>TRANS_COMP</name>
13442       <description>Transfer Complete Signal Enable.</description>
13443       <bitOffset>1</bitOffset>
13444       <bitWidth>1</bitWidth>
13445      </field>
13446      <field>
13447       <name>BLK_GAP</name>
13448       <description>Block Gap Event Signal Enable.</description>
13449       <bitOffset>2</bitOffset>
13450       <bitWidth>1</bitWidth>
13451      </field>
13452      <field>
13453       <name>DMA</name>
13454       <description>DMA Interrupt Signal Enable.</description>
13455       <bitOffset>3</bitOffset>
13456       <bitWidth>1</bitWidth>
13457      </field>
13458      <field>
13459       <name>BUFFER_WR</name>
13460       <description>Buffer Write Ready Signal Enable.</description>
13461       <bitOffset>4</bitOffset>
13462       <bitWidth>1</bitWidth>
13463      </field>
13464      <field>
13465       <name>BUFFER_RD</name>
13466       <description>Buffer Read Ready Signal Enable.</description>
13467       <bitOffset>5</bitOffset>
13468       <bitWidth>1</bitWidth>
13469      </field>
13470      <field>
13471       <name>CARD_INSERT</name>
13472       <description>Card Insertion Signal Enable.</description>
13473       <bitOffset>6</bitOffset>
13474       <bitWidth>1</bitWidth>
13475      </field>
13476      <field>
13477       <name>CARD_REMOVAL</name>
13478       <description>Card Removal Signal Enable.</description>
13479       <bitOffset>7</bitOffset>
13480       <bitWidth>1</bitWidth>
13481      </field>
13482      <field>
13483       <name>CARD_INT</name>
13484       <description>Card Interrupt Signal Enable.</description>
13485       <bitOffset>8</bitOffset>
13486       <bitWidth>1</bitWidth>
13487      </field>
13488      <field>
13489       <name>RETUNING</name>
13490       <description>Re-Tuning Event Signal Enable.</description>
13491       <bitOffset>12</bitOffset>
13492       <bitWidth>1</bitWidth>
13493      </field>
13494     </fields>
13495    </register>
13496    <register>
13497     <name>ER_INT_SIGNAL</name>
13498     <description>Error Interrupt Signal Enable.</description>
13499     <addressOffset>0x03A</addressOffset>
13500     <size>16</size>
13501     <fields>
13502      <field>
13503       <name>CMD_TO</name>
13504       <description>Command Timeout Error Signal Enable.</description>
13505       <bitOffset>0</bitOffset>
13506       <bitWidth>1</bitWidth>
13507      </field>
13508      <field>
13509       <name>CMD_CRC</name>
13510       <description>Command CRC Error Signal Enable.</description>
13511       <bitOffset>1</bitOffset>
13512       <bitWidth>1</bitWidth>
13513      </field>
13514      <field>
13515       <name>CMD_END_BIT</name>
13516       <description>Command End Bit Error Signal Enable.</description>
13517       <bitOffset>2</bitOffset>
13518       <bitWidth>1</bitWidth>
13519      </field>
13520      <field>
13521       <name>CMD_IDX</name>
13522       <description>Command Index Error Signal Enable.</description>
13523       <bitOffset>3</bitOffset>
13524       <bitWidth>1</bitWidth>
13525      </field>
13526      <field>
13527       <name>DATA_TO</name>
13528       <description>Data Timeout Error Signal Enable.</description>
13529       <bitOffset>4</bitOffset>
13530       <bitWidth>1</bitWidth>
13531      </field>
13532      <field>
13533       <name>DATA_CRC</name>
13534       <description>Data CRC Error Signal Enable.</description>
13535       <bitOffset>5</bitOffset>
13536       <bitWidth>1</bitWidth>
13537      </field>
13538      <field>
13539       <name>DATA_END_BIT</name>
13540       <description>Data End Bit Error Signal Enable.</description>
13541       <bitOffset>6</bitOffset>
13542       <bitWidth>1</bitWidth>
13543      </field>
13544      <field>
13545       <name>CURR_LIM</name>
13546       <description>Current Limit Error Signal Enable.</description>
13547       <bitOffset>7</bitOffset>
13548       <bitWidth>1</bitWidth>
13549      </field>
13550      <field>
13551       <name>AUTO_CMD</name>
13552       <description>Auto CMD Error Signal Enable.</description>
13553       <bitOffset>8</bitOffset>
13554       <bitWidth>1</bitWidth>
13555      </field>
13556      <field>
13557       <name>ADMA</name>
13558       <description>ADMA Error Signal Enable.</description>
13559       <bitOffset>9</bitOffset>
13560       <bitWidth>1</bitWidth>
13561      </field>
13562      <field>
13563       <name>TUNING</name>
13564       <description>Tuning Error Signal Enable.</description>
13565       <bitOffset>10</bitOffset>
13566       <bitWidth>1</bitWidth>
13567      </field>
13568      <field>
13569       <name>TAR_RESP</name>
13570       <description>Target Response Error Signal Enable.</description>
13571       <bitOffset>12</bitOffset>
13572       <bitWidth>1</bitWidth>
13573      </field>
13574     </fields>
13575    </register>
13576    <register>
13577     <name>AUTO_CMD_ER</name>
13578     <description>Auto CMD Error Status.</description>
13579     <addressOffset>0x03C</addressOffset>
13580     <size>16</size>
13581     <fields>
13582      <field>
13583       <name>NOT_EXCUTED</name>
13584       <description>Auto CMD12 Not Executed.</description>
13585       <bitOffset>0</bitOffset>
13586       <bitWidth>1</bitWidth>
13587      </field>
13588      <field>
13589       <name>TO</name>
13590       <description>Auto CMD Timeout Error.</description>
13591       <bitOffset>1</bitOffset>
13592       <bitWidth>1</bitWidth>
13593      </field>
13594      <field>
13595       <name>CRC</name>
13596       <description>Auto CMD CRC Error.</description>
13597       <bitOffset>2</bitOffset>
13598       <bitWidth>1</bitWidth>
13599      </field>
13600      <field>
13601       <name>END_BIT</name>
13602       <description>Auto CMD End Bit Error.</description>
13603       <bitOffset>3</bitOffset>
13604       <bitWidth>1</bitWidth>
13605      </field>
13606      <field>
13607       <name>INDEX</name>
13608       <description>Auto CMD Index Error.</description>
13609       <bitOffset>4</bitOffset>
13610       <bitWidth>1</bitWidth>
13611      </field>
13612      <field>
13613       <name>NOT_ISSUED</name>
13614       <description>Command Not Issued By Auto CMD12 Error.</description>
13615       <bitOffset>7</bitOffset>
13616       <bitWidth>1</bitWidth>
13617      </field>
13618     </fields>
13619    </register>
13620    <register>
13621     <name>HOST_CN_2</name>
13622     <description>Host Control 2.</description>
13623     <addressOffset>0x03E</addressOffset>
13624     <size>16</size>
13625     <fields>
13626      <field>
13627       <name>UHS</name>
13628       <description>UHS Mode Select.</description>
13629       <bitOffset>0</bitOffset>
13630       <bitWidth>2</bitWidth>
13631      </field>
13632      <field>
13633       <name>SIGNAL_V1_8</name>
13634       <description>1.8V Signaling Enable.</description>
13635       <bitOffset>3</bitOffset>
13636       <bitWidth>1</bitWidth>
13637      </field>
13638      <field>
13639       <name>DRIVER_STRENGTH</name>
13640       <description>Driver Strength Select.</description>
13641       <bitOffset>4</bitOffset>
13642       <bitWidth>2</bitWidth>
13643      </field>
13644      <field>
13645       <name>EXCUTE</name>
13646       <description>Execute Tuning.</description>
13647       <bitOffset>6</bitOffset>
13648       <bitWidth>1</bitWidth>
13649      </field>
13650      <field>
13651       <name>SAMPLING_CLK</name>
13652       <description>Sampling Clock Select.</description>
13653       <bitOffset>7</bitOffset>
13654       <bitWidth>1</bitWidth>
13655      </field>
13656      <field>
13657       <name>ASYNCH_INT</name>
13658       <description>Asynchronous Interrupt Enable.</description>
13659       <bitOffset>14</bitOffset>
13660       <bitWidth>1</bitWidth>
13661      </field>
13662      <field>
13663       <name>PRESET_VAL_EN</name>
13664       <description>Preset Value Enable.</description>
13665       <bitOffset>15</bitOffset>
13666       <bitWidth>1</bitWidth>
13667      </field>
13668     </fields>
13669    </register>
13670    <register>
13671     <name>CFG_0</name>
13672     <description>Capabilities 0-31.</description>
13673     <addressOffset>0x040</addressOffset>
13674     <size>32</size>
13675     <access>read-only</access>
13676     <fields>
13677      <field>
13678       <name>TO_CLK_FREQ</name>
13679       <description>Timeout Clock Frequency.</description>
13680       <bitOffset>0</bitOffset>
13681       <bitWidth>6</bitWidth>
13682       <access>read-only</access>
13683      </field>
13684      <field>
13685       <name>TO_CLK_UNIT</name>
13686       <description>Timeout Clock Unit.</description>
13687       <bitOffset>7</bitOffset>
13688       <bitWidth>1</bitWidth>
13689       <access>read-only</access>
13690      </field>
13691      <field>
13692       <name>CLK_FREQ</name>
13693       <description>Base Clock Frequency For SD Clock.</description>
13694       <bitOffset>8</bitOffset>
13695       <bitWidth>8</bitWidth>
13696       <access>read-only</access>
13697      </field>
13698      <field>
13699       <name>MAX_BLK_LEN</name>
13700       <description>Max Block Length.</description>
13701       <bitOffset>16</bitOffset>
13702       <bitWidth>2</bitWidth>
13703       <access>read-only</access>
13704      </field>
13705      <field>
13706       <name>BIT_8</name>
13707       <description>8-bit Support for Embedded Device.</description>
13708       <bitOffset>18</bitOffset>
13709       <bitWidth>1</bitWidth>
13710       <access>read-only</access>
13711      </field>
13712      <field>
13713       <name>ADMA2</name>
13714       <description>ADMA2 Support.</description>
13715       <bitOffset>19</bitOffset>
13716       <bitWidth>1</bitWidth>
13717       <access>read-only</access>
13718      </field>
13719      <field>
13720       <name>HS</name>
13721       <description>High Speed Support.</description>
13722       <bitOffset>21</bitOffset>
13723       <bitWidth>1</bitWidth>
13724       <access>read-only</access>
13725      </field>
13726      <field>
13727       <name>SDMA</name>
13728       <description>SDMA Support.</description>
13729       <bitOffset>22</bitOffset>
13730       <bitWidth>1</bitWidth>
13731       <access>read-only</access>
13732      </field>
13733      <field>
13734       <name>SUSPEND</name>
13735       <description>Suspend/Resume Support.</description>
13736       <bitOffset>23</bitOffset>
13737       <bitWidth>1</bitWidth>
13738       <access>read-only</access>
13739      </field>
13740      <field>
13741       <name>V3_3</name>
13742       <description>Voltage Support 3.3V.</description>
13743       <bitOffset>24</bitOffset>
13744       <bitWidth>1</bitWidth>
13745       <access>read-only</access>
13746      </field>
13747      <field>
13748       <name>V3_0</name>
13749       <description>Voltage Support 3.0V.</description>
13750       <bitOffset>25</bitOffset>
13751       <bitWidth>1</bitWidth>
13752       <access>read-only</access>
13753      </field>
13754      <field>
13755       <name>V1_8</name>
13756       <description>Voltage Support 1.8V.</description>
13757       <bitOffset>26</bitOffset>
13758       <bitWidth>1</bitWidth>
13759       <access>read-only</access>
13760      </field>
13761      <field>
13762       <name>BIT_64_SYS_BUS</name>
13763       <description>64-bit System Bus Support.</description>
13764       <bitOffset>28</bitOffset>
13765       <bitWidth>1</bitWidth>
13766       <access>read-only</access>
13767      </field>
13768      <field>
13769       <name>ASYNC_INT</name>
13770       <description>Asynchronous Interrupt Support.</description>
13771       <bitOffset>29</bitOffset>
13772       <bitWidth>1</bitWidth>
13773       <access>read-only</access>
13774      </field>
13775      <field>
13776       <name>SLOT_TYPE</name>
13777       <description>Slot Type.</description>
13778       <bitOffset>30</bitOffset>
13779       <bitWidth>2</bitWidth>
13780       <access>read-only</access>
13781      </field>
13782     </fields>
13783    </register>
13784    <register>
13785     <name>CFG_1</name>
13786     <description>Capabilities 32-63.</description>
13787     <addressOffset>0x044</addressOffset>
13788     <size>32</size>
13789     <access>read-only</access>
13790     <fields>
13791      <field>
13792       <name>SDR50</name>
13793       <description>SDR50 Support.</description>
13794       <bitOffset>0</bitOffset>
13795       <bitWidth>1</bitWidth>
13796       <access>read-only</access>
13797      </field>
13798      <field>
13799       <name>SDR104</name>
13800       <description>SDR104 Support.</description>
13801       <bitOffset>1</bitOffset>
13802       <bitWidth>0</bitWidth>
13803       <access>read-only</access>
13804      </field>
13805      <field>
13806       <name>DDR50</name>
13807       <description>DDR50 Support.</description>
13808       <bitOffset>2</bitOffset>
13809       <bitWidth>1</bitWidth>
13810       <access>read-only</access>
13811      </field>
13812      <field>
13813       <name>DRIVER_A</name>
13814       <description>Driver Type A Support.</description>
13815       <bitOffset>4</bitOffset>
13816       <bitWidth>1</bitWidth>
13817       <access>read-only</access>
13818      </field>
13819      <field>
13820       <name>DRIVER_C</name>
13821       <description>Driver Type C Support.</description>
13822       <bitOffset>5</bitOffset>
13823       <bitWidth>1</bitWidth>
13824       <access>read-only</access>
13825      </field>
13826      <field>
13827       <name>DRIVER_D</name>
13828       <description>Driver Type D Support.</description>
13829       <bitOffset>6</bitOffset>
13830       <bitWidth>1</bitWidth>
13831       <access>read-only</access>
13832      </field>
13833      <field>
13834       <name>TIMER_CNT_TUNING</name>
13835       <description>Timer Count for Re-Tuning.</description>
13836       <bitOffset>8</bitOffset>
13837       <bitWidth>4</bitWidth>
13838       <access>read-only</access>
13839      </field>
13840      <field>
13841       <name>TUNING_SDR50</name>
13842       <description>Use Tuning for SDR50.</description>
13843       <bitOffset>13</bitOffset>
13844       <bitWidth>1</bitWidth>
13845       <access>read-only</access>
13846      </field>
13847      <field>
13848       <name>RETUNING</name>
13849       <description>Re-Tuning Modes.</description>
13850       <bitOffset>14</bitOffset>
13851       <bitWidth>2</bitWidth>
13852       <access>read-only</access>
13853      </field>
13854      <field>
13855       <name>CLK_MULTI</name>
13856       <description>Clock Multiplier.</description>
13857       <bitOffset>16</bitOffset>
13858       <bitWidth>8</bitWidth>
13859       <access>read-only</access>
13860      </field>
13861     </fields>
13862    </register>
13863    <register>
13864     <name>MAX_CURR_CFG</name>
13865     <description>Maximum Current Capabilities.</description>
13866     <addressOffset>0x048</addressOffset>
13867     <size>32</size>
13868     <access>read-only</access>
13869     <fields>
13870      <field>
13871       <name>V3_3</name>
13872       <description>Maximum Current for 3.3V.</description>
13873       <bitOffset>0</bitOffset>
13874       <bitWidth>8</bitWidth>
13875       <access>read-only</access>
13876      </field>
13877      <field>
13878       <name>V3_0</name>
13879       <description>Maximum Current for 3.0V.</description>
13880       <bitOffset>8</bitOffset>
13881       <bitWidth>8</bitWidth>
13882       <access>read-only</access>
13883      </field>
13884      <field>
13885       <name>V1_8</name>
13886       <description>Maximum Current for 1.8V.</description>
13887       <bitOffset>16</bitOffset>
13888       <bitWidth>8</bitWidth>
13889       <access>read-only</access>
13890      </field>
13891     </fields>
13892    </register>
13893    <register>
13894     <name>FORCE_CMD</name>
13895     <description>Force Event for Auto CMD Error Status.</description>
13896     <addressOffset>0x050</addressOffset>
13897     <size>16</size>
13898     <access>write-only</access>
13899     <fields>
13900      <field>
13901       <name>NOT_EXCU</name>
13902       <description>Force Event for Auto CMD12 Not Executed.</description>
13903       <bitOffset>0</bitOffset>
13904       <bitWidth>1</bitWidth>
13905       <access>write-only</access>
13906      </field>
13907      <field>
13908       <name>TO</name>
13909       <description>Force Event for Auto CMD Timeout Error.</description>
13910       <bitOffset>1</bitOffset>
13911       <bitWidth>1</bitWidth>
13912       <access>write-only</access>
13913      </field>
13914      <field>
13915       <name>CRC</name>
13916       <description>Force Event for Auto CMD CRC Error.</description>
13917       <bitOffset>2</bitOffset>
13918       <bitWidth>1</bitWidth>
13919       <access>write-only</access>
13920      </field>
13921      <field>
13922       <name>END_BIT</name>
13923       <description>Force Event for Auto CMD End Bit Error.</description>
13924       <bitOffset>3</bitOffset>
13925       <bitWidth>1</bitWidth>
13926       <access>write-only</access>
13927      </field>
13928      <field>
13929       <name>INDEX</name>
13930       <description>Force Event for Auto CMD Index Error.</description>
13931       <bitOffset>4</bitOffset>
13932       <bitWidth>1</bitWidth>
13933       <access>write-only</access>
13934      </field>
13935      <field>
13936       <name>NOT_ISSUED</name>
13937       <description>Force Event for Command Not Issued By Auto CMD12 Error.</description>
13938       <bitOffset>7</bitOffset>
13939       <bitWidth>1</bitWidth>
13940       <access>write-only</access>
13941      </field>
13942     </fields>
13943    </register>
13944    <register>
13945     <name>FORCE_EVENT_INT_STAT</name>
13946     <description>Force Event for Error Interrupt Status.</description>
13947     <addressOffset>0x052</addressOffset>
13948     <size>16</size>
13949     <fields>
13950      <field>
13951       <name>CMD_TO</name>
13952       <description>Force Event for Command Timeout Error.</description>
13953       <bitOffset>0</bitOffset>
13954       <bitWidth>1</bitWidth>
13955       <access>read-only</access>
13956      </field>
13957      <field>
13958       <name>CMD_CRC</name>
13959       <description>Force Event for Command CRC Error.</description>
13960       <bitOffset>1</bitOffset>
13961       <bitWidth>1</bitWidth>
13962       <access>read-only</access>
13963      </field>
13964      <field>
13965       <name>CMD_END_BIT</name>
13966       <description>Force Event for Command End Bit Error.</description>
13967       <bitOffset>2</bitOffset>
13968       <bitWidth>1</bitWidth>
13969       <access>read-only</access>
13970      </field>
13971      <field>
13972       <name>CMD_INDEX</name>
13973       <description>Force Event for Command Index Error.</description>
13974       <bitOffset>3</bitOffset>
13975       <bitWidth>1</bitWidth>
13976       <access>read-only</access>
13977      </field>
13978      <field>
13979       <name>DATA_TO</name>
13980       <description>Force Event for Data Timeout Error.</description>
13981       <bitOffset>4</bitOffset>
13982       <bitWidth>1</bitWidth>
13983       <access>read-only</access>
13984      </field>
13985      <field>
13986       <name>DATA_CRC</name>
13987       <description>Force Event for Data CRC Error.</description>
13988       <bitOffset>5</bitOffset>
13989       <bitWidth>1</bitWidth>
13990       <access>read-only</access>
13991      </field>
13992      <field>
13993       <name>DATA_END_BIT</name>
13994       <description>Force Event for Data End Bit Error.</description>
13995       <bitOffset>6</bitOffset>
13996       <bitWidth>1</bitWidth>
13997       <access>read-only</access>
13998      </field>
13999      <field>
14000       <name>CURR_LIMIT</name>
14001       <description>Force Event for Current Limit Error.</description>
14002       <bitOffset>7</bitOffset>
14003       <bitWidth>1</bitWidth>
14004       <access>read-only</access>
14005      </field>
14006      <field>
14007       <name>AUTO_CMD</name>
14008       <description>Force Event for Auto CMD Error.</description>
14009       <bitOffset>8</bitOffset>
14010       <bitWidth>1</bitWidth>
14011       <access>read-only</access>
14012      </field>
14013      <field>
14014       <name>ADMA</name>
14015       <description>Force Event for ADMA Error.</description>
14016       <bitOffset>9</bitOffset>
14017       <bitWidth>1</bitWidth>
14018      </field>
14019      <field>
14020       <name>VENDOR</name>
14021       <description>Force Event for Vendor Specific Error Status.</description>
14022       <bitOffset>12</bitOffset>
14023       <bitWidth>3</bitWidth>
14024       <access>write-only</access>
14025      </field>
14026     </fields>
14027    </register>
14028    <register>
14029     <name>ADMA_ER</name>
14030     <description>ADMA Error Status.</description>
14031     <addressOffset>0x054</addressOffset>
14032     <size>8</size>
14033     <fields>
14034      <field>
14035       <name>STATE</name>
14036       <description>ADMA Error State.</description>
14037       <bitOffset>0</bitOffset>
14038       <bitWidth>2</bitWidth>
14039      </field>
14040      <field>
14041       <name>LEN_MISMATCH</name>
14042       <description>ADMA Length Mismatch Error.</description>
14043       <bitOffset>2</bitOffset>
14044       <bitWidth>1</bitWidth>
14045      </field>
14046     </fields>
14047    </register>
14048    <register>
14049     <name>ADMA_ADDR_0</name>
14050     <description>ADMA System Address 0-31.</description>
14051     <addressOffset>0x058</addressOffset>
14052     <size>32</size>
14053     <fields>
14054      <field>
14055       <name>ADDR</name>
14056       <description>ADMA System Address  Part 1 (part 2 is ADMA_ADDR_1).</description>
14057       <bitOffset>0</bitOffset>
14058       <bitWidth>32</bitWidth>
14059      </field>
14060     </fields>
14061    </register>
14062    <register>
14063     <name>ADMA_ADDR_1</name>
14064     <description>ADMA System Address 32-63.</description>
14065     <addressOffset>0x05C</addressOffset>
14066     <size>32</size>
14067     <fields>
14068      <field>
14069       <name>ADDR</name>
14070       <description>ADMA System Address  Part 1 (part 2 is ADMA_ADDR_1).</description>
14071       <bitOffset>0</bitOffset>
14072       <bitWidth>32</bitWidth>
14073      </field>
14074     </fields>
14075    </register>
14076    <register>
14077     <name>PRESET_0</name>
14078     <description>Preset Value for Initialization.</description>
14079     <addressOffset>0x060</addressOffset>
14080     <size>16</size>
14081     <access>read-only</access>
14082     <fields>
14083      <field>
14084       <name>SDCLK_FREQ</name>
14085       <description>SDCLK Frequency Select Value.</description>
14086       <bitOffset>0</bitOffset>
14087       <bitWidth>10</bitWidth>
14088       <access>read-only</access>
14089      </field>
14090      <field>
14091       <name>CLK_GEN</name>
14092       <description>Clock Generator Select Value.</description>
14093       <bitOffset>10</bitOffset>
14094       <bitWidth>1</bitWidth>
14095       <access>read-only</access>
14096      </field>
14097      <field>
14098       <name>DRIVER_STRENGTH</name>
14099       <description>Driver Strength Select Value.</description>
14100       <bitOffset>14</bitOffset>
14101       <bitWidth>2</bitWidth>
14102       <access>read-only</access>
14103      </field>
14104     </fields>
14105    </register>
14106    <register>
14107     <name>PRESET_1</name>
14108     <description>Preset Value for Default Speed.</description>
14109     <addressOffset>0x062</addressOffset>
14110     <size>16</size>
14111     <access>read-only</access>
14112     <fields>
14113      <field>
14114       <name>SDCLK_FREQ</name>
14115       <description>SDCLK Frequency Select Value.</description>
14116       <bitOffset>0</bitOffset>
14117       <bitWidth>10</bitWidth>
14118       <access>read-only</access>
14119      </field>
14120      <field>
14121       <name>CLK_GEN</name>
14122       <description>Clock Generator Select Value.</description>
14123       <bitOffset>10</bitOffset>
14124       <bitWidth>1</bitWidth>
14125       <access>read-only</access>
14126      </field>
14127      <field>
14128       <name>DRIVER_STRENGTH</name>
14129       <description>Driver Strength Select Value.</description>
14130       <bitOffset>14</bitOffset>
14131       <bitWidth>2</bitWidth>
14132       <access>read-only</access>
14133      </field>
14134     </fields>
14135    </register>
14136    <register>
14137     <name>PRESET_2</name>
14138     <description>Preset Value for High Speed.</description>
14139     <addressOffset>0x064</addressOffset>
14140     <size>16</size>
14141     <access>read-only</access>
14142     <fields>
14143      <field>
14144       <name>SDCLK_FREQ</name>
14145       <description>SDCLK Frequency Select Value.</description>
14146       <bitOffset>0</bitOffset>
14147       <bitWidth>10</bitWidth>
14148       <access>read-only</access>
14149      </field>
14150      <field>
14151       <name>CLK_GEN</name>
14152       <description>Clock Generator Select Value.</description>
14153       <bitOffset>10</bitOffset>
14154       <bitWidth>1</bitWidth>
14155       <access>read-only</access>
14156      </field>
14157      <field>
14158       <name>DRIVER_STRENGTH</name>
14159       <description>Driver Strength Select Value.</description>
14160       <bitOffset>14</bitOffset>
14161       <bitWidth>2</bitWidth>
14162       <access>read-only</access>
14163      </field>
14164     </fields>
14165    </register>
14166    <register>
14167     <name>PRESET_3</name>
14168     <description>Preset Value for SDR12.</description>
14169     <addressOffset>0x066</addressOffset>
14170     <size>16</size>
14171     <access>read-only</access>
14172     <fields>
14173      <field>
14174       <name>SDCLK_FREQ</name>
14175       <description>SDCLK Frequency Select Value.</description>
14176       <bitOffset>0</bitOffset>
14177       <bitWidth>10</bitWidth>
14178       <access>read-only</access>
14179      </field>
14180      <field>
14181       <name>CLK_GEN</name>
14182       <description>Clock Generator Select Value.</description>
14183       <bitOffset>10</bitOffset>
14184       <bitWidth>1</bitWidth>
14185       <access>read-only</access>
14186      </field>
14187      <field>
14188       <name>DRIVER_STRENGTH</name>
14189       <description>Driver Strength Select Value.</description>
14190       <bitOffset>14</bitOffset>
14191       <bitWidth>2</bitWidth>
14192       <access>read-only</access>
14193      </field>
14194     </fields>
14195    </register>
14196    <register>
14197     <name>PRESET_4</name>
14198     <description>Preset Value for SDR25.</description>
14199     <addressOffset>0x068</addressOffset>
14200     <size>16</size>
14201     <access>read-only</access>
14202     <fields>
14203      <field>
14204       <name>SDCLK_FREQ</name>
14205       <description>SDCLK Frequency Select Value.</description>
14206       <bitOffset>0</bitOffset>
14207       <bitWidth>10</bitWidth>
14208       <access>read-only</access>
14209      </field>
14210      <field>
14211       <name>CLK_GEN</name>
14212       <description>Clock Generator Select Value.</description>
14213       <bitOffset>10</bitOffset>
14214       <bitWidth>1</bitWidth>
14215       <access>read-only</access>
14216      </field>
14217      <field>
14218       <name>DRIVER_STRENGTH</name>
14219       <description>Driver Strength Select Value.</description>
14220       <bitOffset>14</bitOffset>
14221       <bitWidth>2</bitWidth>
14222       <access>read-only</access>
14223      </field>
14224     </fields>
14225    </register>
14226    <register>
14227     <name>PRESET_5</name>
14228     <description>Preset Value for SDR50.</description>
14229     <addressOffset>0x06A</addressOffset>
14230     <size>16</size>
14231     <access>read-only</access>
14232     <fields>
14233      <field>
14234       <name>SDCLK_FREQ</name>
14235       <description>SDCLK Frequency Select Value.</description>
14236       <bitOffset>0</bitOffset>
14237       <bitWidth>10</bitWidth>
14238       <access>read-only</access>
14239      </field>
14240      <field>
14241       <name>CLK_GEN</name>
14242       <description>Clock Generator Select Value.</description>
14243       <bitOffset>10</bitOffset>
14244       <bitWidth>1</bitWidth>
14245       <access>read-only</access>
14246      </field>
14247      <field>
14248       <name>DRIVER_STRENGTH</name>
14249       <description>Driver Strength Select Value.</description>
14250       <bitOffset>14</bitOffset>
14251       <bitWidth>2</bitWidth>
14252       <access>read-only</access>
14253      </field>
14254     </fields>
14255    </register>
14256    <register>
14257     <name>PRESET_6</name>
14258     <description>Preset Value for SDR104.</description>
14259     <addressOffset>0x06C</addressOffset>
14260     <size>16</size>
14261     <access>read-only</access>
14262     <fields>
14263      <field>
14264       <name>SDCLK_FREQ</name>
14265       <description>SDCLK Frequency Select Value.</description>
14266       <bitOffset>0</bitOffset>
14267       <bitWidth>10</bitWidth>
14268       <access>read-only</access>
14269      </field>
14270      <field>
14271       <name>CLK_GEN</name>
14272       <description>Clock Generator Select Value.</description>
14273       <bitOffset>10</bitOffset>
14274       <bitWidth>1</bitWidth>
14275       <access>read-only</access>
14276      </field>
14277      <field>
14278       <name>DRIVER_STRENGTH</name>
14279       <description>Driver Strength Select Value.</description>
14280       <bitOffset>14</bitOffset>
14281       <bitWidth>2</bitWidth>
14282       <access>read-only</access>
14283      </field>
14284     </fields>
14285    </register>
14286    <register>
14287     <name>PRESET_7</name>
14288     <description>Preset Value for DDR50.</description>
14289     <addressOffset>0x06E</addressOffset>
14290     <size>16</size>
14291     <access>read-only</access>
14292     <fields>
14293      <field>
14294       <name>SDCLK_FREQ</name>
14295       <description>SDCLK Frequency Select Value.</description>
14296       <bitOffset>0</bitOffset>
14297       <bitWidth>10</bitWidth>
14298       <access>read-only</access>
14299      </field>
14300      <field>
14301       <name>CLK_GEN</name>
14302       <description>Clock Generator Select Value.</description>
14303       <bitOffset>10</bitOffset>
14304       <bitWidth>1</bitWidth>
14305       <access>read-only</access>
14306      </field>
14307      <field>
14308       <name>DRIVER_STRENGTH</name>
14309       <description>Driver Strength Select Value.</description>
14310       <bitOffset>14</bitOffset>
14311       <bitWidth>2</bitWidth>
14312       <access>read-only</access>
14313      </field>
14314     </fields>
14315    </register>
14316    <register>
14317     <name>SHARED_BUS</name>
14318     <description>SHARED_BUS.</description>
14319     <addressOffset>0x0E0</addressOffset>
14320     <size>32</size>
14321    </register>
14322    <register>
14323     <name>SLOT_INT</name>
14324     <description>Slot Interrupt Status.</description>
14325     <addressOffset>0x0FC</addressOffset>
14326     <size>16</size>
14327     <access>read-only</access>
14328     <fields>
14329      <field>
14330       <name>INT_SIGNALS</name>
14331       <description>Interrupt Signal For Each Slot.</description>
14332       <bitOffset>0</bitOffset>
14333       <bitWidth>1</bitWidth>
14334       <access>read-only</access>
14335      </field>
14336     </fields>
14337    </register>
14338    <register>
14339     <name>HOST_CN_VER</name>
14340     <description>Host Controller Version.</description>
14341     <addressOffset>0x0FE</addressOffset>
14342     <size>16</size>
14343     <fields>
14344      <field>
14345       <name>SPEC_VER</name>
14346       <description>Specification Version Number.</description>
14347       <bitOffset>0</bitOffset>
14348       <bitWidth>8</bitWidth>
14349      </field>
14350      <field>
14351       <name>VEND_VER</name>
14352       <description>Vendor Version Number.</description>
14353       <bitOffset>8</bitOffset>
14354       <bitWidth>8</bitWidth>
14355      </field>
14356     </fields>
14357    </register>
14358   </registers>
14359  </peripheral>
14360<!--SDHC SDHC/SDIO Controller-->
14361  <peripheral>
14362   <name>SEMA</name>
14363   <description>The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources.
14364                                     The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software
14365                                     architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be
14366
14367                                     modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.</description>
14368   <baseAddress>0x4003E000</baseAddress>
14369   <addressBlock>
14370    <offset>0x00</offset>
14371    <size>0x1000</size>
14372    <usage>registers</usage>
14373   </addressBlock>
14374   <registers>
14375    <register>
14376     <dim>8</dim>
14377     <dimIncrement>4</dimIncrement>
14378     <name>SEMAPHORES[%s]</name>
14379     <description>Read to test and set, returns prior value. Write 0 to clear semaphore.</description>
14380     <addressOffset>0x00</addressOffset>
14381     <size>32</size>
14382     <fields>
14383      <field>
14384       <name>sema</name>
14385       <bitOffset>0</bitOffset>
14386       <bitWidth>1</bitWidth>
14387      </field>
14388     </fields>
14389    </register>
14390    <register>
14391     <name>irq0</name>
14392     <description>Semaphore IRQ0 register.</description>
14393     <addressOffset>0x40</addressOffset>
14394     <size>32</size>
14395     <fields>
14396      <field>
14397       <name>en</name>
14398       <bitOffset>0</bitOffset>
14399       <bitWidth>1</bitWidth>
14400      </field>
14401      <field>
14402       <name>cm4_irq</name>
14403       <bitOffset>16</bitOffset>
14404       <bitWidth>1</bitWidth>
14405      </field>
14406     </fields>
14407    </register>
14408    <register>
14409     <name>mail0</name>
14410     <description>Semaphore Mailbox 0 register.</description>
14411     <addressOffset>0x44</addressOffset>
14412     <size>32</size>
14413     <fields>
14414      <field>
14415       <name>data</name>
14416       <bitOffset>0</bitOffset>
14417       <bitWidth>32</bitWidth>
14418      </field>
14419     </fields>
14420    </register>
14421    <register>
14422     <name>irq1</name>
14423     <description>Semaphore IRQ1 register.</description>
14424     <addressOffset>0x48</addressOffset>
14425     <size>32</size>
14426     <fields>
14427      <field>
14428       <name>en</name>
14429       <bitOffset>0</bitOffset>
14430       <bitWidth>1</bitWidth>
14431      </field>
14432      <field>
14433       <name>rv32_irq</name>
14434       <bitOffset>16</bitOffset>
14435       <bitWidth>1</bitWidth>
14436      </field>
14437     </fields>
14438    </register>
14439    <register>
14440     <name>mail1</name>
14441     <description>Semaphore Mailbox 1 register.</description>
14442     <addressOffset>0x4C</addressOffset>
14443     <size>32</size>
14444     <fields>
14445      <field>
14446       <name>data</name>
14447       <bitOffset>0</bitOffset>
14448       <bitWidth>32</bitWidth>
14449      </field>
14450     </fields>
14451    </register>
14452    <register>
14453     <name>status</name>
14454     <description>Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken.</description>
14455     <addressOffset>0x100</addressOffset>
14456     <size>32</size>
14457     <fields>
14458      <field>
14459       <name>status0</name>
14460       <bitOffset>0</bitOffset>
14461       <bitWidth>1</bitWidth>
14462      </field>
14463      <field>
14464       <name>status1</name>
14465       <bitOffset>1</bitOffset>
14466       <bitWidth>1</bitWidth>
14467      </field>
14468      <field>
14469       <name>status2</name>
14470       <bitOffset>2</bitOffset>
14471       <bitWidth>1</bitWidth>
14472      </field>
14473      <field>
14474       <name>status3</name>
14475       <bitOffset>3</bitOffset>
14476       <bitWidth>1</bitWidth>
14477      </field>
14478      <field>
14479       <name>status4</name>
14480       <bitOffset>4</bitOffset>
14481       <bitWidth>1</bitWidth>
14482      </field>
14483      <field>
14484       <name>status5</name>
14485       <bitOffset>5</bitOffset>
14486       <bitWidth>1</bitWidth>
14487      </field>
14488      <field>
14489       <name>status6</name>
14490       <bitOffset>6</bitOffset>
14491       <bitWidth>1</bitWidth>
14492      </field>
14493      <field>
14494       <name>status7</name>
14495       <bitOffset>7</bitOffset>
14496       <bitWidth>1</bitWidth>
14497      </field>
14498     </fields>
14499    </register>
14500   </registers>
14501  </peripheral>
14502<!--SEMA The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources.
14503                                     The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software
14504                                     architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be
14505
14506                                     modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.-->
14507  <peripheral>
14508   <name>SIMO</name>
14509   <description>Single Inductor Multiple Output Switching Converter</description>
14510   <baseAddress>0x40004400</baseAddress>
14511   <addressBlock>
14512    <offset>0x00</offset>
14513    <size>0x400</size>
14514    <usage>registers</usage>
14515   </addressBlock>
14516   <registers>
14517    <register>
14518     <name>VREGO_A</name>
14519     <description>Buck Voltage Regulator A Control Register</description>
14520     <addressOffset>0x0004</addressOffset>
14521     <access>read-write</access>
14522     <fields>
14523      <field>
14524       <name>VSETA</name>
14525       <description>Regulator Output Voltage Setting</description>
14526       <bitOffset>0</bitOffset>
14527       <bitWidth>7</bitWidth>
14528      </field>
14529      <field>
14530       <name>RANGEA</name>
14531       <description>Regulator Output Range Set</description>
14532       <bitOffset>7</bitOffset>
14533       <bitWidth>1</bitWidth>
14534       <enumeratedValues>
14535        <enumeratedValue>
14536         <name>low</name>
14537         <description>Low output voltage range</description>
14538         <value>0</value>
14539        </enumeratedValue>
14540        <enumeratedValue>
14541         <name>high</name>
14542         <description>High output voltage range</description>
14543         <value>1</value>
14544        </enumeratedValue>
14545       </enumeratedValues>
14546      </field>
14547     </fields>
14548    </register>
14549    <register>
14550     <name>VREGO_B</name>
14551     <description>Buck Voltage Regulator B Control Register</description>
14552     <addressOffset>0x0008</addressOffset>
14553     <access>read-write</access>
14554     <fields>
14555      <field>
14556       <name>VSETB</name>
14557       <description>Regulator Output Voltage Setting</description>
14558       <bitOffset>0</bitOffset>
14559       <bitWidth>7</bitWidth>
14560      </field>
14561      <field>
14562       <name>RANGEB</name>
14563       <description>Regulator Output Range Set</description>
14564       <bitOffset>7</bitOffset>
14565       <bitWidth>1</bitWidth>
14566       <enumeratedValues>
14567        <enumeratedValue>
14568         <name>low</name>
14569         <description>Low output voltage range</description>
14570         <value>0</value>
14571        </enumeratedValue>
14572        <enumeratedValue>
14573         <name>high</name>
14574         <description>High output voltage range</description>
14575         <value>1</value>
14576        </enumeratedValue>
14577       </enumeratedValues>
14578      </field>
14579     </fields>
14580    </register>
14581    <register>
14582     <name>VREGO_C</name>
14583     <description>Buck Voltage Regulator C Control Register</description>
14584     <addressOffset>0x000C</addressOffset>
14585     <access>read-write</access>
14586     <fields>
14587      <field>
14588       <name>VSETC</name>
14589       <description>Regulator Output Voltage Setting</description>
14590       <bitOffset>0</bitOffset>
14591       <bitWidth>7</bitWidth>
14592      </field>
14593      <field>
14594       <name>RANGEC</name>
14595       <description>Regulator Output Range Set</description>
14596       <bitOffset>7</bitOffset>
14597       <bitWidth>1</bitWidth>
14598       <enumeratedValues>
14599        <enumeratedValue>
14600         <name>low</name>
14601         <description>Low output voltage range</description>
14602         <value>0</value>
14603        </enumeratedValue>
14604        <enumeratedValue>
14605         <name>high</name>
14606         <description>High output voltage range</description>
14607         <value>1</value>
14608        </enumeratedValue>
14609       </enumeratedValues>
14610      </field>
14611     </fields>
14612    </register>
14613    <register>
14614     <name>VREGO_D</name>
14615     <description>Buck Voltage Regulator D Control Register</description>
14616     <addressOffset>0x0010</addressOffset>
14617     <access>read-write</access>
14618     <fields>
14619      <field>
14620       <name>VSETD</name>
14621       <description>Regulator Output Voltage Setting</description>
14622       <bitOffset>0</bitOffset>
14623       <bitWidth>7</bitWidth>
14624      </field>
14625      <field>
14626       <name>RANGED</name>
14627       <description>Regulator Output Range Set</description>
14628       <bitOffset>7</bitOffset>
14629       <bitWidth>1</bitWidth>
14630       <enumeratedValues>
14631        <enumeratedValue>
14632         <name>low</name>
14633         <description>Low output voltage range</description>
14634         <value>0</value>
14635        </enumeratedValue>
14636        <enumeratedValue>
14637         <name>high</name>
14638         <description>High output voltage range</description>
14639         <value>1</value>
14640        </enumeratedValue>
14641       </enumeratedValues>
14642      </field>
14643     </fields>
14644    </register>
14645    <register>
14646     <name>IPKA</name>
14647     <description>High Side FET Peak Current VREGO_A/VREGO_B Register</description>
14648     <addressOffset>0x0014</addressOffset>
14649     <access>read-write</access>
14650     <fields>
14651      <field>
14652       <name>IPKSETA</name>
14653       <description>Voltage Regulator Peak Current Setting</description>
14654       <bitOffset>0</bitOffset>
14655       <bitWidth>4</bitWidth>
14656      </field>
14657      <field>
14658       <name>IPKSETB</name>
14659       <description>Voltage Regulator Peak Current Setting</description>
14660       <bitOffset>4</bitOffset>
14661       <bitWidth>4</bitWidth>
14662      </field>
14663     </fields>
14664    </register>
14665    <register>
14666     <name>IPKB</name>
14667     <description>High Side FET Peak Current VREGO_C/VREGO_D Register</description>
14668     <addressOffset>0x0018</addressOffset>
14669     <access>read-write</access>
14670     <fields>
14671      <field>
14672       <name>IPKSETC</name>
14673       <description>Voltage Regulator Peak Current Setting</description>
14674       <bitOffset>0</bitOffset>
14675       <bitWidth>4</bitWidth>
14676      </field>
14677      <field>
14678       <name>IPKSETD</name>
14679       <description>Voltage Regulator Peak Current Setting</description>
14680       <bitOffset>4</bitOffset>
14681       <bitWidth>4</bitWidth>
14682      </field>
14683     </fields>
14684    </register>
14685    <register>
14686     <name>MAXTON</name>
14687     <description>Maximum High Side FET Time On Register</description>
14688     <addressOffset>0x001C</addressOffset>
14689     <access>read-write</access>
14690     <fields>
14691      <field>
14692       <name>TONSET</name>
14693       <description>Sets the maximum on time for the high side FET, each increment represents 500ns</description>
14694       <bitOffset>0</bitOffset>
14695       <bitWidth>4</bitWidth>
14696      </field>
14697     </fields>
14698    </register>
14699    <register>
14700     <name>ILOAD_A</name>
14701     <description>Buck Cycle Count VREGO_A Register</description>
14702     <addressOffset>0x0020</addressOffset>
14703     <access>read-only</access>
14704     <fields>
14705      <field>
14706       <name>ILOADA</name>
14707       <description>Number of buck cycles that occur within the cycle clock</description>
14708       <bitOffset>0</bitOffset>
14709       <bitWidth>8</bitWidth>
14710      </field>
14711     </fields>
14712    </register>
14713    <register>
14714     <name>ILOAD_B</name>
14715     <description>Buck Cycle Count VREGO_B Register</description>
14716     <addressOffset>0x0024</addressOffset>
14717     <access>read-only</access>
14718     <fields>
14719      <field>
14720       <name>ILOADB</name>
14721       <description>Number of buck cycles that occur within the cycle clock</description>
14722       <bitOffset>0</bitOffset>
14723       <bitWidth>8</bitWidth>
14724      </field>
14725     </fields>
14726    </register>
14727    <register>
14728     <name>ILOAD_C</name>
14729     <description>Buck Cycle Count VREGO_C Register</description>
14730     <addressOffset>0x0028</addressOffset>
14731     <access>read-only</access>
14732     <fields>
14733      <field>
14734       <name>ILOADC</name>
14735       <description>Number of buck cycles that occur within the cycle clock</description>
14736       <bitOffset>0</bitOffset>
14737       <bitWidth>8</bitWidth>
14738      </field>
14739     </fields>
14740    </register>
14741    <register>
14742     <name>ILOAD_D</name>
14743     <description>Buck Cycle Count VREGO_D Register</description>
14744     <addressOffset>0x002C</addressOffset>
14745     <access>read-only</access>
14746     <fields>
14747      <field>
14748       <name>ILOADD</name>
14749       <description>Number of buck cycles that occur within the cycle clock</description>
14750       <bitOffset>0</bitOffset>
14751       <bitWidth>8</bitWidth>
14752      </field>
14753     </fields>
14754    </register>
14755    <register>
14756     <name>BUCK_ALERT_THR_A</name>
14757     <description>Buck Cycle Count Alert VERGO_A Register</description>
14758     <addressOffset>0x0030</addressOffset>
14759     <access>read-write</access>
14760     <fields>
14761      <field>
14762       <name>BUCKTHRA</name>
14763       <description>Threshold for ILOADA to generate the BUCK_ALERT</description>
14764       <bitOffset>0</bitOffset>
14765       <bitWidth>8</bitWidth>
14766      </field>
14767     </fields>
14768    </register>
14769    <register>
14770     <name>BUCK_ALERT_THR_B</name>
14771     <description>Buck Cycle Count Alert VERGO_B Register</description>
14772     <addressOffset>0x0034</addressOffset>
14773     <access>read-write</access>
14774     <fields>
14775      <field>
14776       <name>BUCKTHRB</name>
14777       <description>Threshold for ILOADB to generate the BUCK_ALERT</description>
14778       <bitOffset>0</bitOffset>
14779       <bitWidth>8</bitWidth>
14780      </field>
14781     </fields>
14782    </register>
14783    <register>
14784     <name>BUCK_ALERT_THR_C</name>
14785     <description>Buck Cycle Count Alert VERGO_C Register</description>
14786     <addressOffset>0x0038</addressOffset>
14787     <access>read-write</access>
14788     <fields>
14789      <field>
14790       <name>BUCKTHRC</name>
14791       <description>Threshold for ILOADC to generate the BUCK_ALERT</description>
14792       <bitOffset>0</bitOffset>
14793       <bitWidth>8</bitWidth>
14794      </field>
14795     </fields>
14796    </register>
14797    <register>
14798     <name>BUCK_ALERT_THR_D</name>
14799     <description>Buck Cycle Count Alert VERGO_D Register</description>
14800     <addressOffset>0x003C</addressOffset>
14801     <access>read-write</access>
14802     <fields>
14803      <field>
14804       <name>BUCKTHRD</name>
14805       <description>Threshold for ILOADD to generate the BUCK_ALERT</description>
14806       <bitOffset>0</bitOffset>
14807       <bitWidth>8</bitWidth>
14808      </field>
14809     </fields>
14810    </register>
14811    <register>
14812     <name>BUCK_OUT_READY</name>
14813     <description>Buck Regulator Output Ready Register</description>
14814     <addressOffset>0x0040</addressOffset>
14815     <access>read-only</access>
14816     <fields>
14817      <field>
14818       <name>BUCKOUTRDYA</name>
14819       <description>When set, indicates that the output voltage has reached its regulated value</description>
14820       <bitOffset>0</bitOffset>
14821       <bitWidth>1</bitWidth>
14822       <enumeratedValues>
14823        <enumeratedValue>
14824         <name>notrdy</name>
14825         <description>Output voltage not in range</description>
14826         <value>0</value>
14827        </enumeratedValue>
14828        <enumeratedValue>
14829         <name>rdy</name>
14830         <description>Output voltage in range</description>
14831         <value>1</value>
14832        </enumeratedValue>
14833       </enumeratedValues>
14834      </field>
14835      <field derivedFrom="BUCKOUTRDYA">
14836       <name>BUCKOUTRDYB</name>
14837       <description>When set, indicates that the output voltage has reached its regulated value</description>
14838       <bitOffset>1</bitOffset>
14839       <bitWidth>1</bitWidth>
14840      </field>
14841      <field derivedFrom="BUCKOUTRDYA">
14842       <name>BUCKOUTRDYC</name>
14843       <description>When set, indicates that the output voltage has reached its regulated value</description>
14844       <bitOffset>2</bitOffset>
14845       <bitWidth>1</bitWidth>
14846      </field>
14847      <field derivedFrom="BUCKOUTRDYA">
14848       <name>BUCKOUTRDYD</name>
14849       <description>When set, indicates that the output voltage has reached its regulated value</description>
14850       <bitOffset>3</bitOffset>
14851       <bitWidth>1</bitWidth>
14852      </field>
14853     </fields>
14854    </register>
14855    <register>
14856     <name>ZERO_CROSS_CAL_A</name>
14857     <description>Zero Cross Calibration VERGO_A Register</description>
14858     <addressOffset>0x0044</addressOffset>
14859     <access>read-only</access>
14860     <fields>
14861      <field>
14862       <name>ZXCALA</name>
14863       <description>Zero Cross Calibrartion Value VREGO_A</description>
14864       <bitOffset>0</bitOffset>
14865       <bitWidth>4</bitWidth>
14866      </field>
14867     </fields>
14868    </register>
14869    <register>
14870     <name>ZERO_CROSS_CAL_B</name>
14871     <description>Zero Cross Calibration VERGO_B Register</description>
14872     <addressOffset>0x0048</addressOffset>
14873     <access>read-only</access>
14874     <fields>
14875      <field>
14876       <name>ZXCALB</name>
14877       <description>Zero Cross Calibrartion Value VREGO_B</description>
14878       <bitOffset>0</bitOffset>
14879       <bitWidth>4</bitWidth>
14880      </field>
14881     </fields>
14882    </register>
14883    <register>
14884     <name>ZERO_CROSS_CAL_C</name>
14885     <description>Zero Cross Calibration VERGO_C Register</description>
14886     <addressOffset>0x004C</addressOffset>
14887     <access>read-only</access>
14888     <fields>
14889      <field>
14890       <name>ZXCALC</name>
14891       <description>Zero Cross Calibrartion Value VREGO_C</description>
14892       <bitOffset>0</bitOffset>
14893       <bitWidth>4</bitWidth>
14894      </field>
14895     </fields>
14896    </register>
14897    <register>
14898     <name>ZERO_CROSS_CAL_D</name>
14899     <description>Zero Cross Calibration VERGO_D Register</description>
14900     <addressOffset>0x0050</addressOffset>
14901     <access>read-only</access>
14902     <fields>
14903      <field>
14904       <name>ZXCALD</name>
14905       <description>Zero Cross Calibrartion Value VREGO_D</description>
14906       <bitOffset>0</bitOffset>
14907       <bitWidth>4</bitWidth>
14908      </field>
14909     </fields>
14910    </register>
14911   </registers>
14912  </peripheral>
14913<!--SIMO Single Inductor Multiple Output Switching Converter-->
14914  <peripheral>
14915   <name>SIR</name>
14916   <description>System Initialization Registers.</description>
14917   <baseAddress>0x40000400</baseAddress>
14918   <access>read-only</access>
14919   <addressBlock>
14920    <offset>0x00</offset>
14921    <size>0x400</size>
14922    <usage>registers</usage>
14923   </addressBlock>
14924   <registers>
14925    <register>
14926     <name>SISTAT</name>
14927     <description>System Initialization Status Register.</description>
14928     <addressOffset>0x00</addressOffset>
14929     <access>read-only</access>
14930     <fields>
14931      <field>
14932       <name>MAGIC</name>
14933       <description>Magic Word Validation.  This bit is set by the system initialization block following power-up.</description>
14934       <bitOffset>0</bitOffset>
14935       <bitWidth>1</bitWidth>
14936       <access>read-only</access>
14937       <enumeratedValues>
14938        <usage>read</usage>
14939        <enumeratedValue>
14940         <name>magicNotSet</name>
14941         <description>Magic word was not set (OTP has not been initialized properly).</description>
14942         <value>0</value>
14943        </enumeratedValue>
14944        <enumeratedValue>
14945         <name>magicSet</name>
14946         <description>Magic word was set (OTP contains valid settings).</description>
14947         <value>1</value>
14948        </enumeratedValue>
14949       </enumeratedValues>
14950      </field>
14951      <field>
14952       <name>CRCERR</name>
14953       <description>CRC Error Status.  This bit is set by the system initialization block following power-up.</description>
14954       <bitOffset>1</bitOffset>
14955       <bitWidth>1</bitWidth>
14956       <access>read-only</access>
14957       <enumeratedValues>
14958        <usage>read</usage>
14959        <enumeratedValue>
14960         <name>noError</name>
14961         <description>No CRC errors occurred during the read of the OTP memory block.</description>
14962         <value>0</value>
14963        </enumeratedValue>
14964        <enumeratedValue>
14965         <name>error</name>
14966         <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description>
14967         <value>1</value>
14968        </enumeratedValue>
14969       </enumeratedValues>
14970      </field>
14971     </fields>
14972    </register>
14973    <register>
14974     <name>SIADDR</name>
14975     <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description>
14976     <addressOffset>0x04</addressOffset>
14977     <access>read-only</access>
14978     <fields>
14979      <field>
14980       <name>ERRADDR</name>
14981       <bitOffset>0</bitOffset>
14982       <bitWidth>32</bitWidth>
14983      </field>
14984     </fields>
14985    </register>
14986    <register>
14987     <name>FSTAT</name>
14988     <description>funcstat register.</description>
14989     <addressOffset>0x100</addressOffset>
14990     <access>read-only</access>
14991     <fields>
14992      <field>
14993       <name>FPU</name>
14994       <description>FPU Function.</description>
14995       <bitOffset>0</bitOffset>
14996       <bitWidth>1</bitWidth>
14997       <enumeratedValues>
14998        <enumeratedValue>
14999         <name>no</name>
15000         <value>0</value>
15001        </enumeratedValue>
15002        <enumeratedValue>
15003         <name>yes</name>
15004         <value>1</value>
15005        </enumeratedValue>
15006       </enumeratedValues>
15007      </field>
15008      <field>
15009       <name>USB</name>
15010       <description>USB Function.</description>
15011       <bitOffset>1</bitOffset>
15012       <bitWidth>1</bitWidth>
15013       <enumeratedValues>
15014        <enumeratedValue>
15015         <name>no</name>
15016         <value>0</value>
15017        </enumeratedValue>
15018        <enumeratedValue>
15019         <name>yes</name>
15020         <value>1</value>
15021        </enumeratedValue>
15022       </enumeratedValues>
15023      </field>
15024      <field>
15025       <name>ADC</name>
15026       <description>ADC Function.</description>
15027       <bitOffset>2</bitOffset>
15028       <bitWidth>1</bitWidth>
15029       <enumeratedValues>
15030        <enumeratedValue>
15031         <name>no</name>
15032         <value>0</value>
15033        </enumeratedValue>
15034        <enumeratedValue>
15035         <name>yes</name>
15036         <value>1</value>
15037        </enumeratedValue>
15038       </enumeratedValues>
15039      </field>
15040      <field>
15041       <name>SDIO</name>
15042       <description>SDIO Function.</description>
15043       <bitOffset>6</bitOffset>
15044       <bitWidth>1</bitWidth>
15045       <enumeratedValues>
15046        <enumeratedValue>
15047         <name>no</name>
15048         <value>0</value>
15049        </enumeratedValue>
15050        <enumeratedValue>
15051         <name>yes</name>
15052         <value>1</value>
15053        </enumeratedValue>
15054       </enumeratedValues>
15055      </field>
15056      <field>
15057       <name>SMPHR</name>
15058       <description>SMPHR function.</description>
15059       <bitOffset>7</bitOffset>
15060       <bitWidth>1</bitWidth>
15061       <enumeratedValues>
15062        <enumeratedValue>
15063         <name>no</name>
15064         <value>0</value>
15065        </enumeratedValue>
15066        <enumeratedValue>
15067         <name>yes</name>
15068         <value>1</value>
15069        </enumeratedValue>
15070       </enumeratedValues>
15071      </field>
15072     </fields>
15073    </register>
15074    <register>
15075     <name>SFSTAT</name>
15076     <description>Security function status register.</description>
15077     <addressOffset>0x104</addressOffset>
15078     <access>read-only</access>
15079     <fields>
15080      <field>
15081       <name>TRNG</name>
15082       <description> TRNG Function.</description>
15083       <bitOffset>2</bitOffset>
15084       <bitWidth>1</bitWidth>
15085       <enumeratedValues>
15086        <enumeratedValue>
15087         <name>no</name>
15088         <value>0</value>
15089        </enumeratedValue>
15090        <enumeratedValue>
15091         <name>yes</name>
15092         <value>1</value>
15093        </enumeratedValue>
15094       </enumeratedValues>
15095      </field>
15096      <field>
15097       <name>AES</name>
15098       <description>AES Block.</description>
15099       <bitOffset>3</bitOffset>
15100       <bitWidth>1</bitWidth>
15101       <enumeratedValues>
15102        <enumeratedValue>
15103         <name>no</name>
15104         <value>0</value>
15105        </enumeratedValue>
15106        <enumeratedValue>
15107         <name>yes</name>
15108         <value>1</value>
15109        </enumeratedValue>
15110       </enumeratedValues>
15111      </field>
15112     </fields>
15113    </register>
15114   </registers>
15115  </peripheral>
15116<!--SIR System Initialization Registers.-->
15117  <peripheral>
15118   <name>SPI0</name>
15119   <description>SPI peripheral.</description>
15120   <baseAddress>0x400BE000</baseAddress>
15121   <addressBlock>
15122    <offset>0x00</offset>
15123    <size>0x1000</size>
15124    <usage>registers</usage>
15125   </addressBlock>
15126   <interrupt>
15127    <name>SPI0</name>
15128    <value>56</value>
15129   </interrupt>
15130   <registers>
15131    <register>
15132     <name>FIFO32</name>
15133     <description>Register for reading and writing the FIFO.</description>
15134     <addressOffset>0x00</addressOffset>
15135     <size>32</size>
15136     <access>read-write</access>
15137     <fields>
15138      <field>
15139       <name>DATA</name>
15140       <description>Read to pull from RX FIFO, write to put into TX FIFO.</description>
15141       <bitOffset>0</bitOffset>
15142       <bitWidth>32</bitWidth>
15143      </field>
15144     </fields>
15145    </register>
15146    <register>
15147     <dim>2</dim>
15148     <dimIncrement>2</dimIncrement>
15149     <name>FIFO16[%s]</name>
15150     <description>Register for reading and writing the FIFO.</description>
15151     <addressOffset>0x00</addressOffset>
15152     <size>16</size>
15153     <access>read-write</access>
15154     <fields>
15155      <field>
15156       <name>DATA</name>
15157       <description>Read to pull from RX FIFO, write to put into TX FIFO.</description>
15158       <bitOffset>0</bitOffset>
15159       <bitWidth>16</bitWidth>
15160      </field>
15161     </fields>
15162    </register>
15163    <register>
15164     <dim>4</dim>
15165     <dimIncrement>1</dimIncrement>
15166     <name>FIFO8[%s]</name>
15167     <description>Register for reading and writing the FIFO.</description>
15168     <addressOffset>0x00</addressOffset>
15169     <size>8</size>
15170     <access>read-write</access>
15171     <fields>
15172      <field>
15173       <name>DATA</name>
15174       <description>Read to pull from RX FIFO, write to put into TX FIFO.</description>
15175       <bitOffset>0</bitOffset>
15176       <bitWidth>8</bitWidth>
15177      </field>
15178     </fields>
15179    </register>
15180    <register>
15181     <name>CTRL0</name>
15182     <description>Register for controlling SPI peripheral.</description>
15183     <addressOffset>0x04</addressOffset>
15184     <access>read-write</access>
15185     <fields>
15186      <field>
15187       <name>EN</name>
15188       <description>SPI Enable.</description>
15189       <bitOffset>0</bitOffset>
15190       <bitWidth>1</bitWidth>
15191       <enumeratedValues>
15192        <enumeratedValue>
15193         <name>dis</name>
15194         <description>SPI is disabled.</description>
15195         <value>0</value>
15196        </enumeratedValue>
15197        <enumeratedValue>
15198         <name>en</name>
15199         <description>SPI is enabled.</description>
15200         <value>1</value>
15201        </enumeratedValue>
15202       </enumeratedValues>
15203      </field>
15204      <field>
15205       <name>MST_MODE</name>
15206       <description>Master Mode Enable.</description>
15207       <bitOffset>1</bitOffset>
15208       <bitWidth>1</bitWidth>
15209       <enumeratedValues>
15210        <enumeratedValue>
15211         <name>dis</name>
15212         <description>SPI is Slave mode.</description>
15213         <value>0</value>
15214        </enumeratedValue>
15215        <enumeratedValue>
15216         <name>en</name>
15217         <description>SPI is  Master mode.</description>
15218         <value>1</value>
15219        </enumeratedValue>
15220       </enumeratedValues>
15221      </field>
15222      <field>
15223       <name>SS_IO</name>
15224       <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description>
15225       <bitOffset>4</bitOffset>
15226       <bitWidth>1</bitWidth>
15227       <enumeratedValues>
15228        <enumeratedValue>
15229         <name>output</name>
15230         <description>Slave select 0 is output.</description>
15231         <value>0</value>
15232        </enumeratedValue>
15233        <enumeratedValue>
15234         <name>input</name>
15235         <description>Slave Select 0 is input, only valid if MMEN=1.</description>
15236         <value>1</value>
15237        </enumeratedValue>
15238       </enumeratedValues>
15239      </field>
15240      <field>
15241       <name>START</name>
15242       <description>Start Transmit.</description>
15243       <bitOffset>5</bitOffset>
15244       <bitWidth>1</bitWidth>
15245       <enumeratedValues>
15246        <enumeratedValue>
15247         <name>start</name>
15248         <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description>
15249         <value>1</value>
15250        </enumeratedValue>
15251       </enumeratedValues>
15252      </field>
15253      <field>
15254       <name>SS_CTRL</name>
15255       <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description>
15256       <bitOffset>8</bitOffset>
15257       <bitWidth>1</bitWidth>
15258       <enumeratedValues>
15259        <enumeratedValue>
15260         <name>DEASSERT</name>
15261         <description>SPI De-asserts Slave Select at the end of a transaction.</description>
15262         <value>0</value>
15263        </enumeratedValue>
15264        <enumeratedValue>
15265         <name>ASSERT</name>
15266         <description>SPI leaves Slave Select asserted at the end of a transaction.</description>
15267         <value>1</value>
15268        </enumeratedValue>
15269       </enumeratedValues>
15270      </field>
15271      <field>
15272       <name>SS_ACTIVE</name>
15273       <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description>
15274       <bitOffset>16</bitOffset>
15275       <bitWidth>4</bitWidth>
15276       <enumeratedValues>
15277        <enumeratedValue>
15278         <name>SS0</name>
15279         <description>SS0 is selected.</description>
15280         <value>0x1</value>
15281        </enumeratedValue>
15282        <enumeratedValue>
15283         <name>SS1</name>
15284         <description>SS1 is selected.</description>
15285         <value>0x2</value>
15286        </enumeratedValue>
15287        <enumeratedValue>
15288         <name>SS2</name>
15289         <description>SS2 is selected.</description>
15290         <value>0x4</value>
15291        </enumeratedValue>
15292        <enumeratedValue>
15293         <name>SS3</name>
15294         <description>SS3 is selected.</description>
15295         <value>0x8</value>
15296        </enumeratedValue>
15297       </enumeratedValues>
15298      </field>
15299     </fields>
15300    </register>
15301    <register>
15302     <name>CTRL1</name>
15303     <description>Register for controlling SPI peripheral.</description>
15304     <addressOffset>0x08</addressOffset>
15305     <access>read-write</access>
15306     <fields>
15307      <field>
15308       <name>TX_NUM_CHAR</name>
15309       <description>Nubmer of Characters to transmit.</description>
15310       <bitOffset>0</bitOffset>
15311       <bitWidth>16</bitWidth>
15312      </field>
15313      <field>
15314       <name>RX_NUM_CHAR</name>
15315       <description>Nubmer of Characters to receive.</description>
15316       <bitOffset>16</bitOffset>
15317       <bitWidth>16</bitWidth>
15318      </field>
15319     </fields>
15320    </register>
15321    <register>
15322     <name>CTRL2</name>
15323     <description>Register for controlling SPI peripheral.</description>
15324     <addressOffset>0x0C</addressOffset>
15325     <access>read-write</access>
15326     <fields>
15327      <field>
15328       <name>CLKPHA</name>
15329       <description>Clock Phase.</description>
15330       <bitOffset>0</bitOffset>
15331       <bitWidth>1</bitWidth>
15332       <enumeratedValues>
15333        <enumeratedValue>
15334         <name>Rising_Edge</name>
15335         <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description>
15336         <value>0</value>
15337        </enumeratedValue>
15338        <enumeratedValue>
15339         <name>Falling_Edge</name>
15340         <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description>
15341         <value>1</value>
15342        </enumeratedValue>
15343       </enumeratedValues>
15344      </field>
15345      <field>
15346       <name>CLKPOL</name>
15347       <description>Clock Polarity.</description>
15348       <bitOffset>1</bitOffset>
15349       <bitWidth>1</bitWidth>
15350       <enumeratedValues>
15351        <enumeratedValue>
15352         <name>Normal</name>
15353         <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description>
15354         <value>0</value>
15355        </enumeratedValue>
15356        <enumeratedValue>
15357         <name>Inverted</name>
15358         <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description>
15359         <value>1</value>
15360        </enumeratedValue>
15361       </enumeratedValues>
15362      </field>
15363      <field>
15364       <name>SCLK_FB_INV</name>
15365       <description>SCLK_FB_INV.</description>
15366       <bitOffset>4</bitOffset>
15367       <bitWidth>1</bitWidth>
15368      </field>
15369      <field>
15370       <name>NUMBITS</name>
15371       <description>Number of Bits per character.</description>
15372       <bitOffset>8</bitOffset>
15373       <bitWidth>4</bitWidth>
15374       <enumeratedValues>
15375        <enumeratedValue>
15376         <name>0</name>
15377         <description>16 bits per character.</description>
15378         <value>0</value>
15379        </enumeratedValue>
15380       </enumeratedValues>
15381      </field>
15382      <field>
15383       <name>DATA_WIDTH</name>
15384       <description>SPI Data width.</description>
15385       <bitOffset>12</bitOffset>
15386       <bitWidth>2</bitWidth>
15387       <enumeratedValues>
15388        <enumeratedValue>
15389         <name>Mono</name>
15390         <description>1 data pin.</description>
15391         <value>0</value>
15392        </enumeratedValue>
15393        <enumeratedValue>
15394         <name>Dual</name>
15395         <description>2 data pins.</description>
15396         <value>1</value>
15397        </enumeratedValue>
15398        <enumeratedValue>
15399         <name>Quad</name>
15400         <description>4 data pins.</description>
15401         <value>2</value>
15402        </enumeratedValue>
15403       </enumeratedValues>
15404      </field>
15405      <field>
15406       <name>THREE_WIRE</name>
15407       <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description>
15408       <bitOffset>15</bitOffset>
15409       <bitWidth>1</bitWidth>
15410       <enumeratedValues>
15411        <enumeratedValue>
15412         <name>dis</name>
15413         <description>Use four wire mode (Mono only).</description>
15414         <value>0</value>
15415        </enumeratedValue>
15416        <enumeratedValue>
15417         <name>en</name>
15418         <description>Use three wire mode.</description>
15419         <value>1</value>
15420        </enumeratedValue>
15421       </enumeratedValues>
15422      </field>
15423      <field>
15424       <name>SS_POL</name>
15425       <description>Slave Select Polarity, each Slave Select can have unique polarity.</description>
15426       <bitOffset>16</bitOffset>
15427       <bitWidth>8</bitWidth>
15428       <enumeratedValues>
15429        <enumeratedValue>
15430         <name>SS0_high</name>
15431         <description>SS0 active high.</description>
15432         <value>0x1</value>
15433        </enumeratedValue>
15434        <enumeratedValue>
15435         <name>SS1_high</name>
15436         <description>SS1 active high.</description>
15437         <value>0x2</value>
15438        </enumeratedValue>
15439        <enumeratedValue>
15440         <name>SS2_high</name>
15441         <description>SS2 active high.</description>
15442         <value>0x4</value>
15443        </enumeratedValue>
15444        <enumeratedValue>
15445         <name>SS3_high</name>
15446         <description>SS3 active high.</description>
15447         <value>0x8</value>
15448        </enumeratedValue>
15449       </enumeratedValues>
15450      </field>
15451     </fields>
15452    </register>
15453    <register>
15454     <name>SSTIME</name>
15455     <description>Register for controlling SPI peripheral/Slave Select Timing.</description>
15456     <addressOffset>0x10</addressOffset>
15457     <access>read-write</access>
15458     <fields>
15459      <field>
15460       <name>PRE</name>
15461       <description>Slave Select Pre delay 1.</description>
15462       <bitOffset>0</bitOffset>
15463       <bitWidth>8</bitWidth>
15464       <enumeratedValues>
15465        <enumeratedValue>
15466         <name>256</name>
15467         <description>256 system clocks between SS active and first serial clock edge.</description>
15468         <value>0</value>
15469        </enumeratedValue>
15470       </enumeratedValues>
15471      </field>
15472      <field>
15473       <name>POST</name>
15474       <description>Slave Select Post delay 2.</description>
15475       <bitOffset>8</bitOffset>
15476       <bitWidth>8</bitWidth>
15477       <enumeratedValues>
15478        <enumeratedValue>
15479         <name>256</name>
15480         <description>256 system clocks between last serial clock edge and SS inactive.</description>
15481         <value>0</value>
15482        </enumeratedValue>
15483       </enumeratedValues>
15484      </field>
15485      <field>
15486       <name>INACT</name>
15487       <description>Slave Select Inactive delay.</description>
15488       <bitOffset>16</bitOffset>
15489       <bitWidth>8</bitWidth>
15490       <enumeratedValues>
15491        <enumeratedValue>
15492         <name>256</name>
15493         <description>256 system clocks between transactions.</description>
15494         <value>0</value>
15495        </enumeratedValue>
15496       </enumeratedValues>
15497      </field>
15498     </fields>
15499    </register>
15500    <register>
15501     <name>CLKCTRL</name>
15502     <description>Register for controlling SPI clock rate.</description>
15503     <addressOffset>0x14</addressOffset>
15504     <access>read-write</access>
15505     <fields>
15506      <field>
15507       <name>LO</name>
15508       <description>Low duty cycle control. In timer mode, reload[7:0].</description>
15509       <bitOffset>0</bitOffset>
15510       <bitWidth>8</bitWidth>
15511       <enumeratedValues>
15512        <enumeratedValue>
15513         <name>Dis</name>
15514         <description>Duty cycle control of serial clock generation is disabled.</description>
15515         <value>0</value>
15516        </enumeratedValue>
15517       </enumeratedValues>
15518      </field>
15519      <field>
15520       <name>HI</name>
15521       <description>High duty cycle control. In timer mode, reload[15:8].</description>
15522       <bitOffset>8</bitOffset>
15523       <bitWidth>8</bitWidth>
15524       <enumeratedValues>
15525        <enumeratedValue>
15526         <name>Dis</name>
15527         <description>Duty cycle control of serial clock generation is disabled.</description>
15528         <value>0</value>
15529        </enumeratedValue>
15530       </enumeratedValues>
15531      </field>
15532      <field>
15533       <name>CLKDIV</name>
15534       <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description>
15535       <bitOffset>16</bitOffset>
15536       <bitWidth>4</bitWidth>
15537      </field>
15538      <field>
15539       <name>AFP_FCD</name>
15540       <description>Automatic frequency prescalar.</description>
15541       <bitOffset>24</bitOffset>
15542       <bitWidth>3</bitWidth>
15543      </field>
15544     </fields>
15545    </register>
15546    <register>
15547     <name>DMA</name>
15548     <description>Register for controlling DMA.</description>
15549     <addressOffset>0x1C</addressOffset>
15550     <access>read-write</access>
15551     <fields>
15552      <field>
15553       <name>TX_THD_VAL</name>
15554       <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description>
15555       <bitOffset>0</bitOffset>
15556       <bitWidth>5</bitWidth>
15557      </field>
15558      <field>
15559       <name>TX_FIFO_EN</name>
15560       <description>Transmit FIFO enabled for SPI transactions.</description>
15561       <bitOffset>6</bitOffset>
15562       <bitWidth>1</bitWidth>
15563       <enumeratedValues>
15564        <enumeratedValue>
15565         <name>dis</name>
15566         <description>Transmit FIFO is not enabled.</description>
15567         <value>0</value>
15568        </enumeratedValue>
15569        <enumeratedValue>
15570         <name>en</name>
15571         <description>Transmit FIFO is enabled.</description>
15572         <value>1</value>
15573        </enumeratedValue>
15574       </enumeratedValues>
15575      </field>
15576      <field>
15577       <name>TX_FLUSH</name>
15578       <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description>
15579       <bitOffset>7</bitOffset>
15580       <bitWidth>1</bitWidth>
15581       <enumeratedValues>
15582        <enumeratedValue>
15583         <name>CLEAR</name>
15584         <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description>
15585         <value>1</value>
15586        </enumeratedValue>
15587       </enumeratedValues>
15588      </field>
15589      <field>
15590       <name>TX_LVL</name>
15591       <description>Count of entries in TX FIFO.</description>
15592       <bitOffset>8</bitOffset>
15593       <bitWidth>6</bitWidth>
15594       <access>read-only</access>
15595      </field>
15596      <field>
15597       <name>DMA_TX_EN</name>
15598       <description>TX DMA Enable.</description>
15599       <bitOffset>15</bitOffset>
15600       <bitWidth>1</bitWidth>
15601       <enumeratedValues>
15602        <enumeratedValue>
15603         <name>DIS</name>
15604         <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description>
15605         <value>0</value>
15606        </enumeratedValue>
15607        <enumeratedValue>
15608         <name>en</name>
15609         <description>TX DMA requests are enabled.</description>
15610         <value>1</value>
15611        </enumeratedValue>
15612       </enumeratedValues>
15613      </field>
15614      <field>
15615       <name>RX_THD_VAL</name>
15616       <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description>
15617       <bitOffset>16</bitOffset>
15618       <bitWidth>5</bitWidth>
15619      </field>
15620      <field>
15621       <name>RX_FIFO_EN</name>
15622       <description>Receive FIFO enabled for SPI transactions.</description>
15623       <bitOffset>22</bitOffset>
15624       <bitWidth>1</bitWidth>
15625       <enumeratedValues>
15626        <enumeratedValue>
15627         <name>DIS</name>
15628         <description>Receive FIFO is not enabled.</description>
15629         <value>0</value>
15630        </enumeratedValue>
15631        <enumeratedValue>
15632         <name>en</name>
15633         <description>Receive FIFO is enabled.</description>
15634         <value>1</value>
15635        </enumeratedValue>
15636       </enumeratedValues>
15637      </field>
15638      <field>
15639       <name>RX_FLUSH</name>
15640       <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description>
15641       <bitOffset>23</bitOffset>
15642       <bitWidth>1</bitWidth>
15643       <enumeratedValues>
15644        <enumeratedValue>
15645         <name>CLEAR</name>
15646         <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description>
15647         <value>1</value>
15648        </enumeratedValue>
15649       </enumeratedValues>
15650      </field>
15651      <field>
15652       <name>RX_LVL</name>
15653       <description>Count of entries in RX FIFO.</description>
15654       <bitOffset>24</bitOffset>
15655       <bitWidth>6</bitWidth>
15656       <access>read-only</access>
15657      </field>
15658      <field>
15659       <name>DMA_RX_EN</name>
15660       <description>RX DMA Enable.</description>
15661       <bitOffset>31</bitOffset>
15662       <bitWidth>1</bitWidth>
15663       <enumeratedValues>
15664        <enumeratedValue>
15665         <name>dis</name>
15666         <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description>
15667         <value>0</value>
15668        </enumeratedValue>
15669        <enumeratedValue>
15670         <name>en</name>
15671         <description>RX DMA requests are enabled.</description>
15672         <value>1</value>
15673        </enumeratedValue>
15674       </enumeratedValues>
15675      </field>
15676     </fields>
15677    </register>
15678    <register>
15679     <name>INTFL</name>
15680     <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description>
15681     <addressOffset>0x20</addressOffset>
15682     <access>read-write</access>
15683     <fields>
15684      <field>
15685       <name>TX_THD</name>
15686       <description>TX FIFO Threshold Crossed.</description>
15687       <bitOffset>0</bitOffset>
15688       <bitWidth>1</bitWidth>
15689       <enumeratedValues>
15690        <enumeratedValue>
15691         <name>clear</name>
15692         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15693         <value>1</value>
15694        </enumeratedValue>
15695       </enumeratedValues>
15696      </field>
15697      <field>
15698       <name>TX_EM</name>
15699       <description>TX FIFO Empty.</description>
15700       <bitOffset>1</bitOffset>
15701       <bitWidth>1</bitWidth>
15702       <enumeratedValues>
15703        <enumeratedValue>
15704         <name>clear</name>
15705         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15706         <value>1</value>
15707        </enumeratedValue>
15708       </enumeratedValues>
15709      </field>
15710      <field>
15711       <name>RX_THD</name>
15712       <description>RX FIFO Threshold Crossed.</description>
15713       <bitOffset>2</bitOffset>
15714       <bitWidth>1</bitWidth>
15715       <enumeratedValues>
15716        <enumeratedValue>
15717         <name>clear</name>
15718         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15719         <value>1</value>
15720        </enumeratedValue>
15721       </enumeratedValues>
15722      </field>
15723      <field>
15724       <name>RX_FULL</name>
15725       <description>RX FIFO FULL.</description>
15726       <bitOffset>3</bitOffset>
15727       <bitWidth>1</bitWidth>
15728       <enumeratedValues>
15729        <enumeratedValue>
15730         <name>clear</name>
15731         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15732         <value>1</value>
15733        </enumeratedValue>
15734       </enumeratedValues>
15735      </field>
15736      <field>
15737       <name>SSA</name>
15738       <description>Slave Select Asserted.</description>
15739       <bitOffset>4</bitOffset>
15740       <bitWidth>1</bitWidth>
15741       <enumeratedValues>
15742        <enumeratedValue>
15743         <name>clear</name>
15744         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15745         <value>1</value>
15746        </enumeratedValue>
15747       </enumeratedValues>
15748      </field>
15749      <field>
15750       <name>SSD</name>
15751       <description>Slave Select Deasserted.</description>
15752       <bitOffset>5</bitOffset>
15753       <bitWidth>1</bitWidth>
15754       <enumeratedValues>
15755        <enumeratedValue>
15756         <name>clear</name>
15757         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15758         <value>1</value>
15759        </enumeratedValue>
15760       </enumeratedValues>
15761      </field>
15762      <field>
15763       <name>FAULT</name>
15764       <description>Multi-Master Mode Fault.</description>
15765       <bitOffset>8</bitOffset>
15766       <bitWidth>1</bitWidth>
15767       <enumeratedValues>
15768        <enumeratedValue>
15769         <name>clear</name>
15770         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15771         <value>1</value>
15772        </enumeratedValue>
15773       </enumeratedValues>
15774      </field>
15775      <field>
15776       <name>ABORT</name>
15777       <description>Slave Abort Detected.</description>
15778       <bitOffset>9</bitOffset>
15779       <bitWidth>1</bitWidth>
15780       <enumeratedValues>
15781        <enumeratedValue>
15782         <name>clear</name>
15783         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15784         <value>1</value>
15785        </enumeratedValue>
15786       </enumeratedValues>
15787      </field>
15788      <field>
15789       <name>MST_DONE</name>
15790       <description>Master Done, set when SPI Master has completed any transactions.</description>
15791       <bitOffset>11</bitOffset>
15792       <bitWidth>1</bitWidth>
15793       <enumeratedValues>
15794        <enumeratedValue>
15795         <name>clear</name>
15796         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15797         <value>1</value>
15798        </enumeratedValue>
15799       </enumeratedValues>
15800      </field>
15801      <field>
15802       <name>TX_OV</name>
15803       <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description>
15804       <bitOffset>12</bitOffset>
15805       <bitWidth>1</bitWidth>
15806       <enumeratedValues>
15807        <enumeratedValue>
15808         <name>clear</name>
15809         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15810         <value>1</value>
15811        </enumeratedValue>
15812       </enumeratedValues>
15813      </field>
15814      <field>
15815       <name>TX_UN</name>
15816       <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description>
15817       <bitOffset>13</bitOffset>
15818       <bitWidth>1</bitWidth>
15819       <enumeratedValues>
15820        <enumeratedValue>
15821         <name>clear</name>
15822         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15823         <value>1</value>
15824        </enumeratedValue>
15825       </enumeratedValues>
15826      </field>
15827      <field>
15828       <name>RX_OV</name>
15829       <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description>
15830       <bitOffset>14</bitOffset>
15831       <bitWidth>1</bitWidth>
15832       <enumeratedValues>
15833        <enumeratedValue>
15834         <name>clear</name>
15835         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15836         <value>1</value>
15837        </enumeratedValue>
15838       </enumeratedValues>
15839      </field>
15840      <field>
15841       <name>RX_UN</name>
15842       <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description>
15843       <bitOffset>15</bitOffset>
15844       <bitWidth>1</bitWidth>
15845       <enumeratedValues>
15846        <enumeratedValue>
15847         <name>clear</name>
15848         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
15849         <value>1</value>
15850        </enumeratedValue>
15851       </enumeratedValues>
15852      </field>
15853     </fields>
15854    </register>
15855    <register>
15856     <name>INTEN</name>
15857     <description>Register for enabling interrupts.</description>
15858     <addressOffset>0x24</addressOffset>
15859     <access>read-write</access>
15860     <fields>
15861      <field>
15862       <name>TX_THD</name>
15863       <description>TX FIFO Threshold interrupt enable.</description>
15864       <bitOffset>0</bitOffset>
15865       <bitWidth>1</bitWidth>
15866       <enumeratedValues>
15867        <enumeratedValue>
15868         <name>dis</name>
15869         <description>Interrupt is disabled.</description>
15870         <value>0</value>
15871        </enumeratedValue>
15872        <enumeratedValue>
15873         <name>en</name>
15874         <description>Interrupt is enabled.</description>
15875         <value>1</value>
15876        </enumeratedValue>
15877       </enumeratedValues>
15878      </field>
15879      <field>
15880       <name>TX_EM</name>
15881       <description>TX FIFO Empty interrupt enable.</description>
15882       <bitOffset>1</bitOffset>
15883       <bitWidth>1</bitWidth>
15884       <enumeratedValues>
15885        <enumeratedValue>
15886         <name>dis</name>
15887         <description>Interrupt is disabled.</description>
15888         <value>0</value>
15889        </enumeratedValue>
15890        <enumeratedValue>
15891         <name>en</name>
15892         <description>Interrupt is enabled.</description>
15893         <value>1</value>
15894        </enumeratedValue>
15895       </enumeratedValues>
15896      </field>
15897      <field>
15898       <name>RX_THD</name>
15899       <description>RX FIFO Threshold Crossed interrupt enable.</description>
15900       <bitOffset>2</bitOffset>
15901       <bitWidth>1</bitWidth>
15902       <enumeratedValues>
15903        <enumeratedValue>
15904         <name>dis</name>
15905         <description>Interrupt is disabled.</description>
15906         <value>0</value>
15907        </enumeratedValue>
15908        <enumeratedValue>
15909         <name>en</name>
15910         <description>Interrupt is enabled.</description>
15911         <value>1</value>
15912        </enumeratedValue>
15913       </enumeratedValues>
15914      </field>
15915      <field>
15916       <name>RX_FULL</name>
15917       <description>RX FIFO FULL interrupt enable.</description>
15918       <bitOffset>3</bitOffset>
15919       <bitWidth>1</bitWidth>
15920       <enumeratedValues>
15921        <enumeratedValue>
15922         <name>dis</name>
15923         <description>Interrupt is disabled.</description>
15924         <value>0</value>
15925        </enumeratedValue>
15926        <enumeratedValue>
15927         <name>en</name>
15928         <description>Interrupt is enabled.</description>
15929         <value>1</value>
15930        </enumeratedValue>
15931       </enumeratedValues>
15932      </field>
15933      <field>
15934       <name>SSA</name>
15935       <description>Slave Select Asserted interrupt enable.</description>
15936       <bitOffset>4</bitOffset>
15937       <bitWidth>1</bitWidth>
15938       <enumeratedValues>
15939        <enumeratedValue>
15940         <name>dis</name>
15941         <description>Interrupt is disabled.</description>
15942         <value>0</value>
15943        </enumeratedValue>
15944        <enumeratedValue>
15945         <name>en</name>
15946         <description>Interrupt is enabled.</description>
15947         <value>1</value>
15948        </enumeratedValue>
15949       </enumeratedValues>
15950      </field>
15951      <field>
15952       <name>SSD</name>
15953       <description>Slave Select Deasserted interrupt enable.</description>
15954       <bitOffset>5</bitOffset>
15955       <bitWidth>1</bitWidth>
15956       <enumeratedValues>
15957        <enumeratedValue>
15958         <name>dis</name>
15959         <description>Interrupt is disabled.</description>
15960         <value>0</value>
15961        </enumeratedValue>
15962        <enumeratedValue>
15963         <name>en</name>
15964         <description>Interrupt is enabled.</description>
15965         <value>1</value>
15966        </enumeratedValue>
15967       </enumeratedValues>
15968      </field>
15969      <field>
15970       <name>FAULT</name>
15971       <description>Multi-Master Mode Fault interrupt enable.</description>
15972       <bitOffset>8</bitOffset>
15973       <bitWidth>1</bitWidth>
15974       <enumeratedValues>
15975        <enumeratedValue>
15976         <name>dis</name>
15977         <description>Interrupt is disabled.</description>
15978         <value>0</value>
15979        </enumeratedValue>
15980        <enumeratedValue>
15981         <name>en</name>
15982         <description>Interrupt is enabled.</description>
15983         <value>1</value>
15984        </enumeratedValue>
15985       </enumeratedValues>
15986      </field>
15987      <field>
15988       <name>ABORT</name>
15989       <description>Slave Abort Detected interrupt enable.</description>
15990       <bitOffset>9</bitOffset>
15991       <bitWidth>1</bitWidth>
15992       <enumeratedValues>
15993        <enumeratedValue>
15994         <name>dis</name>
15995         <description>Interrupt is disabled.</description>
15996         <value>0</value>
15997        </enumeratedValue>
15998        <enumeratedValue>
15999         <name>en</name>
16000         <description>Interrupt is enabled.</description>
16001         <value>1</value>
16002        </enumeratedValue>
16003       </enumeratedValues>
16004      </field>
16005      <field>
16006       <name>MST_DONE</name>
16007       <description>Master Done interrupt enable.</description>
16008       <bitOffset>11</bitOffset>
16009       <bitWidth>1</bitWidth>
16010       <enumeratedValues>
16011        <enumeratedValue>
16012         <name>dis</name>
16013         <description>Interrupt is disabled.</description>
16014         <value>0</value>
16015        </enumeratedValue>
16016        <enumeratedValue>
16017         <name>en</name>
16018         <description>Interrupt is enabled.</description>
16019         <value>1</value>
16020        </enumeratedValue>
16021       </enumeratedValues>
16022      </field>
16023      <field>
16024       <name>TX_OV</name>
16025       <description>Transmit FIFO Overrun interrupt enable.</description>
16026       <bitOffset>12</bitOffset>
16027       <bitWidth>1</bitWidth>
16028       <enumeratedValues>
16029        <enumeratedValue>
16030         <name>dis</name>
16031         <description>Interrupt is disabled.</description>
16032         <value>0</value>
16033        </enumeratedValue>
16034        <enumeratedValue>
16035         <name>en</name>
16036         <description>Interrupt is enabled.</description>
16037         <value>1</value>
16038        </enumeratedValue>
16039       </enumeratedValues>
16040      </field>
16041      <field>
16042       <name>TX_UN</name>
16043       <description>Transmit FIFO Underrun interrupt enable.</description>
16044       <bitOffset>13</bitOffset>
16045       <bitWidth>1</bitWidth>
16046       <enumeratedValues>
16047        <enumeratedValue>
16048         <name>dis</name>
16049         <description>Interrupt is disabled.</description>
16050         <value>0</value>
16051        </enumeratedValue>
16052        <enumeratedValue>
16053         <name>en</name>
16054         <description>Interrupt is enabled.</description>
16055         <value>1</value>
16056        </enumeratedValue>
16057       </enumeratedValues>
16058      </field>
16059      <field>
16060       <name>RX_OV</name>
16061       <description>Receive FIFO Overrun interrupt enable.</description>
16062       <bitOffset>14</bitOffset>
16063       <bitWidth>1</bitWidth>
16064       <enumeratedValues>
16065        <enumeratedValue>
16066         <name>dis</name>
16067         <description>Interrupt is disabled.</description>
16068         <value>0</value>
16069        </enumeratedValue>
16070        <enumeratedValue>
16071         <name>en</name>
16072         <description>Interrupt is enabled.</description>
16073         <value>1</value>
16074        </enumeratedValue>
16075       </enumeratedValues>
16076      </field>
16077      <field>
16078       <name>RX_UN</name>
16079       <description>Receive FIFO Underrun interrupt enable.</description>
16080       <bitOffset>15</bitOffset>
16081       <bitWidth>1</bitWidth>
16082       <enumeratedValues>
16083        <enumeratedValue>
16084         <name>dis</name>
16085         <description>Interrupt is disabled.</description>
16086         <value>0</value>
16087        </enumeratedValue>
16088        <enumeratedValue>
16089         <name>en</name>
16090         <description>Interrupt is enabled.</description>
16091         <value>1</value>
16092        </enumeratedValue>
16093       </enumeratedValues>
16094      </field>
16095     </fields>
16096    </register>
16097    <register>
16098     <name>WKFL</name>
16099     <description>Register for wake up flags. All bits in this register are write 1 to clear.</description>
16100     <addressOffset>0x28</addressOffset>
16101     <access>read-write</access>
16102     <fields>
16103      <field>
16104       <name>TX_THD</name>
16105       <description>Wake on TX FIFO Threshold Crossed.</description>
16106       <bitOffset>0</bitOffset>
16107       <bitWidth>1</bitWidth>
16108       <enumeratedValues>
16109        <enumeratedValue>
16110         <name>clear</name>
16111         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
16112         <value>1</value>
16113        </enumeratedValue>
16114       </enumeratedValues>
16115      </field>
16116      <field>
16117       <name>TX_EM</name>
16118       <description>Wake on TX FIFO Empty.</description>
16119       <bitOffset>1</bitOffset>
16120       <bitWidth>1</bitWidth>
16121       <enumeratedValues>
16122        <enumeratedValue>
16123         <name>clear</name>
16124         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
16125         <value>1</value>
16126        </enumeratedValue>
16127       </enumeratedValues>
16128      </field>
16129      <field>
16130       <name>RX_THD</name>
16131       <description>Wake on RX FIFO Threshold Crossed.</description>
16132       <bitOffset>2</bitOffset>
16133       <bitWidth>1</bitWidth>
16134       <enumeratedValues>
16135        <enumeratedValue>
16136         <name>clear</name>
16137         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
16138         <value>1</value>
16139        </enumeratedValue>
16140       </enumeratedValues>
16141      </field>
16142      <field>
16143       <name>RX_FULL</name>
16144       <description>Wake on RX FIFO Full.</description>
16145       <bitOffset>3</bitOffset>
16146       <bitWidth>1</bitWidth>
16147       <enumeratedValues>
16148        <enumeratedValue>
16149         <name>clear</name>
16150         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
16151         <value>1</value>
16152        </enumeratedValue>
16153       </enumeratedValues>
16154      </field>
16155     </fields>
16156    </register>
16157    <register>
16158     <name>WKEN</name>
16159     <description>Register for wake up enable.</description>
16160     <addressOffset>0x2C</addressOffset>
16161     <access>read-write</access>
16162     <fields>
16163      <field>
16164       <name>TX_THD</name>
16165       <description>Wake on TX FIFO Threshold Crossed Enable.</description>
16166       <bitOffset>0</bitOffset>
16167       <bitWidth>1</bitWidth>
16168       <enumeratedValues>
16169        <enumeratedValue>
16170         <name>dis</name>
16171         <description>Wakeup source disabled.</description>
16172         <value>0</value>
16173        </enumeratedValue>
16174        <enumeratedValue>
16175         <name>en</name>
16176         <description>Wakeup source enabled.</description>
16177         <value>1</value>
16178        </enumeratedValue>
16179       </enumeratedValues>
16180      </field>
16181      <field>
16182       <name>TX_EM</name>
16183       <description>Wake on TX FIFO Empty Enable.</description>
16184       <bitOffset>1</bitOffset>
16185       <bitWidth>1</bitWidth>
16186       <enumeratedValues>
16187        <enumeratedValue>
16188         <name>dis</name>
16189         <description>Wakeup source disabled.</description>
16190         <value>0</value>
16191        </enumeratedValue>
16192        <enumeratedValue>
16193         <name>en</name>
16194         <description>Wakeup source enabled.</description>
16195         <value>1</value>
16196        </enumeratedValue>
16197       </enumeratedValues>
16198      </field>
16199      <field>
16200       <name>RX_THD</name>
16201       <description>Wake on RX FIFO Threshold Crossed Enable.</description>
16202       <bitOffset>2</bitOffset>
16203       <bitWidth>1</bitWidth>
16204       <enumeratedValues>
16205        <enumeratedValue>
16206         <name>dis</name>
16207         <description>Wakeup source disabled.</description>
16208         <value>0</value>
16209        </enumeratedValue>
16210        <enumeratedValue>
16211         <name>en</name>
16212         <description>Wakeup source enabled.</description>
16213         <value>1</value>
16214        </enumeratedValue>
16215       </enumeratedValues>
16216      </field>
16217      <field>
16218       <name>RX_FULL</name>
16219       <description>Wake on RX FIFO Full Enable.</description>
16220       <bitOffset>3</bitOffset>
16221       <bitWidth>1</bitWidth>
16222       <enumeratedValues>
16223        <enumeratedValue>
16224         <name>dis</name>
16225         <description>Wakeup source disabled.</description>
16226         <value>0</value>
16227        </enumeratedValue>
16228        <enumeratedValue>
16229         <name>en</name>
16230         <description>Wakeup source enabled.</description>
16231         <value>1</value>
16232        </enumeratedValue>
16233       </enumeratedValues>
16234      </field>
16235     </fields>
16236    </register>
16237    <register>
16238     <name>STAT</name>
16239     <description>SPI Status register.</description>
16240     <addressOffset>0x30</addressOffset>
16241     <access>read-only</access>
16242     <fields>
16243      <field>
16244       <name>BUSY</name>
16245       <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description>
16246       <bitOffset>0</bitOffset>
16247       <bitWidth>1</bitWidth>
16248       <enumeratedValues>
16249        <enumeratedValue>
16250         <name>not</name>
16251         <description>SPI not active.</description>
16252         <value>0</value>
16253        </enumeratedValue>
16254        <enumeratedValue>
16255         <name>active</name>
16256         <description>SPI active.</description>
16257         <value>1</value>
16258        </enumeratedValue>
16259       </enumeratedValues>
16260      </field>
16261     </fields>
16262    </register>
16263   </registers>
16264  </peripheral>
16265<!--SPI0 SPI peripheral.-->
16266  <peripheral derivedFrom="SPI0">
16267   <name>SPI1</name>
16268   <description>SPI peripheral. 1</description>
16269   <baseAddress>0x40046000</baseAddress>
16270   <interrupt>
16271    <name>SPI1</name>
16272    <description>SPI1 IRQ</description>
16273    <value>16</value>
16274   </interrupt>
16275  </peripheral>
16276<!--SPI1 SPI peripheral. 1-->
16277  <peripheral>
16278   <name>TMR</name>
16279   <description>Low-Power Configurable Timer</description>
16280   <baseAddress>0x40010000</baseAddress>
16281   <addressBlock>
16282    <offset>0x00</offset>
16283    <size>0x1000</size>
16284    <usage>registers</usage>
16285   </addressBlock>
16286   <interrupt>
16287    <name>TMR</name>
16288    <value>5</value>
16289   </interrupt>
16290   <registers>
16291    <register>
16292     <name>CNT</name>
16293     <description>Timer Counter Register.</description>
16294     <addressOffset>0x00</addressOffset>
16295     <access>read-write</access>
16296     <fields>
16297      <field>
16298       <name>COUNT</name>
16299       <description>The current count value for the timer. This field increments as the timer counts.</description>
16300       <bitOffset>0</bitOffset>
16301       <bitWidth>32</bitWidth>
16302      </field>
16303     </fields>
16304    </register>
16305    <register>
16306     <name>CMP</name>
16307     <description>Timer Compare Register.</description>
16308     <addressOffset>0x04</addressOffset>
16309     <access>read-write</access>
16310     <fields>
16311      <field>
16312       <name>COMPARE</name>
16313       <description>The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.</description>
16314       <bitOffset>0</bitOffset>
16315       <bitWidth>32</bitWidth>
16316      </field>
16317     </fields>
16318    </register>
16319    <register>
16320     <name>PWM</name>
16321     <description>Timer PWM Register.</description>
16322     <addressOffset>0x08</addressOffset>
16323     <access>read-write</access>
16324     <fields>
16325      <field>
16326       <name>PWM</name>
16327       <description>Timer PWM Match:
16328                In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value:
16329                In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.</description>
16330       <bitOffset>0</bitOffset>
16331       <bitWidth>32</bitWidth>
16332      </field>
16333     </fields>
16334    </register>
16335    <register>
16336     <name>INTFL</name>
16337     <description>Timer Interrupt Status Register.</description>
16338     <addressOffset>0x0C</addressOffset>
16339     <access>read-write</access>
16340     <fields>
16341      <field>
16342       <name>IRQ_A</name>
16343       <description>Interrupt Flag for Timer A.</description>
16344       <bitOffset>0</bitOffset>
16345       <bitWidth>1</bitWidth>
16346      </field>
16347      <field>
16348       <name>WRDONE_A</name>
16349       <description>Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.</description>
16350       <bitOffset>8</bitOffset>
16351       <bitWidth>1</bitWidth>
16352      </field>
16353      <field>
16354       <name>WR_DIS_A</name>
16355       <description>Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.</description>
16356       <bitOffset>9</bitOffset>
16357       <bitWidth>1</bitWidth>
16358      </field>
16359      <field>
16360       <name>IRQ_B</name>
16361       <description>Interrupt Flag for Timer B.</description>
16362       <bitOffset>16</bitOffset>
16363       <bitWidth>1</bitWidth>
16364      </field>
16365      <field>
16366       <name>WRDONE_B</name>
16367       <description>Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.</description>
16368       <bitOffset>24</bitOffset>
16369       <bitWidth>1</bitWidth>
16370      </field>
16371      <field>
16372       <name>WR_DIS_B</name>
16373       <description>Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.</description>
16374       <bitOffset>25</bitOffset>
16375       <bitWidth>1</bitWidth>
16376      </field>
16377     </fields>
16378    </register>
16379    <register>
16380     <name>CTRL0</name>
16381     <description>Timer Control Register.</description>
16382     <addressOffset>0x10</addressOffset>
16383     <access>read-write</access>
16384     <fields>
16385      <field>
16386       <name>MODE_A</name>
16387       <description>Mode Select for Timer A</description>
16388       <bitOffset>0</bitOffset>
16389       <bitWidth>4</bitWidth>
16390       <enumeratedValues>
16391        <enumeratedValue>
16392         <name>ONE_SHOT</name>
16393         <description>One-Shot Mode</description>
16394         <value>0</value>
16395        </enumeratedValue>
16396        <enumeratedValue>
16397         <name>CONTINUOUS</name>
16398         <description>Continuous Mode</description>
16399         <value>1</value>
16400        </enumeratedValue>
16401        <enumeratedValue>
16402         <name>COUNTER</name>
16403         <description>Counter Mode</description>
16404         <value>2</value>
16405        </enumeratedValue>
16406        <enumeratedValue>
16407         <name>PWM</name>
16408         <description>PWM Mode</description>
16409         <value>3</value>
16410        </enumeratedValue>
16411        <enumeratedValue>
16412         <name>CAPTURE</name>
16413         <description>Capture Mode</description>
16414         <value>4</value>
16415        </enumeratedValue>
16416        <enumeratedValue>
16417         <name>COMPARE</name>
16418         <description>Compare Mode</description>
16419         <value>5</value>
16420        </enumeratedValue>
16421        <enumeratedValue>
16422         <name>GATED</name>
16423         <description>Gated Mode</description>
16424         <value>6</value>
16425        </enumeratedValue>
16426        <enumeratedValue>
16427         <name>CAPCOMP</name>
16428         <description>Capture/Compare Mode</description>
16429         <value>7</value>
16430        </enumeratedValue>
16431        <enumeratedValue>
16432         <name>DUAL_EDGE</name>
16433         <description>Dual Edge Capture Mode</description>
16434         <value>8</value>
16435        </enumeratedValue>
16436        <enumeratedValue>
16437         <name>IGATED</name>
16438         <description>Inactive Gated Mode</description>
16439         <value>14</value>
16440        </enumeratedValue>
16441       </enumeratedValues>
16442      </field>
16443      <field>
16444       <name>CLKDIV_A</name>
16445       <description>Clock Divider Select for Timer A</description>
16446       <bitOffset>4</bitOffset>
16447       <bitWidth>4</bitWidth>
16448       <enumeratedValues>
16449        <enumeratedValue>
16450         <name>DIV_BY_1</name>
16451         <description>Prescaler Divide-By-1</description>
16452         <value>0</value>
16453        </enumeratedValue>
16454        <enumeratedValue>
16455         <name>DIV_BY_2</name>
16456         <description>Prescaler Divide-By-2</description>
16457         <value>1</value>
16458        </enumeratedValue>
16459        <enumeratedValue>
16460         <name>DIV_BY_4</name>
16461         <description>Prescaler Divide-By-4</description>
16462         <value>2</value>
16463        </enumeratedValue>
16464        <enumeratedValue>
16465         <name>DIV_BY_8</name>
16466         <description>Prescaler Divide-By-8</description>
16467         <value>3</value>
16468        </enumeratedValue>
16469        <enumeratedValue>
16470         <name>DIV_BY_16</name>
16471         <description>Prescaler Divide-By-16</description>
16472         <value>4</value>
16473        </enumeratedValue>
16474        <enumeratedValue>
16475         <name>DIV_BY_32</name>
16476         <description>Prescaler Divide-By-32</description>
16477         <value>5</value>
16478        </enumeratedValue>
16479        <enumeratedValue>
16480         <name>DIV_BY_64</name>
16481         <description>Prescaler Divide-By-64</description>
16482         <value>6</value>
16483        </enumeratedValue>
16484        <enumeratedValue>
16485         <name>DIV_BY_128</name>
16486         <description>Prescaler Divide-By-128</description>
16487         <value>7</value>
16488        </enumeratedValue>
16489        <enumeratedValue>
16490         <name>DIV_BY_256</name>
16491         <description>Prescaler Divide-By-256</description>
16492         <value>8</value>
16493        </enumeratedValue>
16494        <enumeratedValue>
16495         <name>DIV_BY_512</name>
16496         <description>Prescaler Divide-By-512</description>
16497         <value>9</value>
16498        </enumeratedValue>
16499        <enumeratedValue>
16500         <name>DIV_BY_1024</name>
16501         <description>Prescaler Divide-By-1024</description>
16502         <value>10</value>
16503        </enumeratedValue>
16504        <enumeratedValue>
16505         <name>DIV_BY_2048</name>
16506         <description>Prescaler Divide-By-2048</description>
16507         <value>11</value>
16508        </enumeratedValue>
16509        <enumeratedValue>
16510         <name>DIV_BY_4096</name>
16511         <description>TBD</description>
16512         <value>12</value>
16513        </enumeratedValue>
16514       </enumeratedValues>
16515      </field>
16516      <field>
16517       <name>POL_A</name>
16518       <description>Timer Polarity for Timer A</description>
16519       <bitOffset>8</bitOffset>
16520       <bitWidth>1</bitWidth>
16521      </field>
16522      <field>
16523       <name>PWMSYNC_A</name>
16524       <description>PWM Synchronization Mode for Timer A</description>
16525       <bitOffset>9</bitOffset>
16526       <bitWidth>1</bitWidth>
16527      </field>
16528      <field>
16529       <name>NOLHPOL_A</name>
16530       <description>PWM Phase A (Non-Overlapping High) Polarity for Timer A</description>
16531       <bitOffset>10</bitOffset>
16532       <bitWidth>1</bitWidth>
16533      </field>
16534      <field>
16535       <name>NOLLPOL_A</name>
16536       <description>PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A</description>
16537       <bitOffset>11</bitOffset>
16538       <bitWidth>1</bitWidth>
16539      </field>
16540      <field>
16541       <name>PWMCKBD_A</name>
16542       <description>PWM Phase A-Prime Output Disable for Timer A</description>
16543       <bitOffset>12</bitOffset>
16544       <bitWidth>1</bitWidth>
16545      </field>
16546      <field>
16547       <name>RST_A</name>
16548       <description>Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.</description>
16549       <bitOffset>13</bitOffset>
16550       <bitWidth>1</bitWidth>
16551      </field>
16552      <field>
16553       <name>CLKEN_A</name>
16554       <description>Write 1 to Enable CLK_TMR for Timer A</description>
16555       <bitOffset>14</bitOffset>
16556       <bitWidth>1</bitWidth>
16557      </field>
16558      <field>
16559       <name>EN_A</name>
16560       <description>Enable for Timer A</description>
16561       <bitOffset>15</bitOffset>
16562       <bitWidth>1</bitWidth>
16563      </field>
16564      <field>
16565       <name>MODE_B</name>
16566       <description>Mode Select for Timer B</description>
16567       <bitOffset>16</bitOffset>
16568       <bitWidth>4</bitWidth>
16569       <enumeratedValues>
16570        <enumeratedValue>
16571         <name>ONE_SHOT</name>
16572         <description>One-Shot Mode</description>
16573         <value>0</value>
16574        </enumeratedValue>
16575        <enumeratedValue>
16576         <name>CONTINUOUS</name>
16577         <description>Continuous Mode</description>
16578         <value>1</value>
16579        </enumeratedValue>
16580        <enumeratedValue>
16581         <name>COUNTER</name>
16582         <description>Counter Mode</description>
16583         <value>2</value>
16584        </enumeratedValue>
16585        <enumeratedValue>
16586         <name>PWM</name>
16587         <description>PWM Mode</description>
16588         <value>3</value>
16589        </enumeratedValue>
16590        <enumeratedValue>
16591         <name>CAPTURE</name>
16592         <description>Capture Mode</description>
16593         <value>4</value>
16594        </enumeratedValue>
16595        <enumeratedValue>
16596         <name>COMPARE</name>
16597         <description>Compare Mode</description>
16598         <value>5</value>
16599        </enumeratedValue>
16600        <enumeratedValue>
16601         <name>GATED</name>
16602         <description>Gated Mode</description>
16603         <value>6</value>
16604        </enumeratedValue>
16605        <enumeratedValue>
16606         <name>CAPCOMP</name>
16607         <description>Capture/Compare Mode</description>
16608         <value>7</value>
16609        </enumeratedValue>
16610        <enumeratedValue>
16611         <name>DUAL_EDGE</name>
16612         <description>Dual Edge Capture Mode</description>
16613         <value>8</value>
16614        </enumeratedValue>
16615        <enumeratedValue>
16616         <name>IGATED</name>
16617         <description>Inactive Gated Mode</description>
16618         <value>14</value>
16619        </enumeratedValue>
16620       </enumeratedValues>
16621      </field>
16622      <field>
16623       <name>CLKDIV_B</name>
16624       <description>Clock Divider Select for Timer B</description>
16625       <bitOffset>20</bitOffset>
16626       <bitWidth>4</bitWidth>
16627       <enumeratedValues>
16628        <enumeratedValue>
16629         <name>DIV_BY_1</name>
16630         <description>Prescaler Divide-By-1</description>
16631         <value>0</value>
16632        </enumeratedValue>
16633        <enumeratedValue>
16634         <name>DIV_BY_2</name>
16635         <description>Prescaler Divide-By-2</description>
16636         <value>1</value>
16637        </enumeratedValue>
16638        <enumeratedValue>
16639         <name>DIV_BY_4</name>
16640         <description>Prescaler Divide-By-4</description>
16641         <value>2</value>
16642        </enumeratedValue>
16643        <enumeratedValue>
16644         <name>DIV_BY_8</name>
16645         <description>Prescaler Divide-By-8</description>
16646         <value>3</value>
16647        </enumeratedValue>
16648        <enumeratedValue>
16649         <name>DIV_BY_16</name>
16650         <description>Prescaler Divide-By-16</description>
16651         <value>4</value>
16652        </enumeratedValue>
16653        <enumeratedValue>
16654         <name>DIV_BY_32</name>
16655         <description>Prescaler Divide-By-32</description>
16656         <value>5</value>
16657        </enumeratedValue>
16658        <enumeratedValue>
16659         <name>DIV_BY_64</name>
16660         <description>Prescaler Divide-By-64</description>
16661         <value>6</value>
16662        </enumeratedValue>
16663        <enumeratedValue>
16664         <name>DIV_BY_128</name>
16665         <description>Prescaler Divide-By-128</description>
16666         <value>7</value>
16667        </enumeratedValue>
16668        <enumeratedValue>
16669         <name>DIV_BY_256</name>
16670         <description>Prescaler Divide-By-256</description>
16671         <value>8</value>
16672        </enumeratedValue>
16673        <enumeratedValue>
16674         <name>DIV_BY_512</name>
16675         <description>Prescaler Divide-By-512</description>
16676         <value>9</value>
16677        </enumeratedValue>
16678        <enumeratedValue>
16679         <name>DIV_BY_1024</name>
16680         <description>Prescaler Divide-By-1024</description>
16681         <value>10</value>
16682        </enumeratedValue>
16683        <enumeratedValue>
16684         <name>DIV_BY_2048</name>
16685         <description>Prescaler Divide-By-2048</description>
16686         <value>11</value>
16687        </enumeratedValue>
16688        <enumeratedValue>
16689         <name>DIV_BY_4096</name>
16690         <description>TBD</description>
16691         <value>12</value>
16692        </enumeratedValue>
16693       </enumeratedValues>
16694      </field>
16695      <field>
16696       <name>POL_B</name>
16697       <description>Timer Polarity for Timer B</description>
16698       <bitOffset>24</bitOffset>
16699       <bitWidth>1</bitWidth>
16700      </field>
16701      <field>
16702       <name>PWMSYNC_B</name>
16703       <description>PWM Synchronization Mode for Timer B</description>
16704       <bitOffset>25</bitOffset>
16705       <bitWidth>1</bitWidth>
16706      </field>
16707      <field>
16708       <name>NOLHPOL_B</name>
16709       <description>PWM Phase A (Non-Overlapping High) Polarity for Timer B</description>
16710       <bitOffset>26</bitOffset>
16711       <bitWidth>1</bitWidth>
16712      </field>
16713      <field>
16714       <name>NOLLPOL_B</name>
16715       <description>PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B</description>
16716       <bitOffset>27</bitOffset>
16717       <bitWidth>1</bitWidth>
16718      </field>
16719      <field>
16720       <name>PWMCKBD_B</name>
16721       <description>PWM Phase A-Prime Output Disable for Timer B</description>
16722       <bitOffset>28</bitOffset>
16723       <bitWidth>1</bitWidth>
16724      </field>
16725      <field>
16726       <name>RST_B</name>
16727       <description>Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.</description>
16728       <bitOffset>29</bitOffset>
16729       <bitWidth>1</bitWidth>
16730      </field>
16731      <field>
16732       <name>CLKEN_B</name>
16733       <description>Write 1 to Enable CLK_TMR for Timer B</description>
16734       <bitOffset>30</bitOffset>
16735       <bitWidth>1</bitWidth>
16736      </field>
16737      <field>
16738       <name>EN_B</name>
16739       <description>Enable for Timer B</description>
16740       <bitOffset>31</bitOffset>
16741       <bitWidth>1</bitWidth>
16742      </field>
16743     </fields>
16744    </register>
16745    <register>
16746     <name>NOLCMP</name>
16747     <description>Timer Non-Overlapping Compare Register.</description>
16748     <addressOffset>0x14</addressOffset>
16749     <access>read-write</access>
16750     <fields>
16751      <field>
16752       <name>LO_A</name>
16753       <description>Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.</description>
16754       <bitOffset>0</bitOffset>
16755       <bitWidth>8</bitWidth>
16756      </field>
16757      <field>
16758       <name>HI_A</name>
16759       <description>Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.</description>
16760       <bitOffset>8</bitOffset>
16761       <bitWidth>8</bitWidth>
16762      </field>
16763      <field>
16764       <name>LO_B</name>
16765       <description>Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.</description>
16766       <bitOffset>16</bitOffset>
16767       <bitWidth>8</bitWidth>
16768      </field>
16769      <field>
16770       <name>HI_B</name>
16771       <description>Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.</description>
16772       <bitOffset>24</bitOffset>
16773       <bitWidth>8</bitWidth>
16774      </field>
16775     </fields>
16776    </register>
16777    <register>
16778     <name>CTRL1</name>
16779     <description>Timer Configuration Register.</description>
16780     <addressOffset>0x18</addressOffset>
16781     <access>read-write</access>
16782     <fields>
16783      <field>
16784       <name>CLKSEL_A</name>
16785       <description>Timer Clock Select for Timer A</description>
16786       <bitOffset>0</bitOffset>
16787       <bitWidth>2</bitWidth>
16788      </field>
16789      <field>
16790       <name>CLKEN_A</name>
16791       <description>Timer A Enable Status</description>
16792       <bitOffset>2</bitOffset>
16793       <bitWidth>1</bitWidth>
16794      </field>
16795      <field>
16796       <name>CLKRDY_A</name>
16797       <description>CLK_TMR Ready Flag for Timer A</description>
16798       <bitOffset>3</bitOffset>
16799       <bitWidth>1</bitWidth>
16800      </field>
16801      <field>
16802       <name>EVENT_SEL_A</name>
16803       <description>Event Select for Timer A</description>
16804       <bitOffset>4</bitOffset>
16805       <bitWidth>3</bitWidth>
16806      </field>
16807      <field>
16808       <name>NEGTRIG_A</name>
16809       <description>Negative Edge Trigger for Event for Timer A</description>
16810       <bitOffset>7</bitOffset>
16811       <bitWidth>1</bitWidth>
16812      </field>
16813      <field>
16814       <name>IE_A</name>
16815       <description>Interrupt Enable for Timer A</description>
16816       <bitOffset>8</bitOffset>
16817       <bitWidth>1</bitWidth>
16818      </field>
16819      <field>
16820       <name>CAPEVENT_SEL_A</name>
16821       <description>Capture Event Select for Timer A</description>
16822       <bitOffset>9</bitOffset>
16823       <bitWidth>2</bitWidth>
16824      </field>
16825      <field>
16826       <name>SW_CAPEVENT_A</name>
16827       <description>Software Capture Event for Timer A</description>
16828       <bitOffset>11</bitOffset>
16829       <bitWidth>1</bitWidth>
16830      </field>
16831      <field>
16832       <name>WE_A</name>
16833       <description>Wake-Up Enable for Timer A</description>
16834       <bitOffset>12</bitOffset>
16835       <bitWidth>1</bitWidth>
16836      </field>
16837      <field>
16838       <name>OUTEN_A</name>
16839       <description>OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A</description>
16840       <bitOffset>13</bitOffset>
16841       <bitWidth>1</bitWidth>
16842      </field>
16843      <field>
16844       <name>OUTBEN_A</name>
16845       <description>PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A</description>
16846       <bitOffset>14</bitOffset>
16847       <bitWidth>1</bitWidth>
16848      </field>
16849      <field>
16850       <name>CLKSEL_B</name>
16851       <description>Timer Clock Select for Timer B</description>
16852       <bitOffset>16</bitOffset>
16853       <bitWidth>2</bitWidth>
16854      </field>
16855      <field>
16856       <name>CLKEN_B</name>
16857       <description>Timer B Enable Status</description>
16858       <bitOffset>18</bitOffset>
16859       <bitWidth>1</bitWidth>
16860      </field>
16861      <field>
16862       <name>CLKRDY_B</name>
16863       <description>CLK_TMR Ready Flag for Timer B</description>
16864       <bitOffset>19</bitOffset>
16865       <bitWidth>1</bitWidth>
16866      </field>
16867      <field>
16868       <name>EVENT_SEL_B</name>
16869       <description>Event Select for Timer B</description>
16870       <bitOffset>20</bitOffset>
16871       <bitWidth>3</bitWidth>
16872      </field>
16873      <field>
16874       <name>NEGTRIG_B</name>
16875       <description>Negative Edge Trigger for Event for Timer B</description>
16876       <bitOffset>23</bitOffset>
16877       <bitWidth>1</bitWidth>
16878      </field>
16879      <field>
16880       <name>IE_B</name>
16881       <description>Interrupt Enable for Timer B</description>
16882       <bitOffset>24</bitOffset>
16883       <bitWidth>1</bitWidth>
16884      </field>
16885      <field>
16886       <name>CAPEVENT_SEL_B</name>
16887       <description>Capture Event Select for Timer B</description>
16888       <bitOffset>25</bitOffset>
16889       <bitWidth>2</bitWidth>
16890      </field>
16891      <field>
16892       <name>SW_CAPEVENT_B</name>
16893       <description>Software Capture Event for Timer B</description>
16894       <bitOffset>27</bitOffset>
16895       <bitWidth>1</bitWidth>
16896      </field>
16897      <field>
16898       <name>WE_B</name>
16899       <description>Wake-Up Enable for Timer B</description>
16900       <bitOffset>28</bitOffset>
16901       <bitWidth>1</bitWidth>
16902      </field>
16903      <field>
16904       <name>CASCADE</name>
16905       <description>Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.</description>
16906       <bitOffset>31</bitOffset>
16907       <bitWidth>1</bitWidth>
16908      </field>
16909     </fields>
16910    </register>
16911    <register>
16912     <name>WKFL</name>
16913     <description>Timer Wakeup Status Register.</description>
16914     <addressOffset>0x1C</addressOffset>
16915     <access>read-write</access>
16916     <fields>
16917      <field>
16918       <name>A</name>
16919       <description>Wake-Up Flag for Timer A</description>
16920       <bitOffset>0</bitOffset>
16921       <bitWidth>1</bitWidth>
16922      </field>
16923      <field>
16924       <name>B</name>
16925       <description>Wake-Up Flag for Timer B</description>
16926       <bitOffset>16</bitOffset>
16927       <bitWidth>1</bitWidth>
16928      </field>
16929     </fields>
16930    </register>
16931   </registers>
16932  </peripheral>
16933<!--TMR Low-Power Configurable Timer-->
16934  <peripheral derivedFrom="TMR">
16935   <name>TMR1</name>
16936   <description>Low-Power Configurable Timer 1</description>
16937   <baseAddress>0x40011000</baseAddress>
16938   <interrupt>
16939    <name>TMR1</name>
16940    <description>TMR1 IRQ</description>
16941    <value>6</value>
16942   </interrupt>
16943  </peripheral>
16944<!--TMR1 Low-Power Configurable Timer 1-->
16945  <peripheral derivedFrom="TMR">
16946   <name>TMR2</name>
16947   <description>Low-Power Configurable Timer 2</description>
16948   <baseAddress>0x40012000</baseAddress>
16949   <interrupt>
16950    <name>TMR2</name>
16951    <description>TMR2 IRQ</description>
16952    <value>7</value>
16953   </interrupt>
16954  </peripheral>
16955<!--TMR2 Low-Power Configurable Timer 2-->
16956  <peripheral derivedFrom="TMR">
16957   <name>TMR3</name>
16958   <description>Low-Power Configurable Timer 3</description>
16959   <baseAddress>0x40013000</baseAddress>
16960   <interrupt>
16961    <name>TMR3</name>
16962    <description>TMR3 IRQ</description>
16963    <value>8</value>
16964   </interrupt>
16965  </peripheral>
16966<!--TMR3 Low-Power Configurable Timer 3-->
16967  <peripheral derivedFrom="TMR">
16968   <name>TMR4</name>
16969   <description>Low-Power Configurable Timer 4</description>
16970   <baseAddress>0x40080C00</baseAddress>
16971   <interrupt>
16972    <name>TMR4</name>
16973    <description>TMR4 IRQ</description>
16974    <value>9</value>
16975   </interrupt>
16976  </peripheral>
16977<!--TMR4 Low-Power Configurable Timer 4-->
16978  <peripheral derivedFrom="TMR">
16979   <name>TMR5</name>
16980   <description>Low-Power Configurable Timer 5</description>
16981   <baseAddress>0x40081000</baseAddress>
16982   <interrupt>
16983    <name>TMR5</name>
16984    <description>TMR5 IRQ</description>
16985    <value>10</value>
16986   </interrupt>
16987  </peripheral>
16988<!--TMR5 Low-Power Configurable Timer 5-->
16989  <peripheral>
16990   <name>TRNG</name>
16991   <description>Random Number Generator.</description>
16992   <baseAddress>0x4004D000</baseAddress>
16993   <addressBlock>
16994    <offset>0x00</offset>
16995    <size>0x1000</size>
16996    <usage>registers</usage>
16997   </addressBlock>
16998   <interrupt>
16999    <name>TRNG</name>
17000    <description>TRNG interrupt.</description>
17001    <value>4</value>
17002   </interrupt>
17003   <registers>
17004    <register>
17005     <name>CTRL</name>
17006     <description>TRNG Control Register.</description>
17007     <addressOffset>0x00</addressOffset>
17008     <resetValue>0x00000003</resetValue>
17009     <fields>
17010      <field>
17011       <name>RND_IE</name>
17012       <description>To enable IRQ generation when a new 32-bit Random number is ready.</description>
17013       <bitOffset>1</bitOffset>
17014       <bitWidth>1</bitWidth>
17015       <enumeratedValues>
17016        <enumeratedValue>
17017         <name>disable</name>
17018         <description>Disable</description>
17019         <value>0</value>
17020        </enumeratedValue>
17021        <enumeratedValue>
17022         <name>enable</name>
17023         <description>Enable</description>
17024         <value>1</value>
17025        </enumeratedValue>
17026       </enumeratedValues>
17027      </field>
17028      <field>
17029       <name>KEYGEN</name>
17030       <description>AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.</description>
17031       <bitOffset>3</bitOffset>
17032       <bitWidth>1</bitWidth>
17033      </field>
17034      <field>
17035       <name>KEYWIPE</name>
17036       <description>To wipe the Battery Backed key.</description>
17037       <bitOffset>15</bitOffset>
17038       <bitWidth>1</bitWidth>
17039      </field>
17040     </fields>
17041    </register>
17042    <register>
17043     <name>STATUS</name>
17044     <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description>
17045     <addressOffset>0x04</addressOffset>
17046     <fields>
17047      <field>
17048       <name>RDY</name>
17049       <description>32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1.</description>
17050       <bitOffset>0</bitOffset>
17051       <bitWidth>1</bitWidth>
17052       <enumeratedValues>
17053        <enumeratedValue>
17054         <name>Busy</name>
17055         <description>TRNG Busy</description>
17056         <value>0</value>
17057        </enumeratedValue>
17058        <enumeratedValue>
17059         <name>Ready</name>
17060         <description>32 bit random data is ready</description>
17061         <value>1</value>
17062        </enumeratedValue>
17063       </enumeratedValues>
17064      </field>
17065     </fields>
17066    </register>
17067    <register>
17068     <name>DATA</name>
17069     <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description>
17070     <addressOffset>0x08</addressOffset>
17071     <access>read-only</access>
17072     <fields>
17073      <field>
17074       <name>DATA</name>
17075       <description>Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000.</description>
17076       <bitOffset>0</bitOffset>
17077       <bitWidth>32</bitWidth>
17078      </field>
17079     </fields>
17080    </register>
17081   </registers>
17082  </peripheral>
17083<!--TRNG Random Number Generator.-->
17084  <peripheral>
17085   <name>TRIMSIR</name>
17086   <description>Trim System Initilazation Registers</description>
17087   <baseAddress>0x40005400</baseAddress>
17088   <addressBlock>
17089    <offset>0x00</offset>
17090    <size>0x400</size>
17091    <usage>registers</usage>
17092   </addressBlock>
17093   <registers>
17094    <register>
17095     <name>RTC</name>
17096     <description>RTC Trim System Initialization Register.</description>
17097     <addressOffset>0x08</addressOffset>
17098     <fields>
17099      <field>
17100       <name>X1TRIM</name>
17101       <description>RTC X1 Trim.</description>
17102       <bitOffset>16</bitOffset>
17103       <bitWidth>5</bitWidth>
17104      </field>
17105      <field>
17106       <name>X2TRIM</name>
17107       <description>RTC X2 Trim.</description>
17108       <bitOffset>21</bitOffset>
17109       <bitWidth>5</bitWidth>
17110      </field>
17111      <field>
17112       <name>LOCK</name>
17113       <description>Lock.</description>
17114       <bitOffset>31</bitOffset>
17115       <bitWidth>1</bitWidth>
17116      </field>
17117     </fields>
17118    </register>
17119    <register>
17120     <name>SIMO</name>
17121     <description>SIMO Trim System Initialization Register.</description>
17122     <addressOffset>0x34</addressOffset>
17123     <access>read-only</access>
17124     <fields>
17125      <field>
17126       <name>CLKDIV</name>
17127       <description>SIMO Clock Divide.</description>
17128       <bitOffset>0</bitOffset>
17129       <bitWidth>3</bitWidth>
17130       <enumeratedValues>
17131        <enumeratedValue>
17132         <name>DIV1</name>
17133         <value>0</value>
17134        </enumeratedValue>
17135        <enumeratedValue>
17136         <name>DIV16</name>
17137         <value>1</value>
17138        </enumeratedValue>
17139        <enumeratedValue>
17140         <name>DIV32</name>
17141         <value>3</value>
17142        </enumeratedValue>
17143        <enumeratedValue>
17144         <name>DIV64</name>
17145         <value>5</value>
17146        </enumeratedValue>
17147        <enumeratedValue>
17148         <name>DIV128</name>
17149         <value>7</value>
17150        </enumeratedValue>
17151       </enumeratedValues>
17152      </field>
17153     </fields>
17154    </register>
17155    <register>
17156     <name>IPOLO</name>
17157     <description>IPO Low Trim System Initialization Register.</description>
17158     <addressOffset>0x3C</addressOffset>
17159     <access>read-only</access>
17160     <fields>
17161      <field>
17162       <name>IPO_LIMITLO</name>
17163       <description>IPO Low Limit Trim.</description>
17164       <bitOffset>0</bitOffset>
17165       <bitWidth>8</bitWidth>
17166      </field>
17167     </fields>
17168    </register>
17169    <register>
17170     <name>CTRL</name>
17171     <description>Control Trim System Initialization Register.</description>
17172     <addressOffset>0x40</addressOffset>
17173     <fields>
17174      <field>
17175       <name>VDDA_LIMITLO</name>
17176       <description>VDDA Low Trim Limit.</description>
17177       <bitOffset>0</bitOffset>
17178       <bitWidth>7</bitWidth>
17179      </field>
17180      <field>
17181       <name>VDDA_LIMITHI</name>
17182       <description>VDDA High Trim Limit.</description>
17183       <bitOffset>8</bitOffset>
17184       <bitWidth>7</bitWidth>
17185      </field>
17186      <field>
17187       <name>IPO_LIMITHI</name>
17188       <description>IPO High Trim Limit.</description>
17189       <bitOffset>15</bitOffset>
17190       <bitWidth>9</bitWidth>
17191      </field>
17192      <field>
17193       <name>INRO_SEL</name>
17194       <description>INRO Clock Select.</description>
17195       <bitOffset>24</bitOffset>
17196       <bitWidth>2</bitWidth>
17197       <enumeratedValues>
17198        <enumeratedValue>
17199         <name>8KHZ</name>
17200         <value>0</value>
17201        </enumeratedValue>
17202        <enumeratedValue>
17203         <name>16KHZ</name>
17204         <value>1</value>
17205        </enumeratedValue>
17206        <enumeratedValue>
17207         <name>30KHZ</name>
17208         <value>2</value>
17209        </enumeratedValue>
17210       </enumeratedValues>
17211      </field>
17212      <field>
17213       <name>INRO_TRIM</name>
17214       <description>INRO Clock Trim.</description>
17215       <bitOffset>29</bitOffset>
17216       <bitWidth>3</bitWidth>
17217      </field>
17218     </fields>
17219    </register>
17220    <register>
17221     <name>INRO</name>
17222     <description>RTC Trim System Initialization Register.</description>
17223     <addressOffset>0x44</addressOffset>
17224     <fields>
17225      <field>
17226       <name>TRIM16K</name>
17227       <description>INRO 16KHz Trim.</description>
17228       <bitOffset>0</bitOffset>
17229       <bitWidth>3</bitWidth>
17230      </field>
17231      <field>
17232       <name>TRIM30K</name>
17233       <description>INRO 30KHz Trim.</description>
17234       <bitOffset>3</bitOffset>
17235       <bitWidth>3</bitWidth>
17236      </field>
17237      <field>
17238       <name>LPCLKSEL</name>
17239       <description>INRO Low Power Mode Clock Select.</description>
17240       <bitOffset>6</bitOffset>
17241       <bitWidth>2</bitWidth>
17242       <enumeratedValues>
17243        <enumeratedValue>
17244         <name>8KHZ</name>
17245         <value>0</value>
17246        </enumeratedValue>
17247        <enumeratedValue>
17248         <name>16KHZ</name>
17249         <value>1</value>
17250        </enumeratedValue>
17251        <enumeratedValue>
17252         <name>30KHZ</name>
17253         <value>2</value>
17254        </enumeratedValue>
17255       </enumeratedValues>
17256      </field>
17257     </fields>
17258    </register>
17259   </registers>
17260  </peripheral>
17261<!--TRIMSIR Trim System Initilazation Registers-->
17262  <peripheral>
17263   <name>UART</name>
17264   <description>UART Low Power Registers</description>
17265   <baseAddress>0x40042000</baseAddress>
17266   <addressBlock>
17267    <offset>0x00</offset>
17268    <size>0x1000</size>
17269    <usage>registers</usage>
17270   </addressBlock>
17271   <registers>
17272    <register>
17273     <name>CTRL</name>
17274     <description>Control register</description>
17275     <addressOffset>0x0000</addressOffset>
17276     <fields>
17277      <field>
17278       <name>RX_THD_VAL</name>
17279       <description>This field specifies the depth of receive FIFO for interrupt generation (value 0 and &gt; 16 are ignored) </description>
17280       <bitOffset>0</bitOffset>
17281       <bitWidth>4</bitWidth>
17282      </field>
17283      <field>
17284       <name>PAR_EN</name>
17285       <description>Parity Enable</description>
17286       <bitOffset>4</bitOffset>
17287       <bitWidth>1</bitWidth>
17288      </field>
17289      <field>
17290       <name>PAR_EO</name>
17291       <description>when PAREN=1 selects odd or even parity odd is 1 even is 0</description>
17292       <bitOffset>5</bitOffset>
17293       <bitWidth>1</bitWidth>
17294      </field>
17295      <field>
17296       <name>PAR_MD</name>
17297       <description>Selects parity based on 1s or 0s count (when PAREN=1) </description>
17298       <bitOffset>6</bitOffset>
17299       <bitWidth>1</bitWidth>
17300      </field>
17301      <field>
17302       <name>CTS_DIS</name>
17303       <description>CTS Sampling Disable </description>
17304       <bitOffset>7</bitOffset>
17305       <bitWidth>1</bitWidth>
17306      </field>
17307      <field>
17308       <name>TX_FLUSH</name>
17309       <description>Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description>
17310       <bitOffset>8</bitOffset>
17311       <bitWidth>1</bitWidth>
17312      </field>
17313      <field>
17314       <name>RX_FLUSH</name>
17315       <description>Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description>
17316       <bitOffset>9</bitOffset>
17317       <bitWidth>1</bitWidth>
17318      </field>
17319      <field>
17320       <name>CHAR_SIZE</name>
17321       <description>Selects UART character size</description>
17322       <bitOffset>10</bitOffset>
17323       <bitWidth>2</bitWidth>
17324       <enumeratedValues>
17325        <enumeratedValue>
17326         <name>5bits</name>
17327         <description>5 bits</description>
17328         <value>0</value>
17329        </enumeratedValue>
17330        <enumeratedValue>
17331         <name>6bits</name>
17332         <description>6 bits</description>
17333         <value>1</value>
17334        </enumeratedValue>
17335        <enumeratedValue>
17336         <name>7bits</name>
17337         <description>7 bits</description>
17338         <value>2</value>
17339        </enumeratedValue>
17340        <enumeratedValue>
17341         <name>8bits</name>
17342         <description>8 bits</description>
17343         <value>3</value>
17344        </enumeratedValue>
17345       </enumeratedValues>
17346      </field>
17347      <field>
17348       <name>STOPBITS</name>
17349       <description>Selects the number of stop bits that will be generated</description>
17350       <bitOffset>12</bitOffset>
17351       <bitWidth>1</bitWidth>
17352      </field>
17353      <field>
17354       <name>HFC_EN</name>
17355       <description>Enables/disables hardware flow control</description>
17356       <bitOffset>13</bitOffset>
17357       <bitWidth>1</bitWidth>
17358      </field>
17359      <field>
17360       <name>RTSDC</name>
17361       <description>Hardware Flow Control RTS Mode</description>
17362       <bitOffset>14</bitOffset>
17363       <bitWidth>1</bitWidth>
17364      </field>
17365      <field>
17366       <name>BCLKEN</name>
17367       <description>Baud clock enable</description>
17368       <bitOffset>15</bitOffset>
17369       <bitWidth>1</bitWidth>
17370      </field>
17371      <field>
17372       <name>BCLKSRC</name>
17373       <description>To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock.</description>
17374       <bitOffset>16</bitOffset>
17375       <bitWidth>2</bitWidth>
17376       <enumeratedValues>
17377        <enumeratedValue>
17378         <name>Peripheral_Clock</name>
17379         <description>apb clock</description>
17380         <value>0</value>
17381        </enumeratedValue>
17382        <enumeratedValue>
17383         <name>External_Clock</name>
17384         <description>Clock 1</description>
17385         <value>1</value>
17386        </enumeratedValue>
17387        <enumeratedValue>
17388         <name>CLK2</name>
17389         <description>Clock 2</description>
17390         <value>2</value>
17391        </enumeratedValue>
17392        <enumeratedValue>
17393         <name>CLK3</name>
17394         <description>Clock 3</description>
17395         <value>3</value>
17396        </enumeratedValue>
17397       </enumeratedValues>
17398      </field>
17399      <field>
17400       <name>DPFE_EN</name>
17401       <description>Data/Parity bit frame error detection enable</description>
17402       <bitOffset>18</bitOffset>
17403       <bitWidth>1</bitWidth>
17404      </field>
17405      <field>
17406       <name>BCLKRDY</name>
17407       <description>Baud clock Ready read only bit</description>
17408       <bitOffset>19</bitOffset>
17409       <bitWidth>1</bitWidth>
17410      </field>
17411      <field>
17412       <name>UCAGM</name>
17413       <description>UART Clock Auto Gating mode</description>
17414       <bitOffset>20</bitOffset>
17415       <bitWidth>1</bitWidth>
17416      </field>
17417      <field>
17418       <name>FDM</name>
17419       <description>Fractional Division Mode</description>
17420       <bitOffset>21</bitOffset>
17421       <bitWidth>1</bitWidth>
17422      </field>
17423      <field>
17424       <name>DESM</name>
17425       <description>RX Dual Edge Sampling Mode</description>
17426       <bitOffset>22</bitOffset>
17427       <bitWidth>1</bitWidth>
17428      </field>
17429     </fields>
17430    </register>
17431    <register>
17432     <name>STATUS</name>
17433     <description>Status register</description>
17434     <addressOffset>0x0004</addressOffset>
17435     <access>read-only</access>
17436     <fields>
17437      <field>
17438       <name>TX_BUSY</name>
17439       <description>Read-only flag indicating the UART transmit status</description>
17440       <bitOffset>0</bitOffset>
17441       <bitWidth>1</bitWidth>
17442      </field>
17443      <field>
17444       <name>RX_BUSY</name>
17445       <description>Read-only flag indicating the UART receiver status</description>
17446       <bitOffset>1</bitOffset>
17447       <bitWidth>1</bitWidth>
17448      </field>
17449      <field>
17450       <name>RX_EM</name>
17451       <description>Read-only flag indicating the RX FIFO state</description>
17452       <bitOffset>4</bitOffset>
17453       <bitWidth>1</bitWidth>
17454      </field>
17455      <field>
17456       <name>RX_FULL</name>
17457       <description>Read-only flag indicating the RX FIFO state</description>
17458       <bitOffset>5</bitOffset>
17459       <bitWidth>1</bitWidth>
17460      </field>
17461      <field>
17462       <name>TX_EM</name>
17463       <description>Read-only flag indicating the TX FIFO state</description>
17464       <bitOffset>6</bitOffset>
17465       <bitWidth>1</bitWidth>
17466      </field>
17467      <field>
17468       <name>TX_FULL</name>
17469       <description>Read-only flag indicating the TX FIFO state</description>
17470       <bitOffset>7</bitOffset>
17471       <bitWidth>1</bitWidth>
17472      </field>
17473      <field>
17474       <name>RX_LVL</name>
17475       <description>Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) </description>
17476       <bitOffset>8</bitOffset>
17477       <bitWidth>4</bitWidth>
17478      </field>
17479      <field>
17480       <name>TX_LVL</name>
17481       <description>Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) </description>
17482       <bitOffset>12</bitOffset>
17483       <bitWidth>4</bitWidth>
17484      </field>
17485     </fields>
17486    </register>
17487    <register>
17488     <name>INT_EN</name>
17489     <description>Interrupt Enable control register</description>
17490     <addressOffset>0x0008</addressOffset>
17491     <fields>
17492      <field>
17493       <name>RX_FERR</name>
17494       <description>Enable Interrupt For RX Frame Error</description>
17495       <bitOffset>0</bitOffset>
17496       <bitWidth>1</bitWidth>
17497      </field>
17498      <field>
17499       <name>RX_PAR</name>
17500       <description>Enable Interrupt For RX Parity Error</description>
17501       <bitOffset>1</bitOffset>
17502       <bitWidth>1</bitWidth>
17503      </field>
17504      <field>
17505       <name>CTS_EV</name>
17506       <description>Enable Interrupt For CTS signal change Error</description>
17507       <bitOffset>2</bitOffset>
17508       <bitWidth>1</bitWidth>
17509      </field>
17510      <field>
17511       <name>RX_OV</name>
17512       <description>Enable Interrupt For RX FIFO Overrun Error</description>
17513       <bitOffset>3</bitOffset>
17514       <bitWidth>1</bitWidth>
17515      </field>
17516      <field>
17517       <name>RX_THD</name>
17518       <description>Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD</description>
17519       <bitOffset>4</bitOffset>
17520       <bitWidth>1</bitWidth>
17521      </field>
17522      <field>
17523       <name>TX_OB</name>
17524       <description>Enable Interrupt For TX FIFO has one byte remaining</description>
17525       <bitOffset>5</bitOffset>
17526       <bitWidth>1</bitWidth>
17527      </field>
17528      <field>
17529       <name>TX_HE</name>
17530       <description>Enable Interrupt For TX FIFO has half empty</description>
17531       <bitOffset>6</bitOffset>
17532       <bitWidth>1</bitWidth>
17533      </field>
17534     </fields>
17535    </register>
17536    <register>
17537     <name>INT_FL</name>
17538     <description>Interrupt status flags Control register</description>
17539     <addressOffset>0x000C</addressOffset>
17540     <fields>
17541      <field>
17542       <name>RX_FERR</name>
17543       <description>Flag for RX Frame Error Interrupt.</description>
17544       <bitOffset>0</bitOffset>
17545       <bitWidth>1</bitWidth>
17546      </field>
17547      <field>
17548       <name>RX_PAR</name>
17549       <description>Flag for RX Parity Error interrupt</description>
17550       <bitOffset>1</bitOffset>
17551       <bitWidth>1</bitWidth>
17552      </field>
17553      <field>
17554       <name>CTS_EV</name>
17555       <description>Flag for CTS signal change interrupt (hardware flow control disabled) </description>
17556       <bitOffset>2</bitOffset>
17557       <bitWidth>1</bitWidth>
17558      </field>
17559      <field>
17560       <name>RX_OV</name>
17561       <description>Flag for RX FIFO Overrun interrupt</description>
17562       <bitOffset>3</bitOffset>
17563       <bitWidth>1</bitWidth>
17564      </field>
17565      <field>
17566       <name>RX_THD</name>
17567       <description>Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field</description>
17568       <bitOffset>4</bitOffset>
17569       <bitWidth>1</bitWidth>
17570      </field>
17571      <field>
17572       <name>TX_OB</name>
17573       <description>Flag for interrupt when TX FIFO has one byte remaining</description>
17574       <bitOffset>5</bitOffset>
17575       <bitWidth>1</bitWidth>
17576      </field>
17577      <field>
17578       <name>TX_HE</name>
17579       <description>Flag for interrupt when TX FIFO is half empty</description>
17580       <bitOffset>6</bitOffset>
17581       <bitWidth>1</bitWidth>
17582      </field>
17583     </fields>
17584    </register>
17585    <register>
17586     <name>CLKDIV</name>
17587     <description>Clock Divider register</description>
17588     <addressOffset>0x0010</addressOffset>
17589     <fields>
17590      <field>
17591       <name>CLKDIV</name>
17592       <description>Baud rate divisor value</description>
17593       <bitOffset>0</bitOffset>
17594       <bitWidth>20</bitWidth>
17595      </field>
17596     </fields>
17597    </register>
17598    <register>
17599     <name>OSR</name>
17600     <description>Over Sampling Rate register</description>
17601     <addressOffset>0x0014</addressOffset>
17602     <fields>
17603      <field>
17604       <name>OSR</name>
17605       <description>OSR</description>
17606       <bitOffset>0</bitOffset>
17607       <bitWidth>3</bitWidth>
17608      </field>
17609     </fields>
17610    </register>
17611    <register>
17612     <name>TXPEEK</name>
17613     <description>TX FIFO Output Peek register</description>
17614     <addressOffset>0x0018</addressOffset>
17615     <fields>
17616      <field>
17617       <name>DATA</name>
17618       <description>Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field.</description>
17619       <bitOffset>0</bitOffset>
17620       <bitWidth>8</bitWidth>
17621      </field>
17622     </fields>
17623    </register>
17624    <register>
17625     <name>PNR</name>
17626     <description> Pin register</description>
17627     <addressOffset>0x001C</addressOffset>
17628     <fields>
17629      <field>
17630       <name>CTS</name>
17631       <description>Current sampled value of CTS IO</description>
17632       <bitOffset>0</bitOffset>
17633       <bitWidth>1</bitWidth>
17634       <access>read-only</access>
17635      </field>
17636      <field>
17637       <name>RTS</name>
17638       <description>This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level.</description>
17639       <bitOffset>1</bitOffset>
17640       <bitWidth>1</bitWidth>
17641      </field>
17642     </fields>
17643    </register>
17644    <register>
17645     <name>FIFO</name>
17646     <description>FIFO Read/Write register</description>
17647     <addressOffset>0x0020</addressOffset>
17648     <fields>
17649      <field>
17650       <name>DATA</name>
17651       <description>Load/unload location for TX and RX FIFO buffers.</description>
17652       <bitOffset>0</bitOffset>
17653       <bitWidth>8</bitWidth>
17654      </field>
17655      <field>
17656       <name>RX_PAR</name>
17657       <description>Parity error flag for next byte to be read from FIFO.</description>
17658       <bitOffset>8</bitOffset>
17659       <bitWidth>1</bitWidth>
17660      </field>
17661     </fields>
17662    </register>
17663    <register>
17664     <name>DMA</name>
17665     <description>DMA Configuration register</description>
17666     <addressOffset>0x0030</addressOffset>
17667     <fields>
17668      <field>
17669       <name>TX_THD_VAL</name>
17670       <description>TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory.</description>
17671       <bitOffset>0</bitOffset>
17672       <bitWidth>4</bitWidth>
17673      </field>
17674      <field>
17675       <name>TX_EN</name>
17676       <description>TX DMA channel enable</description>
17677       <bitOffset>4</bitOffset>
17678       <bitWidth>1</bitWidth>
17679      </field>
17680      <field>
17681       <name>RX_THD_VAL</name>
17682       <description>Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory.</description>
17683       <bitOffset>5</bitOffset>
17684       <bitWidth>4</bitWidth>
17685      </field>
17686      <field>
17687       <name>RX_EN</name>
17688       <description>RX DMA channel enable</description>
17689       <bitOffset>9</bitOffset>
17690       <bitWidth>1</bitWidth>
17691      </field>
17692     </fields>
17693    </register>
17694    <register>
17695     <name>WKEN</name>
17696     <description>Wake up enable Control register</description>
17697     <addressOffset>0x0034</addressOffset>
17698     <fields>
17699      <field>
17700       <name>RX_NE</name>
17701       <description>Wake-Up Enable for RX FIFO Not Empty</description>
17702       <bitOffset>0</bitOffset>
17703       <bitWidth>1</bitWidth>
17704      </field>
17705      <field>
17706       <name>RX_FULL</name>
17707       <description>Wake-Up Enable for RX FIFO Full</description>
17708       <bitOffset>1</bitOffset>
17709       <bitWidth>1</bitWidth>
17710      </field>
17711      <field>
17712       <name>RX_THD</name>
17713       <description>Wake-Up Enable for RX FIFO Threshold Met</description>
17714       <bitOffset>2</bitOffset>
17715       <bitWidth>1</bitWidth>
17716      </field>
17717     </fields>
17718    </register>
17719    <register>
17720     <name>WKFL</name>
17721     <description>Wake up Flags register</description>
17722     <addressOffset>0x0038</addressOffset>
17723     <fields>
17724      <field>
17725       <name>RX_NE</name>
17726       <description>Wake-Up Flag for RX FIFO Not Empty</description>
17727       <bitOffset>0</bitOffset>
17728       <bitWidth>1</bitWidth>
17729      </field>
17730      <field>
17731       <name>RX_FULL</name>
17732       <description>Wake-Up Flag for RX FIFO Full</description>
17733       <bitOffset>1</bitOffset>
17734       <bitWidth>1</bitWidth>
17735      </field>
17736      <field>
17737       <name>RX_THD</name>
17738       <description>Wake-Up Flag for RX FIFO Threshold Met</description>
17739       <bitOffset>2</bitOffset>
17740       <bitWidth>1</bitWidth>
17741      </field>
17742     </fields>
17743    </register>
17744   </registers>
17745  </peripheral>
17746<!--UART UART Low Power Registers-->
17747  <peripheral derivedFrom="UART">
17748   <name>UART1</name>
17749   <description>UART Low Power Registers 1</description>
17750   <baseAddress>0x40043000</baseAddress>
17751  </peripheral>
17752<!--UART1 UART Low Power Registers 1-->
17753  <peripheral derivedFrom="UART">
17754   <name>UART2</name>
17755   <description>UART Low Power Registers 2</description>
17756   <baseAddress>0x40044000</baseAddress>
17757  </peripheral>
17758<!--UART2 UART Low Power Registers 2-->
17759  <peripheral derivedFrom="UART">
17760   <name>UART3</name>
17761   <description>UART Low Power Registers 3</description>
17762   <baseAddress>0x40081400</baseAddress>
17763  </peripheral>
17764<!--UART3 UART Low Power Registers 3-->
17765  <peripheral>
17766   <name>USBHS</name>
17767   <description>USB 2.0 High-speed Controller.</description>
17768   <baseAddress>0x400B1000</baseAddress>
17769   <addressBlock>
17770    <offset>0</offset>
17771    <size>0x1000</size>
17772    <usage>registers</usage>
17773   </addressBlock>
17774   <interrupt>
17775    <name>USB</name>
17776    <value>2</value>
17777   </interrupt>
17778   <registers>
17779    <register>
17780     <name>FADDR</name>
17781     <description>Function address register.</description>
17782     <addressOffset>0x00</addressOffset>
17783     <size>8</size>
17784     <resetMask>0x00</resetMask>
17785     <fields>
17786      <field>
17787       <name>ADDR</name>
17788       <description>Function address for this controller.</description>
17789       <bitOffset>0</bitOffset>
17790       <bitWidth>7</bitWidth>
17791       <access>read-write</access>
17792      </field>
17793      <field>
17794       <name>UPDATE</name>
17795       <description>Set when ADDR is written, cleared when new address takes effect.</description>
17796       <bitOffset>7</bitOffset>
17797       <bitWidth>1</bitWidth>
17798       <access>read-only</access>
17799      </field>
17800     </fields>
17801    </register>
17802    <register>
17803     <name>POWER</name>
17804     <description>Power management register.</description>
17805     <addressOffset>0x01</addressOffset>
17806     <size>8</size>
17807     <fields>
17808      <field>
17809       <name>EN_SUSPENDM</name>
17810       <description>Enable SUSPENDM signal.</description>
17811       <bitOffset>0</bitOffset>
17812       <bitWidth>1</bitWidth>
17813       <access>read-write</access>
17814      </field>
17815      <field>
17816       <name>SUSPEND</name>
17817       <description>Suspend mode detected.</description>
17818       <bitOffset>1</bitOffset>
17819       <bitWidth>1</bitWidth>
17820       <access>read-only</access>
17821      </field>
17822      <field>
17823       <name>RESUME</name>
17824       <description>Generate resume signaling.</description>
17825       <bitOffset>2</bitOffset>
17826       <bitWidth>1</bitWidth>
17827       <access>read-write</access>
17828      </field>
17829      <field>
17830       <name>RESET</name>
17831       <description>Bus reset detected.</description>
17832       <bitOffset>3</bitOffset>
17833       <bitWidth>1</bitWidth>
17834       <access>read-only</access>
17835      </field>
17836      <field>
17837       <name>HS_MODE</name>
17838       <description>High-speed mode detected.</description>
17839       <bitOffset>4</bitOffset>
17840       <bitWidth>1</bitWidth>
17841       <access>read-only</access>
17842      </field>
17843      <field>
17844       <name>HS_ENABLE</name>
17845       <description>High-speed mode enable.</description>
17846       <bitOffset>5</bitOffset>
17847       <bitWidth>1</bitWidth>
17848       <access>read-write</access>
17849      </field>
17850      <field>
17851       <name>SOFTCONN</name>
17852       <description>Softconn.</description>
17853       <bitOffset>6</bitOffset>
17854       <bitWidth>1</bitWidth>
17855       <access>read-write</access>
17856      </field>
17857      <field>
17858       <name>ISO_UPDATE</name>
17859       <description>Wait for SOF during Isochronous xfers.</description>
17860       <bitOffset>7</bitOffset>
17861       <bitWidth>1</bitWidth>
17862       <access>read-write</access>
17863      </field>
17864     </fields>
17865    </register>
17866    <register>
17867     <name>INTRIN</name>
17868     <description>Interrupt register for EP0 and IN EP1-15.</description>
17869     <addressOffset>0x02</addressOffset>
17870     <size>16</size>
17871     <fields>
17872      <field>
17873       <name>EP15_IN_INT</name>
17874       <description>Endpoint 15 interrupt.</description>
17875       <bitOffset>15</bitOffset>
17876       <bitWidth>1</bitWidth>
17877       <access>read-only</access>
17878      </field>
17879      <field>
17880       <name>EP14_IN_INT</name>
17881       <description>Endpoint 14 interrupt.</description>
17882       <bitOffset>14</bitOffset>
17883       <bitWidth>1</bitWidth>
17884       <access>read-only</access>
17885      </field>
17886      <field>
17887       <name>EP13_IN_INT</name>
17888       <description>Endpoint 13 interrupt.</description>
17889       <bitOffset>13</bitOffset>
17890       <bitWidth>1</bitWidth>
17891       <access>read-only</access>
17892      </field>
17893      <field>
17894       <name>EP12_IN_INT</name>
17895       <description>Endpoint 12 interrupt.</description>
17896       <bitOffset>12</bitOffset>
17897       <bitWidth>1</bitWidth>
17898       <access>read-only</access>
17899      </field>
17900      <field>
17901       <name>EP11_IN_INT</name>
17902       <description>Endpoint 11 interrupt.</description>
17903       <bitOffset>11</bitOffset>
17904       <bitWidth>1</bitWidth>
17905       <access>read-only</access>
17906      </field>
17907      <field>
17908       <name>EP10_IN_INT</name>
17909       <description>Endpoint 10 interrupt.</description>
17910       <bitOffset>10</bitOffset>
17911       <bitWidth>1</bitWidth>
17912       <access>read-only</access>
17913      </field>
17914      <field>
17915       <name>EP9_IN_INT</name>
17916       <description>Endpoint 9 interrupt.</description>
17917       <bitOffset>9</bitOffset>
17918       <bitWidth>1</bitWidth>
17919       <access>read-only</access>
17920      </field>
17921      <field>
17922       <name>EP8_IN_INT</name>
17923       <description>Endpoint 8 interrupt.</description>
17924       <bitOffset>8</bitOffset>
17925       <bitWidth>1</bitWidth>
17926       <access>read-only</access>
17927      </field>
17928      <field>
17929       <name>EP7_IN_INT</name>
17930       <description>Endpoint 7 interrupt.</description>
17931       <bitOffset>7</bitOffset>
17932       <bitWidth>1</bitWidth>
17933       <access>read-only</access>
17934      </field>
17935      <field>
17936       <name>EP6_IN_INT</name>
17937       <description>Endpoint 6 interrupt.</description>
17938       <bitOffset>6</bitOffset>
17939       <bitWidth>1</bitWidth>
17940       <access>read-only</access>
17941      </field>
17942      <field>
17943       <name>EP5_IN_INT</name>
17944       <description>Endpoint 5 interrupt.</description>
17945       <bitOffset>5</bitOffset>
17946       <bitWidth>1</bitWidth>
17947       <access>read-only</access>
17948      </field>
17949      <field>
17950       <name>EP4_IN_INT</name>
17951       <description>Endpoint 4 interrupt.</description>
17952       <bitOffset>4</bitOffset>
17953       <bitWidth>1</bitWidth>
17954       <access>read-only</access>
17955      </field>
17956      <field>
17957       <name>EP3_IN_INT</name>
17958       <description>Endpoint 3 interrupt.</description>
17959       <bitOffset>3</bitOffset>
17960       <bitWidth>1</bitWidth>
17961       <access>read-only</access>
17962      </field>
17963      <field>
17964       <name>EP2_IN_INT</name>
17965       <description>Endpoint 2 interrupt.</description>
17966       <bitOffset>2</bitOffset>
17967       <bitWidth>1</bitWidth>
17968       <access>read-only</access>
17969      </field>
17970      <field>
17971       <name>EP1_IN_INT</name>
17972       <description>Endpoint 1 interrupt.</description>
17973       <bitOffset>1</bitOffset>
17974       <bitWidth>1</bitWidth>
17975       <access>read-only</access>
17976      </field>
17977      <field>
17978       <name>EP0_IN_INT</name>
17979       <description>Endpoint 0 interrupt.</description>
17980       <bitOffset>0</bitOffset>
17981       <bitWidth>1</bitWidth>
17982       <access>read-only</access>
17983      </field>
17984     </fields>
17985    </register>
17986    <register>
17987     <name>INTROUT</name>
17988     <description>Interrupt register for OUT EP 1-15.</description>
17989     <addressOffset>0x04</addressOffset>
17990     <size>16</size>
17991     <fields>
17992      <field>
17993       <name>EP15_OUT_INT</name>
17994       <description>Endpoint 15 interrupt.</description>
17995       <bitOffset>15</bitOffset>
17996       <bitWidth>1</bitWidth>
17997       <access>read-only</access>
17998      </field>
17999      <field>
18000       <name>EP14_OUT_INT</name>
18001       <description>Endpoint 14 interrupt.</description>
18002       <bitOffset>14</bitOffset>
18003       <bitWidth>1</bitWidth>
18004       <access>read-only</access>
18005      </field>
18006      <field>
18007       <name>EP13_OUT_INT</name>
18008       <description>Endpoint 13 interrupt.</description>
18009       <bitOffset>13</bitOffset>
18010       <bitWidth>1</bitWidth>
18011       <access>read-only</access>
18012      </field>
18013      <field>
18014       <name>EP12_OUT_INT</name>
18015       <description>Endpoint 12 interrupt.</description>
18016       <bitOffset>12</bitOffset>
18017       <bitWidth>1</bitWidth>
18018       <access>read-only</access>
18019      </field>
18020      <field>
18021       <name>EP11_OUT_INT</name>
18022       <description>Endpoint 11 interrupt.</description>
18023       <bitOffset>11</bitOffset>
18024       <bitWidth>1</bitWidth>
18025       <access>read-only</access>
18026      </field>
18027      <field>
18028       <name>EP10_OUT_INT</name>
18029       <description>Endpoint 10 interrupt.</description>
18030       <bitOffset>10</bitOffset>
18031       <bitWidth>1</bitWidth>
18032       <access>read-only</access>
18033      </field>
18034      <field>
18035       <name>EP9_OUT_INT</name>
18036       <description>Endpoint 9 interrupt.</description>
18037       <bitOffset>9</bitOffset>
18038       <bitWidth>1</bitWidth>
18039       <access>read-only</access>
18040      </field>
18041      <field>
18042       <name>EP8_OUT_INT</name>
18043       <description>Endpoint 8 interrupt.</description>
18044       <bitOffset>8</bitOffset>
18045       <bitWidth>1</bitWidth>
18046       <access>read-only</access>
18047      </field>
18048      <field>
18049       <name>EP7_OUT_INT</name>
18050       <description>Endpoint 7 interrupt.</description>
18051       <bitOffset>7</bitOffset>
18052       <bitWidth>1</bitWidth>
18053       <access>read-only</access>
18054      </field>
18055      <field>
18056       <name>EP6_OUT_INT</name>
18057       <description>Endpoint 6 interrupt.</description>
18058       <bitOffset>6</bitOffset>
18059       <bitWidth>1</bitWidth>
18060       <access>read-only</access>
18061      </field>
18062      <field>
18063       <name>EP5_OUT_INT</name>
18064       <description>Endpoint 5 interrupt.</description>
18065       <bitOffset>5</bitOffset>
18066       <bitWidth>1</bitWidth>
18067       <access>read-only</access>
18068      </field>
18069      <field>
18070       <name>EP4_OUT_INT</name>
18071       <description>Endpoint 4 interrupt.</description>
18072       <bitOffset>4</bitOffset>
18073       <bitWidth>1</bitWidth>
18074       <access>read-only</access>
18075      </field>
18076      <field>
18077       <name>EP3_OUT_INT</name>
18078       <description>Endpoint 3 interrupt.</description>
18079       <bitOffset>3</bitOffset>
18080       <bitWidth>1</bitWidth>
18081       <access>read-only</access>
18082      </field>
18083      <field>
18084       <name>EP2_OUT_INT</name>
18085       <description>Endpoint 2 interrupt.</description>
18086       <bitOffset>2</bitOffset>
18087       <bitWidth>1</bitWidth>
18088       <access>read-only</access>
18089      </field>
18090      <field>
18091       <name>EP1_OUT_INT</name>
18092       <description>Endpoint 1 interrupt.</description>
18093       <bitOffset>1</bitOffset>
18094       <bitWidth>1</bitWidth>
18095       <access>read-only</access>
18096      </field>
18097     </fields>
18098    </register>
18099    <register>
18100     <name>INTRINEN</name>
18101     <description>Interrupt enable for EP 0 and IN EP 1-15.</description>
18102     <addressOffset>0x06</addressOffset>
18103     <size>16</size>
18104     <fields>
18105      <field>
18106       <name>EP15_IN_INT_EN</name>
18107       <description>Endpoint 15 interrupt enable.</description>
18108       <bitOffset>15</bitOffset>
18109       <bitWidth>1</bitWidth>
18110       <access>read-write</access>
18111      </field>
18112      <field>
18113       <name>EP14_IN_INT_EN</name>
18114       <description>Endpoint 14 interrupt enable.</description>
18115       <bitOffset>14</bitOffset>
18116       <bitWidth>1</bitWidth>
18117       <access>read-write</access>
18118      </field>
18119      <field>
18120       <name>EP13_IN_INT_EN</name>
18121       <description>Endpoint 13 interrupt enable.</description>
18122       <bitOffset>13</bitOffset>
18123       <bitWidth>1</bitWidth>
18124       <access>read-write</access>
18125      </field>
18126      <field>
18127       <name>EP12_IN_INT_EN</name>
18128       <description>Endpoint 12 interrupt enable.</description>
18129       <bitOffset>12</bitOffset>
18130       <bitWidth>1</bitWidth>
18131       <access>read-write</access>
18132      </field>
18133      <field>
18134       <name>EP11_IN_INT_EN</name>
18135       <description>Endpoint 11 interrupt enable.</description>
18136       <bitOffset>11</bitOffset>
18137       <bitWidth>1</bitWidth>
18138       <access>read-write</access>
18139      </field>
18140      <field>
18141       <name>EP10_IN_INT_EN</name>
18142       <description>Endpoint 10 interrupt enable.</description>
18143       <bitOffset>10</bitOffset>
18144       <bitWidth>1</bitWidth>
18145       <access>read-write</access>
18146      </field>
18147      <field>
18148       <name>EP9_IN_INT_EN</name>
18149       <description>Endpoint 9 interrupt enable.</description>
18150       <bitOffset>9</bitOffset>
18151       <bitWidth>1</bitWidth>
18152       <access>read-write</access>
18153      </field>
18154      <field>
18155       <name>EP8_IN_INT_EN</name>
18156       <description>Endpoint 8 interrupt enable.</description>
18157       <bitOffset>8</bitOffset>
18158       <bitWidth>1</bitWidth>
18159       <access>read-write</access>
18160      </field>
18161      <field>
18162       <name>EP7_IN_INT_EN</name>
18163       <description>Endpoint 7 interrupt enable.</description>
18164       <bitOffset>7</bitOffset>
18165       <bitWidth>1</bitWidth>
18166       <access>read-write</access>
18167      </field>
18168      <field>
18169       <name>EP6_IN_INT_EN</name>
18170       <description>Endpoint 6 interrupt enable.</description>
18171       <bitOffset>6</bitOffset>
18172       <bitWidth>1</bitWidth>
18173       <access>read-write</access>
18174      </field>
18175      <field>
18176       <name>EP5_IN_INT_EN</name>
18177       <description>Endpoint 5 interrupt enable.</description>
18178       <bitOffset>5</bitOffset>
18179       <bitWidth>1</bitWidth>
18180       <access>read-write</access>
18181      </field>
18182      <field>
18183       <name>EP4_IN_INT_EN</name>
18184       <description>Endpoint 4 interrupt enable.</description>
18185       <bitOffset>4</bitOffset>
18186       <bitWidth>1</bitWidth>
18187       <access>read-write</access>
18188      </field>
18189      <field>
18190       <name>EP3_IN_INT_EN</name>
18191       <description>Endpoint 3 interrupt enable.</description>
18192       <bitOffset>3</bitOffset>
18193       <bitWidth>1</bitWidth>
18194       <access>read-write</access>
18195      </field>
18196      <field>
18197       <name>EP2_IN_INT_EN</name>
18198       <description>Endpoint 2 interrupt enable.</description>
18199       <bitOffset>2</bitOffset>
18200       <bitWidth>1</bitWidth>
18201       <access>read-write</access>
18202      </field>
18203      <field>
18204       <name>EP1_IN_INT_EN</name>
18205       <description>Endpoint 1 interrupt enable.</description>
18206       <bitOffset>1</bitOffset>
18207       <bitWidth>1</bitWidth>
18208       <access>read-write</access>
18209      </field>
18210      <field>
18211       <name>EP0_INT_EN</name>
18212       <description>Endpoint 0 interrupt enable.</description>
18213       <bitOffset>0</bitOffset>
18214       <bitWidth>1</bitWidth>
18215       <access>read-write</access>
18216      </field>
18217     </fields>
18218    </register>
18219    <register>
18220     <name>INTROUTEN</name>
18221     <description>Interrupt enable for OUT EP 1-15.</description>
18222     <addressOffset>0x08</addressOffset>
18223     <size>16</size>
18224     <fields>
18225      <field>
18226       <name>EP15_OUT_INT_EN</name>
18227       <description>Endpoint 15 interrupt.</description>
18228       <bitOffset>15</bitOffset>
18229       <bitWidth>1</bitWidth>
18230       <access>read-write</access>
18231      </field>
18232      <field>
18233       <name>EP14_OUT_INT_EN</name>
18234       <description>Endpoint 14 interrupt.</description>
18235       <bitOffset>14</bitOffset>
18236       <bitWidth>1</bitWidth>
18237       <access>read-write</access>
18238      </field>
18239      <field>
18240       <name>EP13_OUT_INT_EN</name>
18241       <description>Endpoint 13 interrupt.</description>
18242       <bitOffset>13</bitOffset>
18243       <bitWidth>1</bitWidth>
18244       <access>read-write</access>
18245      </field>
18246      <field>
18247       <name>EP12_OUT_INT_EN</name>
18248       <description>Endpoint 12 interrupt.</description>
18249       <bitOffset>12</bitOffset>
18250       <bitWidth>1</bitWidth>
18251       <access>read-write</access>
18252      </field>
18253      <field>
18254       <name>EP11_OUT_INT_EN</name>
18255       <description>Endpoint 11 interrupt.</description>
18256       <bitOffset>11</bitOffset>
18257       <bitWidth>1</bitWidth>
18258       <access>read-write</access>
18259      </field>
18260      <field>
18261       <name>EP10_OUT_INT_EN</name>
18262       <description>Endpoint 10 interrupt.</description>
18263       <bitOffset>10</bitOffset>
18264       <bitWidth>1</bitWidth>
18265       <access>read-write</access>
18266      </field>
18267      <field>
18268       <name>EP9_OUT_INT_EN</name>
18269       <description>Endpoint 9 interrupt.</description>
18270       <bitOffset>9</bitOffset>
18271       <bitWidth>1</bitWidth>
18272       <access>read-write</access>
18273      </field>
18274      <field>
18275       <name>EP8_OUT_INT_EN</name>
18276       <description>Endpoint 8 interrupt.</description>
18277       <bitOffset>8</bitOffset>
18278       <bitWidth>1</bitWidth>
18279       <access>read-write</access>
18280      </field>
18281      <field>
18282       <name>EP7_OUT_INT_EN</name>
18283       <description>Endpoint 7 interrupt.</description>
18284       <bitOffset>7</bitOffset>
18285       <bitWidth>1</bitWidth>
18286       <access>read-write</access>
18287      </field>
18288      <field>
18289       <name>EP6_OUT_INT_EN</name>
18290       <description>Endpoint 6 interrupt.</description>
18291       <bitOffset>6</bitOffset>
18292       <bitWidth>1</bitWidth>
18293       <access>read-write</access>
18294      </field>
18295      <field>
18296       <name>EP5_OUT_INT_EN</name>
18297       <description>Endpoint 5 interrupt.</description>
18298       <bitOffset>5</bitOffset>
18299       <bitWidth>1</bitWidth>
18300       <access>read-write</access>
18301      </field>
18302      <field>
18303       <name>EP4_OUT_INT_EN</name>
18304       <description>Endpoint 4 interrupt.</description>
18305       <bitOffset>4</bitOffset>
18306       <bitWidth>1</bitWidth>
18307       <access>read-write</access>
18308      </field>
18309      <field>
18310       <name>EP3_OUT_INT_EN</name>
18311       <description>Endpoint 3 interrupt.</description>
18312       <bitOffset>3</bitOffset>
18313       <bitWidth>1</bitWidth>
18314       <access>read-write</access>
18315      </field>
18316      <field>
18317       <name>EP2_OUT_INT_EN</name>
18318       <description>Endpoint 2 interrupt.</description>
18319       <bitOffset>2</bitOffset>
18320       <bitWidth>1</bitWidth>
18321       <access>read-write</access>
18322      </field>
18323      <field>
18324       <name>EP1_OUT_INT_EN</name>
18325       <description>Endpoint 1 interrupt.</description>
18326       <bitOffset>1</bitOffset>
18327       <bitWidth>1</bitWidth>
18328       <access>read-write</access>
18329      </field>
18330     </fields>
18331    </register>
18332    <register>
18333     <name>INTRUSB</name>
18334     <description>Interrupt register for common USB interrupts.</description>
18335     <addressOffset>0x0A</addressOffset>
18336     <size>8</size>
18337     <fields>
18338      <field>
18339       <name>SOF_INT</name>
18340       <description>Start of Frame.</description>
18341       <bitOffset>3</bitOffset>
18342       <bitWidth>1</bitWidth>
18343       <access>read-only</access>
18344      </field>
18345      <field>
18346       <name>RESET_INT</name>
18347       <description>Bus reset detected.</description>
18348       <bitOffset>2</bitOffset>
18349       <bitWidth>1</bitWidth>
18350       <access>read-only</access>
18351      </field>
18352      <field>
18353       <name>RESUME_INT</name>
18354       <description>Resume detected.</description>
18355       <bitOffset>1</bitOffset>
18356       <bitWidth>1</bitWidth>
18357       <access>read-only</access>
18358      </field>
18359      <field>
18360       <name>SUSPEND_INT</name>
18361       <description>Suspend detected.</description>
18362       <bitOffset>0</bitOffset>
18363       <bitWidth>1</bitWidth>
18364       <access>read-only</access>
18365      </field>
18366     </fields>
18367    </register>
18368    <register>
18369     <name>INTRUSBEN</name>
18370     <description>Interrupt enable for common USB interrupts.</description>
18371     <addressOffset>0x0B</addressOffset>
18372     <size>8</size>
18373     <fields>
18374      <field>
18375       <name>SOF_INT_EN</name>
18376       <description>Start of Frame.</description>
18377       <bitOffset>3</bitOffset>
18378       <bitWidth>1</bitWidth>
18379       <access>read-write</access>
18380      </field>
18381      <field>
18382       <name>RESET_INT_EN</name>
18383       <description>Bus reset detected.</description>
18384       <bitOffset>2</bitOffset>
18385       <bitWidth>1</bitWidth>
18386       <access>read-write</access>
18387      </field>
18388      <field>
18389       <name>RESUME_INT_EN</name>
18390       <description>Resume detected.</description>
18391       <bitOffset>1</bitOffset>
18392       <bitWidth>1</bitWidth>
18393       <access>read-write</access>
18394      </field>
18395      <field>
18396       <name>SUSPEND_INT_EN</name>
18397       <description>Suspend detected.</description>
18398       <bitOffset>0</bitOffset>
18399       <bitWidth>1</bitWidth>
18400       <access>read-write</access>
18401      </field>
18402     </fields>
18403    </register>
18404    <register>
18405     <name>FRAME</name>
18406     <description>Frame number.</description>
18407     <addressOffset>0x0C</addressOffset>
18408     <size>16</size>
18409     <fields>
18410      <field>
18411       <name>FRAMENUM</name>
18412       <description>Read the last received frame number, that is the 11-bit frame number received in the SOF packet.</description>
18413       <bitOffset>0</bitOffset>
18414       <bitWidth>11</bitWidth>
18415       <access>read-only</access>
18416      </field>
18417     </fields>
18418    </register>
18419    <register>
18420     <name>INDEX</name>
18421     <description>Index for banked registers.</description>
18422     <addressOffset>0x0E</addressOffset>
18423     <size>8</size>
18424     <fields>
18425      <field>
18426       <name>INDEX</name>
18427       <description>Index Register Access Selector. </description>
18428       <bitOffset>0</bitOffset>
18429       <bitWidth>4</bitWidth>
18430       <access>read-write</access>
18431      </field>
18432     </fields>
18433    </register>
18434    <register>
18435     <name>TESTMODE</name>
18436     <description>USB 2.0 test mode enable register.</description>
18437     <addressOffset>0x0F</addressOffset>
18438     <size>8</size>
18439     <fields>
18440      <field>
18441       <name>FORCE_FS</name>
18442       <description>Force USB to Full-speed after reset.</description>
18443       <bitOffset>5</bitOffset>
18444       <bitWidth>1</bitWidth>
18445       <access>read-write</access>
18446      </field>
18447      <field>
18448       <name>FORCE_HS</name>
18449       <description>Force USB to High-speed after reset.</description>
18450       <bitOffset>4</bitOffset>
18451       <bitWidth>1</bitWidth>
18452       <access>read-write</access>
18453      </field>
18454      <field>
18455       <name>TEST_PKT</name>
18456       <description>Transmit fixed test packet.</description>
18457       <bitOffset>3</bitOffset>
18458       <bitWidth>1</bitWidth>
18459       <access>read-write</access>
18460      </field>
18461      <field>
18462       <name>TEST_K</name>
18463       <description>Force USB to continuous K state.</description>
18464       <bitOffset>2</bitOffset>
18465       <bitWidth>1</bitWidth>
18466       <access>read-write</access>
18467      </field>
18468      <field>
18469       <name>TEST_J</name>
18470       <description>Force USB to continuous J state.</description>
18471       <bitOffset>1</bitOffset>
18472       <bitWidth>1</bitWidth>
18473       <access>read-write</access>
18474      </field>
18475      <field>
18476       <name>TEST_SE0_NAK</name>
18477       <description>Respond to any valid IN token with NAK.</description>
18478       <bitOffset>0</bitOffset>
18479       <bitWidth>1</bitWidth>
18480       <access>read-write</access>
18481      </field>
18482     </fields>
18483    </register>
18484    <register>
18485     <name>INMAXP</name>
18486     <description>Maximum packet size for INx endpoint (x == INDEX).</description>
18487     <addressOffset>0x10</addressOffset>
18488     <size>16</size>
18489     <fields>
18490      <field>
18491       <name>MAXPACKETSIZE</name>
18492       <description>Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9</description>
18493       <bitOffset>0</bitOffset>
18494       <bitWidth>11</bitWidth>
18495      </field>
18496      <field>
18497       <name>NUMPACKMINUS1</name>
18498       <description>Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases. </description>
18499       <bitOffset>11</bitOffset>
18500       <bitWidth>5</bitWidth>
18501      </field>
18502     </fields>
18503    </register>
18504    <register>
18505     <name>CSR0</name>
18506     <description>Control status register for EP 0 (when INDEX == 0).</description>
18507     <addressOffset>0x12</addressOffset>
18508     <size>8</size>
18509     <fields>
18510      <field>
18511       <name>SERV_SETUP_END</name>
18512       <description>Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set </description>
18513       <bitOffset>7</bitOffset>
18514       <bitWidth>1</bitWidth>
18515       <access>read-write</access>
18516      </field>
18517      <field>
18518       <name>SERV_OUTPKTRDY</name>
18519       <description>Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set.</description>
18520       <bitOffset>6</bitOffset>
18521       <bitWidth>1</bitWidth>
18522       <access>read-write</access>
18523      </field>
18524      <field>
18525       <name>SEND_STALL</name>
18526       <description>Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set. </description>
18527       <bitOffset>5</bitOffset>
18528       <bitWidth>1</bitWidth>
18529       <access>read-write</access>
18530      </field>
18531      <field>
18532       <name>SETUP_END</name>
18533       <description>Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear.</description>
18534       <bitOffset>4</bitOffset>
18535       <bitWidth>1</bitWidth>
18536       <access>read-only</access>
18537      </field>
18538      <field>
18539       <name>DATA_END</name>
18540       <description>Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet. </description>
18541       <bitOffset>3</bitOffset>
18542       <bitWidth>1</bitWidth>
18543       <access>read-write</access>
18544      </field>
18545      <field>
18546       <name>SENT_STALL</name>
18547       <description> Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear. </description>
18548       <bitOffset>2</bitOffset>
18549       <bitWidth>1</bitWidth>
18550       <access>read-write</access>
18551      </field>
18552      <field>
18553       <name>INPKTRDY</name>
18554       <description>EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared. </description>
18555       <bitOffset>1</bitOffset>
18556       <bitWidth>1</bitWidth>
18557       <access>read-write</access>
18558      </field>
18559      <field>
18560       <name>OUTPKTRDY</name>
18561       <description>EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO. </description>
18562       <bitOffset>0</bitOffset>
18563       <bitWidth>1</bitWidth>
18564       <access>read-only</access>
18565      </field>
18566     </fields>
18567    </register>
18568    <register>
18569     <name>INCSRL</name>
18570     <description>Control status lower register for INx endpoint (x == INDEX).</description>
18571     <alternateRegister>CSR0</alternateRegister>
18572     <addressOffset>0x12</addressOffset>
18573     <size>8</size>
18574     <fields>
18575      <field>
18576       <name>INCOMPTX</name>
18577       <description>Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear.</description>
18578       <bitOffset>7</bitOffset>
18579       <bitWidth>1</bitWidth>
18580       <access>read-write</access>
18581      </field>
18582      <field>
18583       <name>CLRDATATOG</name>
18584       <description>Write 1 to clear IN endpoint data-toggle to 0.</description>
18585       <bitOffset>6</bitOffset>
18586       <bitWidth>1</bitWidth>
18587       <access>read-write</access>
18588      </field>
18589      <field>
18590       <name>SENTSTALL</name>
18591       <description>Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear.</description>
18592       <bitOffset>5</bitOffset>
18593       <bitWidth>1</bitWidth>
18594       <access>read-write</access>
18595      </field>
18596      <field>
18597       <name>SENDSTALL</name>
18598       <description>Send STALL Handshake.</description>
18599       <bitOffset>4</bitOffset>
18600       <bitWidth>1</bitWidth>
18601       <access>read-only</access>
18602       <enumeratedValues>
18603        <enumeratedValue>
18604         <name>terminate</name>
18605         <description>Terminate STALL handhsake</description>
18606         <value>0</value>
18607        </enumeratedValue>
18608        <enumeratedValue>
18609         <name>respond</name>
18610         <description>Respond to an IN token with a STALL handshake</description>
18611         <value>1</value>
18612        </enumeratedValue>
18613       </enumeratedValues>
18614      </field>
18615      <field>
18616       <name>FLUSHFIFO</name>
18617       <description>Flush Next Packet from IN FIFO. Write 1 to clear</description>
18618       <bitOffset>3</bitOffset>
18619       <bitWidth>1</bitWidth>
18620       <access>read-write</access>
18621      </field>
18622      <field>
18623       <name>UNDERRUN</name>
18624       <description>Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear</description>
18625       <bitOffset>2</bitOffset>
18626       <bitWidth>1</bitWidth>
18627       <access>read-write</access>
18628      </field>
18629      <field>
18630       <name>FIFONOTEMPTY</name>
18631       <description>Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear. </description>
18632       <bitOffset>1</bitOffset>
18633       <bitWidth>1</bitWidth>
18634       <access>read-write</access>
18635      </field>
18636      <field>
18637       <name>INPKTRDY</name>
18638       <description>IN Packet Ready. Write a 1 to clear </description>
18639       <bitOffset>0</bitOffset>
18640       <bitWidth>1</bitWidth>
18641       <access>read-only</access>
18642      </field>
18643     </fields>
18644    </register>
18645    <register>
18646     <name>INCSRU</name>
18647     <description>Control status upper register for INx endpoint (x == INDEX).</description>
18648     <addressOffset>0x13</addressOffset>
18649     <size>8</size>
18650     <fields>
18651      <field>
18652       <name>AUTOSET</name>
18653       <description>Auto Set inpktrdy. </description>
18654       <bitOffset>7</bitOffset>
18655       <bitWidth>1</bitWidth>
18656       <access>read-write</access>
18657       <enumeratedValues>
18658        <enumeratedValue>
18659         <name>set</name>
18660         <description>USBHS_INCSRL_inpktrdy must be set by firmware.</description>
18661         <value>0</value>
18662        </enumeratedValue>
18663        <enumeratedValue>
18664         <name>auto</name>
18665         <description>USBHS_INCSRL_inpktrdy is automatically set. </description>
18666         <value>1</value>
18667        </enumeratedValue>
18668       </enumeratedValues>
18669      </field>
18670      <field>
18671       <name>ISO</name>
18672       <description>Isochronous Transfer Enable</description>
18673       <bitOffset>6</bitOffset>
18674       <bitWidth>1</bitWidth>
18675       <access>read-write</access>
18676       <enumeratedValues>
18677        <enumeratedValue>
18678         <name>interrupt</name>
18679         <description>Enable IN Bulk and IN interrupt transfers.</description>
18680         <value>0</value>
18681        </enumeratedValue>
18682        <enumeratedValue>
18683         <name>isochronous</name>
18684         <description>Enable IN Isochronous transfers. </description>
18685         <value>1</value>
18686        </enumeratedValue>
18687       </enumeratedValues>
18688      </field>
18689      <field>
18690       <name>MODE</name>
18691       <description> Endpoint Direction Mode.</description>
18692       <bitOffset>5</bitOffset>
18693       <bitWidth>1</bitWidth>
18694       <access>read-write</access>
18695       <enumeratedValues>
18696        <enumeratedValue>
18697         <name>out</name>
18698         <description>Endpoint direction is OUT.</description>
18699         <value>0</value>
18700        </enumeratedValue>
18701        <enumeratedValue>
18702         <name>in</name>
18703         <description>Endpoint direction is IN. </description>
18704         <value>1</value>
18705        </enumeratedValue>
18706       </enumeratedValues>
18707      </field>
18708      <field>
18709       <name>FRCDATATOG</name>
18710       <description> Force In Data - Toggle</description>
18711       <bitOffset>3</bitOffset>
18712       <bitWidth>1</bitWidth>
18713       <access>read-write</access>
18714       <enumeratedValues>
18715        <enumeratedValue>
18716         <name>received</name>
18717         <description>Toggle data-toglge only when an ACK is received.</description>
18718         <value>0</value>
18719        </enumeratedValue>
18720        <enumeratedValue>
18721         <name>dontcare</name>
18722         <description>Toggle data-toggle regardless of ACK. </description>
18723         <value>1</value>
18724        </enumeratedValue>
18725       </enumeratedValues>
18726      </field>
18727      <field>
18728       <name>DPKTBUFDIS</name>
18729       <description> Double Packet Buffering Disable </description>
18730       <bitOffset>1</bitOffset>
18731       <bitWidth>1</bitWidth>
18732       <access>read-write</access>
18733       <enumeratedValues>
18734        <enumeratedValue>
18735         <name>en</name>
18736         <description>Enable Double packet buffering.</description>
18737         <value>0</value>
18738        </enumeratedValue>
18739        <enumeratedValue>
18740         <name>dis</name>
18741         <description>Disable Double Packet Buffering.</description>
18742         <value>1</value>
18743        </enumeratedValue>
18744       </enumeratedValues>
18745      </field>
18746     </fields>
18747    </register>
18748    <register>
18749     <name>OUTMAXP</name>
18750     <description>Maximum packet size for OUTx endpoint (x == INDEX).</description>
18751     <addressOffset>0x14</addressOffset>
18752     <size>16</size>
18753     <fields>
18754      <field>
18755       <name>NUMPACKMINUS1</name>
18756       <description>Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize. </description>
18757       <bitOffset>11</bitOffset>
18758       <bitWidth>5</bitWidth>
18759      </field>
18760      <field>
18761       <name>MAXPACKETSIZE</name>
18762       <description>Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9.</description>
18763       <bitOffset>0</bitOffset>
18764       <bitWidth>11</bitWidth>
18765      </field>
18766     </fields>
18767    </register>
18768    <register>
18769     <name>OUTCSRL</name>
18770     <description>Control status lower register for OUTx endpoint (x == INDEX).</description>
18771     <addressOffset>0x16</addressOffset>
18772     <size>8</size>
18773     <fields>
18774      <field>
18775       <name>CLRDATATOG</name>
18776       <bitOffset>7</bitOffset>
18777       <bitWidth>1</bitWidth>
18778       <access>read-write</access>
18779      </field>
18780      <field>
18781       <name>SENTSTALL</name>
18782       <bitOffset>6</bitOffset>
18783       <bitWidth>1</bitWidth>
18784       <access>read-write</access>
18785      </field>
18786      <field>
18787       <name>SENDSTALL</name>
18788       <bitOffset>5</bitOffset>
18789       <bitWidth>1</bitWidth>
18790       <access>read-write</access>
18791      </field>
18792      <field>
18793       <name>FLUSHFIFO</name>
18794       <bitOffset>4</bitOffset>
18795       <bitWidth>1</bitWidth>
18796       <access>read-write</access>
18797      </field>
18798      <field>
18799       <name>DATAERROR</name>
18800       <bitOffset>3</bitOffset>
18801       <bitWidth>1</bitWidth>
18802       <access>read-only</access>
18803      </field>
18804      <field>
18805       <name>OVERRUN</name>
18806       <bitOffset>2</bitOffset>
18807       <bitWidth>1</bitWidth>
18808       <access>read-write</access>
18809      </field>
18810      <field>
18811       <name>FIFOFULL</name>
18812       <bitOffset>1</bitOffset>
18813       <bitWidth>1</bitWidth>
18814       <access>read-only</access>
18815      </field>
18816      <field>
18817       <name>OUTPKTRDY</name>
18818       <bitOffset>0</bitOffset>
18819       <bitWidth>1</bitWidth>
18820       <access>read-write</access>
18821      </field>
18822     </fields>
18823    </register>
18824    <register>
18825     <name>OUTCSRU</name>
18826     <description>Control status upper register for OUTx endpoint (x == INDEX).</description>
18827     <addressOffset>0x17</addressOffset>
18828     <size>8</size>
18829     <fields>
18830      <field>
18831       <name>AUTOCLEAR</name>
18832       <bitOffset>7</bitOffset>
18833       <bitWidth>1</bitWidth>
18834       <access>read-write</access>
18835      </field>
18836      <field>
18837       <name>ISO</name>
18838       <bitOffset>6</bitOffset>
18839       <bitWidth>1</bitWidth>
18840       <access>read-write</access>
18841      </field>
18842      <field>
18843       <name>DISNYET</name>
18844       <bitOffset>4</bitOffset>
18845       <bitWidth>1</bitWidth>
18846       <access>read-write</access>
18847      </field>
18848      <field>
18849       <name>DPKTBUFDIS</name>
18850       <bitOffset>1</bitOffset>
18851       <bitWidth>1</bitWidth>
18852       <access>read-write</access>
18853      </field>
18854      <field>
18855       <name>INCOMPRX</name>
18856       <bitOffset>0</bitOffset>
18857       <bitWidth>1</bitWidth>
18858       <access>read-only</access>
18859      </field>
18860     </fields>
18861    </register>
18862    <register>
18863     <name>COUNT0</name>
18864     <description>Number of received bytes in EP 0 FIFO (INDEX == 0).</description>
18865     <addressOffset>0x18</addressOffset>
18866     <size>16</size>
18867     <fields>
18868      <field>
18869       <name>COUNT0</name>
18870       <description>Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1 </description>
18871       <bitOffset>0</bitOffset>
18872       <bitWidth>7</bitWidth>
18873       <access>read-only</access>
18874      </field>
18875     </fields>
18876    </register>
18877    <register>
18878     <name>OUTCOUNT</name>
18879     <description>Number of received bytes in OUT EPx FIFO (x == INDEX).</description>
18880     <alternateRegister>COUNT0</alternateRegister>
18881     <addressOffset>0x18</addressOffset>
18882     <size>16</size>
18883     <fields>
18884      <field>
18885       <name>OUTCOUNT</name>
18886       <description>Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO. </description>
18887       <bitOffset>0</bitOffset>
18888       <bitWidth>13</bitWidth>
18889       <access>read-only</access>
18890      </field>
18891     </fields>
18892    </register>
18893    <register>
18894     <name>FIFO0</name>
18895     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
18896     <addressOffset>0x20</addressOffset>
18897     <fields>
18898      <field>
18899       <name>USBHS_FIFO0</name>
18900       <description>USBHS Endpoint FIFO Read/Write Register.</description>
18901       <bitOffset>0</bitOffset>
18902       <bitWidth>32</bitWidth>
18903      </field>
18904     </fields>
18905    </register>
18906    <register>
18907     <name>FIFO1</name>
18908     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
18909     <addressOffset>0x24</addressOffset>
18910     <fields>
18911      <field>
18912       <name>USBHS_FIFO1</name>
18913       <description>USBHS Endpoint FIFO Read/Write Register.</description>
18914       <bitOffset>0</bitOffset>
18915       <bitWidth>32</bitWidth>
18916      </field>
18917     </fields>
18918    </register>
18919    <register>
18920     <name>FIFO2</name>
18921     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
18922     <addressOffset>0x28</addressOffset>
18923     <fields>
18924      <field>
18925       <name>USBHS_FIFO2</name>
18926       <description>USBHS Endpoint FIFO Read/Write Register.</description>
18927       <bitOffset>0</bitOffset>
18928       <bitWidth>32</bitWidth>
18929      </field>
18930     </fields>
18931    </register>
18932    <register>
18933     <name>FIFO3</name>
18934     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
18935     <addressOffset>0x2c</addressOffset>
18936     <fields>
18937      <field>
18938       <name>USBHS_FIFO3</name>
18939       <description>USBHS Endpoint FIFO Read/Write Register.</description>
18940       <bitOffset>0</bitOffset>
18941       <bitWidth>32</bitWidth>
18942      </field>
18943     </fields>
18944    </register>
18945    <register>
18946     <name>FIFO4</name>
18947     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
18948     <addressOffset>0x30</addressOffset>
18949     <fields>
18950      <field>
18951       <name>USBHS_FIFO4</name>
18952       <description>USBHS Endpoint FIFO Read/Write Register.</description>
18953       <bitOffset>0</bitOffset>
18954       <bitWidth>32</bitWidth>
18955      </field>
18956     </fields>
18957    </register>
18958    <register>
18959     <name>FIFO5</name>
18960     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
18961     <addressOffset>0x34</addressOffset>
18962     <fields>
18963      <field>
18964       <name>USBHS_FIFO5</name>
18965       <description>USBHS Endpoint FIFO Read/Write Register.</description>
18966       <bitOffset>0</bitOffset>
18967       <bitWidth>32</bitWidth>
18968      </field>
18969     </fields>
18970    </register>
18971    <register>
18972     <name>FIFO6</name>
18973     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
18974     <addressOffset>0x38</addressOffset>
18975     <fields>
18976      <field>
18977       <name>USBHS_FIFO6</name>
18978       <description>USBHS Endpoint FIFO Read/Write Register.</description>
18979       <bitOffset>0</bitOffset>
18980       <bitWidth>32</bitWidth>
18981      </field>
18982     </fields>
18983    </register>
18984    <register>
18985     <name>FIFO7</name>
18986     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
18987     <addressOffset>0x3c</addressOffset>
18988     <fields>
18989      <field>
18990       <name>USBHS_FIFO7</name>
18991       <description>USBHS Endpoint FIFO Read/Write Register.</description>
18992       <bitOffset>0</bitOffset>
18993       <bitWidth>32</bitWidth>
18994      </field>
18995     </fields>
18996    </register>
18997    <register>
18998     <name>FIFO8</name>
18999     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
19000     <addressOffset>0x40</addressOffset>
19001     <fields>
19002      <field>
19003       <name>USBHS_FIFO8</name>
19004       <description>USBHS Endpoint FIFO Read/Write Register.</description>
19005       <bitOffset>0</bitOffset>
19006       <bitWidth>32</bitWidth>
19007      </field>
19008     </fields>
19009    </register>
19010    <register>
19011     <name>FIFO9</name>
19012     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
19013     <addressOffset>0x44</addressOffset>
19014     <fields>
19015      <field>
19016       <name>USBHS_FIFO9</name>
19017       <description>USBHS Endpoint FIFO Read/Write Register.</description>
19018       <bitOffset>0</bitOffset>
19019       <bitWidth>32</bitWidth>
19020      </field>
19021     </fields>
19022    </register>
19023    <register>
19024     <name>FIFO10</name>
19025     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
19026     <addressOffset>0x48</addressOffset>
19027     <fields>
19028      <field>
19029       <name>USBHS_FIFO10</name>
19030       <description>USBHS Endpoint FIFO Read/Write Register.</description>
19031       <bitOffset>0</bitOffset>
19032       <bitWidth>32</bitWidth>
19033      </field>
19034     </fields>
19035    </register>
19036    <register>
19037     <name>FIFO11</name>
19038     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
19039     <addressOffset>0x4c</addressOffset>
19040     <fields>
19041      <field>
19042       <name>USBHS_FIFO11</name>
19043       <description>USBHS Endpoint FIFO Read/Write Register.</description>
19044       <bitOffset>0</bitOffset>
19045       <bitWidth>32</bitWidth>
19046      </field>
19047     </fields>
19048    </register>
19049    <register>
19050     <name>FIFO12</name>
19051     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
19052     <addressOffset>0x50</addressOffset>
19053     <fields>
19054      <field>
19055       <name>USBHS_FIFO12</name>
19056       <description>USBHS Endpoint FIFO Read/Write Register.</description>
19057       <bitOffset>0</bitOffset>
19058       <bitWidth>32</bitWidth>
19059      </field>
19060     </fields>
19061    </register>
19062    <register>
19063     <name>FIFO13</name>
19064     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
19065     <addressOffset>0x54</addressOffset>
19066     <fields>
19067      <field>
19068       <name>USBHS_FIFO13</name>
19069       <description>USBHS Endpoint FIFO Read/Write Register.</description>
19070       <bitOffset>0</bitOffset>
19071       <bitWidth>32</bitWidth>
19072      </field>
19073     </fields>
19074    </register>
19075    <register>
19076     <name>FIFO14</name>
19077     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
19078     <addressOffset>0x58</addressOffset>
19079     <fields>
19080      <field>
19081       <name>USBHS_FIFO14</name>
19082       <description>USBHS Endpoint FIFO Read/Write Register.</description>
19083       <bitOffset>0</bitOffset>
19084       <bitWidth>32</bitWidth>
19085      </field>
19086     </fields>
19087    </register>
19088    <register>
19089     <name>FIFO15</name>
19090     <description>Read for OUT data FIFO, write for IN data FIFO.</description>
19091     <addressOffset>0x5c</addressOffset>
19092     <fields>
19093      <field>
19094       <name>USBHS_FIFO15</name>
19095       <description>USBHS Endpoint FIFO Read/Write Register.</description>
19096       <bitOffset>0</bitOffset>
19097       <bitWidth>32</bitWidth>
19098      </field>
19099     </fields>
19100    </register>
19101    <register>
19102     <name>HWVERS</name>
19103     <description>HWVERS</description>
19104     <addressOffset>0x6c</addressOffset>
19105     <size>16</size>
19106     <fields>
19107      <field>
19108       <name>USBHS_HWVERS</name>
19109       <description>USBHS Register.</description>
19110       <bitOffset>0</bitOffset>
19111       <bitWidth>16</bitWidth>
19112      </field>
19113     </fields>
19114    </register>
19115    <register>
19116     <name>EPINFO</name>
19117     <description>Endpoint hardware information.</description>
19118     <addressOffset>0x78</addressOffset>
19119     <size>8</size>
19120     <fields>
19121      <field>
19122       <name>OUTENDPOINTS</name>
19123       <bitOffset>4</bitOffset>
19124       <bitWidth>4</bitWidth>
19125       <access>read-only</access>
19126      </field>
19127      <field>
19128       <name>INTENDPOINTS</name>
19129       <bitOffset>0</bitOffset>
19130       <bitWidth>4</bitWidth>
19131       <access>read-only</access>
19132      </field>
19133     </fields>
19134    </register>
19135    <register>
19136     <name>RAMINFO</name>
19137     <description>RAM width information.</description>
19138     <addressOffset>0x79</addressOffset>
19139     <size>8</size>
19140     <fields>
19141      <field>
19142       <name>RAMBITS</name>
19143       <bitOffset>0</bitOffset>
19144       <bitWidth>4</bitWidth>
19145       <access>read-only</access>
19146      </field>
19147     </fields>
19148    </register>
19149    <register>
19150     <name>SOFTRESET</name>
19151     <description>Software reset register.</description>
19152     <addressOffset>0x7A</addressOffset>
19153     <size>8</size>
19154     <fields>
19155      <field>
19156       <name>RSTXS</name>
19157       <bitOffset>1</bitOffset>
19158       <bitWidth>1</bitWidth>
19159       <access>read-write</access>
19160      </field>
19161      <field>
19162       <name>RSTS</name>
19163       <bitOffset>0</bitOffset>
19164       <bitWidth>1</bitWidth>
19165       <access>read-write</access>
19166      </field>
19167     </fields>
19168    </register>
19169    <register>
19170     <name>CTUCH</name>
19171     <description>Chirp timeout timer setting.</description>
19172     <addressOffset>0x80</addressOffset>
19173     <size>16</size>
19174     <fields>
19175      <field>
19176       <name>C_T_UCH</name>
19177       <description>HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host. </description>
19178       <bitOffset>0</bitOffset>
19179       <bitWidth>16</bitWidth>
19180      </field>
19181     </fields>
19182    </register>
19183    <register>
19184     <name>CTHSRTN</name>
19185     <description>Sets delay between HS resume to UTM normal operating mode.</description>
19186     <addressOffset>0x82</addressOffset>
19187     <size>16</size>
19188     <fields>
19189      <field>
19190       <name>C_T_HSTRN</name>
19191       <description>High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation.</description>
19192       <bitOffset>0</bitOffset>
19193       <bitWidth>16</bitWidth>
19194      </field>
19195     </fields>
19196    </register>
19197    <register>
19198     <name>MXM_USB_REG_00</name>
19199     <description>MXM_USB_REG_00</description>
19200     <addressOffset>0x400</addressOffset>
19201    </register>
19202    <register>
19203     <name>M31_PHY_UTMI_RESET</name>
19204     <description>M31_PHY_UTMI_RESET</description>
19205     <addressOffset>0x404</addressOffset>
19206    </register>
19207    <register>
19208     <name>M31_PHY_UTMI_VCONTROL</name>
19209     <description>M31_PHY_UTMI_VCONTROL</description>
19210     <addressOffset>0x408</addressOffset>
19211    </register>
19212    <register>
19213     <name>M31_PHY_CLK_EN</name>
19214     <description>M31_PHY_CLK_EN</description>
19215     <addressOffset>0x40C</addressOffset>
19216    </register>
19217    <register>
19218     <name>M31_PHY_PONRST</name>
19219     <description>M31_PHY_PONRST</description>
19220     <addressOffset>0x410</addressOffset>
19221    </register>
19222    <register>
19223     <name>M31_PHY_NONCRY_RSTB</name>
19224     <description>M31_PHY_NONCRY_RSTB</description>
19225     <addressOffset>0x414</addressOffset>
19226    </register>
19227    <register>
19228     <name>M31_PHY_NONCRY_EN</name>
19229     <description>M31_PHY_NONCRY_EN</description>
19230     <addressOffset>0x418</addressOffset>
19231    </register>
19232    <register>
19233     <name>M31_PHY_U2_COMPLIANCE_EN</name>
19234     <description>M31_PHY_U2_COMPLIANCE_EN</description>
19235     <addressOffset>0x420</addressOffset>
19236    </register>
19237    <register>
19238     <name>M31_PHY_U2_COMPLIANCE_DAC_ADJ</name>
19239     <description>M31_PHY_U2_COMPLIANCE_DAC_ADJ</description>
19240     <addressOffset>0x424</addressOffset>
19241    </register>
19242    <register>
19243     <name>M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN</name>
19244     <description>M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN</description>
19245     <addressOffset>0x428</addressOffset>
19246    </register>
19247    <register>
19248     <name>M31_PHY_CLK_RDY</name>
19249     <description>M31_PHY_CLK_RDY</description>
19250     <addressOffset>0x42C</addressOffset>
19251    </register>
19252    <register>
19253     <name>M31_PHY_PLL_EN</name>
19254     <description>M31_PHY_PLL_EN</description>
19255     <addressOffset>0x430</addressOffset>
19256    </register>
19257    <register>
19258     <name>M31_PHY_BIST_OK</name>
19259     <description>M31_PHY_BIST_OK</description>
19260     <addressOffset>0x434</addressOffset>
19261    </register>
19262    <register>
19263     <name>M31_PHY_DATA_OE</name>
19264     <description>M31_PHY_DATA_OE</description>
19265     <addressOffset>0x438</addressOffset>
19266    </register>
19267    <register>
19268     <name>M31_PHY_OSCOUTEN</name>
19269     <description>M31_PHY_OSCOUTEN</description>
19270     <addressOffset>0x43C</addressOffset>
19271    </register>
19272    <register>
19273     <name>M31_PHY_LPM_ALIVE</name>
19274     <description>M31_PHY_LPM_ALIVE</description>
19275     <addressOffset>0x440</addressOffset>
19276    </register>
19277    <register>
19278     <name>M31_PHY_HS_BIST_MODE</name>
19279     <description>M31_PHY_HS_BIST_MODE</description>
19280     <addressOffset>0x444</addressOffset>
19281    </register>
19282    <register>
19283     <name>M31_PHY_CORECLKIN</name>
19284     <description>M31_PHY_CORECLKIN</description>
19285     <addressOffset>0x448</addressOffset>
19286    </register>
19287    <register>
19288     <name>M31_PHY_XTLSEL</name>
19289     <description>M31_PHY_XTLSEL</description>
19290     <addressOffset>0x44C</addressOffset>
19291    </register>
19292    <register>
19293     <name>M31_PHY_LS_EN</name>
19294     <description>M31_PHY_LS_EN</description>
19295     <addressOffset>0x450</addressOffset>
19296    </register>
19297    <register>
19298     <name>M31_PHY_DEBUG_SEL</name>
19299     <description>M31_PHY_DEBUG_SEL</description>
19300     <addressOffset>0x454</addressOffset>
19301    </register>
19302    <register>
19303     <name>M31_PHY_DEBUG_OUT</name>
19304     <description>M31_PHY_DEBUG_OUT</description>
19305     <addressOffset>0x458</addressOffset>
19306    </register>
19307    <register>
19308     <name>M31_PHY_OUTCLKSEL</name>
19309     <description>M31_PHY_OUTCLKSEL</description>
19310     <addressOffset>0x45C</addressOffset>
19311    </register>
19312    <register>
19313     <name>M31_PHY_XCFGI_31_0</name>
19314     <description>M31_PHY_XCFGI_31_0</description>
19315     <addressOffset>0x460</addressOffset>
19316    </register>
19317    <register>
19318     <name>M31_PHY_XCFGI_63_32</name>
19319     <description>M31_PHY_XCFGI_63_32</description>
19320     <addressOffset>0x464</addressOffset>
19321    </register>
19322    <register>
19323     <name>M31_PHY_XCFGI_95_64</name>
19324     <description>M31_PHY_XCFGI_95_64</description>
19325     <addressOffset>0x468</addressOffset>
19326    </register>
19327    <register>
19328     <name>M31_PHY_XCFGI_127_96</name>
19329     <description>M31_PHY_XCFGI_127_96</description>
19330     <addressOffset>0x46C</addressOffset>
19331    </register>
19332    <register>
19333     <name>M31_PHY_XCFGI_137_128</name>
19334     <description>M31_PHY_XCFGI_137_128</description>
19335     <addressOffset>0x470</addressOffset>
19336    </register>
19337    <register>
19338     <name>M31_PHY_XCFG_HS_COARSE_TUNE_NUM</name>
19339     <description>M31_PHY_XCFG_HS_COARSE_TUNE_NUM</description>
19340     <addressOffset>0x474</addressOffset>
19341    </register>
19342    <register>
19343     <name>M31_PHY_XCFG_HS_FINE_TUNE_NUM</name>
19344     <description>M31_PHY_XCFG_HS_FINE_TUNE_NUM</description>
19345     <addressOffset>0x478</addressOffset>
19346    </register>
19347    <register>
19348     <name>M31_PHY_XCFG_FS_COARSE_TUNE_NUM</name>
19349     <description>M31_PHY_XCFG_FS_COARSE_TUNE_NUM</description>
19350     <addressOffset>0x47C</addressOffset>
19351    </register>
19352    <register>
19353     <name>M31_PHY_XCFG_FS_FINE_TUNE_NUM</name>
19354     <description>M31_PHY_XCFG_FS_FINE_TUNE_NUM</description>
19355     <addressOffset>0x480</addressOffset>
19356    </register>
19357    <register>
19358     <name>M31_PHY_XCFG_LOCK_RANGE_MAX</name>
19359     <description>M31_PHY_XCFG_LOCK_RANGE_MAX</description>
19360     <addressOffset>0x484</addressOffset>
19361    </register>
19362    <register>
19363     <name>M31_PHY_XCFGI_LOCK_RANGE_MIN</name>
19364     <description>M31_PHY_XCFGI_LOCK_RANGE_MIN</description>
19365     <addressOffset>0x488</addressOffset>
19366    </register>
19367    <register>
19368     <name>M31_PHY_XCFG_OB_RSEL</name>
19369     <description>M31_PHY_XCFG_OB_RSEL</description>
19370     <addressOffset>0x48C</addressOffset>
19371    </register>
19372    <register>
19373     <name>M31_PHY_XCFG_OC_RSEL</name>
19374     <description>M31_PHY_XCFG_OC_RSEL</description>
19375     <addressOffset>0x490</addressOffset>
19376    </register>
19377    <register>
19378     <name>M31_PHY_XCFGO</name>
19379     <description>M31_PHY_XCFGO</description>
19380     <addressOffset>0x494</addressOffset>
19381    </register>
19382    <register>
19383     <name>MXM_INT</name>
19384     <description>USB Added Maxim Interrupt Flag Register.</description>
19385     <addressOffset>0x498</addressOffset>
19386     <fields>
19387      <field>
19388       <name>VBUS</name>
19389       <description>VBUS</description>
19390       <bitOffset>0</bitOffset>
19391       <bitWidth>1</bitWidth>
19392      </field>
19393      <field>
19394       <name>NOVBUS</name>
19395       <description>NOVBUS</description>
19396       <bitOffset>1</bitOffset>
19397       <bitWidth>1</bitWidth>
19398      </field>
19399     </fields>
19400    </register>
19401    <register>
19402     <name>MXM_INT_EN</name>
19403     <description>USB Added Maxim Interrupt Enable Register.</description>
19404     <addressOffset>0x49C</addressOffset>
19405     <fields>
19406      <field>
19407       <name>VBUS</name>
19408       <description>VBUS</description>
19409       <bitOffset>0</bitOffset>
19410       <bitWidth>1</bitWidth>
19411      </field>
19412      <field>
19413       <name>NOVBUS</name>
19414       <description>NOVBUS</description>
19415       <bitOffset>1</bitOffset>
19416       <bitWidth>1</bitWidth>
19417      </field>
19418     </fields>
19419    </register>
19420    <register>
19421     <name>MXM_SUSPEND</name>
19422     <description>USB Added Maxim Suspend Register.</description>
19423     <addressOffset>0x4A0</addressOffset>
19424     <fields>
19425      <field>
19426       <name>SEL</name>
19427       <description>Suspend register</description>
19428       <bitOffset>0</bitOffset>
19429       <bitWidth>1</bitWidth>
19430      </field>
19431     </fields>
19432    </register>
19433    <register>
19434     <name>MXM_REG_A4</name>
19435     <description>USB Added Maxim Power Status Register</description>
19436     <addressOffset>0x4A4</addressOffset>
19437     <fields>
19438      <field>
19439       <name>VRST_VDDB_N_A</name>
19440       <description>VRST_VDDB_N_A</description>
19441       <bitOffset>0</bitOffset>
19442       <bitWidth>1</bitWidth>
19443      </field>
19444     </fields>
19445    </register>
19446   </registers>
19447  </peripheral>
19448<!--USBHS USB 2.0 High-speed Controller.-->
19449  <peripheral>
19450   <name>WDT</name>
19451   <description>Windowed Watchdog Timer</description>
19452   <baseAddress>0x40003000</baseAddress>
19453   <addressBlock>
19454    <offset>0x00</offset>
19455    <size>0x0400</size>
19456    <usage>registers</usage>
19457   </addressBlock>
19458   <interrupt>
19459    <name>WWDT</name>
19460    <value>1</value>
19461   </interrupt>
19462   <registers>
19463    <register>
19464     <name>CTRL</name>
19465     <description>Watchdog Timer Control Register.</description>
19466     <addressOffset>0x00</addressOffset>
19467     <access>read-write</access>
19468     <fields>
19469      <field>
19470       <name>INT_LATE_VAL</name>
19471       <description>Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description>
19472       <bitOffset>0</bitOffset>
19473       <bitWidth>4</bitWidth>
19474       <enumeratedValues>
19475        <enumeratedValue>
19476         <name>wdt2pow31</name>
19477         <description>2**31 clock cycles.</description>
19478         <value>0</value>
19479        </enumeratedValue>
19480        <enumeratedValue>
19481         <name>wdt2pow30</name>
19482         <description>2**30 clock cycles.</description>
19483         <value>1</value>
19484        </enumeratedValue>
19485        <enumeratedValue>
19486         <name>wdt2pow29</name>
19487         <description>2**29 clock cycles.</description>
19488         <value>2</value>
19489        </enumeratedValue>
19490        <enumeratedValue>
19491         <name>wdt2pow28</name>
19492         <description>2**28 clock cycles.</description>
19493         <value>3</value>
19494        </enumeratedValue>
19495        <enumeratedValue>
19496         <name>wdt2pow27</name>
19497         <description>2^27 clock cycles.</description>
19498         <value>4</value>
19499        </enumeratedValue>
19500        <enumeratedValue>
19501         <name>wdt2pow26</name>
19502         <description>2**26 clock cycles.</description>
19503         <value>5</value>
19504        </enumeratedValue>
19505        <enumeratedValue>
19506         <name>wdt2pow25</name>
19507         <description>2**25 clock cycles.</description>
19508         <value>6</value>
19509        </enumeratedValue>
19510        <enumeratedValue>
19511         <name>wdt2pow24</name>
19512         <description>2**24 clock cycles.</description>
19513         <value>7</value>
19514        </enumeratedValue>
19515        <enumeratedValue>
19516         <name>wdt2pow23</name>
19517         <description>2**23 clock cycles.</description>
19518         <value>8</value>
19519        </enumeratedValue>
19520        <enumeratedValue>
19521         <name>wdt2pow22</name>
19522         <description>2**22 clock cycles.</description>
19523         <value>9</value>
19524        </enumeratedValue>
19525        <enumeratedValue>
19526         <name>wdt2pow21</name>
19527         <description>2**21 clock cycles.</description>
19528         <value>10</value>
19529        </enumeratedValue>
19530        <enumeratedValue>
19531         <name>wdt2pow20</name>
19532         <description>2**20 clock cycles.</description>
19533         <value>11</value>
19534        </enumeratedValue>
19535        <enumeratedValue>
19536         <name>wdt2pow19</name>
19537         <description>2**19 clock cycles.</description>
19538         <value>12</value>
19539        </enumeratedValue>
19540        <enumeratedValue>
19541         <name>wdt2pow18</name>
19542         <description>2**18 clock cycles.</description>
19543         <value>13</value>
19544        </enumeratedValue>
19545        <enumeratedValue>
19546         <name>wdt2pow17</name>
19547         <description>2**17 clock cycles.</description>
19548         <value>14</value>
19549        </enumeratedValue>
19550        <enumeratedValue>
19551         <name>wdt2pow16</name>
19552         <description>2**16 clock cycles.</description>
19553         <value>15</value>
19554        </enumeratedValue>
19555       </enumeratedValues>
19556      </field>
19557      <field>
19558       <name>RST_LATE_VAL</name>
19559       <description>Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description>
19560       <bitOffset>4</bitOffset>
19561       <bitWidth>4</bitWidth>
19562       <enumeratedValues>
19563        <enumeratedValue>
19564         <name>wdt2pow31</name>
19565         <description>2**31 clock cycles.</description>
19566         <value>0</value>
19567        </enumeratedValue>
19568        <enumeratedValue>
19569         <name>wdt2pow30</name>
19570         <description>2**30 clock cycles.</description>
19571         <value>1</value>
19572        </enumeratedValue>
19573        <enumeratedValue>
19574         <name>wdt2pow29</name>
19575         <description>2**29 clock cycles.</description>
19576         <value>2</value>
19577        </enumeratedValue>
19578        <enumeratedValue>
19579         <name>wdt2pow28</name>
19580         <description>2**28 clock cycles.</description>
19581         <value>3</value>
19582        </enumeratedValue>
19583        <enumeratedValue>
19584         <name>wdt2pow27</name>
19585         <description>2^27 clock cycles.</description>
19586         <value>4</value>
19587        </enumeratedValue>
19588        <enumeratedValue>
19589         <name>wdt2pow26</name>
19590         <description>2**26 clock cycles.</description>
19591         <value>5</value>
19592        </enumeratedValue>
19593        <enumeratedValue>
19594         <name>wdt2pow25</name>
19595         <description>2**25 clock cycles.</description>
19596         <value>6</value>
19597        </enumeratedValue>
19598        <enumeratedValue>
19599         <name>wdt2pow24</name>
19600         <description>2**24 clock cycles.</description>
19601         <value>7</value>
19602        </enumeratedValue>
19603        <enumeratedValue>
19604         <name>wdt2pow23</name>
19605         <description>2**23 clock cycles.</description>
19606         <value>8</value>
19607        </enumeratedValue>
19608        <enumeratedValue>
19609         <name>wdt2pow22</name>
19610         <description>2**22 clock cycles.</description>
19611         <value>9</value>
19612        </enumeratedValue>
19613        <enumeratedValue>
19614         <name>wdt2pow21</name>
19615         <description>2**21 clock cycles.</description>
19616         <value>10</value>
19617        </enumeratedValue>
19618        <enumeratedValue>
19619         <name>wdt2pow20</name>
19620         <description>2**20 clock cycles.</description>
19621         <value>11</value>
19622        </enumeratedValue>
19623        <enumeratedValue>
19624         <name>wdt2pow19</name>
19625         <description>2**19 clock cycles.</description>
19626         <value>12</value>
19627        </enumeratedValue>
19628        <enumeratedValue>
19629         <name>wdt2pow18</name>
19630         <description>2**18 clock cycles.</description>
19631         <value>13</value>
19632        </enumeratedValue>
19633        <enumeratedValue>
19634         <name>wdt2pow17</name>
19635         <description>2**17 clock cycles.</description>
19636         <value>14</value>
19637        </enumeratedValue>
19638        <enumeratedValue>
19639         <name>wdt2pow16</name>
19640         <description>2**16 clock cycles.</description>
19641         <value>15</value>
19642        </enumeratedValue>
19643       </enumeratedValues>
19644      </field>
19645      <field>
19646       <name>EN</name>
19647       <description>Windowed Watchdog Timer Enable.</description>
19648       <bitOffset>8</bitOffset>
19649       <bitWidth>1</bitWidth>
19650       <enumeratedValues>
19651        <enumeratedValue>
19652         <name>dis</name>
19653         <description>Disable.</description>
19654         <value>0</value>
19655        </enumeratedValue>
19656        <enumeratedValue>
19657         <name>en</name>
19658         <description>Enable.</description>
19659         <value>1</value>
19660        </enumeratedValue>
19661       </enumeratedValues>
19662      </field>
19663      <field>
19664       <name>INT_LATE</name>
19665       <description>Windowed Watchdog Timer Interrupt Flag Too Late.</description>
19666       <bitOffset>9</bitOffset>
19667       <bitWidth>1</bitWidth>
19668       <enumeratedValues>
19669        <usage>read-write</usage>
19670        <enumeratedValue>
19671         <name>inactive</name>
19672         <description>No interrupt is pending.</description>
19673         <value>0</value>
19674        </enumeratedValue>
19675        <enumeratedValue>
19676         <name>pending</name>
19677         <description>An interrupt is pending.</description>
19678         <value>1</value>
19679        </enumeratedValue>
19680       </enumeratedValues>
19681      </field>
19682      <field>
19683       <name>WDT_INT_EN</name>
19684       <description>Windowed Watchdog Timer Interrupt Enable.</description>
19685       <bitOffset>10</bitOffset>
19686       <bitWidth>1</bitWidth>
19687       <enumeratedValues>
19688        <enumeratedValue>
19689         <name>dis</name>
19690         <description>Disable.</description>
19691         <value>0</value>
19692        </enumeratedValue>
19693        <enumeratedValue>
19694         <name>en</name>
19695         <description>Enable.</description>
19696         <value>1</value>
19697        </enumeratedValue>
19698       </enumeratedValues>
19699      </field>
19700      <field>
19701       <name>WDT_RST_EN</name>
19702       <description>Windowed Watchdog Timer Reset Enable.</description>
19703       <bitOffset>11</bitOffset>
19704       <bitWidth>1</bitWidth>
19705       <enumeratedValues>
19706        <enumeratedValue>
19707         <name>dis</name>
19708         <description>Disable.</description>
19709         <value>0</value>
19710        </enumeratedValue>
19711        <enumeratedValue>
19712         <name>en</name>
19713         <description>Enable.</description>
19714         <value>1</value>
19715        </enumeratedValue>
19716       </enumeratedValues>
19717      </field>
19718      <field>
19719       <name>INT_EARLY</name>
19720       <description>Windowed Watchdog Timer Interrupt Flag Too Soon.</description>
19721       <bitOffset>12</bitOffset>
19722       <bitWidth>1</bitWidth>
19723       <enumeratedValues>
19724        <usage>read-write</usage>
19725        <enumeratedValue>
19726         <name>inactive</name>
19727         <description>No interrupt is pending.</description>
19728         <value>0</value>
19729        </enumeratedValue>
19730        <enumeratedValue>
19731         <name>pending</name>
19732         <description>An interrupt is pending.</description>
19733         <value>1</value>
19734        </enumeratedValue>
19735       </enumeratedValues>
19736      </field>
19737      <field>
19738       <name>INT_EARLY_VAL</name>
19739       <description>Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description>
19740       <bitOffset>16</bitOffset>
19741       <bitWidth>4</bitWidth>
19742       <enumeratedValues>
19743        <enumeratedValue>
19744         <name>wdt2pow31</name>
19745         <description>2**31 clock cycles.</description>
19746         <value>0</value>
19747        </enumeratedValue>
19748        <enumeratedValue>
19749         <name>wdt2pow30</name>
19750         <description>2**30 clock cycles.</description>
19751         <value>1</value>
19752        </enumeratedValue>
19753        <enumeratedValue>
19754         <name>wdt2pow29</name>
19755         <description>2**29 clock cycles.</description>
19756         <value>2</value>
19757        </enumeratedValue>
19758        <enumeratedValue>
19759         <name>wdt2pow28</name>
19760         <description>2**28 clock cycles.</description>
19761         <value>3</value>
19762        </enumeratedValue>
19763        <enumeratedValue>
19764         <name>wdt2pow27</name>
19765         <description>2^27 clock cycles.</description>
19766         <value>4</value>
19767        </enumeratedValue>
19768        <enumeratedValue>
19769         <name>wdt2pow26</name>
19770         <description>2**26 clock cycles.</description>
19771         <value>5</value>
19772        </enumeratedValue>
19773        <enumeratedValue>
19774         <name>wdt2pow25</name>
19775         <description>2**25 clock cycles.</description>
19776         <value>6</value>
19777        </enumeratedValue>
19778        <enumeratedValue>
19779         <name>wdt2pow24</name>
19780         <description>2**24 clock cycles.</description>
19781         <value>7</value>
19782        </enumeratedValue>
19783        <enumeratedValue>
19784         <name>wdt2pow23</name>
19785         <description>2**23 clock cycles.</description>
19786         <value>8</value>
19787        </enumeratedValue>
19788        <enumeratedValue>
19789         <name>wdt2pow22</name>
19790         <description>2**22 clock cycles.</description>
19791         <value>9</value>
19792        </enumeratedValue>
19793        <enumeratedValue>
19794         <name>wdt2pow21</name>
19795         <description>2**21 clock cycles.</description>
19796         <value>10</value>
19797        </enumeratedValue>
19798        <enumeratedValue>
19799         <name>wdt2pow20</name>
19800         <description>2**20 clock cycles.</description>
19801         <value>11</value>
19802        </enumeratedValue>
19803        <enumeratedValue>
19804         <name>wdt2pow19</name>
19805         <description>2**19 clock cycles.</description>
19806         <value>12</value>
19807        </enumeratedValue>
19808        <enumeratedValue>
19809         <name>wdt2pow18</name>
19810         <description>2**18 clock cycles.</description>
19811         <value>13</value>
19812        </enumeratedValue>
19813        <enumeratedValue>
19814         <name>wdt2pow17</name>
19815         <description>2**17 clock cycles.</description>
19816         <value>14</value>
19817        </enumeratedValue>
19818        <enumeratedValue>
19819         <name>wdt2pow16</name>
19820         <description>2**16 clock cycles.</description>
19821         <value>15</value>
19822        </enumeratedValue>
19823       </enumeratedValues>
19824      </field>
19825      <field>
19826       <name>RST_EARLY_VAL</name>
19827       <description>Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description>
19828       <bitOffset>20</bitOffset>
19829       <bitWidth>4</bitWidth>
19830       <enumeratedValues>
19831        <enumeratedValue>
19832         <name>wdt2pow31</name>
19833         <description>2**31 clock cycles.</description>
19834         <value>0</value>
19835        </enumeratedValue>
19836        <enumeratedValue>
19837         <name>wdt2pow30</name>
19838         <description>2**30 clock cycles.</description>
19839         <value>1</value>
19840        </enumeratedValue>
19841        <enumeratedValue>
19842         <name>wdt2pow29</name>
19843         <description>2**29 clock cycles.</description>
19844         <value>2</value>
19845        </enumeratedValue>
19846        <enumeratedValue>
19847         <name>wdt2pow28</name>
19848         <description>2**28 clock cycles.</description>
19849         <value>3</value>
19850        </enumeratedValue>
19851        <enumeratedValue>
19852         <name>wdt2pow27</name>
19853         <description>2^27 clock cycles.</description>
19854         <value>4</value>
19855        </enumeratedValue>
19856        <enumeratedValue>
19857         <name>wdt2pow26</name>
19858         <description>2**26 clock cycles.</description>
19859         <value>5</value>
19860        </enumeratedValue>
19861        <enumeratedValue>
19862         <name>wdt2pow25</name>
19863         <description>2**25 clock cycles.</description>
19864         <value>6</value>
19865        </enumeratedValue>
19866        <enumeratedValue>
19867         <name>wdt2pow24</name>
19868         <description>2**24 clock cycles.</description>
19869         <value>7</value>
19870        </enumeratedValue>
19871        <enumeratedValue>
19872         <name>wdt2pow23</name>
19873         <description>2**23 clock cycles.</description>
19874         <value>8</value>
19875        </enumeratedValue>
19876        <enumeratedValue>
19877         <name>wdt2pow22</name>
19878         <description>2**22 clock cycles.</description>
19879         <value>9</value>
19880        </enumeratedValue>
19881        <enumeratedValue>
19882         <name>wdt2pow21</name>
19883         <description>2**21 clock cycles.</description>
19884         <value>10</value>
19885        </enumeratedValue>
19886        <enumeratedValue>
19887         <name>wdt2pow20</name>
19888         <description>2**20 clock cycles.</description>
19889         <value>11</value>
19890        </enumeratedValue>
19891        <enumeratedValue>
19892         <name>wdt2pow19</name>
19893         <description>2**19 clock cycles.</description>
19894         <value>12</value>
19895        </enumeratedValue>
19896        <enumeratedValue>
19897         <name>wdt2pow18</name>
19898         <description>2**18 clock cycles.</description>
19899         <value>13</value>
19900        </enumeratedValue>
19901        <enumeratedValue>
19902         <name>wdt2pow17</name>
19903         <description>2**17 clock cycles.</description>
19904         <value>14</value>
19905        </enumeratedValue>
19906        <enumeratedValue>
19907         <name>wdt2pow16</name>
19908         <description>2**16 clock cycles.</description>
19909         <value>15</value>
19910        </enumeratedValue>
19911       </enumeratedValues>
19912      </field>
19913      <field>
19914       <name>CLKRDY_IE</name>
19915       <description>Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock.</description>
19916       <bitOffset>27</bitOffset>
19917       <bitWidth>1</bitWidth>
19918      </field>
19919      <field>
19920       <name>CLKRDY</name>
19921       <description>Clock Status.</description>
19922       <bitOffset>28</bitOffset>
19923       <bitWidth>1</bitWidth>
19924      </field>
19925      <field>
19926       <name>WIN_EN</name>
19927       <description>Enables the Windowed Watchdog Function.</description>
19928       <bitOffset>29</bitOffset>
19929       <bitWidth>1</bitWidth>
19930       <enumeratedValues>
19931        <enumeratedValue>
19932         <name>dis</name>
19933         <description>Windowed Mode Disabled (i.e. Compatibility Mode).</description>
19934         <value>0</value>
19935        </enumeratedValue>
19936        <enumeratedValue>
19937         <name>en</name>
19938         <description>Windowed Mode Enabled.</description>
19939         <value>1</value>
19940        </enumeratedValue>
19941       </enumeratedValues>
19942      </field>
19943      <field>
19944       <name>RST_EARLY</name>
19945       <description>Windowed Watchdog Timer Reset Flag Too Soon.</description>
19946       <bitOffset>30</bitOffset>
19947       <bitWidth>1</bitWidth>
19948       <enumeratedValues>
19949        <usage>read-write</usage>
19950        <enumeratedValue>
19951         <name>noEvent</name>
19952         <description>The event has not occurred.</description>
19953         <value>0</value>
19954        </enumeratedValue>
19955        <enumeratedValue>
19956         <name>occurred</name>
19957         <description>The event has occurred.</description>
19958         <value>1</value>
19959        </enumeratedValue>
19960       </enumeratedValues>
19961      </field>
19962      <field>
19963       <name>RST_LATE</name>
19964       <description>Windowed Watchdog Timer Reset Flag Too Late.</description>
19965       <bitOffset>31</bitOffset>
19966       <bitWidth>1</bitWidth>
19967       <enumeratedValues>
19968        <usage>read-write</usage>
19969        <enumeratedValue>
19970         <name>noEvent</name>
19971         <description>The event has not occurred.</description>
19972         <value>0</value>
19973        </enumeratedValue>
19974        <enumeratedValue>
19975         <name>occurred</name>
19976         <description>The event has occurred.</description>
19977         <value>1</value>
19978        </enumeratedValue>
19979       </enumeratedValues>
19980      </field>
19981     </fields>
19982    </register>
19983    <register>
19984     <name>RST</name>
19985     <description>Windowed Watchdog Timer Reset Register.</description>
19986     <addressOffset>0x04</addressOffset>
19987     <access>write-only</access>
19988     <fields>
19989      <field>
19990       <name>RESET</name>
19991       <description>Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled.</description>
19992       <bitOffset>0</bitOffset>
19993       <bitWidth>8</bitWidth>
19994       <enumeratedValues>
19995        <enumeratedValue>
19996         <name>seq0</name>
19997         <description>The first value to be written to reset the WDT.</description>
19998         <value>0x000000A5</value>
19999        </enumeratedValue>
20000        <enumeratedValue>
20001         <name>seq1</name>
20002         <description>The second value to be written to reset the WDT.</description>
20003         <value>0x0000005A</value>
20004        </enumeratedValue>
20005       </enumeratedValues>
20006      </field>
20007     </fields>
20008    </register>
20009    <register>
20010     <name>CLKSEL</name>
20011     <description>Windowed Watchdog Timer Clock Select Register.</description>
20012     <addressOffset>0x08</addressOffset>
20013     <access>read-write</access>
20014     <fields>
20015      <field>
20016       <name>SOURCE</name>
20017       <description>WWDT Clock Selection Register.</description>
20018       <bitOffset>0</bitOffset>
20019       <bitWidth>3</bitWidth>
20020      </field>
20021     </fields>
20022    </register>
20023    <register>
20024     <name>CNT</name>
20025     <description>Windowed Watchdog Timer Count Register.</description>
20026     <addressOffset>0x0C</addressOffset>
20027     <access>read-only</access>
20028     <fields>
20029      <field>
20030       <name>COUNT</name>
20031       <description>Current Value of the Windowed Watchdog Timer Counter.</description>
20032       <bitOffset>0</bitOffset>
20033       <bitWidth>32</bitWidth>
20034      </field>
20035     </fields>
20036    </register>
20037   </registers>
20038  </peripheral>
20039<!--WDT Windowed Watchdog Timer-->
20040  <peripheral derivedFrom="WDT">
20041   <name>WDT1</name>
20042   <description>Windowed Watchdog Timer 1</description>
20043   <baseAddress>0x40080800</baseAddress>
20044   <interrupt>
20045    <name>WDT1</name>
20046    <description>WDT1 IRQ</description>
20047    <value>57</value>
20048   </interrupt>
20049  </peripheral>
20050<!--WDT1 Windowed Watchdog Timer 1-->
20051  <peripheral>
20052   <name>WUT</name>
20053   <description>Wake Up Timer</description>
20054   <baseAddress>0x40006400</baseAddress>
20055   <addressBlock>
20056    <offset>0x00</offset>
20057    <size>0x0400</size>
20058    <usage>registers</usage>
20059   </addressBlock>
20060   <interrupt>
20061    <name>WUT</name>
20062    <value>53</value>
20063   </interrupt>
20064   <registers>
20065    <register>
20066     <name>CNT</name>
20067     <description>Wakeup Timer Count Register</description>
20068     <addressOffset>0x0000</addressOffset>
20069     <access>read-write</access>
20070     <fields>
20071      <field>
20072       <name>COUNT</name>
20073       <description>Timer Count Value. </description>
20074       <bitOffset>0</bitOffset>
20075       <bitWidth>32</bitWidth>
20076      </field>
20077     </fields>
20078    </register>
20079    <register>
20080     <name>CMP</name>
20081     <description>Wakeup Timer Compare Register</description>
20082     <addressOffset>0x0004</addressOffset>
20083     <access>read-write</access>
20084     <fields>
20085      <field>
20086       <name>COMPARE</name>
20087       <description>Timer Compare Value.</description>
20088       <bitOffset>0</bitOffset>
20089       <bitWidth>32</bitWidth>
20090      </field>
20091     </fields>
20092    </register>
20093    <register>
20094     <name>INTFL</name>
20095     <description>Wakeup Timer Interrupt Register</description>
20096     <addressOffset>0x000C</addressOffset>
20097     <access>read-write</access>
20098     <fields>
20099      <field>
20100       <name>IRQ_CLR</name>
20101       <description>Timer Interrupt.</description>
20102       <bitOffset>0</bitOffset>
20103       <bitWidth>1</bitWidth>
20104      </field>
20105     </fields>
20106    </register>
20107    <register>
20108     <name>CTRL</name>
20109     <description>Wakeup Timer Control Register</description>
20110     <addressOffset>0x0010</addressOffset>
20111     <access>read-write</access>
20112     <fields>
20113      <field>
20114       <name>TMODE</name>
20115       <description>Timer Mode Select.</description>
20116       <bitOffset>0</bitOffset>
20117       <bitWidth>3</bitWidth>
20118       <enumeratedValues>
20119        <enumeratedValue>
20120         <name>oneShot</name>
20121         <description>One Shot Mode.</description>
20122         <value>0</value>
20123        </enumeratedValue>
20124        <enumeratedValue>
20125         <name>continuous</name>
20126         <description>Continuous Mode.</description>
20127         <value>1</value>
20128        </enumeratedValue>
20129        <enumeratedValue>
20130         <name>counter</name>
20131         <description>Counter Mode.</description>
20132         <value>2</value>
20133        </enumeratedValue>
20134        <enumeratedValue>
20135         <name>pwm</name>
20136         <description>PWM Mode.</description>
20137         <value>3</value>
20138        </enumeratedValue>
20139        <enumeratedValue>
20140         <name>capture</name>
20141         <description>Capture Mode.</description>
20142         <value>4</value>
20143        </enumeratedValue>
20144        <enumeratedValue>
20145         <name>compare</name>
20146         <description>Compare Mode.</description>
20147         <value>5</value>
20148        </enumeratedValue>
20149        <enumeratedValue>
20150         <name>gated</name>
20151         <description>Gated Mode.</description>
20152         <value>6</value>
20153        </enumeratedValue>
20154        <enumeratedValue>
20155         <name>captureCompare</name>
20156         <description>Capture/Compare Mode.</description>
20157         <value>7</value>
20158        </enumeratedValue>
20159       </enumeratedValues>
20160      </field>
20161      <field>
20162       <name>PRES</name>
20163       <description>Timer Prescaler Select.</description>
20164       <bitOffset>3</bitOffset>
20165       <bitWidth>3</bitWidth>
20166       <enumeratedValues>
20167        <enumeratedValue>
20168         <name>DIV1</name>
20169         <value>0</value>
20170        </enumeratedValue>
20171        <enumeratedValue>
20172         <name>DIV2</name>
20173         <value>1</value>
20174        </enumeratedValue>
20175        <enumeratedValue>
20176         <name>DIV4</name>
20177         <value>2</value>
20178        </enumeratedValue>
20179        <enumeratedValue>
20180         <name>DIV8</name>
20181         <value>3</value>
20182        </enumeratedValue>
20183        <enumeratedValue>
20184         <name>DIV16</name>
20185         <value>4</value>
20186        </enumeratedValue>
20187        <enumeratedValue>
20188         <name>DIV32</name>
20189         <value>5</value>
20190        </enumeratedValue>
20191        <enumeratedValue>
20192         <name>DIV64</name>
20193         <value>6</value>
20194        </enumeratedValue>
20195        <enumeratedValue>
20196         <name>DIV128</name>
20197         <value>7</value>
20198        </enumeratedValue>
20199        <enumeratedValue>
20200         <name>DIV256</name>
20201         <value>0</value>
20202        </enumeratedValue>
20203        <enumeratedValue>
20204         <name>DIV512</name>
20205         <value>2</value>
20206        </enumeratedValue>
20207        <enumeratedValue>
20208         <name>DIV1024</name>
20209         <value>3</value>
20210        </enumeratedValue>
20211        <enumeratedValue>
20212         <name>DIV2048</name>
20213         <value>4</value>
20214        </enumeratedValue>
20215        <enumeratedValue>
20216         <name>DIV4096</name>
20217         <value>5</value>
20218        </enumeratedValue>
20219       </enumeratedValues>
20220      </field>
20221      <field>
20222       <name>TPOL</name>
20223       <description>Timer pOLARITY.</description>
20224       <bitOffset>6</bitOffset>
20225       <bitWidth>1</bitWidth>
20226      </field>
20227      <field>
20228       <name>TEN</name>
20229       <description>Timer Enable.</description>
20230       <bitOffset>7</bitOffset>
20231       <bitWidth>1</bitWidth>
20232       <enumeratedValues>
20233        <enumeratedValue>
20234         <name>timer_dis</name>
20235         <value>0</value>
20236        </enumeratedValue>
20237        <enumeratedValue>
20238         <name>timer_en</name>
20239         <value>1</value>
20240        </enumeratedValue>
20241       </enumeratedValues>
20242      </field>
20243      <field>
20244       <name>PRES3</name>
20245       <description>Timer Prescaler Select.</description>
20246       <bitOffset>8</bitOffset>
20247       <bitWidth>1</bitWidth>
20248       <enumeratedValues>
20249        <enumeratedValue>
20250         <name>pres3_1</name>
20251         <value>0</value>
20252        </enumeratedValue>
20253        <enumeratedValue>
20254         <name>pres3_2</name>
20255         <value>0</value>
20256        </enumeratedValue>
20257        <enumeratedValue>
20258         <name>pres3_4</name>
20259         <value>0</value>
20260        </enumeratedValue>
20261        <enumeratedValue>
20262         <name>pres3_8</name>
20263         <value>0</value>
20264        </enumeratedValue>
20265        <enumeratedValue>
20266         <name>pres3_16</name>
20267         <value>0</value>
20268        </enumeratedValue>
20269        <enumeratedValue>
20270         <name>pres3_32</name>
20271         <value>0</value>
20272        </enumeratedValue>
20273        <enumeratedValue>
20274         <name>pres3_64</name>
20275         <value>0</value>
20276        </enumeratedValue>
20277        <enumeratedValue>
20278         <name>pres3_128</name>
20279         <value>0</value>
20280        </enumeratedValue>
20281        <enumeratedValue>
20282         <name>pres3_256</name>
20283         <value>1</value>
20284        </enumeratedValue>
20285        <enumeratedValue>
20286         <name>pres3_512</name>
20287         <value>1</value>
20288        </enumeratedValue>
20289        <enumeratedValue>
20290         <name>pres3_1024</name>
20291         <value>1</value>
20292        </enumeratedValue>
20293        <enumeratedValue>
20294         <name>pres3_2048</name>
20295         <value>1</value>
20296        </enumeratedValue>
20297        <enumeratedValue>
20298         <name>pres3_4096</name>
20299         <value>1</value>
20300        </enumeratedValue>
20301       </enumeratedValues>
20302      </field>
20303     </fields>
20304    </register>
20305    <register>
20306     <name>NOLCMP</name>
20307     <description>Non Overlaping Compare Register</description>
20308     <addressOffset>0x0014</addressOffset>
20309     <access>read-write</access>
20310     <fields>
20311      <field>
20312       <name>NOLLCMP</name>
20313       <description>Non Overlaping Low Compare.</description>
20314       <bitOffset>0</bitOffset>
20315       <bitWidth>8</bitWidth>
20316      </field>
20317      <field>
20318       <name>NOLHCMP</name>
20319       <description>Non Overlaping High Compare.</description>
20320       <bitOffset>8</bitOffset>
20321       <bitWidth>8</bitWidth>
20322      </field>
20323     </fields>
20324    </register>
20325    <register>
20326     <name>PRESET</name>
20327     <description>Preset register.</description>
20328     <addressOffset>0x0018</addressOffset>
20329     <fields>
20330      <field>
20331       <name>PRESET</name>
20332       <description>Preset Value.</description>
20333       <bitOffset>0</bitOffset>
20334       <bitWidth>32</bitWidth>
20335      </field>
20336     </fields>
20337    </register>
20338    <register>
20339     <name>RELOAD</name>
20340     <description>Reload register.</description>
20341     <addressOffset>0x001C</addressOffset>
20342     <fields>
20343      <field>
20344       <name>RELOAD</name>
20345       <description>Reload Value.</description>
20346       <bitOffset>0</bitOffset>
20347       <bitWidth>32</bitWidth>
20348      </field>
20349     </fields>
20350    </register>
20351    <register>
20352     <name>SNAPSHOT</name>
20353     <description>Snapshot register.</description>
20354     <addressOffset>0x0020</addressOffset>
20355     <fields>
20356      <field>
20357       <name>SNAPSHOT</name>
20358       <description>Snapshot Value.</description>
20359       <bitOffset>0</bitOffset>
20360       <bitWidth>32</bitWidth>
20361      </field>
20362     </fields>
20363    </register>
20364   </registers>
20365  </peripheral>
20366<!--WUT Wake Up Timer-->
20367 </peripherals>
20368</device>
20369