Maxim-Integrated Maxim max78002 ARMCM4 1.0 MAX78002 Machine Learning System-on-Chip. CM4 r2p1 little true true 3 false 8 32 0x20 read-write 0x00000000 0xFFFFFFFF ADC Inter-Integrated Circuit. ADC 0x40034000 32 0x00 0x1000 registers ADC ADC IRQ 20 CTRL0 Control Register 0. 0x00 ADC_EN ADC Enable. [0:0] read-write dis Disable ADC. 0 en enable ADC. 1 BIAS_EN Bias Enable. [1:1] read-write dis Disable Bias. 0 en Enable Bias. 1 SKIP_CAL Skip Calibration Enable. [2:2] read-write no_skip Do not skip calibration. 0 skip Skip calibration. 1 CHOP_FORCE Chop Force Control. [3:3] read-write dis Do not force chop mode. 0 en Force chop Mode. 1 RESETB Reset ADC. [4:4] read-write reset reset ADC. 0 activate activate ADC. 1 CTRL1 Control Register 1. 0x04 START Start conversion control. [0:0] read-write stop Stop conversions. 0 start Start conversions. 1 TRIG_MODE Trigger mode control. [1:1] read-write software software trigger mode. 0 hardware hardware trigger mode. 1 CNV_MODE Conversion mode control. [2:2] read-write atomic Do one conversion sequence. 0 continuous Do continuous conversion sequences. 1 SAMP_CK_OFF Sample clock off control. [3:3] read-write always Sample clock always generated. 0 cnv_only Sample clock generated only when converting. 1 TRIG_SEL Hardware trigger source select. [6:4] read-write TS_SEL Temp sensor select. [7:7] read-write dis Temp sensor is not one of the slots in the sequence. 0 en Temp sensor is one of the slots in the sequence. 1 AVG Number of samples to average for each output data code. [10:8] read-write avg1 1 Sample per output code. 0 avg2 2 Samples per output code. 1 avg4 4 Samples per output code. 2 avg8 8 Samples per output code. 3 avg16 16 Samples per output code. 4 avg32 32 Samples per output code. 5 NUM_SLOTS Number of slots enabled for the conversion sequence [20:16] read-write CLKCTRL Clock Control Register. 0x08 CLKSEL Clock source select. [1:0] read-write HCLK Select HCLK. 0 CLK_ADC0 Select CLK_ADC0. 1 CLK_ADC1 Select CLK_ADC1. 2 CLK_ADC2 Select CLK_ADC2. 3 CLKDIV Clock divider control. [6:4] read-write DIV2 Divide by 2. 0 DIV4 Divide by 4. 1 DIV8 Divide by 8. 2 DIV16 Divide by 16. 3 DIV1 Divide by 1. 4 SAMPCLKCTRL Sample Clock Control Register. 0x0C read-write TRACK_CNT Number of cycles for SAMPLE_CLK high time. [7:0] read-write IDLE_CNT Number of cycles for SAMPLE_CLK low time. [31:16] read-write CHSEL0 Channel Select Register 0. 0x10 slot0_id channel assignment for slot 0. [4:0] read-write slot1_id channel assignment for slot 1. [12:8] read-write slot2_id channel assignment for slot 2. [20:16] read-write slot3_id channel assignment for slot 3. [28:24] read-write CHSEL1 Channel Select Register 1. 0x14 slot4_id channel assignment for slot 4. [4:0] read-write slot5_id channel assignment for slot 5. [12:8] read-write slot6_id channel assignment for slot 6. [20:16] read-write slot7_id channel assignment for slot 7. [28:24] read-write CHSEL2 Channel Select Register 2. 0x18 slot8_id channel assignment for slot 8. [4:0] read-write slot9_id channel assignment for slot 9. [12:8] read-write slot10_id channel assignment for slot 10. [20:16] read-write slot11_id channel assignment for slot 11. [28:24] read-write CHSEL3 Channel Select Register 3. 0x1C slot12_id channel assignment for slot 12. [4:0] read-write slot13_id channel assignment for slot 13. [12:8] read-write slot14_id channel assignment for slot 14. [20:16] read-write slot15_id channel assignment for slot 15. [28:24] read-write CHSEL4 Channel Select Register 4. 0x20 slot16_id channel assignment for slot 16. [4:0] read-write slot17_id channel assignment for slot 17. [12:8] read-write slot18_id channel assignment for slot 18. [20:16] read-write slot19_id channel assignment for slot 19. [28:24] read-write CHSEL5 Channel Select Register 5. 0x24 slot20_id channel assignment for slot 20. [4:0] read-write slot21_id channel assignment for slot 21. [12:8] read-write slot22_id channel assignment for slot 22. [20:16] read-write slot23_id channel assignment for slot 23. [28:24] read-write CHSEL6 Channel Select Register 6. 0x28 slot24_id channel assignment for slot 24. [4:0] read-write slot25_id channel assignment for slot 25. [12:8] read-write slot26_id channel assignment for slot 26. [20:16] read-write slot27_id channel assignment for slot 27. [28:24] read-write CHSEL7 Channel Select Register 7. 0x2C slot28_id channel assignment for slot 28. [4:0] read-write slot29_id channel assignment for slot 29. [12:8] read-write slot30_id channel assignment for slot 30. [20:16] read-write slot31_id channel assignment for slot 31. [28:24] read-write RESTART Restart Count Control Register 0x30 CNT Number of sample periods to skip before restarting a continuous mode sequence [15:0] read-write DATAFMT Channel Data Format Register 0x3C MODE Data format control [31:0] read-write FIFODMACTRL FIFO and DMA control 0x40 DMA_EN DMA Enable. [0:0] read-write dis Disable DMA. 0 en Enable DMA. 1 FLUSH FIFO Flush. [1:1] read-write normal Normal FIFO operation. 0 flush Flush FIFO. 1 DATA_FORMAT DATA format control. [3:2] read-write data_status Data and Status in FIFO. 0 data_only Only Data in FIFO. 1 raw_data_only Only Raw Data in FIFO. 2 THRESH FIFO Threshold. These bits define the FIFO interrupt threshold. [15:8] read-write DATA Data Register (FIFO). 0x44 DATA Conversion data. [15:0] read-only CHAN Channel for the data. [20:16] read-only INVALID Invalid status for the data. [24:24] read-only CLIPPED Clipped status for the data. [31:31] read-only STATUS Status Register 0x48 READY Indication that the ADC is in ON power state [0:0] read-only EMPTY FIFO Empty [1:1] read-only FULL FIFO full [2:2] read-only FIFO_LEVEL Number of entries in FIFO available to read [15:8] read-only CHSTATUS Channel Status 0x4C CLIPPED [31:0] read-write INTEN Interrupt Enable Register. 0x50 READY ADC is ready. [0:0] read-write ABORT Conversion start is aborted. [2:2] read-write START_DET Conversion start is detected. [3:3] read-write SEQ_STARTED [4:4] read-write SEQ_DONE [5:5] read-write CONV_DONE [6:6] read-write CLIPPED [7:7] read-write FIFO_LVL [8:8] read-write FIFO_UFL [9:9] read-write FIFO_OFL [10:10] read-write INTFL Interrupt Flags Register. 0x54 READY ADC is ready. [0:0] read-write oneToClear ABORT Conversion start is aborted. [2:2] read-write oneToClear START_DET Conversion start is detected. [3:3] read-write oneToClear SEQ_STARTED [4:4] read-write oneToClear SEQ_DONE [5:5] read-write oneToClear CONV_DONE [6:6] read-write oneToClear CLIPPED [7:7] read-write oneToClear FIFO_LVL [8:8] read-write oneToClear FIFO_UFL [9:9] read-write oneToClear FIFO_OFL [10:10] read-write oneToClear SFRADDROFFSET SFR Address Offset Register 0x60 OFFSET Address Offset for SAR Digital [7:0] read-write SFRADDR SFR Address Register 0x64 ADDR Address to SAR Digital [7:0] read-write SFRWRDATA SFR Write Data Register 0x68 DATA DATA to SAR Digital [7:0] read-write SFRRDDATA SFR Read Data Register 0x6C DATA DATA from SAR Digital [7:0] read-only SFRSTATUS SFR Status Register 0x70 NACK NACK status for SAR Digital SFR communication [0:0] read-only AES AES Keys. 0x40007400 0x00 0x400 registers CTRL AES Control Register 0x0000 32 EN AES Enable [0:0] read-write DMA_RX_EN DMA Request To Read Data Output FIFO [1:1] read-write DMA_TX_EN DMA Request To Write Data Input FIFO [2:2] read-write START Start AES Calculation [3:3] read-write INPUT_FLUSH Flush the data input FIFO [4:4] read-write OUTPUT_FLUSH Flush the data output FIFO [5:5] read-write KEY_SIZE Encryption Key Size [7:6] read-write AES128 128 Bits. 0 AES192 192 Bits. 1 AES256 256 Bits. 2 TYPE Encryption Type Selection [9:8] read-write STATUS AES Status Register 0x0004 BUSY AES Busy Status [0:0] read-write INPUT_EM Data input FIFO empty status [1:1] read-write INPUT_FULL Data input FIFO full status [2:2] read-write OUTPUT_EM Data output FIFO empty status [3:3] read-write OUTPUT_FULL Data output FIFO full status [4:4] read-write INTFL AES Interrupt Flag Register 0x0008 DONE AES Done Interrupt [0:0] read-write KEY_CHANGE External AES Key Changed Interrupt [1:1] read-write KEY_ZERO External AES Key Zero Interrupt [2:2] read-write OV Data Output FIFO Overrun Interrupt [3:3] read-write KEY_ONE KEY_ONE [4:4] read-write INTEN AES Interrupt Enable Register 0x000C DONE AES Done Interrupt Enable [0:0] read-write KEY_CHANGE External AES Key Changed Interrupt Enable [1:1] read-write KEY_ZERO External AES Key Zero Interrupt Enable [2:2] read-write OV Data Output FIFO Overrun Interrupt Enable [3:3] read-write KEY_ONE KEY_ONE [4:4] read-write FIFO AES Data Register 0x0010 DATA AES FIFO [0:0] read-write AESKEYS AES Key Registers. 0x40007800 0x00 0x400 registers KEY0 AES Key 0. 0x000 32 KEY1 AES Key 1. 0x080 32 KEY2 AES Key 2. 0x100 32 KEY3 AES Key 3. 0x180 32 CAMERAIF Parallel Camera Interface. 0x4000E000 32 read-write 0 0x1000 registers CameraIF 91 VER Hardware Version. 0x0000 read-write minor Minor Version Number. [7:0] read-write major Major Version Number. [15:8] read-write FIFO_SIZE FIFO Depth. 0x0004 read-write fifo_size FIFO size. [7:0] read-write CTRL Control Register. 0x0008 read-write READ_MODE Read Mode. 0 2 read-write dis Camera Interface Disabled. 0 single_img Single Image Capture. 1 continuous Continuous Image Capture. 2 DATA_WIDTH Data Width. 2 2 read-write 8bit 8 bit. 0 10bit 10 bit. 1 12bit 12 bit. 2 DS_TIMING_EN DS Timing Enable. 4 1 read-write dis Timing from VSYNC and HSYNC. 0 en Timing embedded in data using SAV and EAV codes. 1 FIFO_THRSH Data FIFO Threshold. 5 5 read-write RX_DMA DMA Enable. 16 1 read-write dis DMA disabled. 0 en DMA enabled. 1 RX_DMA_THRSH DMA Threshold. 17 4 read-write THREE_CH_EN Three-channel mode enable. 30 1 read-write PCIF_SYS PCIF Control. 31 1 read-write dis PCIF disabled. 0 en PCIF enabled. 1 INT_EN Interupt Enable Register. 0x000C read-write IMG_DONE Image Done. 0 1 read-write FIFO_FULL FIFO Full. 1 1 read-write FIFO_THRESH FIFO Threshold Level Met. 2 1 read-write FIFO_NOT_EMPTY FIFO Not Empty. 3 1 read-write INT_FL Interupt Flag Register. 0x0010 read-write IMG_DONE Image Done. 0 1 read-write FIFO_FULL FIFO Full. 1 1 read-write FIFO_THRESH FIFO Threshold Level Met. 2 1 read-write FIFO_NOT_EMPTY FIFO Not Empty. 3 1 read-write DS_TIMING_CODES DS Timing Code Register. 0x0014 read-write SAV Start Active Video Code. [7:0] read-write EAV End Active Video Code. [15:8] read-write FIFO_DATA FIFO DATA Register. 0x0030 read-write DATA Data from FIFO to be read by DMA. [31:0] read-write CRC CRC Registers. 0x4000F000 0x00 0x1000 registers CTRL CRC Control 0x0000 32 EN CRC Enable [0:0] read-write DMA_EN DMA Request Enable [1:1] read-write MSB MSB Select [2:2] read-write BYTE_SWAP_IN Byte Swap CRC Data Input [3:3] read-write BYTE_SWAP_OUT Byte Swap CRC Value Output [4:4] read-write BUSY CRC Busy [16:16] read-write DATAIN32 CRC Data Input 0x0004 DATA CRC Data [31:0] read-write 2 2 DATAIN16[%s] CRC Data Input 0x0004 16 read-write DATA CRC Data 0 16 read-write 4 1 DATAIN8[%s] CRC Data Input 0x0004 8 read-write DATA CRC Data 0 8 read-write POLY CRC Polynomial 0x0008 POLY CRC Polynomial [31:0] read-write VAL Current CRC Value 0x000C VALUE Current CRC Value [31:0] read-write CSI2 Camera Serial Interface Registers. 0x40062000 0x00 0x1000 registers CFG_NUM_LANES CFG_NUM_LANES. 0x000 32 LANES Num Lanes for RX controller. 0 4 CFG_CLK_LANE_EN CFG_CLK_LANE_EN. 0x004 32 EN Enable lane clock setting for controller. 0 1 CFG_DATA_LANE_EN CFG_DATA_LANE_EN. 0x008 32 EN Enable data lane setting for controller. 0 8 CFG_FLUSH_COUNT CFG_FLUSH_COUNT. 0x00C 32 COUNT Flush count setting for controller. 0 4 CFG_BIT_ERR CFG_BIT_ERR. 0x010 32 MBE Multiple bit ECC error. 0 1 SBE Single bit ECC error. 1 1 HEADER Header bit location of single bit ECC error. 2 5 CRC CRC error. 7 1 VID_ERR_SEND_LVL Video Error Send Level. 8 1 VID_ERR_FIFO_WR_OV Video Error Fifo Overflow. 9 1 IRQ_STATUS IRQ_STATUS. 0x014 32 CRC CRC error. 0 1 SBE Single bit ECC error. 1 1 MBE Multiple bit ECC error. 2 1 ULPS_ACTIVE ULPS active status change. 3 1 ULPS_MARK_ACTIVE ULPS mark active status change. 4 1 VID_ERR_SEND_LVL Video Error Send Level. 5 1 VID_ERR_FIFO_WR_OV Video Error Fifo Overflow. 6 1 IRQ_ENABLE IRQ_ENABLE. 0x018 32 CRC CRC error. 0 1 SBE Single bit ECC error. 1 1 MBE Multiple bit ECC error. 2 1 ULPS_ACTIVE ULPS active status change. 3 1 ULPS_MARK_ACTIVE ULPS mark active status change. 4 1 VID_ERR_SEND_LVL Video Error Send Level. 5 1 VID_ERR_FIFO_WR_OV Video Error Fifo Overflow. 6 1 IRQ_CLR IRQ_CLR. 0x01C 32 CRC CRC error. 0 1 SBE Single bit ECC error. 1 1 MBE Multiple bit ECC error. 2 1 ULPS_ACTIVE ULPS active status change. 3 1 ULPS_MARK_ACTIVE ULPS mark active status change. 4 1 VID_ERR_SEND_LVL Video Error Send Level. 5 1 VID_ERR_FIFO_WR_OV Video Error Fifo Overflow. 6 1 ULPS_CLK_STATUS ULPS_CLK_STATUS. 0x020 32 FIFO FIFO Read/Write register. 0 1 ULPS_STATUS ULPS_STATUS. 0x024 32 DATA_LANE0 Data Lane 0. 0 1 DATA_LANE1 Data Lane 1. 1 1 ULPS_CLK_MARK_STATUS ULPS_CLK_MARK_STATUS. 0x028 32 CLK_LANE Clock Lane. 0 1 ULPS_MARK_STATUS ULPS_MARK_STATUS. 0x02C 32 DATA_LANE0 Data Lane 0. 0 1 DATA_LANE1 Data Lane 1. 1 1 PPI_ERRSOT_HS PPI_ERRSOT_HS. 0x030 32 PPI_ERRSOTSYNC_HS PPI_ERRSOTSYNC_HS. 0x034 32 PPI_ERRESC PPI_ERRESC. 0x038 32 PPI_ERRSYNCESC PPI_ERRSYNCESC. 0x03C 32 PPI_ERRCONTROL PPI_ERRCONTROL. 0x040 32 CFG_CPHY_EN CFG_CPHY_EN. 0x044 32 CFG_PPI_16_EN CFG_PPI_16_EN. 0x048 32 CFG_PACKET_INTERFACE_EN CFG_PACKET_INTERFACE_EN. 0x04C 32 CFG_VCX_EN CFG_VCX_EN. 0x050 32 CFG_BYTE_DATA_FORMAT CFG_BYTE_DATA_FORMAT. 0x054 32 CFG_DISABLE_PAYLOAD_0 CFG_DISABLE_PAYLOAD_0. 0x058 32 NULL NULL. 0 1 BLANK BLANK. 1 1 EMBEDDED EMBEDDED. 2 1 YUV420_8BIT YUV420_8BIT. 8 1 YUV420_10BIT YUV420_10BIT. 9 1 YUV420_8BIT_LEG YUV420_8BIT_LEG. 10 1 YUV420_8BIT_CSP YUV420_8BIT_CSP. 12 1 YUV420_10BIT_CSP YUV420_10BIT_CSP. 13 1 YUV422_8BIT YUV422_8BIT. 14 1 YUV422_10BIT YUV422_10BIT. 15 1 RGB444 RGB444. 16 1 RGB555 RGB555. 17 1 RGB565 RGB565. 18 1 RGB666 RGB666. 19 1 RGB888 RGB888. 20 1 RAW6 RAW6. 24 1 RAW7 RAW7. 25 1 RAW8 RAW8. 26 1 RAW10 RAW10. 27 1 RAW12 RAW12. 28 1 RAW14 RAW14. 29 1 RAW16 RAW16. 30 1 RAW20 RAW20. 31 1 CFG_DISABLE_PAYLOAD_1 CFG_DISABLE_PAYLOAD_1. 0x05C 32 USR_DEF_TYPE30 User defined type 0x30. 0 1 USR_DEF_TYPE31 User defined type 0x31. 1 1 USR_DEF_TYPE32 User defined type 0x32. 2 1 USR_DEF_TYPE33 User defined type 0x33. 3 1 USR_DEF_TYPE34 User defined type 0x34. 4 1 USR_DEF_TYPE35 User defined type 0x35. 5 1 USR_DEF_TYPE36 User defined type 0x36. 6 1 USR_DEF_TYPE37 User defined type 0x37. 7 1 CFG_VID_IGNORE_VC CFG_VID_IGNORE_VC. 0x080 32 CFG_VID_VC CFG_VID_VC. 0x084 32 CFG_P_FIFO_SEND_LEVEL CFG_P_FIFO_SEND_LEVEL. 0x088 32 CFG_VID_VSYNC CFG_VID_VSYNC. 0x08C 32 CFG_VID_HSYNC_FP CFG_VID_HSYNC_FP. 0x090 32 CFG_VID_HSYNC CFG_VID_HSYNC. 0x094 32 CFG_VID_HSYNC_BP CFG_VID_HSYNC_BP. 0x098 32 CFG_DATABUS16_SEL CFG_DATABUS16_SEL. 0x400 32 EN Enable 16-bit data bus. 0 1 CFG_D0_SWAP_SEL CFG_D0_SWAP_SEL. 0x404 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_D1_SWAP_SEL CFG_D1_SWAP_SEL. 0x408 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_D2_SWAP_SEL CFG_D2_SWAP_SEL. 0x40C 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_D3_SWAP_SEL CFG_D3_SWAP_SEL. 0x410 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_C0_SWAP_SEL CFG_C0_SWAP_SEL. 0x414 32 SRC Control Source. 0 3 PAD_CDRX_L0 PAD_CDRX_L0. 0 PAD_CDRX_L1 PAD_CDRX_L1. 1 PAD_CDRX_L2 PAD_CDRX_L2. 2 PAD_CDRX_L3 PAD_CDRX_L3. 3 PAD_CDRX_L4 PAD_CDRX_L4. 4 CFG_DPDN_SWAP CFG_DPDN_SWAP. 0x418 32 SWAP_DATA_LANE0 SWAP_DATA_LANE0. 0 1 SWAP_DATA_LANE1 SWAP_DATA_LANE1. 1 1 SWAP_DATA_LANE2 SWAP_DATA_LANE2. 2 1 SWAP_DATA_LANE3 SWAP_DATA_LANE3. 3 1 SWAP_CLK_LANE SWAP_CLK_LANE. 4 1 RG_CFGCLK_1US_CNT RG_CFGCLK_1US_CNT. 0x41C 32 RG_HSRX_CLK_PRE_TIME_GRP0 RG_HSRX_CLK_PRE_TIME_GRP0. 0x420 32 RG_HSRX_DATA_PRE_TIME_GRP0 RG_HSRX_DATA_PRE_TIME_GRP0. 0x424 32 RESET_DESKEW RESET_DESKEW. 0x428 32 DATA_LANE0 DATA_LANE0. 0 1 DATA_LANE1 DATA_LANE1. 1 1 DATA_LANE2 DATA_LANE2. 2 1 DATA_LANE3 DATA_LANE3. 3 1 PMA_RDY PMA_RDY. 0x42C 32 XCFGI_DW00 XCFGI_DW00. 0x430 32 XCFGI_DW01 XCFGI_DW01. 0x434 32 XCFGI_DW02 XCFGI_DW02. 0x438 32 XCFGI_DW03 XCFGI_DW03. 0x43C 32 XCFGI_DW04 XCFGI_DW04. 0x440 32 XCFGI_DW05 XCFGI_DW05. 0x444 32 XCFGI_DW06 XCFGI_DW06. 0x448 32 XCFGI_DW07 XCFGI_DW07. 0x44C 32 XCFGI_DW08 XCFGI_DW08. 0x450 32 XCFGI_DW09 XCFGI_DW09. 0x454 32 XCFGI_DW0A XCFGI_DW0A. 0x458 32 XCFGI_DW0B XCFGI_DW0B. 0x45C 32 XCFGI_DW0C XCFGI_DW0C. 0x460 32 XCFGI_DW0D XCFGI_DW0D. 0x464 32 GPIO_MODE GPIO_MODE. 0x468 32 GPIO_DP_IE GPIO_DP_IE. 0x46C 32 GPIO_DN_IE GPIO_DN_IE. 0x470 32 GPIO_DP_C GPIO_DP_C. 0x474 32 GPIO_DN_C GPIO_DN_C. 0x478 32 VCONTROL PMA_RDY. 0x47C 32 NORMAL_MODE NORMAL_MODE. 0 1 LP_RX_DC_TEST LP_RX_DC_TEST. 1 1 LP_RX_DC_1 LP_RX_DC_1. 2 1 LP_RX_DC_0 LP_RX_DC_0. 3 1 CAL_SEN_1 CAL_SEN_1. 4 1 CAL_SEN_0 CAL_SEN_0. 5 1 HSRT_0 HSRT_0. 7 1 HSRT_1 HSRT_1. 8 1 LP_RX_PARTBERT LP_RX_PARTBERT. 10 1 HS_INT_LOOPBACK HS_INT_LOOPBACK. 11 1 HS_RX_PARTBERT HS_RX_PARTBERT. 27 1 HS_RX_PRBS9 HS_RX_PRBS9. 28 1 SUSPEND_MODE SUSPEND_MODE. 31 1 MPSOV1 MPSOV1. 0x480 32 MPSOV2 MPSOV2. 0x484 32 MPSOV3 MPSOV3. 0x488 32 RG_CDRX_DSIRX_EN RG_CDRX_DSIRX_EN. 0x490 32 RXMODE RXMODE. 0 1 CSI CSI RX Mode. 0 DSI DSI RX Mode. 1 RG_CDRX_L012_SUBLVDS_EN RG_CDRX_L012_SUBLVDS_EN. 0x494 32 RG_CDRX_L012_HSRT_CTRL RG_CDRX_L012_HSRT_CTRL. 0x498 32 RG_CDRX_BISTHS_PLL_EN RG_CDRX_BISTHS_PLL_EN. 0x49C 32 RG_CDRX_BISTHS_PLL_PRE_DIV2 RG_CDRX_BISTHS_PLL_PRE_DIV2. 0x4A0 32 RXMODE RXMODE. 0 1 CSI CSI RX Mode. 0 DSI DSI RX Mode. 1 RG_CDRX_BISTHS_PLL_FBK_INT RG_CDRX_BISTHS_PLL_FBK_INT. 0x4A4 32 DBG1_MUX_SEL DBG1_MUX_SEL. 0x4A8 32 DBG2_MUX_SEL DBG2_MUX_SEL. 0x4AC 32 DBG1_MUX_DOUT DBG1_MUX_DOUT. 0x4B0 32 DBG2_MUX_DOUT DBG2_MUX_DOUT. 0x4B4 32 AON_POWER_READY_N AON_POWER_READY_N. 0x4B8 32 DPHY_RST_N DPHY_RST_N. 0x4BC 32 RXBYTECLKHS_INV RXBYTECLKHS_INV. 0x4C0 32 VFIFO_CFG0 Video FIFO Configuration Register 0. 0x500 32 VC CSI Virtual Channel. 0 2 DMAMODE DMA Mode, the condition to trigger DMA request.. 6 2 NO_DMA No DMA. 0 DMA_REQ Immediately send DMA request. 1 FIFO_THD Wait for FIFO above threshold. 2 FIFO_FULL Wait for FIFO is full. 3 AHBWAIT AHB Wait Enable. 8 1 FIFORM FIFO Read Mode. 9 1 ERRDE Error Detection Enable. 10 1 FBWM Full Band Width mode. 11 1 VFIFO_CFG1 Video FIFO Configuration Register 1. 0x504 32 AHBWCYC Maximal AHB Wait Clock Cycles. 0 16 WAIT_FIRST_FS WAIT_FIRST_FS. 16 1 ACCU_FRAME_CTRL ACCU_FRAME_CTRL. 17 1 ACCU_LINE_CTRL ACCU_LINE_CTRL. 18 1 ACCU_LINE_CNT ACCU_LINE_CNT. 19 1 ACCU_PIXEL_CNT ACCU_PIXEL_CNT. 20 1 ACCU_PIXEL_ZERO ACCU_PIXEL_ZERO. 21 1 VFIFO_CTRL Video FIFO Control Register. 0x508 32 FIFOEN Video FIFO Enable. 0 1 DIS Disable. 0 EN Enable. 1 FLUSH Write 1 to flush FIFO contents. 4 1 THD FIFO Threshold. 8 7 VFIFO_STS Video FIFO Status Register. 0x50C 32 FEMPTY FIFO empty. 0 1 FTHD FIFO above threshold. 1 1 FFULL FIFO full. 2 1 UNDERRUN FIFO underrun 3 1 OVERRUN FIFO overrun 4 1 OUTSYNC CSI out of sync 5 1 FMTERR CSI Pixel Format Error 6 1 AHBWTO AHB wait time out 7 1 FS CSI Frame Start 8 1 FE CSI Frame End 9 1 LS CSI Line Start 10 1 LE CSI Line End 11 1 FELT FIFO remaining entity count 16 7 FMT CSI pixel format of current transaction 24 6 VFIFO_LINE_NUM Video FIFO CSI Line Number Per Frame. 0x510 32 LINE_NUM Number of lines per frame. 0 13 VFIFO_PIXEL_NUM Video FIFO CSI Pixel Number Per Line. 0x514 32 PIXEL_NUM Number of pixels per line. 0 14 VFIFO_LINE_CNT Video FIFO CSI Line Count. 0x518 32 LINE_CNT Number of received lines in current frame. 0 12 VFIFO_PIXEL_CNT Video FIFO CSI Pixel Count. 0x51C 32 PIXEL_CNT Number of received pixels in current line in a frame. 0 13 VFIFO_FRAME_STS Video FIFO Frame Status Register. 0x520 32 FRAME_STATE Frame State. 0 3 ERROR_CODE Error Codes. 3 3 VFIFO_RAW_CTRL Video FIFO RAW-to-RGB Control Register. 0x524 32 RAW_CEN RAW conversion enable. 0 1 RAW_FF_AFO RAW conversion FIFO automatic flush-out. 1 1 RAW_FF_FO RAW conversion FIFO flush-out trigger. 4 1 RAW_FMT RAW format. 8 2 RGRG_GBGB RGRG GBGB 0 GRGR_BGBG GRGR BGBG 1 GBGB_RGRG GBGB RGRG 2 BGBG_GRGR BGBG GRGR 3 RGB_TYP RGB type. 12 3 RGB444 RGB444. 0 RGB555 RGB555. 1 RGB565 RGB565. 2 RGB666 RGB666. 3 RGG888 RGG888. 4 VFIFO_RAW_BUF0_ADDR Video FIFO RAW-to-RGB Line Buffer0 Address. 0x528 32 ADDR RAM address for RAW conversion buffer 0, word-aligned. 2 30 VFIFO_RAW_BUF1_ADDR Video FIFO RAW-to-RGB Line Buffer1 Address. 0x52C 32 ADDR RAM address for RAW conversion buffer 1, word-aligned. 2 30 VFIFO_AHBM_CTRL Video FIFO AHB Master Control Register. 0x530 32 AHBMEN AHB Master Enable. 0 1 AHBMCLR AHB Master Status Clear. 1 1 BSTLEN AHB Burst Length. 4 2 VFIFO_THD Video FIFO THD. 0 ONE_WORD ONE_WORD. 1 FOUR_WORDS FOUR_WORDS. 2 EIGHT_WORDS EIGHT_WORDS. 3 VFIFO_AHBM_STS Video FIFO AHB Master Status Register. 0x534 32 HRDY_TO AHB master HREADY time-out. 0 1 IDLE_TO AHB master Idle time-out. 1 1 TRANS_MAX AHB master maximal transfer count occurrence. 2 1 VFIFO_AHBM_START_ADDR Video FIFO AHB Master Start Address Register. 0x538 32 AHBM_START_ADDR AHB master transfer starting address, word-aligned. 2 30 VFIFO_AHBM_ADDR_RANGE Video FIFO AHB Master Address Range Register. 0x53C 32 AHBM_ADDR_RANGE AHB master address range. 2 14 VFIFO_AHBM_MAX_TRANS Video FIFO AHB Master Maximal Transfer Number Register. 0x540 32 AHBM_MAX_TRANS AHB master maximal number of transfer word count. 0 32 VFIFO_AHBM_TRANS_CNT Video FIFO AHB Master Transfer Count Register. 0x544 32 AHBM_TRANS_CNT AHB master number of words been transferred. 0 32 RX_EINT_VFF_IE RX Video FIFO Interrupt Enable Register. 0x600 32 FNEMPTY Video FIFO not empty interrupt enable. 0 1 FTHD Video FIFO above threshold interrupt enable. 1 1 FFULL Video FIFO full interrupt enable. 2 1 UNDERRUN Video FIFO underrun interrupt enable 3 1 OVERRUN Video FIFO overrun interrupt enable 4 1 OUTSYNC CSI out of sync interrupt enable 5 1 FMTERR CSI Pixel Format Error interrupt enable 6 1 AHBWTO AHB wait time out interrupt enable 7 1 FS CSI Frame Start interrupt enable 8 1 FE CSI Frame End interrupt enable 9 1 LS CSI Line Start interrupt enable 10 1 LE CSI Line End interrupt enable 11 1 RAW_OVR Raw FIFO Overrun Interrupt Enable 12 1 RAW_AHBERR Raw AHB Error Interrupt Enable 13 1 FNEMP_MD Video FIFO not empty detection mode 16 1 FTHD_MD Video FIFO threshold detection mode 17 1 FFUL_MD Video FIFO full detection mode 18 1 AHBM_RDTO AHBM_RDTO 24 1 AHBM_IDTO AHBM_IDTO 25 1 AHBM_MAX AHBM_MAX 26 1 RX_EINT_VFF_IF RX Video FIFO Interrupt Flag Register. 0x604 32 FNEMPTY Video FIFO not empty interrupt flag. 0 1 FTHD Video FIFO above threshold interrupt flag. 1 1 FFULL Video FIFO full interrupt flag. 2 1 UNDERRUN Video FIFO underrun interrupt flag 3 1 OVERRUN Video FIFO overrun interrupt flag 4 1 OUTSYNC CSI out of sync interrupt flag 5 1 FMTERR CSI Pixel Format Error interrupt flag 6 1 AHBWTO AHB wait time out interrupt flag 7 1 FS CSI Frame Start interrupt flag 8 1 FE CSI Frame End interrupt flag 9 1 LS CSI Line Start interrupt flag 10 1 LE CSI Line End interrupt flag 11 1 RAW_OVR Raw FIFO Overrun Interrupt Enable 12 1 RAW_AHBERR Raw AHB Error Interrupt Enable 13 1 AHBM_RDTO AHBM_RDTO 24 1 AHBM_IDTO AHBM_IDTO 25 1 AHBM_MAX AHBM_MAX 26 1 RX_EINT_PPI_IE RX D-PHY Interrupt Enable Register. 0x608 32 DL0STOP DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt enable. 0 1 DL1STOP DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt enable. 1 1 CL0STOP DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt enable. 4 1 DL0ECONT0 DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt enable 6 1 DL0ECONT1 DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt enable 7 1 DL0ESOT DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt enable 8 1 DL1ESOT DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt enable 9 1 DL0ESOTS DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt enable 12 1 DL1ESOTS DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt enable 13 1 DL0EESC DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt enable 16 1 DL1EESC DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt enable 17 1 DL0ESESC DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable 20 1 DL1ESESC DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable 21 1 DL0ECTL DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt enable 24 1 DL1ECTL DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt enable 25 1 RX_EINT_PPI_IF RX D-PHY Interrupt Flag Register. 0x60C 32 DL0STOP DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt flag. 0 1 DL1STOP DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt flag. 1 1 CL0STOP DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt flag. 4 1 DL0ECONT0 DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt flag 6 1 DL0ECONT1 DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt flag 7 1 DL0ESOT DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt flag 8 1 DL1ESOT DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt flag 9 1 DL0ESOTS DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt flag 12 1 DL1ESOTS DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt flag 13 1 DL0EESC DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt flag 16 1 DL1EESC DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt flag 17 1 DL0ESESC DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag 20 1 DL1ESESC DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag 21 1 DL0ECTL DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt flag 24 1 DL1ECTL DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt flag 25 1 RX_EINT_CTRL_IE RX Controller Interrupt Enable Register. 0x610 32 EECC2 CSI RX ECC 2-bit Error interrupt enable. 0 1 EECC1 CSI RX ECC 1-bit Error interrupt enable. 1 1 ECRC CSI RX CRC Error interrupt enable. 2 1 EID CSI RX Packet Header Data ID Error interrupt enable 3 1 PKTFFOV CSI RX Packet FIFO Overrun interrupt enable 4 1 DL0ULPSA CSI Data Lane0 ULPSS Active interrupt enable 8 1 DL1ULPSA CSI Data Lane1 ULPSS Active interrupt enable 9 1 DL0ULPSM CSI Data Lane0 ULPSS Mark interrupt enable 12 1 DL1ULPSM CSI Data Lane1 ULPSS Mark interrupt enable 13 1 CL0ULPSA CSI Clock Lane0 ULPSS Active interrupt enable 16 1 CL0ULPSM CSI Data Lane0 ULPSS Mark interrupt enable 17 1 RX_EINT_CTRL_IF RX Controller Interrupt Flag Register. 0x614 32 EECC2 CSI RX ECC 2-bit Error interrupt flag. 0 1 EECC1 CSI RX ECC 1-bit Error interrupt flag. 1 1 ECRC CSI RX CRC Error interrupt flag. 2 1 EID CSI RX Packet Header Data ID Error interrupt flag 3 1 PKTFFOV CSI RX Packet FIFO Overrun interrupt flag 4 1 DL0ULPSA CSI Data Lane0 ULPSS Active interrupt flag 8 1 DL1ULPSA CSI Data Lane1 ULPSS Active interrupt flag 9 1 DL0ULPSM CSI Data Lane0 ULPSS Mark interrupt flag 12 1 DL1ULPSM CSI Data Lane1 ULPSS Mark interrupt flag 13 1 CL0ULPSA CSI Clock Lane0 ULPSS Active interrupt flag 16 1 CL0ULPSM CSI Data Lane0 ULPSS Mark interrupt flag 17 1 PPI_STOPSTATE DPHY PPI Stop State Register. 0x700 32 DL0STOP CSI Data Lane0 Stop State. 0 1 DL1STOP CSI Data Lane1 Stop State. 1 1 CL0STOP CSI Clock Lane0 Stop State. 2 1 PPI_TURNAROUND_CFG DPHY PPI Turn-Around Configuration Register. 0x704 32 DL0TAREQ CSI Data Lane0 turn around request. 0 1 DL0TADIS CSI Data Lane0 turn around disable. 1 1 DL0FRCRX CSI Data Lane0 force RX mode. 2 1 DMA DMA Controller Fully programmable, chaining capable DMA channels. 0x40028000 32 0x00 0x1000 registers DMA0 28 DMA1 29 DMA2 30 DMA3 31 DMA4 68 DMA5 69 DMA6 70 DMA7 71 DMA8 72 DMA9 73 DMA10 74 DMA11 75 DMA12 76 DMA13 77 DMA14 78 DMA15 79 INTEN DMA Control Register. 0x000 CH0 Channel 0 Interrupt Enable. 0 1 dis Disable. 0 en Enable. 1 CH1 Channel 1 Interrupt Enable. 1 1 CH2 Channel 2 Interrupt Enable. 2 1 CH3 Channel 3 Interrupt Enable. 3 1 CH4 Channel 4 Interrupt Enable. 4 1 CH5 Channel 5 Interrupt Enable. 5 1 CH6 Channel 6 Interrupt Enable. 6 1 CH7 Channel 7 Interrupt Enable. 7 1 INTFL DMA Interrupt Register. 0x004 read-only CH0 Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CH1 1 1 CH2 2 1 CH3 3 1 CH4 4 1 CH5 5 1 CH6 6 1 CH7 7 1 8 0x20 CH[%s] DMA Channel registers. dma_ch 0x100 read-write CTRL DMA Channel Control Register. 0x000 EN Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 RLDEN Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. 1 1 dis Disable. 0 en Enable. 1 PRI DMA Priority. 2 2 high Highest Priority. 0 medHigh Medium High Priority. 1 medLow Medium Low Priority. 2 low Lowest Priority. 3 REQUEST Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. 4 6 MEMTOMEM Memory To Memory 0x00 SPI1RX SPI1 RX 0x01 UART0RX UART0 RX 0x04 UART1RX UART1 RX 0x05 I2C0RX I2C0 RX 0x07 I2C1RX I2C1 RX 0x08 ADC ADC 0x09 I2C2RX I2C2 RX 0x0A CSI2RX CSI2 RX 0x0C PCIFRX PCIF RX 0x0D UART2RX UART2 RX 0x0E SPI0RX SPI0 RX 0x0F AESRX AES RX 0x10 I2SRX I2S RX 0x1E SPI1TX SPI1 TX 0x21 UART0TX UART0 TX 0x24 UART1TX UART1 TX 0x25 I2C0TX I2C0 TX 0x27 I2C1TX I2C1 TX 0x28 I2C2TX I2C2 TX 0x2A CRCTX CRC TX 0x2C UART2TX UART2 TX 0x2E SPI0TX SPI0 TX 0x2F AESTX AES TX 0x30 I2STX I2S TX 0x3E TO_WAIT Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. 10 1 dis Disable. 0 en Enable. 1 TO_PER Timeout Period Select. 11 3 to4 Timeout of 3 to 4 prescale clocks. 0 to8 Timeout of 7 to 8 prescale clocks. 1 to16 Timeout of 15 to 16 prescale clocks. 2 to32 Timeout of 31 to 32 prescale clocks. 3 to64 Timeout of 63 to 64 prescale clocks. 4 to128 Timeout of 127 to 128 prescale clocks. 5 to256 Timeout of 255 to 256 prescale clocks. 6 to512 Timeout of 511 to 512 prescale clocks. 7 TO_CLKDIV Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. 14 2 dis Disable timer. 0 div256 hclk / 256. 1 div64k hclk / 64k. 2 div16M hclk / 16M. 3 SRCWD Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. 16 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 SRCINC Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. 18 1 dis Disable. 0 en Enable. 1 DSTWD Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). 20 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 DSTINC Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. 22 1 dis Disable. 0 en Enable. 1 BURST_SIZE Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. 24 5 DIS_IE Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. 30 1 dis Disable. 0 en Enable. 1 CTZ_IE Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. 31 1 dis Disable. 0 en Enable. 1 STATUS DMA Channel Status Register. 0x004 STATUS Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). 0 1 read-only dis Disable. 0 en Enable. 1 IPEND Channel Interrupt. 1 1 read-only inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CTZ_IF Count-to-Zero (CTZ) Interrupt Flag 2 1 oneToClear RLD_IF Reload Event Interrupt Flag. 3 1 oneToClear BUS_ERR Bus Error. Indicates that an AHB abort was received and the channel has been disabled. 4 1 oneToClear TO_IF Time-Out Event Interrupt Flag. 6 1 oneToClear SRC Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. 0x008 ADDR 0 32 DST Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. 0x00C ADDR 0 32 CNT DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. 0x010 CNT DMA Counter. 0 24 SRCRLD Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. 0x014 ADDR Source Address Reload Value. 0 31 DSTRLD Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. 0x018 ADDR Destination Address Reload Value. 0 31 CNTRLD DMA Channel Count Reload Register. 0x01C CNT Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. 0 24 EN Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. 31 1 dis Disable. 0 en Enable. 1 DVS Dynamic Voltage Scaling DVS_ 0x40003C00 0x00 0x0030 registers DVS Dynamic Voltage Scaling Interrupt 83 CTL Control Register 0x00 MON_ENA Enable the DVS monitoring circuit 0 1 ADJ_ENA Enable the power supply adjustment based on measurements 1 1 PS_FB_DIS Power Supply Feedback Disable 2 1 CTRL_TAP_ENA Use the TAP Select for automatic adjustment or monitoring 3 1 PROP_DLY Additional delay to monitor lines 4 2 MON_ONESHOT Measure delay once 6 1 GO_DIRECT Operate in automatic mode or move directly 7 1 DIRECT_REG Step incrementally to target voltage 8 1 PRIME_ENA Include a delay line priming signal before monitoring 9 1 LIMIT_IE Enable Limit Error Interrupt 10 1 RANGE_IE Enable Range Error Interrupt 11 1 ADJ_IE Enable Adjustment Error Interrupt 12 1 REF_SEL Select TAP used for voltage adjustment 13 4 INC_VAL Step size to increment voltage when in automatic mode 17 3 DVS_PS_APB_DIS Prevent the application code from adjusting Vcore 20 1 DVS_HI_RANGE_ANY Any high range signal from a delay line will cause a voltage adjustment 21 1 FB_TO_IE Enable Voltage Adjustment Timeout Interrupt 22 1 FC_LV_IE Enable Low Voltage Interrupt 23 1 PD_ACK_ENA Prevent DVS from ack'ing a request to enter a low power mode until in the idle state 24 1 ADJ_ABORT Causes the DVS to enter the idle state immediately on a request to enter a low power mode 25 1 STAT Status Fields 0x04 0x00000000 DVS_STATE State machine state 0 4 ADJ_UP_ENA DVS Raising voltage 4 1 ADJ_DWN_ENA DVS Lowering voltage 5 1 ADJ_ACTIVE Adjustment to a Direct Voltage 6 1 CTR_TAP_OK Tap Enabled and the Tap is withing Hi/Low limits 7 1 CTR_TAP_SEL Status of selected center tap delay line detect output 8 1 SLOW_TRIP_DET Provides the current combined status of all selected Low Range delay lines 9 1 FAST_TRIP_DET Provides the current combined status of all selected High Range delay lines 10 1 PS_IN_RANGE Indicates if the power supply is in range 11 1 PS_VCNTR Voltage Count value sent to the power supply 12 7 MON_DLY_OK Indicates the monitor delay count is at 0 19 1 ADJ_DLY_OK Indicates the adjustment delay count is at 0 20 1 LO_LIMIT_DET Power supply voltage counter is at low limit 21 1 HI_LIMIT_DET Power supply voltage counter is at high limit 22 1 VALID_TAP At least one delay line has been enabled 23 1 LIMIT_ERR Interrupt flag that indicates a voltage count is at/beyond manufacturer limits 24 1 RANGE_ERR Interrupt flag that indicates a tap has an invalid value 25 1 ADJ_ERR Interrupt flag that indicates up and down adjustment requested simultaneously 26 1 REF_SEL_ERR Indicates the ref select register bit is out of range 27 1 FB_TO_ERR Interrupt flag that indicates a timeout while adjusting the voltage 28 1 FB_TO_ERR_S Interrupt flag that mirror FB_TO_ERR and is write one clear 29 1 FC_LV_DET_INT Interrupt flag that indicates the power supply voltage requested is below the low threshold 30 1 FC_LV_DET_S Interrupt flag that mirrors FC_LV_DET_INT 31 1 DIRECT Direct control of target voltage 0x08 VOLTAGE Sets the target power supply value 0 7 MON Monitor Delay 0x00C DLY Number of prescaled clocks between delay line samples 0 24 PRE Number of clocks before DVS_MON_DLY is decremented 24 8 ADJ_UP Up Delay Register 0x010 DLY Number of prescaled clocks between updates of the adjustment delay counter 0 16 PRE Number of clocks before DVS_ADJ_UP_DLY is decremented 16 8 ADJ_DWN Down Delay Register 0x014 DLY Number of prescaled clocks between updates of the adjustment delay counter 0 16 PRE Number of clocks before DVS_ADJ_DWN_DLY is decremented 16 8 THRES_CMP Up Delay Register 0x018 VCNTR_THRES_CNT Value used to determine 'low voltage' range 0 7 VCNTR_THRES_MASK Mask applied to threshold and vcount to determine if the device is in a low voltage range 8 7 5 4 TAP_SEL[%s] DVS Tap Select Register 0x1C LO Select delay line tap for lower bound of auto adjustment 0 5 LO_TAP_STAT Returns last delay line tap value 5 1 CTR_TAP_STAT Returns last delay line tap value 6 1 HI_TAP_STAT Returns last delay line tap value 7 1 HI Selects delay line tap for high point of auto adjustment 8 5 CTR Selects delay line tap for center point of auto adjustment 16 5 COARSE Selects delay line tap for coarse or fixed delay portion of the line 24 3 DET_DLY Number of HCLK between delay line launch and sampling 29 2 DELAY_ACT Set if the delay is active 31 1 FCR Function Control Register. 0x40000800 0x00 0x400 registers FCTRL0 Function Control 0. 0x00 read-write USBCLKSEL USB Core Clock Select. 16 2 I2C0DGEN0 I2C0 SDA Pad Deglitcher enable. 20 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C0DGEN1 I2C0 SCL Pad Deglitcher enable. 21 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C1DGEN0 I2C1 SDA Pad Deglitcher enable. 22 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C1DGEN1 I2C1 SCL Pad Deglitcher enable. 23 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C2DGEN0 I2C2 SDA Pad Deglitcher enable. 24 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C2DGEN1 I2C2 SCL Pad Deglitcher enable. 25 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 AUTOCAL0 Automatic Calibration 0. 0x04 read-write ACEN Auto-calibration Enable. 0 1 dis Disabled. 0 en Enabled. 1 ACRUN Autocalibration Run. 1 1 not Not Running. 0 run Running. 1 LDTRM Load Trim. 2 1 GAININV Invert Gain. 3 1 not Not Running. 0 run Running. 1 ATOMIC Atomic mode. 4 1 not Not Running. 0 run Running. 1 MU MU value. 8 12 HIRC96MACTMROUT HIRC96M Trim Value. 23 9 AUTOCAL1 Automatic Calibration 1. 0x08 read-write INITTRM Initial Trim Setting. 0 9 AUTOCAL2 Automatic Calibration 2 0x0C read-write DONECNT Auto-callibration Done Counter Setting. 0 8 ACDIV Auto-callibration Div Setting. 8 13 URVBOOTADDR RISC-V Boot Address. 0x10 read-write URVCTRL RISC-V Control Register. 0x14 read-write MEMSEL RAM2, RAM3 exclusive ownership. 0 1 IFLUSHEN URV instruction flush enable. 1 1 XO32MKS RISC-V Control Register. 0x18 read-write CLK Kick Start XO Counter Setting 0 7 EN Kick Start XO Enable 7 1 DRIVER Kick Start XO Driver 8 3 PULSE Kick Start XO 2X Pulse 11 1 CLKSEL Kick Start XO Clock Select 12 2 none No kick start clock. 0 test Test Clock in P1.2 (TMR3[22]=1). 1 ISO Internal secondary oscilator 2 IPO Internal Primary Oscilator 3 TS0 Temp Sensor trim0 0x20 read-write GAIN Unsigned gain for temp sensor normalization Temp degrees C = (ADC result * TS_GAIN) + TS_OFFSET. 0 12 TS1 Temp Sensor trim1 0x24 read-write OFFSET Signed gain for temp sensor normalization Temp degrees C = (ADC result * TS_GAIN) + TS_OFFSET. 0 14 TS_OFFSET_SIGN Sign extension of TS_OFFSET[13:0] 14 18 ADCREFTRIM0 Temp Sensor trim1 0x28 read-write VREFP Trimming code for VREFP output of reference buffer 0 7 VREFM Trimming code for VREFM output of reference buffer 8 7 VCM Trimming code for VCM output of reference buffer 16 2 VX2_TUNE Controls tuning capacitor in fine DAC (offset binary) 24 6 ADCREFTRIM1 Temp Sensor trim1 0x2C read-write VREFP Trimming code for VREFP output of reference buffer 0 7 VREFM Trimming code for VREFM output of reference buffer 8 7 VCM Trimming code for VCM output of reference buffer 16 2 VX2_TUNE Controls tuning capacitor in fine DAC (offset binary) 24 6 ADCREFTRIM2 Temp Sensor trim1 0x30 read-write VREFP Trimming code for VREFP output of reference buffer 0 7 VREFM Trimming code for VREFM output of reference buffer 8 7 VCM Trimming code for VCM output of reference buffer 16 2 VX2_TUNE Controls tuning capacitor in fine DAC (offset binary) 24 6 FLC Flash Memory Control. FLSH_ 0x40029000 0x00 0x1000 registers Flash_Controller Flash Controller interrupt. 23 ADDR Flash Write Address. 0x00 ADDR Address for next operation. 0 32 CLKDIV Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. 0x04 0x00000064 CLKDIV Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. 0 8 CTRL Flash Control Register. 0x08 WR Write. This bit is automatically cleared after the operation. 0 1 complete No operation/complete. 0 start Start operation. 1 ME Mass Erase. This bit is automatically cleared after the operation. 1 1 PGE Page Erase. This bit is automatically cleared after the operation. 2 1 WDTH Data Width. This bits selects write data width. 4 1 size128 128-bit. 0 size32 32-bit. 1 ERASE_CODE Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. 8 8 nop No operation. 0 erasePage Enable Page Erase. 0x55 eraseAll Enable Mass Erase. The debug port must be enabled. 0xAA PEND Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. 24 1 read-only idle Idle. 0 busy Busy. 1 LVE Low Voltage enable. 25 1 UNLOCK Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. 28 4 unlocked Flash Unlocked. 2 locked Flash Locked. 3 INTR Flash Interrupt Register. 0x24 DONE Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 AF Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. 1 1 noError No Failure. 0 error Failure occurs. 1 DONEIE Flash Done Interrupt Enable. 8 1 disable Disable. 0 enable Enable. 1 AFIE 9 1 4 4 DATA[%s] Flash Write Data. 0x30 DATA Data next operation. 0 32 ACTRL Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. 0x40 write-only ACTRL Access control. 0 32 WELR0 WELR0 0x80 WELR0 Access control. 0 32 RLR0 RLR0 0x84 RLR0 Access control. 0 32 WELR1 WELR1 0x88 WELR1 Access control. 0 32 RLR1 RLR1 0x8C RLR1 Access control. 0 32 WELR2 WELR2 90 WELR2 Access control. 0 32 RLR2 RLR2 0x94 RLR2 Access control. 0 32 WELR3 WELR3 0x98 WELR3 Access control. 0 32 RLR3 RLR3 0x9C RLR3 Access control. 0 32 WELR4 WELR4 0xA0 WELR4 Access control. 0 32 RLR4 RLR4 0xA4 RLR4 Access control. 0 32 GCR Global Control Registers. 0x40000000 0 0x400 registers SYSCTRL System Control. 0x00 0xFFFFFFFE BSTAPEN Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE. 0 1 FLASH_PAGE_FLIP Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 4 1 normal Physical layout matches logical layout. 0 swapped Bottom half mapped to logical top half and vice versa. 1 ICC0_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 ROMDONE ROM_DONE status. Used to disable SWD interface during system initialization procedure 12 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 SWD_DIS Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set). 14 1 CHKRES ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 OVR Operating Voltage Range. 16 2 V0_9 0.9V 0 V1_0 1.0V 1 V1_1 1.1V 2 RST0 Reset. 0x04 DMA DMA Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT0 Watchdog Timer 0 Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 TMR0 Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TMR1 Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TMR2 Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TMR3 Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 UART0 UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI1 SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 13 1 I2C0 I2C 0 Reset. 16 1 RTC Real Time Clock Reset. 17 1 SMPHR Semaphore Reset. 22 1 USB USB Reset. 23 1 TRNG TRNG Reset. This reset is only available during the manufacture testing phase. 24 1 CNN CNN Reset. 25 1 ADC ADC Reset. 26 1 UART2 UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. 28 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCTRL Clock Control. 0x08 0x00000008 SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the IPLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSCLK_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 ISO The internal 60 MHz oscillator is used for the system clock. 0 IPLL The internal 120 MHz IPLL is used for the system clock. 1 EBO The external 25 MHz input is used for the system clock. 2 INRO 8 kHz LIRC is used for the system clock. 3 IPO The internal 100 MHz oscillator is used for the system clock. 4 IBRO The internal 7.3725 MHz oscillator is used for the system clock. 5 ERTCO External 32 kHz input is used for the system clock. 6 EXTCLK External clock input is used for the system clock. 7 SYSCLK_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 EBO_EN External Base Oscillator 16 1 dis Is Disabled. 0 en Is Enabled. 1 ERTCO_EN 32 kHz Oscillator Enable. 17 1 ISO_EN 60 MHz Internal Oscillator Enable. 18 1 IPO_EN 100 MHz Clock Enable. 19 1 IBRO_EN 7.3725 MHz Clock Enable. 20 1 IBRO_VS 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO. 21 1 Vcor VCore Supply 0 1V Dedicated 1V regulated supply. 1 EBO_RDY External Base Oscillator Ready. 24 1 read-only not Is not Ready. 0 ready Is Ready. 1 ERTCO_RDY 32 kHz Crystal Oscillator Ready. 25 1 ISO_RDY 60 MHz Oscillator Ready. 26 1 IPO_RDY 100 MHz Clock Ready. 27 1 IBRO_RDY 7.3725 MHz HIRC Ready. 28 1 INRO_RDY 8 kHz Low Frequency Reference Clock Ready. 29 1 PM Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 4 active Active Mode. 0 sleep Cortex-M4 Active, RISC-V Sleep Mode. 1 standby Standby Mode. 2 backup Backup Mode. 4 lpm LPM or CM4 Deep Sleep Mode. 8 upm UPM. 9 powerdown Power Down Mode. 10 GPIO_WE GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTC_WE RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 USB_WE USB Wake Up Enable. This bit enables USB IRQ as wakeup source 6 1 WUT_WE WUT Wake Up Enable. This bit enables the Wake-Up Timer as wakeup source. 7 1 AINCOMP_WE AIN COMP Wake Up Enable. This bit enables AIN COMP as wakeup source. 9 1 ISO_PD 60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode. 15 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 IPO_PD 100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. 16 1 IBRO_PD 7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. 17 1 EBO_BP EBO Bypass 20 1 IPLL_CTRL IPLL Control 0x10 EN 0 1 RDY 1 1 PCLKDIV Peripheral Clock Divider. 0x18 0x00000001 SDIOCLKDIV 7 1 IPO_DIV2 48 MHz 0 IPO_DIV4 24 MHz 1 CNNCLKDIV CNN Clock Divider. 14 3 div2 0 div4 1 div8 2 div16 3 div1 4 CNNCLKSEL CNN Clock Select. 17 2 PCLK 0 ISO 1 IPLL 3 PCLKDIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Clock Disable. 1 1 USB USB Clock Disable. 3 1 DMA DMA Clock Disable. 5 1 SPI1 SPI 1 Clock Disable. 6 1 UART0 UART 0 Clock Disable. 9 1 UART1 UART 1 Clock Disable. 10 1 I2C0 I2C 0 Clock Disable. 13 1 TMR0 Timer 0 Clock Disable. 15 1 TMR1 Timer 1 Clock Disable. 16 1 TMR2 Timer 2 Clock Disable. 17 1 TMR3 Timer 3 Clock Disable. 18 1 ADC ADC Clock Disable. 23 1 CNN CNN Clock Disable. 25 1 I2C1 I2C 1 Clock Disable. 28 1 PT Pluse Train Clock Disable. 29 1 MEMCTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 SYSRAM0ECC SYSRAM0 ECC Select. 16 1 MEMZ Memory Zeroize Control. 0x2C RAM0 System RAM Block 0 Zeroization. 0 1 nop No operation/complete. 0 start Start operation. 1 RAM1 System RAM Block 1 Zeroization. 1 1 RAM2 System RAM Block 2 Zeroization. 2 1 RAM3 System RAM Block 3 Zeroization. 3 1 RAM4 System RAM Block 4 Zeroization. 4 1 RAM5 System RAM Block 5 Zeroization. 5 1 RAM6 System RAM Block 6 Zeroization. 6 1 RAM7 System RAM Block 7 Zeroization. 7 1 RAM0ECC System RAM Block 0 ECC Zeroization. 8 1 ICC0 Instruction Cache 0 Zeroization. 9 1 ICC1 Instruction Cache 1 Zeroization. 10 1 USBFIFO USB FIFO Zeroization. 11 1 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset_read read reset_done Reset complete. 0 busy Starts reset or indicates reset in progress. 1 PT PT Reset. 1 1 SDHC SDHC Reset. 6 1 OWM OWM Reset. 7 1 CRC CRC Reset. 9 1 AES AES Reset. 10 1 SPI0 SPI 0 Reset. 11 1 CSI2PHY CSI2 PHY Reset. 14 1 SMPHR SMPHR Reset. 16 1 I2S I2S Reset. 19 1 I2C2 I2C2 Reset. 20 1 DVS DVS Reset. 24 1 SIMO SIMO Reset. 25 1 PCIF PCIF Reset. 26 1 CSI2 CSI2 Reset. 27 1 CPU1 CPU1 Reset. 31 1 PCLKDIS1 Peripheral Clock Disable. 0x48 UART2 UART2 Clock Disable. 1 1 en Enable. 0 dis Disable. 1 TRNG TRNG Clock Disable. 2 1 SMPHR SMPHR Clock Disable. 9 1 SDHC SDHC Clock Disable. 10 1 OWM One-Wire Clock Disable. 13 1 CRC CRC Clock Disable. 14 1 AES AES Clock Disable. 15 1 SPI0 SPI0 AHB. 16 1 PCIF Parallel Camera Interface Clock Disable. 18 1 I2S I2S Clock Disable. 23 1 I2C2 I2C2 Clock Disable. 24 1 WDT0 Watch Dog Timer 0 Clock Disable. 27 1 CSI2 CSI2 Clock Disable. 30 1 CPU1 CPU1 Clock Disable. 31 1 EVENTEN Event Enable Register. 0x4C DMA Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 TX Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9. 2 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSIE System Status Interrupt Enable Register. 0x54 ICEUNLOCK ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 ECCERR ECC Error Register 0x64 RAM ECC System RAM0 Error Flag. Write 1 to clear. 0 1 ECCCED ECC Not Double Error Detect Register 0x68 RAM ECC System RAM0 Error Flag. Write 1 to clear. 0 1 ECCIE ECC IRQ Enable Register 0x6C RAM ECC System RAM0 Error Interrup Enable 0 1 ECCADDR ECC Error Address Register 0x70 ECCERRAD ECC Error Address. 0 32 GPR0 General Purpose Register 0 0x80 GCFR Global Control Function Register. 0x40005800 0x00 0x400 registers REG0 Register 0. 0x00 read-write cnnx16_0_pwr_en CNNx16_0 Power Domain Enable 0 1 cnnx16_1_pwr_en CNNx16_1 Power Domain Enable 1 1 cnnx16_2_pwr_en CNNx16_2 Power Domain Enable 2 1 cnnx16_3_pwr_en CNNx16_3 Power Domain Enable 3 1 REG1 Register 1. 0x04 read-write cnnx16_0_ram_en CNNx16_0 RAM Power Enable 0 1 cnnx16_1_ram_en CNNx16_1 RAM Power Enable 1 1 cnnx16_2_ram_en CNNx16_2 RAM Power Enable 2 1 cnnx16_3_ram_en CNNx16_3 RAM Power Enable 3 1 REG2 Register 2. 0x08 read-write cnnx16_0_iso CNNx16_0 Power Domain Isolation 0 1 cnnx16_1_iso CNNx16_1 Power Domain Isolation 1 1 cnnx16_2_iso CNNx16_2 Power Domain Isolation 2 1 cnnx16_3_iso CNNx16_3 Power Domain Isolation 3 1 cnnx16_0_data_ret_en CNNx16_0 Pad Retention Control 16 1 cnnx16_1_data_ret_en CNNx16_1 Pad Retention Control 17 1 cnnx16_2_data_ret_en CNNx16_2 Pad Retention Control 18 1 cnnx16_3_data_ret_en CNNx16_3 Pad Retention Control 19 1 cnnx16_0_ram_data_ret_en CNNx16_0 RAM Pad Retention Control 20 1 cnnx16_1_ram_data_ret_en CNNx16_1 RAM Pad Retention Control 21 1 cnnx16_2_ram_data_ret_en CNNx16_2 RAM Pad Retention Control 22 1 cnnx16_3_ram_data_ret_en CNNx16_3 RAM Pad Retention Control 23 1 REG3 Register 3. 0x0C read-write cnnx16_0_rst CNNx16_0 Power Domain Reset 0 1 cnnx16_1_rst CNNx16_1 Power Domain Reset 1 1 cnnx16_2_rst CNNx16_2 Power Domain Reset 2 1 cnnx16_3_rst CNNx16_3 Power Domain Reset 3 1 GPIO0 Individual I/O for each GPIO GPIO 0x40008000 0x00 0x1000 registers GPIO0 GPIO0 interrupt. 24 EN0 GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. 0x00 GPIO_EN Mask of all of the pins on the port. 0 32 ALTERNATE Alternate function enabled. 0 GPIO GPIO function is enabled. 1 EN0_SET GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. 0x04 ALL Mask of all of the pins on the port. 0 32 EN0_CLR GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. 0x08 ALL Mask of all of the pins on the port. 0 32 OUTEN GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. 0x0C EN Mask of all of the pins on the port. 0 32 dis GPIO Output Disable 0 en GPIO Output Enable 1 OUTEN_SET GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. 0x10 ALL Mask of all of the pins on the port. 0 32 OUTEN_CLR GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. 0x14 ALL Mask of all of the pins on the port. 0 32 OUT GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. 0x18 GPIO_OUT Mask of all of the pins on the port. 0 32 low Drive Logic 0 (low) on GPIO output. 0 high Drive logic 1 (high) on GPIO output. 1 OUT_SET GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. 0x1C write-only GPIO_OUT_SET Mask of all of the pins on the port. 0 32 no No Effect. 0 set Set GPIO_OUT bit in this position to '1' 1 OUT_CLR GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. 0x20 write-only GPIO_OUT_CLR Mask of all of the pins on the port. 0 32 IN GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. 0x24 read-only GPIO_IN Mask of all of the pins on the port. 0 32 INTMODE GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. 0x28 GPIO_INTMODE Mask of all of the pins on the port. 0 32 level Interrupts for this pin are level triggered. 0 edge Interrupts for this pin are edge triggered. 1 INTPOL GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. 0x2C GPIO_INTPOL Mask of all of the pins on the port. 0 32 falling Interrupts are latched on a falling edge or low level condition for this pin. 0 rising Interrupts are latched on a rising edge or high condition for this pin. 1 INEN GPIO Input Enable 0x30 INTEN GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. 0x34 GPIO_INTEN Mask of all of the pins on the port. 0 32 dis Interrupts are disabled for this GPIO pin. 0 en Interrupts are enabled for this GPIO pin. 1 INTEN_SET GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. 0x38 GPIO_INTEN_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set GPIO_INT_EN bit in this position to '1' 1 INTEN_CLR GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. 0x3C GPIO_INTEN_CLR Mask of all of the pins on the port. 0 32 no No Effect. 0 clear Clear GPIO_INT_EN bit in this position to '0' 1 INTFL GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. 0x40 read-only GPIO_INTFL Mask of all of the pins on the port. 0 32 no No Interrupt is pending on this GPIO pin. 0 pending An Interrupt is pending on this GPIO pin. 1 INTFL_CLR GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. 0x48 ALL Mask of all of the pins on the port. 0 32 WKEN GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. 0x4C GPIO_WKEN Mask of all of the pins on the port. 0 32 dis PMU wakeup for this GPIO is disabled. 0 en PMU wakeup for this GPIO is enabled. 1 WKEN_SET GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. 0x50 ALL Mask of all of the pins on the port. 0 32 WKEN_CLR GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. 0x54 ALL Mask of all of the pins on the port. 0 32 DUALEDGE GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. 0x5C GPIO_DUALEDGE Mask of all of the pins on the port. 0 32 no No Effect. 0 en Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. 1 PADCTRL0 GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x60 GPIO_PADCTRL0 The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Weak pull-up mode. 1 pd weak pull-down mode. 2 PADCTRL1 GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x64 GPIO_PADCTRL1 The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Weak pull-up mode. 1 pd weak pull-down mode. 2 EN1 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x68 GPIO_EN1 Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 EN1_SET GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. 0x6C ALL Mask of all of the pins on the port. 0 32 EN1_CLR GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. 0x70 ALL Mask of all of the pins on the port. 0 32 EN2 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x74 GPIO_EN2 Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 EN2_SET GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. 0x78 ALL Mask of all of the pins on the port. 0 32 EN2_CLR GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. 0x7C ALL Mask of all of the pins on the port. 0 32 HYSEN GPIO Input Hysteresis Enable. 0xA8 GPIO_HYSEN Mask of all of the pins on the port. 0 32 SRSEL GPIO Slew Rate Enable Register. 0xAC GPIO_SRSEL Mask of all of the pins on the port. 0 32 FAST Fast Slew Rate selected. 0 SLOW Slow Slew Rate selected. 1 DS0 GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. 0xB0 GPIO_DS0 Mask of all of the pins on the port. 0 32 ld GPIO port pin is in low-drive mode. 0 hd GPIO port pin is in high-drive mode. 1 DS1 GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. 0xB4 GPIO_DS1 Mask of all of the pins on the port. 0 32 PS GPIO Pull Select Mode. 0xB8 ALL Mask of all of the pins on the port. 0 32 VSSEL GPIO Voltage Select. 0xC0 ALL Mask of all of the pins on the port. 0 32 GPIO1 Individual I/O for each GPIO 1 0x40009000 GPIO1 GPIO1 IRQ 25 GPIO2 Individual I/O for each GPIO 2 0x40080400 GPIO2 GPIO2 IRQ 26 I2C0 Inter-Integrated Circuit. I2C 0x4001D000 32 0x00 0x1000 registers I2C0 I2C0 IRQ 13 CTRL Control Register0. 0x00 EN I2C Enable. [0:0] read-write dis Disable I2C. 0 en enable I2C. 1 MST_MODE Master Mode Enable. [1:1] read-write slave_mode Slave Mode. 0 master_mode Master Mode. 1 GC_ADDR_EN General Call Address Enable. [2:2] read-write dis Ignore Gneral Call Address. 0 en Acknowledge general call address. 1 IRXM_EN Interactive Receive Mode. [3:3] read-write dis Disable Interactive Receive Mode. 0 en Enable Interactive Receive Mode. 1 IRXM_ACK Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. [4:4] read-write ack return ACK (pulling SDA LOW). 0 nack return NACK (leaving SDA HIGH). 1 SCL_OUT SCL Output. This bits control SCL output when SWOE =1. [6:6] read-write drive_scl_low Drive SCL low. 0 release_scl Release SCL. 1 SDA_OUT SDA Output. This bits control SDA output when SWOE = 1. [7:7] read-write drive_sda_low Drive SDA low. 0 release_sda Release SDA. 1 SCL SCL status. This bit reflects the logic gate of SCL signal. [8:8] read-only SDA SDA status. THis bit reflects the logic gate of SDA signal. [9:9] read-only BB_MODE Software Output Enable. [10:10] read-write outputs_disable I2C Outputs SCLO and SDAO disabled. 0 outputs_enable I2C Outputs SCLO and SDAO enabled. 1 READ Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. [11:11] read-only write Write. 0 read Read. 1 CLKSTR_DIS This bit will disable slave clock stretching when set. [12:12] read-write en Slave clock stretching enabled. 0 dis Slave clock stretching disabled. 1 ONE_MST_MODE SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. [13:13] read-write dis Standard open-drain operation: drive low for 0, Hi-Z for 1 0 en Non-standard push-pull operation: drive low for 0, drive high for 1 1 HS_EN High speed mode enable [15:15] read-write STATUS Status Register. 0x04 BUSY Bus Status. [0:0] read-only idle I2C Bus Idle. 0 busy I2C Bus Busy. 1 RX_EM RX empty. [1:1] read-only not_empty Not Empty. 0 empty Empty. 1 RX_FULL RX Full. [2:2] read-only not_full Not Full. 0 full Full. 1 TX_EM TX Empty. [3:3] not_empty Not Empty. 0 empty Empty. 1 TX_FULL TX Full. [4:4] not_empty Not Empty. 0 empty Empty. 1 MST_BUSY Clock Mode. [5:5] read-only not_actively_driving_scl_clock Device not actively driving SCL clock cycles. 0 actively_driving_scl_clock Device operating as master and actively driving SCL clock cycles. 1 INTFL0 Interrupt Status Register. 0x08 DONE Transfer Done Interrupt. [0:0] INT_FL0_Done inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 IRXM Interactive Receive Interrupt. [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 GC_ADDR_MATCH Slave General Call Address Match Interrupt. [2:2] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADDR_MATCH Slave Address Match Interrupt. [3:3] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 RX_THD Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. [4:4] inactive No interrupt is pending. 0 pending An interrupt is pending. RX_FIFO equal or more bytes than the threshold. 1 TX_THD Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. [5:5] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 STOP STOP Interrupt. [6:6] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 ADDR_ACK Address Acknowledge Interrupt. [7:7] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ARB_ERR Arbritation error Interrupt. [8:8] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TO_ERR timeout Error Interrupt. [9:9] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADDR_NACK_ERR Address NACK Error Interrupt. [10:10] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DATA_ERR Data NACK Error Interrupt. [11:11] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DNR_ERR Do Not Respond Error Interrupt. [12:12] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 START_ERR Start Error Interrupt. [13:13] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 STOP_ERR Stop Error Interrupt. [14:14] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TX_LOCKOUT Transmit Lock Out Interrupt. [15:15] MAMI Multiple Address Match Interrupt [21:16] RD_ADDR_MATCH Slave Read Address Match Interrupt [22:22] WR_ADDR_MATCH Slave Write Address Match Interrupt [23:23] INTEN0 Interrupt Enable Register. 0x0C read-write DONE Transfer Done Interrupt Enable. [0:0] read-write dis Interrupt disabled. 0 en Interrupt enabled when DONE = 1. 1 IRXM Description not available. [1:1] read-write dis Interrupt disabled. 0 en Interrupt enabled when RX_MODE = 1. 1 GC_ADDR_MATCH Slave mode general call address match received input enable. [2:2] read-write dis Interrupt disabled. 0 en Interrupt enabled when GEN_CTRL_ADDR = 1. 1 ADDR_MATCH Slave mode incoming address match interrupt. [3:3] read-write dis Interrupt disabled. 0 en Interrupt enabled when ADDR_MATCH = 1. 1 RX_THD RX FIFO Above Treshold Level Interrupt Enable. [4:4] read-write dis Interrupt disabled. 0 en Interrupt enabled. 1 TX_THD TX FIFO Below Treshold Level Interrupt Enable. [5:5] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOP Stop Interrupt Enable [6:6] read-write dis Interrupt disabled. 0 en Interrupt enabled when STOP = 1. 1 ADDR_ACK Received Address ACK from Slave Interrupt. [7:7] dis Interrupt disabled. 0 en Interrupt enabled. 1 ARB_ERR Master Mode Arbitration Lost Interrupt. [8:8] dis Interrupt disabled. 0 en Interrupt enabled. 1 TO_ERR Timeout Error Interrupt Enable. [9:9] dis Interrupt disabled. 0 en Interrupt enabled. 1 ADDR_NACK_ERR Master Mode Address NACK Received Interrupt. [10:10] dis Interrupt disabled. 0 en Interrupt enabled. 1 DATA_ERR Master Mode Data NACK Received Interrupt. [11:11] dis Interrupt disabled. 0 en Interrupt enabled. 1 DNR_ERR Slave Mode Do Not Respond Interrupt. [12:12] dis Interrupt disabled. 0 en Interrupt enabled. 1 START_ERR Out of Sequence START condition detected interrupt. [13:13] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOP_ERR Out of Sequence STOP condition detected interrupt. [14:14] dis Interrupt disabled. 0 en Interrupt enabled. 1 TX_LOCKOUT TX FIFO Locked Out Interrupt. [15:15] MAMI Multiple Address Match Interrupt [21:16] RD_ADDR_MATCH Slave Read Address Match Interrupt [22:22] WR_ADDR_MATCH Slave Write Address Match Interrupt [23:23] INTFL1 Interrupt Status Register 1. 0x10 RX_OV Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. [0:0] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TX_UN Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 START START Condition Status Flag. [2:2] INTEN1 Interrupt Staus Register 1. 0x14 read-write RX_OV Receiver Overflow Interrupt Enable. [0:0] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 TX_UN Transmit Underflow Interrupt Enable. [1:1] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 START START Condition Interrupt Enable. [2:2] FIFOLEN FIFO Configuration Register. 0x18 RX_DEPTH Receive FIFO Length. [7:0] read-only TX_DEPTH Transmit FIFO Length. [15:8] read-only RXCTRL0 Receive Control Register 0. 0x1C DNR Do Not Respond. [0:0] respond Always respond to address match. 0 not_respond_rx_fifo_empty Do not respond to address match when RX_FIFO is not empty. 1 FLUSH Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. [7:7] not_flushed FIFO not flushed. 0 flush Flush RX_FIFO. 1 THD_LVL Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. [11:8] RXCTRL1 Receive Control Register 1. 0x20 CNT Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. [7:0] LVL Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. [11:8] read-only TXCTRL0 Transmit Control Register 0. 0x24 PRELOAD_MODE Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. [0:0] TX_READY_MODE Transmit FIFO Ready Manual Mode. [1:1] en HW control of I2CTXRDY enabled. 0 dis HW control of I2CTXRDY disabled. 1 GC_ADDR_FLUSH_DIS TX FIFO General Call Address Match Auto Flush Disable. [2:2] en Enabled. 0 dis Disabled. 1 WR_ADDR_FLUSH_DIS TX FIFO Slave Address Match Write Auto Flush Disable. [3:3] en Enabled. 0 dis Disabled. 1 RD_ADDR_FLUSH_DIS TX FIFO Slave Address Match Read Auto Flush Disable. [4:4] en Enabled. 0 dis Disabled. 1 NACK_FLUSH_DIS TX FIFO received NACK Auto Flush Disable. [5:5] en Enabled. 0 dis Disabled. 1 FLUSH Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. [7:7] not_flushed FIFO not flushed. 0 flush Flush TX_FIFO. 1 THD_VAL Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. [11:8] TXCTRL1 Transmit Control Register 1. 0x28 PRELOAD_RDY Transmit FIFO Preload Ready. [0:0] LVL Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. [11:8] read-only FIFO Data Register. 0x2C DATA Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. 0 8 MSTCTRL Master Control Register. 0x30 START Setting this bit to 1 will start a master transfer. [0:0] RESTART Setting this bit to 1 will generate a repeated START. [1:1] STOP Setting this bit to 1 will generate a STOP condition. [2:2] EX_ADDR_EN Slave Extend Address Select. [7:7] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 CLKLO Clock Low Register. 0x34 LO Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. [8:0] CLKHI Clock high Register. 0x38 HI Clock High. In master mode, these bits define the SCL high period. [8:0] HSCLK Clock high Register. 0x3C LO Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. [7:0] HI Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA [15:8] TIMEOUT Timeout Register 0x40 SCL_TO_VAL Timeout [15:0] DMA DMA Register. 0x48 TX_EN TX channel enable. [0:0] dis Disable. 0 en Enable. 1 RX_EN RX channel enable. [1:1] dis Disable. 0 en Enable. 1 4 4 SLAVE_MULTI[%s] Slave Address Register. SLAVE0 0x4C 32 read-write ADDR Slave Address. [9:0] DIS Slave Disable. [10:10] EXT_ADDR_EN Extended Address Select. [15:15] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 SLAVE0 Slave Address Register. 0x4C SLAVE1 Slave Address Register. 0x50 SLAVE2 Slave Address Register. 0x54 SLAVE3 Slave Address Register. 0x58 I2C1 Inter-Integrated Circuit. 1 0x4001E000 I2C1 I2C1 IRQ 36 I2C2 Inter-Integrated Circuit. 2 0x4001F000 I2C2 I2C2 IRQ 62 I2S Inter-IC Sound Interface. I2S 0x40060000 32 0x00 0x1000 registers I2S I2S IRQ 99 CTRL0CH0 Global mode channel. 0x00 LSB_FIRST LSB Transmit Receive First. [1:1] read-write PDM_FILT PDM Filter. [2:2] read-write PDM_EN PDM Enable. [3:3] read-write USEDDR DDR. [4:4] read-write PDM_INV Invert PDM. [5:5] read-write CH_MODE SCK Select. [7:6] read-write WS_POL WS polarity select. [8:8] read-write MSB_LOC MSB location. [9:9] read-only ALIGN Align to MSB or LSB. [10:10] read-only EXT_SEL External SCK/WS selection. [11:11] read-write STEREO Stereo mode of I2S. [13:12] read-only WSIZE Data size when write to FIFO. [15:14] read-write TX_EN TX channel enable. [16:16] read-write RX_EN RX channel enable. [17:17] read-write FLUSH Flushes the TX/RX FIFO buffer. [18:18] read-write RST Write 1 to reset channel. [19:19] read-write FIFO_LSB Bit Field Control. [20:20] read-write RX_THD_VAL depth of receive FIFO for threshold interrupt generation. [31:24] read-write CTRL1CH0 Local channel Setup. 0x10 BITS_WORD I2S word length. [4:0] read-write EN I2S clock enable. [8:8] read-write SMP_SIZE I2S sample size length. [13:9] read-write CLKSEL I2S clock select. [14:14] read-write ADJUST LSB/MSB Justify. [15:15] read-write CLKDIV I2S clock frequency divisor. [31:16] read-write FILTCH0 Filter. 0x20 DMACH0 DMA Control. 0x30 DMA_TX_THD_VAL TX FIFO Level DMA Trigger. [6:0] read-write DMA_TX_EN TX DMA channel enable. [7:7] read-write DMA_RX_THD_VAL RX FIFO Level DMA Trigger. [14:8] read-write DMA_RX_EN RX DMA channel enable. [15:15] read-write TX_LVL Number of data word in the TX FIFO. [23:16] read-write RX_LVL Number of data word in the RX FIFO. [31:24] read-write FIFOCH0 I2S Fifo. 0x40 DATA Load/unload location for TX and RX FIFO buffers. [31:0] read-write INTFL ISR Status. 0x50 RX_OV_CH0 Status for RX FIFO Overrun interrupt. [0:0] read-write RX_THD_CH0 Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. [1:1] read-write TX_OB_CH0 Status for interrupt when TX FIFO has only one byte remaining. [2:2] read-write TX_HE_CH0 Status for interrupt when TX FIFO is half empty. [3:3] read-write INTEN Interrupt Enable. 0x54 RX_OV_CH0 Enable for RX FIFO Overrun interrupt. [0:0] read-write RX_THD_CH0 Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. [1:1] read-write TX_OB_CH0 Enable for interrupt when TX FIFO has only one byte remaining. [2:2] read-write TX_HE_CH0 Enable for interrupt when TX FIFO is half empty. [3:3] read-write EXTSETUP Ext Control. 0x58 EXT_BITS_WORD Word Length for ch_mode. [4:0] read-write WKEN Wakeup Enable. 0x5C WKFL Wakeup Flags. 0x60 ICC0 Instruction Cache Controller Registers 0x4002A000 0x00 0x800 registers INFO Cache ID Register. 0x0000 read-only RELNUM Release Number. Identifies the RTL release version. 0 6 PARTNUM Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. 6 4 ID Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. 10 6 SZ Memory Configuration Register. 0x0004 read-only 0x00080008 CCH Cache Size. Indicates total size in Kbytes of cache. 0 16 MEM Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. 16 16 CTRL Cache Control and Status Register. 0x0100 EN Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. 0 1 dis Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. 0 en Cache Enabled. 1 RDY Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. 16 1 read-only notReady Not Ready. 0 ready Ready. 1 INVALIDATE Invalidate All Registers. 0x0700 read-write INVALID Invalidate. 0 32 ICC1 Instruction Cache Controller Registers 1 0x4002AC00 LPCMP Low Power Comparator 0x40088000 0x00 0x400 registers LPCMP Low Power Comparato 103 3 4 CTRL[%s] Comparator Control Register. 0x00 EN Comparator Enable. 0 1 POL Polarity Select 5 1 INT_EN IRQ Enable. 6 1 OUT Raw Compartor Input. 14 1 INT_FL IRQ Flag 15 1 LPGCR Low Power Global Control. 0x40080000 0x00 0x400 registers RST Low Power Reset Register. 0x08 GPIO2 Low Power GPIO 2 Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT1 Low Power Watchdog Timer 1 Reset. 1 1 TMR4 Low Power Timer 4 Reset. 2 1 TMR5 Low Power Timer 5 Reset. 3 1 UART3 Low Power UART 3 Reset. 4 1 LPCOMP Low Power Comparator Reset. 6 1 PCLKDIS Low Power Peripheral Clock Disable Register. 0x0C GPIO2 Low Power GPIO 2 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 WDT1 Low Power Watchdog 1 Clock Disable. 1 1 TMR4 Low Power Timer 4 Clock Disable. 2 1 TMR5 Low Power Timer 5 Clock Disable. 3 1 UART3 Low Power UART 3 Clock Disable. 4 1 LPCOMP Low Power Comparator Clock Disable. 6 1 MCR Misc Control. 0x40006C00 0x00 0x400 registers ECCEN ECC Enable Register 0x00 RAM0 ECC System RAM0 Enable. 0 1 dis disabled. 0 en enabled. 1 IPO_MTRIM IPO Manual Register 0x04 MTRIM Manual Trim Value. 0 8 TRIM_RANGE Trim Range Select. 8 1 OUTEN Output Enable Register 0x08 SQWOUT_EN Square Wave Output Enable. 0 1 PDOWN_OUT_EN Power Down Output Enable. 1 1 CMP_CTRL Comparator Control Register. 0x0C EN Comparator Enable. 0 1 POL Polarity Select 5 1 INT_EN IRQ Enable. 6 1 OUT Comparator Output State. 14 1 INT_FL IRQ Flag 15 1 CTRL Miscellaneous Control Register. 0x10 CMPHYST Comparator HYST. 0 2 INRO_EN INRO Enable. 2 1 ERTCO_EN ERTCO Enable. 3 1 IBRO_EN IBRO Enable. 4 1 SIMO_CLKSCL_EN SIMO Clock Scaling Enable. 8 1 SIMO_RSTD SIMO System Reset Disable. 9 1 GPIO3_CTRL GPIO3 Pin Control Register. 0x20 P30_DO GPIO3 Pin 0 Data Output. 0 1 P30_OE GPIO3 Pin 0 Output Enable. 1 1 P30_PE GPIO3 Pin 0 Pull-up Enable. 2 1 P30_IN GPIO3 Pin 0 Input Status. 3 1 P31_DO GPIO3 Pin 1 Data Output. 4 1 P31_OE GPIO3 Pin 1 Output Enable. 5 1 P31_PE GPIO3 Pin 1 Pull-up Enable. 6 1 P31_IN GPIO3 Pin 1 Input Status. 7 1 CWD0 Code Word Data0 0x40 data Code word Data0 the register retains its value while vregi supply present 0 32 CWD1 Code Word Data1 0x44 data Code word Data0 the register retains its value while vregi supply present 0 32 ADCCFG0 ADC Config 0 0x50 LP_5K_DIS Disable 5K divider optionin low power modes 0 1 LP_50K_DIS Disable 50K divider optionin low power modes 1 1 EXT_REF External Reference Select Option 2 1 REF_SEL Internal Reference Select Option 3 1 ADCCFG1 ADC Config 1 0x54 CHX_PU_DYN ADC PU dynamic control 0 13 ADCCFG2 ADC Config 2 0x58 CH0 Divider option for ADC input channel 0 0 2 div1 div1 0 div2_5k 5k ohom 1 div2_50k 50k ohom 2 CH1 Divider option for ADC input channel 1 2 2 CH2 Divider option for ADC input channel 2 4 2 CH3 Divider option for ADC input channel 3 6 2 CH4 Divider option for ADC input channel 4 8 2 CH5 Divider option for ADC input channel 5 10 2 CH6 Divider option for ADC input channel 6 12 2 CH7 Divider option for ADC input channel 7 14 2 LDOCTRL LDO Control 0x60 0P9EN LDO 0.9V Enable 0 1 2P5EN LDO 2.5V Enable 1 1 OWM 1-Wire Master Interface. 0x4003D000 32 read-write 0 0x1000 registers OneWire 67 CFG 1-Wire Master Configuration. 0x0000 read-write long_line_mode Long Line Mode. [0:0] read-write force_pres_det Force Line During Presence Detect. [1:1] read-write bit_bang_en Bit Bang Enable. [2:2] read-write ext_pullup_mode Provide an extra output control to control an external pullup. [3:3] read-write ext_pullup_enable Enable External Pullup. [4:4] read-write single_bit_mode Enable Single Bit TX/RX Mode. [5:5] read-write overdrive Enables overdrive speed for 1-Wire operations. [6:6] read-write int_pullup_enable Enable intenral pullup. [7:7] read-write CLK_DIV_1US 1-Wire Master Clock Divisor. 0x0004 read-write divisor Clock Divisor for 1Mhz. [7:0] read-write CTRL_STAT 1-Wire Master Control/Status. 0x0008 read-write start_ow_reset Start OW Reset. [0:0] read-write sra_mode SRA Mode. [1:1] read-write bit_bang_oe Bit Bang Output Enable. [2:2] read-write ow_input OW Input State. [3:3] read-only od_spec_mode Overdrive Spec Mode. [4:4] read-only presence_detect Presence Pulse Detected. [7:7] read-only DATA 1-Wire Master Data Buffer. 0x000C read-write tx_rx TX/RX Buffer. [7:0] read-write INTFL 1-Wire Master Interrupt Flags. 0x0010 read-write ow_reset_done OW Reset Sequence Completed. [0:0] read-write tx_data_empty TX Data Empty Interrupt Flag. [1:1] read-write rx_data_ready RX Data Ready Interrupt Flag [2:2] read-write line_short OW Line Short Detected Interrupt Flag. [3:3] read-write line_low OW Line Low Detected Interrupt Flag. [4:4] read-write INTEN 1-Wire Master Interrupt Enables. 0x0014 read-write ow_reset_done OW Reset Sequence Completed. [0:0] read-write oneToClear tx_data_empty Tx Data Empty Interrupt Enable. [1:1] read-write oneToClear rx_data_ready Rx Data Ready Interrupt Enable. [2:2] read-write oneToClear line_short OW Line Short Detected Interrupt Enable. [3:3] read-write oneToClear line_low OW Line Low Detected Interrupt Enable. [4:4] read-write oneToClear PT Pulse Train Pulse_Train 0x4003C020 32 read-write 0 0x0010 registers RATE_LENGTH Pulse Train Configuration 0x0000 read-write rate_control Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train. 0 27 read-write mode Pulse Train Output Mode/Train Length 27 5 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 2_BIT Pulse train, 2 bit pattern. 2 3_BIT Pulse train, 3 bit pattern. 3 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 TRAIN Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length. 0x0004 read-write LOOP Pulse Train Loop Count 0x0008 read-write count Number of loops for this pulse train to repeat. 0 16 read-write delay Delay between loops of the Pulse Train in PT Peripheral Clock cycles 16 12 read-write RESTART Pulse Train Auto-Restart Configuration. 0x000C read-write pt_x_select Auto-Restart PT X Select 0 5 read-write on_pt_x_loop_exit Enable Auto-Restart on PT X Loop Exit 7 1 read-write pt_y_select Auto-Restart PT Y Select 8 5 read-write on_pt_y_loop_exit Enable Auto-Restart on PT Y Loop Exit 15 1 read-write PT1 Pulse Train 1 0x4003C030 PT2 Pulse Train 2 0x4003C040 PT3 Pulse Train 3 0x4003C050 PTG Pulse Train Generation Pulse_Train 0x4003C000 32 read-write 0 0x0020 registers PT Pulse Train IRQ 59 ENABLE Global Enable/Disable Controls for All Pulse Trains 0x0000 read-write pt0 Enable/Disable control for PT0 0 1 read-write pt1 Enable/Disable control for PT1 1 1 read-write pt2 Enable/Disable control for PT2 2 1 read-write pt3 Enable/Disable control for PT3 3 1 read-write RESYNC Global Resync (All Pulse Trains) Control 0x0004 read-write pt0 Resync control for PT0 0 1 read-write pt1 Resync control for PT1 1 1 read-write pt2 Resync control for PT2 2 1 read-write pt3 Resync control for PT3 3 1 read-write INTFL Pulse Train Interrupt Flags 0x0008 read-write pt0 Pulse Train 0 Stopped Interrupt Flag 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Flag 1 1 read-write pt2 Pulse Train 2 Stopped Interrupt Flag 2 1 read-write pt3 Pulse Train 3 Stopped Interrupt Flag 3 1 read-write INTEN Pulse Train Interrupt Enable/Disable 0x000C read-write pt0 Pulse Train 0 Stopped Interrupt Enable/Disable 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Enable/Disable 1 1 read-write pt2 Pulse Train 2 Stopped Interrupt Enable/Disable 2 1 read-write pt3 Pulse Train 3 Stopped Interrupt Enable/Disable 3 1 read-write SAFE_EN Pulse Train Global Safe Enable. 0x0010 write-only PT0 0 1 write-only PT1 1 1 write-only PT2 2 1 write-only PT3 3 1 write-only SAFE_DIS Pulse Train Global Safe Disable. 0x0014 write-only PT0 0 1 write-only PT1 1 1 write-only PT2 2 1 write-only PT3 3 1 write-only PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers LPCN Low Power Control Register. 0x00 RAMRET0 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 1 dis Disable Ram Retention. 0 en Enable System RAM 0 retention. 1 RAMRET1 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 1 1 dis Disable Ram Retention. 0 en Enable System RAM 1 retention. 1 RAMRET2 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 2 1 dis Disable Ram Retention. 0 en Enable System RAM 2 retention. 1 RAMRET3 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 3 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 RAMRET4 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 4 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 RAMRET5 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 5 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 RAMRET6 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 6 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 RAMRET7 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 7 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 ISOCLK_SELECT 0 = PCLK 1= ISO CLK use for RISV in Low power mode 8 1 FAST_ENTRY_DIS Fast Low Power mode entry disable 9 1 BGOFF Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode (default). 1 WKRST Reset wakeup status registers 31 1 LPWKST0 Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 1 LPWKEN0 Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 LPWKST1 Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 10 LPWKEN1 Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 10 LPWKST2 Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2. 0x14 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 8 LPWKEN2 Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2. 0x18 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 8 LPWKST3 Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3. 0x1C WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 2 LPWKEN3 Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3. 0x20 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 2 LPPWST Low Power Peripheral Wakeup Status Register. 0x30 AINCOMP0 Analog Input Comparator Wakeup Flag. 4 1 BACKUP Backup Mode Wakeup Flag. 16 1 RESET Reset Detected Wakeup Flag. 17 1 LPPWEN Low Power Peripheral Wakeup Enable Register. 0x34 USBLS USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set. 0 2 USBVBUS USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. 2 1 AINCOMP0 AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. 4 1 WDT0 WDT0 Wakeup Enable. This bit allows wakeup from the WDT0. 8 1 WDT1 WDT1 Wakeup Enable. This bit allows wakeup from the WDT1. 9 1 CPU1 CPU1 Wakeup Enable. This bit allows wakeup from the CPU1. 10 1 TMR0 TMR0 Wakeup Enable. This bit allows wakeup from the TMR0. 11 1 TMR1 TMR1 Wakeup Enable. This bit allows wakeup from the TMR1. 12 1 TMR2 TMR2 Wakeup Enable. This bit allows wakeup from the TMR2. 13 1 TMR3 TMR3 Wakeup Enable. This bit allows wakeup from the TMR3. 14 1 TMR4 TMR4 Wakeup Enable. This bit allows wakeup from the TMR4. 15 1 TMR5 TMR5 Wakeup Enable. This bit allows wakeup from the TMR5. 16 1 UART0 UART0 Wakeup Enable. This bit allows wakeup from the UART0. 17 1 UART1 UART1 Wakeup Enable. This bit allows wakeup from the UART1. 18 1 UART2 UART2 Wakeup Enable. This bit allows wakeup from the UART2. 19 1 UART3 UART3 Wakeup Enable. This bit allows wakeup from the UART3. 20 1 I2C0 I2C0 Wakeup Enable. This bit allows wakeup from the I2C0. 21 1 I2C1 I2C1 Wakeup Enable. This bit allows wakeup from the I2C1. 22 1 I2C2 I2C2 Wakeup Enable. This bit allows wakeup from the I2C2. 23 1 I2S I2S Wakeup Enable. This bit allows wakeup from the I2S. 24 1 SPI1 SPI1 Wakeup Enable. This bit allows wakeup from the SPI0. 25 1 LPCMP LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP. 26 1 GP0 General Purpose Register 0 0x48 GP1 General Purpose Register 1 0x4C RTC Real Time Clock and Alarm. 0x40006000 0x00 0x400 registers RTC RTC interrupt. 3 SEC RTC Second Counter. This register contains the 32-bit second counter. 0x00 0x00000000 SEC Seconds Counter. 0 32 SSEC RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 SSEC Sub-Seconds Counter (12-bit). 0 12 TODA Time-of-day Alarm. 0x08 0x00000000 TOD_ALARM Time-of-day Alarm. 0 20 SSECA RTC sub-second alarm. This register contains the reload value for the sub-second alarm. 0x0C 0x00000000 SSEC_ALARM This register contains the reload value for the sub-second alarm. 0 32 CTRL RTC Control Register. 0x10 0x00000008 0xFFFFFF38 EN Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 TOD_ALARM_IE Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 SSEC_ALARM_IE Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 RDY RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 4 1 busy Register has not updated. 0 ready Ready. 1 RDY_IE RTC Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 TOD_ALARM Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active 0 Pending Active 1 SSEC_ALARM Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active 0 Pending Active 1 SQW_EN Square Wave Output Enable. 8 1 inactive Not active 0 Pending Active 1 SQW_SEL Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 9 2 freq1Hz 1 Hz (Compensated). 0 freq512Hz 512 Hz (Compensated). 1 freq4KHz 4 KHz. 2 clkDiv8 RTC Input Clock / 8. 3 RD_EN Asynchronous Counter Read Enable. 14 1 WR_EN Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 15 1 inactive Not active 0 Pending Active 1 TRIM RTC Trim Register. 0x14 0x00000000 TRIM RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. 0 8 VRTC_TMR VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. 8 24 OSCCTRL RTC Oscillator Control Register. 0x18 0x00000000 FILTER_EN Enables analog deglitch filter. 0 1 IBIAS_SEL If IBIAS_EN is 1, selects 4x,2x mode. 1 1 HYST_EN Enables high current hysteresis buffer. 2 1 IBIAS_EN Enables higher 4x,2x current modes. 3 1 BYPASS RTC Crystal Bypass 4 1 SQW_32K RTC 32kHz Square Wave Output 5 1 SDHC SDHC/SDIO Controller 0x40037000 0 0x1000 registers SDHC 66 SDMA SDMA System Address / Argument 2. 0x00 32 ADDR SDMA System Address / Argument 2 of Auto CMD23. 0 32 BLK_SIZE Block Size. 0x04 16 TRANS Transfer Block Size. 0 12 HOST_BUFF Host SDMA Buffer Boundary. 12 3 BLK_CNT Block Count. 0x06 16 COUNT Blocks Count For Current Transfer. 0 16 ARG_1 Argument 1. 0x08 32 CMD Command Argument 1. 0 32 TRANS Transfer Mode. 0x0C 16 DMA_EN DMA Enable. 0 1 enable dma_transfer 1 non_dma_transfer 0 BLK_CNT_EN Block Count Enable. 1 1 count enable 1 disable 0 AUTO_CMD_EN Auto CMD Enable. 2 2 CMD disable 0 cmd12 1 cmd23 2 READ_WRITE Data Transfer Direction Select. 4 1 read read 1 write 0 MULTI Multi / Single Block Select. 5 1 multi enable 1 disable 0 CMD Command. 0x0E 16 RESP_TYPE Response Type Select. 0 2 CRC_CHK_EN Command CRC Check Enable. 3 1 IDX_CHK_EN Command Index Check Enable. 4 1 DATA_PRES_SEL Data Present Select. 5 1 TYPE Command Type. 6 2 IDX Command Index. 8 6 4 4 RESP[%s] Response 0 Register 0-15. 0x010 32 CMD_RESP Command Response. 0 32 BUFFER Buffer Data Port. 0x20 32 DATA Buffer Data. 0 32 PRESENT Present State. 0x024 32 read-only CMD Command Inhibit (CMD). 0 1 read-only DAT Command Inhibit (DAT). 1 1 read-only DAT_LINE_ACTIVE DAT Line Active. 2 1 read-only RETUNING Re-Tuning Request. 3 1 read-only WRITE_TRANSFER Write Transfer Active. 8 1 read-only READ_TRANSFER Read Transfer Active. 9 1 read-only BUFFER_WRITE Buffer Write Enable. 10 1 read-only BUFFER_READ Buffer Read Enable. 11 1 read-only CARD_INSERTED Card Inserted. 16 1 read-only CARD_STATE Card State Stable. 17 1 read-only CARD_DETECT Card Detect Pin Level. 18 1 read-only WP Write Protect Switch Pin Level. 19 1 read-only DAT_SIGNAL_LEVEL DAT[3:0] Line Signal Level. 20 4 CMD_SIGNAL_LEVEL CMD Line Signal Level. 24 1 HOST_CN_1 Host Control 1. 0x028 8 LED_CN LED Control. 0 1 DATA_TRANSFER_WIDTH Data Transfer Width. 1 1 HS_EN High Speed Enable. 2 1 DMA_SELECT DMA Select. 3 2 EXT_DATA_TRANSFER_WIDTH Extended Data Transfer Width. 5 1 CARD_DETECT_TEST Card Detect Test Level. 6 1 CARD_DETECT_SIGNAL Card Detect Signal Selection. 7 1 PWR Power Control. 0x029 8 BUS_POWER SD Bus Power. 0 1 BUS_VOLT_SEL SD Bus Voltage Select. 1 3 BLK_GAP Block Gap Control. 0x02A 8 STOP Stop At Block Gap Request. 0 1 CONT Continue Request. 1 1 READ_WAIT Read Wait Control. 2 1 INTR Interrupt At Block Gap. 3 1 WAKEUP Wakeup Control. 0x02B 8 CARD_INT Wakeup Event Enable On Card Interrupt. 0 1 CARD_INS Wakeup Event Enable On SD Card Insertion. 1 1 CARD_REM Wakeup Event Enable On SD Card Removal. 2 1 CLK_CN Clock Control. 0x02C 16 INTERNAL_CLK_EN Internal Clock Enable. 0 1 INTERNAL_CLK_STABLE Internal Clock Stable. 1 1 read-only SD_CLK_EN SD Clock Enable. 2 1 CLK_GEN_SEL Clock Generator Select. 5 1 read-only UPPER_SDCLK_FREQ_SEL Upper Bits of SDCLK Frequency Select. 6 2 SDCLK_FREQ_SEL SDCLK Frequency Select. 8 8 TO Timeout Control. 0x02E 8 DATA_COUNT_VALUE Data Timeout Counter Value. 0 3 SW_RESET Software Reset. 0x02F 8 RESET_ALL Software Reset For All. 0 1 RESET_CMD Software Reset For CMD Line. 1 1 RESET_DAT Software Reset For DAT Line. 2 1 INT_STAT Normal Interrupt Status. 0x030 16 CMD_COMP Command Complete. 0 1 TRANS_COMP Transfer Complete. 1 1 BLK_GAP_EVENT Block Gap Event. 2 1 DMA DMA Interrupt. 3 1 BUFF_WR_READY Buffer Write Ready. 4 1 BUFF_RD_READY Buffer Read Ready. 5 1 CARD_INSERTION Card Insertion. 6 1 CARD_REMOVAL Card Removal. 7 1 CARD_INTR Card Interrupt. 8 1 RETUNING Re-Tuning Event. 12 1 ERR_INTR Error Interrupt. 15 1 ER_INT_STAT Error Interrupt Status. 0x032 16 CMD_TO Command Timeout Error. 0 1 CMD_CRC Command CRC Error. 1 1 CMD_END_BIT Command End Bit Error. 2 1 CMD_IDX Command Index Error. 3 1 DATA_TO Data Timeout Error. 4 1 DATA_CRC Data CRC Error. 5 1 DATA_END_BIT Data End Bit Error. 6 1 CURRENT_LIMIT Current Limit Error. 7 1 AUTO_CMD_12 Auto CMD Error. 8 1 ADMA ADMA Error. 9 1 DMA DMA Error. 12 1 INT_EN Normal Interrupt Status Enable. 0x034 16 CMD_COMP Command Complete Status Enable. 0 1 TRANS_COMP Transfer Complete Status Enable. 1 1 BLK_GAP Block Gap Event Status Enable. 2 1 DMA DMA Interrupt Status Enable. 3 1 BUFFER_WR Buffer Write Ready Status Enable. 4 1 BUFFER_RD Buffer Read Ready Status Enable. 5 1 CARD_INSERT Card Insertion Status Enable. 6 1 CARD_REMOVAL Card Removal Status Enable. 7 1 CARD_INT Card Interrupt Status Enable. 8 1 RETUNING Re-Tuning Event Status Enable. 12 1 ER_INT_EN Error Interrupt Status Enable. 0x36 16 CMD_TO Command Timeout Error Status Enable. 0 1 CMD_CRC Command CRC Error Status Enable. 1 1 CMD_END_BIT Command End Bit Error Status Enable. 2 1 CMD_IDX Command Index Error Status Enable. 3 1 DATA_TO Data Timeout Error Status Enable. 4 1 DATA_CRC Data CRC Error Status Enable. 5 1 DATA_END_BIT Data End Bit Error Status Enable. 6 1 AUTO_CMD Auto CMD Error Status Enable. 8 1 ADMA ADMA Error Status Enable. 9 1 TUNING Tuning Error Status Enable. 10 1 VENDOR Vendor Specific Error Status Enable. 12 1 INT_SIGNAL Normal Interrupt Signal Enable. 0x038 16 CMD_COMP Command Complete Signal Enable. 0 1 TRANS_COMP Transfer Complete Signal Enable. 1 1 BLK_GAP Block Gap Event Signal Enable. 2 1 DMA DMA Interrupt Signal Enable. 3 1 BUFFER_WR Buffer Write Ready Signal Enable. 4 1 BUFFER_RD Buffer Read Ready Signal Enable. 5 1 CARD_INSERT Card Insertion Signal Enable. 6 1 CARD_REMOVAL Card Removal Signal Enable. 7 1 CARD_INT Card Interrupt Signal Enable. 8 1 RETUNING Re-Tuning Event Signal Enable. 12 1 ER_INT_SIGNAL Error Interrupt Signal Enable. 0x03A 16 CMD_TO Command Timeout Error Signal Enable. 0 1 CMD_CRC Command CRC Error Signal Enable. 1 1 CMD_END_BIT Command End Bit Error Signal Enable. 2 1 CMD_IDX Command Index Error Signal Enable. 3 1 DATA_TO Data Timeout Error Signal Enable. 4 1 DATA_CRC Data CRC Error Signal Enable. 5 1 DATA_END_BIT Data End Bit Error Signal Enable. 6 1 CURR_LIM Current Limit Error Signal Enable. 7 1 AUTO_CMD Auto CMD Error Signal Enable. 8 1 ADMA ADMA Error Signal Enable. 9 1 TUNING Tuning Error Signal Enable. 10 1 TAR_RESP Target Response Error Signal Enable. 12 1 AUTO_CMD_ER Auto CMD Error Status. 0x03C 16 NOT_EXCUTED Auto CMD12 Not Executed. 0 1 TO Auto CMD Timeout Error. 1 1 CRC Auto CMD CRC Error. 2 1 END_BIT Auto CMD End Bit Error. 3 1 INDEX Auto CMD Index Error. 4 1 NOT_ISSUED Command Not Issued By Auto CMD12 Error. 7 1 HOST_CN_2 Host Control 2. 0x03E 16 UHS UHS Mode Select. 0 2 SIGNAL_V1_8 1.8V Signaling Enable. 3 1 DRIVER_STRENGTH Driver Strength Select. 4 2 EXCUTE Execute Tuning. 6 1 SAMPLING_CLK Sampling Clock Select. 7 1 ASYNCH_INT Asynchronous Interrupt Enable. 14 1 PRESET_VAL_EN Preset Value Enable. 15 1 CFG_0 Capabilities 0-31. 0x040 32 read-only TO_CLK_FREQ Timeout Clock Frequency. 0 6 read-only TO_CLK_UNIT Timeout Clock Unit. 7 1 read-only CLK_FREQ Base Clock Frequency For SD Clock. 8 8 read-only MAX_BLK_LEN Max Block Length. 16 2 read-only BIT_8 8-bit Support for Embedded Device. 18 1 read-only ADMA2 ADMA2 Support. 19 1 read-only HS High Speed Support. 21 1 read-only SDMA SDMA Support. 22 1 read-only SUSPEND Suspend/Resume Support. 23 1 read-only V3_3 Voltage Support 3.3V. 24 1 read-only V3_0 Voltage Support 3.0V. 25 1 read-only V1_8 Voltage Support 1.8V. 26 1 read-only BIT_64_SYS_BUS 64-bit System Bus Support. 28 1 read-only ASYNC_INT Asynchronous Interrupt Support. 29 1 read-only SLOT_TYPE Slot Type. 30 2 read-only CFG_1 Capabilities 32-63. 0x044 32 read-only SDR50 SDR50 Support. 0 1 read-only SDR104 SDR104 Support. 1 0 read-only DDR50 DDR50 Support. 2 1 read-only DRIVER_A Driver Type A Support. 4 1 read-only DRIVER_C Driver Type C Support. 5 1 read-only DRIVER_D Driver Type D Support. 6 1 read-only TIMER_CNT_TUNING Timer Count for Re-Tuning. 8 4 read-only TUNING_SDR50 Use Tuning for SDR50. 13 1 read-only RETUNING Re-Tuning Modes. 14 2 read-only CLK_MULTI Clock Multiplier. 16 8 read-only MAX_CURR_CFG Maximum Current Capabilities. 0x048 32 read-only V3_3 Maximum Current for 3.3V. 0 8 read-only V3_0 Maximum Current for 3.0V. 8 8 read-only V1_8 Maximum Current for 1.8V. 16 8 read-only FORCE_CMD Force Event for Auto CMD Error Status. 0x050 16 write-only NOT_EXCU Force Event for Auto CMD12 Not Executed. 0 1 write-only TO Force Event for Auto CMD Timeout Error. 1 1 write-only CRC Force Event for Auto CMD CRC Error. 2 1 write-only END_BIT Force Event for Auto CMD End Bit Error. 3 1 write-only INDEX Force Event for Auto CMD Index Error. 4 1 write-only NOT_ISSUED Force Event for Command Not Issued By Auto CMD12 Error. 7 1 write-only FORCE_EVENT_INT_STAT Force Event for Error Interrupt Status. 0x052 16 CMD_TO Force Event for Command Timeout Error. 0 1 read-only CMD_CRC Force Event for Command CRC Error. 1 1 read-only CMD_END_BIT Force Event for Command End Bit Error. 2 1 read-only CMD_INDEX Force Event for Command Index Error. 3 1 read-only DATA_TO Force Event for Data Timeout Error. 4 1 read-only DATA_CRC Force Event for Data CRC Error. 5 1 read-only DATA_END_BIT Force Event for Data End Bit Error. 6 1 read-only CURR_LIMIT Force Event for Current Limit Error. 7 1 read-only AUTO_CMD Force Event for Auto CMD Error. 8 1 read-only ADMA Force Event for ADMA Error. 9 1 VENDOR Force Event for Vendor Specific Error Status. 12 3 write-only ADMA_ER ADMA Error Status. 0x054 8 STATE ADMA Error State. 0 2 LEN_MISMATCH ADMA Length Mismatch Error. 2 1 ADMA_ADDR_0 ADMA System Address 0-31. 0x058 32 ADDR ADMA System Address Part 1 (part 2 is ADMA_ADDR_1). 0 32 ADMA_ADDR_1 ADMA System Address 32-63. 0x05C 32 ADDR ADMA System Address Part 1 (part 2 is ADMA_ADDR_1). 0 32 PRESET_0 Preset Value for Initialization. 0x060 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only PRESET_1 Preset Value for Default Speed. 0x062 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only PRESET_2 Preset Value for High Speed. 0x064 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only PRESET_3 Preset Value for SDR12. 0x066 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only PRESET_4 Preset Value for SDR25. 0x068 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only PRESET_5 Preset Value for SDR50. 0x06A 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only PRESET_6 Preset Value for SDR104. 0x06C 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only PRESET_7 Preset Value for DDR50. 0x06E 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only SHARED_BUS SHARED_BUS. 0x0E0 32 SLOT_INT Slot Interrupt Status. 0x0FC 16 read-only INT_SIGNALS Interrupt Signal For Each Slot. 0 1 read-only HOST_CN_VER Host Controller Version. 0x0FE 16 SPEC_VER Specification Version Number. 0 8 VEND_VER Vendor Version Number. 8 8 SEMA The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. 0x4003E000 0x00 0x1000 registers 8 4 SEMAPHORES[%s] Read to test and set, returns prior value. Write 0 to clear semaphore. 0x00 32 sema 0 1 irq0 Semaphore IRQ0 register. 0x40 32 en 0 1 cm4_irq 16 1 mail0 Semaphore Mailbox 0 register. 0x44 32 data 0 32 irq1 Semaphore IRQ1 register. 0x48 32 en 0 1 rv32_irq 16 1 mail1 Semaphore Mailbox 1 register. 0x4C 32 data 0 32 status Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. 0x100 32 status0 0 1 status1 1 1 status2 2 1 status3 3 1 status4 4 1 status5 5 1 status6 6 1 status7 7 1 SIMO Single Inductor Multiple Output Switching Converter 0x40004400 0x00 0x400 registers VREGO_A Buck Voltage Regulator A Control Register 0x0004 read-write VSETA Regulator Output Voltage Setting 0 7 RANGEA Regulator Output Range Set 7 1 low Low output voltage range 0 high High output voltage range 1 VREGO_B Buck Voltage Regulator B Control Register 0x0008 read-write VSETB Regulator Output Voltage Setting 0 7 RANGEB Regulator Output Range Set 7 1 low Low output voltage range 0 high High output voltage range 1 VREGO_C Buck Voltage Regulator C Control Register 0x000C read-write VSETC Regulator Output Voltage Setting 0 7 RANGEC Regulator Output Range Set 7 1 low Low output voltage range 0 high High output voltage range 1 VREGO_D Buck Voltage Regulator D Control Register 0x0010 read-write VSETD Regulator Output Voltage Setting 0 7 RANGED Regulator Output Range Set 7 1 low Low output voltage range 0 high High output voltage range 1 IPKA High Side FET Peak Current VREGO_A/VREGO_B Register 0x0014 read-write IPKSETA Voltage Regulator Peak Current Setting 0 4 IPKSETB Voltage Regulator Peak Current Setting 4 4 IPKB High Side FET Peak Current VREGO_C/VREGO_D Register 0x0018 read-write IPKSETC Voltage Regulator Peak Current Setting 0 4 IPKSETD Voltage Regulator Peak Current Setting 4 4 MAXTON Maximum High Side FET Time On Register 0x001C read-write TONSET Sets the maximum on time for the high side FET, each increment represents 500ns 0 4 ILOAD_A Buck Cycle Count VREGO_A Register 0x0020 read-only ILOADA Number of buck cycles that occur within the cycle clock 0 8 ILOAD_B Buck Cycle Count VREGO_B Register 0x0024 read-only ILOADB Number of buck cycles that occur within the cycle clock 0 8 ILOAD_C Buck Cycle Count VREGO_C Register 0x0028 read-only ILOADC Number of buck cycles that occur within the cycle clock 0 8 ILOAD_D Buck Cycle Count VREGO_D Register 0x002C read-only ILOADD Number of buck cycles that occur within the cycle clock 0 8 BUCK_ALERT_THR_A Buck Cycle Count Alert VERGO_A Register 0x0030 read-write BUCKTHRA Threshold for ILOADA to generate the BUCK_ALERT 0 8 BUCK_ALERT_THR_B Buck Cycle Count Alert VERGO_B Register 0x0034 read-write BUCKTHRB Threshold for ILOADB to generate the BUCK_ALERT 0 8 BUCK_ALERT_THR_C Buck Cycle Count Alert VERGO_C Register 0x0038 read-write BUCKTHRC Threshold for ILOADC to generate the BUCK_ALERT 0 8 BUCK_ALERT_THR_D Buck Cycle Count Alert VERGO_D Register 0x003C read-write BUCKTHRD Threshold for ILOADD to generate the BUCK_ALERT 0 8 BUCK_OUT_READY Buck Regulator Output Ready Register 0x0040 read-only BUCKOUTRDYA When set, indicates that the output voltage has reached its regulated value 0 1 notrdy Output voltage not in range 0 rdy Output voltage in range 1 BUCKOUTRDYB When set, indicates that the output voltage has reached its regulated value 1 1 BUCKOUTRDYC When set, indicates that the output voltage has reached its regulated value 2 1 BUCKOUTRDYD When set, indicates that the output voltage has reached its regulated value 3 1 ZERO_CROSS_CAL_A Zero Cross Calibration VERGO_A Register 0x0044 read-only ZXCALA Zero Cross Calibrartion Value VREGO_A 0 4 ZERO_CROSS_CAL_B Zero Cross Calibration VERGO_B Register 0x0048 read-only ZXCALB Zero Cross Calibrartion Value VREGO_B 0 4 ZERO_CROSS_CAL_C Zero Cross Calibration VERGO_C Register 0x004C read-only ZXCALC Zero Cross Calibrartion Value VREGO_C 0 4 ZERO_CROSS_CAL_D Zero Cross Calibration VERGO_D Register 0x0050 read-only ZXCALD Zero Cross Calibrartion Value VREGO_D 0 4 SIR System Initialization Registers. 0x40000400 read-only 0x00 0x400 registers SISTAT System Initialization Status Register. 0x00 read-only MAGIC Magic Word Validation. This bit is set by the system initialization block following power-up. 0 1 read-only read magicNotSet Magic word was not set (OTP has not been initialized properly). 0 magicSet Magic word was set (OTP contains valid settings). 1 CRCERR CRC Error Status. This bit is set by the system initialization block following power-up. 1 1 read-only read noError No CRC errors occurred during the read of the OTP memory block. 0 error A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. 1 SIADDR Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x04 read-only ERRADDR 0 32 FSTAT funcstat register. 0x100 read-only FPU FPU Function. 0 1 no 0 yes 1 USB USB Function. 1 1 no 0 yes 1 ADC ADC Function. 2 1 no 0 yes 1 SDIO SDIO Function. 6 1 no 0 yes 1 SMPHR SMPHR function. 7 1 no 0 yes 1 SFSTAT Security function status register. 0x104 read-only TRNG TRNG Function. 2 1 no 0 yes 1 AES AES Block. 3 1 no 0 yes 1 SPI0 SPI peripheral. 0x400BE000 0x00 0x1000 registers SPI0 56 FIFO32 Register for reading and writing the FIFO. 0x00 32 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 32 2 2 FIFO16[%s] Register for reading and writing the FIFO. 0x00 16 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 16 4 1 FIFO8[%s] Register for reading and writing the FIFO. 0x00 8 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 8 CTRL0 Register for controlling SPI peripheral. 0x04 read-write EN SPI Enable. 0 1 dis SPI is disabled. 0 en SPI is enabled. 1 MST_MODE Master Mode Enable. 1 1 dis SPI is Slave mode. 0 en SPI is Master mode. 1 SS_IO Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 4 1 output Slave select 0 is output. 0 input Slave Select 0 is input, only valid if MMEN=1. 1 START Start Transmit. 5 1 start Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. 1 SS_CTRL Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. 8 1 DEASSERT SPI De-asserts Slave Select at the end of a transaction. 0 ASSERT SPI leaves Slave Select asserted at the end of a transaction. 1 SS_ACTIVE Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 16 4 SS0 SS0 is selected. 0x1 SS1 SS1 is selected. 0x2 SS2 SS2 is selected. 0x4 SS3 SS3 is selected. 0x8 CTRL1 Register for controlling SPI peripheral. 0x08 read-write TX_NUM_CHAR Nubmer of Characters to transmit. 0 16 RX_NUM_CHAR Nubmer of Characters to receive. 16 16 CTRL2 Register for controlling SPI peripheral. 0x0C read-write CLKPHA Clock Phase. 0 1 Rising_Edge Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 0 Falling_Edge Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 1 CLKPOL Clock Polarity. 1 1 Normal Normal Clock. Use when in SPI Mode 0 and Mode 1 0 Inverted Inverted Clock. Use when in SPI Mode 2 and Mode 3 1 SCLK_FB_INV SCLK_FB_INV. 4 1 NUMBITS Number of Bits per character. 8 4 0 16 bits per character. 0 DATA_WIDTH SPI Data width. 12 2 Mono 1 data pin. 0 Dual 2 data pins. 1 Quad 4 data pins. 2 THREE_WIRE Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 15 1 dis Use four wire mode (Mono only). 0 en Use three wire mode. 1 SS_POL Slave Select Polarity, each Slave Select can have unique polarity. 16 8 SS0_high SS0 active high. 0x1 SS1_high SS1 active high. 0x2 SS2_high SS2 active high. 0x4 SS3_high SS3 active high. 0x8 SSTIME Register for controlling SPI peripheral/Slave Select Timing. 0x10 read-write PRE Slave Select Pre delay 1. 0 8 256 256 system clocks between SS active and first serial clock edge. 0 POST Slave Select Post delay 2. 8 8 256 256 system clocks between last serial clock edge and SS inactive. 0 INACT Slave Select Inactive delay. 16 8 256 256 system clocks between transactions. 0 CLKCTRL Register for controlling SPI clock rate. 0x14 read-write LO Low duty cycle control. In timer mode, reload[7:0]. 0 8 Dis Duty cycle control of serial clock generation is disabled. 0 HI High duty cycle control. In timer mode, reload[15:8]. 8 8 Dis Duty cycle control of serial clock generation is disabled. 0 CLKDIV System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. 16 4 AFP_FCD Automatic frequency prescalar. 24 3 DMA Register for controlling DMA. 0x1C read-write TX_THD_VAL Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. 0 5 TX_FIFO_EN Transmit FIFO enabled for SPI transactions. 6 1 dis Transmit FIFO is not enabled. 0 en Transmit FIFO is enabled. 1 TX_FLUSH Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 7 1 CLEAR Clear the Transmit FIFO, clears any pending TX FIFO status. 1 TX_LVL Count of entries in TX FIFO. 8 6 read-only DMA_TX_EN TX DMA Enable. 15 1 DIS TX DMA requests are disabled, andy pending DMA requests are cleared. 0 en TX DMA requests are enabled. 1 RX_THD_VAL Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. 16 5 RX_FIFO_EN Receive FIFO enabled for SPI transactions. 22 1 DIS Receive FIFO is not enabled. 0 en Receive FIFO is enabled. 1 RX_FLUSH Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 23 1 CLEAR Clear the Receive FIFO, clears any pending RX FIFO status. 1 RX_LVL Count of entries in RX FIFO. 24 6 read-only DMA_RX_EN RX DMA Enable. 31 1 dis RX DMA requests are disabled, any pending DMA requests are cleared. 0 en RX DMA requests are enabled. 1 INTFL Register for reading and clearing interrupt flags. All bits are write 1 to clear. 0x20 read-write TX_THD TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL RX FIFO FULL. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSA Slave Select Asserted. 4 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSD Slave Select Deasserted. 5 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 FAULT Multi-Master Mode Fault. 8 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 ABORT Slave Abort Detected. 9 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 MST_DONE Master Done, set when SPI Master has completed any transactions. 11 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_OV Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 12 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_UN Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. 13 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_OV Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. 14 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_UN Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. 15 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 INTEN Register for enabling interrupts. 0x24 read-write TX_THD TX FIFO Threshold interrupt enable. 0 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_EM TX FIFO Empty interrupt enable. 1 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_THD RX FIFO Threshold Crossed interrupt enable. 2 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_FULL RX FIFO FULL interrupt enable. 3 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSA Slave Select Asserted interrupt enable. 4 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSD Slave Select Deasserted interrupt enable. 5 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 FAULT Multi-Master Mode Fault interrupt enable. 8 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 ABORT Slave Abort Detected interrupt enable. 9 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 MST_DONE Master Done interrupt enable. 11 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_OV Transmit FIFO Overrun interrupt enable. 12 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_UN Transmit FIFO Underrun interrupt enable. 13 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_OV Receive FIFO Overrun interrupt enable. 14 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_UN Receive FIFO Underrun interrupt enable. 15 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 WKFL Register for wake up flags. All bits in this register are write 1 to clear. 0x28 read-write TX_THD Wake on TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM Wake on TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD Wake on RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL Wake on RX FIFO Full. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 WKEN Register for wake up enable. 0x2C read-write TX_THD Wake on TX FIFO Threshold Crossed Enable. 0 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 TX_EM Wake on TX FIFO Empty Enable. 1 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_THD Wake on RX FIFO Threshold Crossed Enable. 2 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_FULL Wake on RX FIFO Full Enable. 3 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 STAT SPI Status register. 0x30 read-only BUSY SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 0 1 not SPI not active. 0 active SPI active. 1 SPI1 SPI peripheral. 1 0x40046000 SPI1 SPI1 IRQ 16 TMR Low-Power Configurable Timer 0x40010000 0x00 0x1000 registers TMR 5 CNT Timer Counter Register. 0x00 read-write COUNT The current count value for the timer. This field increments as the timer counts. 0 32 CMP Timer Compare Register. 0x04 read-write COMPARE The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. 0 32 PWM Timer PWM Register. 0x08 read-write PWM Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. 0 32 INTFL Timer Interrupt Status Register. 0x0C read-write IRQ_A Interrupt Flag for Timer A. 0 1 WRDONE_A Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. 8 1 WR_DIS_A Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. 9 1 IRQ_B Interrupt Flag for Timer B. 16 1 WRDONE_B Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. 24 1 WR_DIS_B Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. 25 1 CTRL0 Timer Control Register. 0x10 read-write MODE_A Mode Select for Timer A 0 4 ONE_SHOT One-Shot Mode 0 CONTINUOUS Continuous Mode 1 COUNTER Counter Mode 2 PWM PWM Mode 3 CAPTURE Capture Mode 4 COMPARE Compare Mode 5 GATED Gated Mode 6 CAPCOMP Capture/Compare Mode 7 DUAL_EDGE Dual Edge Capture Mode 8 IGATED Inactive Gated Mode 14 CLKDIV_A Clock Divider Select for Timer A 4 4 DIV_BY_1 Prescaler Divide-By-1 0 DIV_BY_2 Prescaler Divide-By-2 1 DIV_BY_4 Prescaler Divide-By-4 2 DIV_BY_8 Prescaler Divide-By-8 3 DIV_BY_16 Prescaler Divide-By-16 4 DIV_BY_32 Prescaler Divide-By-32 5 DIV_BY_64 Prescaler Divide-By-64 6 DIV_BY_128 Prescaler Divide-By-128 7 DIV_BY_256 Prescaler Divide-By-256 8 DIV_BY_512 Prescaler Divide-By-512 9 DIV_BY_1024 Prescaler Divide-By-1024 10 DIV_BY_2048 Prescaler Divide-By-2048 11 DIV_BY_4096 TBD 12 POL_A Timer Polarity for Timer A 8 1 PWMSYNC_A PWM Synchronization Mode for Timer A 9 1 NOLHPOL_A PWM Phase A (Non-Overlapping High) Polarity for Timer A 10 1 NOLLPOL_A PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A 11 1 PWMCKBD_A PWM Phase A-Prime Output Disable for Timer A 12 1 RST_A Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. 13 1 CLKEN_A Write 1 to Enable CLK_TMR for Timer A 14 1 EN_A Enable for Timer A 15 1 MODE_B Mode Select for Timer B 16 4 ONE_SHOT One-Shot Mode 0 CONTINUOUS Continuous Mode 1 COUNTER Counter Mode 2 PWM PWM Mode 3 CAPTURE Capture Mode 4 COMPARE Compare Mode 5 GATED Gated Mode 6 CAPCOMP Capture/Compare Mode 7 DUAL_EDGE Dual Edge Capture Mode 8 IGATED Inactive Gated Mode 14 CLKDIV_B Clock Divider Select for Timer B 20 4 DIV_BY_1 Prescaler Divide-By-1 0 DIV_BY_2 Prescaler Divide-By-2 1 DIV_BY_4 Prescaler Divide-By-4 2 DIV_BY_8 Prescaler Divide-By-8 3 DIV_BY_16 Prescaler Divide-By-16 4 DIV_BY_32 Prescaler Divide-By-32 5 DIV_BY_64 Prescaler Divide-By-64 6 DIV_BY_128 Prescaler Divide-By-128 7 DIV_BY_256 Prescaler Divide-By-256 8 DIV_BY_512 Prescaler Divide-By-512 9 DIV_BY_1024 Prescaler Divide-By-1024 10 DIV_BY_2048 Prescaler Divide-By-2048 11 DIV_BY_4096 TBD 12 POL_B Timer Polarity for Timer B 24 1 PWMSYNC_B PWM Synchronization Mode for Timer B 25 1 NOLHPOL_B PWM Phase A (Non-Overlapping High) Polarity for Timer B 26 1 NOLLPOL_B PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B 27 1 PWMCKBD_B PWM Phase A-Prime Output Disable for Timer B 28 1 RST_B Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. 29 1 CLKEN_B Write 1 to Enable CLK_TMR for Timer B 30 1 EN_B Enable for Timer B 31 1 NOLCMP Timer Non-Overlapping Compare Register. 0x14 read-write LO_A Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. 0 8 HI_A Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. 8 8 LO_B Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. 16 8 HI_B Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. 24 8 CTRL1 Timer Configuration Register. 0x18 read-write CLKSEL_A Timer Clock Select for Timer A 0 2 CLKEN_A Timer A Enable Status 2 1 CLKRDY_A CLK_TMR Ready Flag for Timer A 3 1 EVENT_SEL_A Event Select for Timer A 4 3 NEGTRIG_A Negative Edge Trigger for Event for Timer A 7 1 IE_A Interrupt Enable for Timer A 8 1 CAPEVENT_SEL_A Capture Event Select for Timer A 9 2 SW_CAPEVENT_A Software Capture Event for Timer A 11 1 WE_A Wake-Up Enable for Timer A 12 1 OUTEN_A OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A 13 1 OUTBEN_A PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A 14 1 CLKSEL_B Timer Clock Select for Timer B 16 2 CLKEN_B Timer B Enable Status 18 1 CLKRDY_B CLK_TMR Ready Flag for Timer B 19 1 EVENT_SEL_B Event Select for Timer B 20 3 NEGTRIG_B Negative Edge Trigger for Event for Timer B 23 1 IE_B Interrupt Enable for Timer B 24 1 CAPEVENT_SEL_B Capture Event Select for Timer B 25 2 SW_CAPEVENT_B Software Capture Event for Timer B 27 1 WE_B Wake-Up Enable for Timer B 28 1 CASCADE Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. 31 1 WKFL Timer Wakeup Status Register. 0x1C read-write A Wake-Up Flag for Timer A 0 1 B Wake-Up Flag for Timer B 16 1 TMR1 Low-Power Configurable Timer 1 0x40011000 TMR1 TMR1 IRQ 6 TMR2 Low-Power Configurable Timer 2 0x40012000 TMR2 TMR2 IRQ 7 TMR3 Low-Power Configurable Timer 3 0x40013000 TMR3 TMR3 IRQ 8 TMR4 Low-Power Configurable Timer 4 0x40080C00 TMR4 TMR4 IRQ 9 TMR5 Low-Power Configurable Timer 5 0x40081000 TMR5 TMR5 IRQ 10 TRNG Random Number Generator. 0x4004D000 0x00 0x1000 registers TRNG TRNG interrupt. 4 CTRL TRNG Control Register. 0x00 0x00000003 RND_IE To enable IRQ generation when a new 32-bit Random number is ready. 1 1 disable Disable 0 enable Enable 1 KEYGEN AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. 3 1 KEYWIPE To wipe the Battery Backed key. 15 1 STATUS Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x04 RDY 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. 0 1 Busy TRNG Busy 0 Ready 32 bit random data is ready 1 DATA Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x08 read-only DATA Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. 0 32 TRIMSIR Trim System Initilazation Registers 0x40005400 0x00 0x400 registers RTC RTC Trim System Initialization Register. 0x08 X1TRIM RTC X1 Trim. 16 5 X2TRIM RTC X2 Trim. 21 5 LOCK Lock. 31 1 SIMO SIMO Trim System Initialization Register. 0x34 read-only CLKDIV SIMO Clock Divide. 0 3 DIV1 0 DIV16 1 DIV32 3 DIV64 5 DIV128 7 IPOLO IPO Low Trim System Initialization Register. 0x3C read-only IPO_LIMITLO IPO Low Limit Trim. 0 8 CTRL Control Trim System Initialization Register. 0x40 VDDA_LIMITLO VDDA Low Trim Limit. 0 7 VDDA_LIMITHI VDDA High Trim Limit. 8 7 IPO_LIMITHI IPO High Trim Limit. 15 9 INRO_SEL INRO Clock Select. 24 2 8KHZ 0 16KHZ 1 30KHZ 2 INRO_TRIM INRO Clock Trim. 29 3 INRO RTC Trim System Initialization Register. 0x44 TRIM16K INRO 16KHz Trim. 0 3 TRIM30K INRO 30KHz Trim. 3 3 LPCLKSEL INRO Low Power Mode Clock Select. 6 2 8KHZ 0 16KHZ 1 30KHZ 2 UART UART Low Power Registers 0x40042000 0x00 0x1000 registers CTRL Control register 0x0000 RX_THD_VAL This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) 0 4 PAR_EN Parity Enable 4 1 PAR_EO when PAREN=1 selects odd or even parity odd is 1 even is 0 5 1 PAR_MD Selects parity based on 1s or 0s count (when PAREN=1) 6 1 CTS_DIS CTS Sampling Disable 7 1 TX_FLUSH Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. 8 1 RX_FLUSH Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. 9 1 CHAR_SIZE Selects UART character size 10 2 5bits 5 bits 0 6bits 6 bits 1 7bits 7 bits 2 8bits 8 bits 3 STOPBITS Selects the number of stop bits that will be generated 12 1 HFC_EN Enables/disables hardware flow control 13 1 RTSDC Hardware Flow Control RTS Mode 14 1 BCLKEN Baud clock enable 15 1 BCLKSRC To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. 16 2 Peripheral_Clock apb clock 0 External_Clock Clock 1 1 CLK2 Clock 2 2 CLK3 Clock 3 3 DPFE_EN Data/Parity bit frame error detection enable 18 1 BCLKRDY Baud clock Ready read only bit 19 1 UCAGM UART Clock Auto Gating mode 20 1 FDM Fractional Division Mode 21 1 DESM RX Dual Edge Sampling Mode 22 1 STATUS Status register 0x0004 read-only TX_BUSY Read-only flag indicating the UART transmit status 0 1 RX_BUSY Read-only flag indicating the UART receiver status 1 1 RX_EM Read-only flag indicating the RX FIFO state 4 1 RX_FULL Read-only flag indicating the RX FIFO state 5 1 TX_EM Read-only flag indicating the TX FIFO state 6 1 TX_FULL Read-only flag indicating the TX FIFO state 7 1 RX_LVL Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) 8 4 TX_LVL Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) 12 4 INT_EN Interrupt Enable control register 0x0008 RX_FERR Enable Interrupt For RX Frame Error 0 1 RX_PAR Enable Interrupt For RX Parity Error 1 1 CTS_EV Enable Interrupt For CTS signal change Error 2 1 RX_OV Enable Interrupt For RX FIFO Overrun Error 3 1 RX_THD Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD 4 1 TX_OB Enable Interrupt For TX FIFO has one byte remaining 5 1 TX_HE Enable Interrupt For TX FIFO has half empty 6 1 INT_FL Interrupt status flags Control register 0x000C RX_FERR Flag for RX Frame Error Interrupt. 0 1 RX_PAR Flag for RX Parity Error interrupt 1 1 CTS_EV Flag for CTS signal change interrupt (hardware flow control disabled) 2 1 RX_OV Flag for RX FIFO Overrun interrupt 3 1 RX_THD Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field 4 1 TX_OB Flag for interrupt when TX FIFO has one byte remaining 5 1 TX_HE Flag for interrupt when TX FIFO is half empty 6 1 CLKDIV Clock Divider register 0x0010 CLKDIV Baud rate divisor value 0 20 OSR Over Sampling Rate register 0x0014 OSR OSR 0 3 TXPEEK TX FIFO Output Peek register 0x0018 DATA Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field. 0 8 PNR Pin register 0x001C CTS Current sampled value of CTS IO 0 1 read-only RTS This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level. 1 1 FIFO FIFO Read/Write register 0x0020 DATA Load/unload location for TX and RX FIFO buffers. 0 8 RX_PAR Parity error flag for next byte to be read from FIFO. 8 1 DMA DMA Configuration register 0x0030 TX_THD_VAL TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory. 0 4 TX_EN TX DMA channel enable 4 1 RX_THD_VAL Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory. 5 4 RX_EN RX DMA channel enable 9 1 WKEN Wake up enable Control register 0x0034 RX_NE Wake-Up Enable for RX FIFO Not Empty 0 1 RX_FULL Wake-Up Enable for RX FIFO Full 1 1 RX_THD Wake-Up Enable for RX FIFO Threshold Met 2 1 WKFL Wake up Flags register 0x0038 RX_NE Wake-Up Flag for RX FIFO Not Empty 0 1 RX_FULL Wake-Up Flag for RX FIFO Full 1 1 RX_THD Wake-Up Flag for RX FIFO Threshold Met 2 1 UART1 UART Low Power Registers 1 0x40043000 UART2 UART Low Power Registers 2 0x40044000 UART3 UART Low Power Registers 3 0x40081400 USBHS USB 2.0 High-speed Controller. 0x400B1000 0 0x1000 registers USB 2 FADDR Function address register. 0x00 8 0x00 ADDR Function address for this controller. 0 7 read-write UPDATE Set when ADDR is written, cleared when new address takes effect. 7 1 read-only POWER Power management register. 0x01 8 EN_SUSPENDM Enable SUSPENDM signal. 0 1 read-write SUSPEND Suspend mode detected. 1 1 read-only RESUME Generate resume signaling. 2 1 read-write RESET Bus reset detected. 3 1 read-only HS_MODE High-speed mode detected. 4 1 read-only HS_ENABLE High-speed mode enable. 5 1 read-write SOFTCONN Softconn. 6 1 read-write ISO_UPDATE Wait for SOF during Isochronous xfers. 7 1 read-write INTRIN Interrupt register for EP0 and IN EP1-15. 0x02 16 EP15_IN_INT Endpoint 15 interrupt. 15 1 read-only EP14_IN_INT Endpoint 14 interrupt. 14 1 read-only EP13_IN_INT Endpoint 13 interrupt. 13 1 read-only EP12_IN_INT Endpoint 12 interrupt. 12 1 read-only EP11_IN_INT Endpoint 11 interrupt. 11 1 read-only EP10_IN_INT Endpoint 10 interrupt. 10 1 read-only EP9_IN_INT Endpoint 9 interrupt. 9 1 read-only EP8_IN_INT Endpoint 8 interrupt. 8 1 read-only EP7_IN_INT Endpoint 7 interrupt. 7 1 read-only EP6_IN_INT Endpoint 6 interrupt. 6 1 read-only EP5_IN_INT Endpoint 5 interrupt. 5 1 read-only EP4_IN_INT Endpoint 4 interrupt. 4 1 read-only EP3_IN_INT Endpoint 3 interrupt. 3 1 read-only EP2_IN_INT Endpoint 2 interrupt. 2 1 read-only EP1_IN_INT Endpoint 1 interrupt. 1 1 read-only EP0_IN_INT Endpoint 0 interrupt. 0 1 read-only INTROUT Interrupt register for OUT EP 1-15. 0x04 16 EP15_OUT_INT Endpoint 15 interrupt. 15 1 read-only EP14_OUT_INT Endpoint 14 interrupt. 14 1 read-only EP13_OUT_INT Endpoint 13 interrupt. 13 1 read-only EP12_OUT_INT Endpoint 12 interrupt. 12 1 read-only EP11_OUT_INT Endpoint 11 interrupt. 11 1 read-only EP10_OUT_INT Endpoint 10 interrupt. 10 1 read-only EP9_OUT_INT Endpoint 9 interrupt. 9 1 read-only EP8_OUT_INT Endpoint 8 interrupt. 8 1 read-only EP7_OUT_INT Endpoint 7 interrupt. 7 1 read-only EP6_OUT_INT Endpoint 6 interrupt. 6 1 read-only EP5_OUT_INT Endpoint 5 interrupt. 5 1 read-only EP4_OUT_INT Endpoint 4 interrupt. 4 1 read-only EP3_OUT_INT Endpoint 3 interrupt. 3 1 read-only EP2_OUT_INT Endpoint 2 interrupt. 2 1 read-only EP1_OUT_INT Endpoint 1 interrupt. 1 1 read-only INTRINEN Interrupt enable for EP 0 and IN EP 1-15. 0x06 16 EP15_IN_INT_EN Endpoint 15 interrupt enable. 15 1 read-write EP14_IN_INT_EN Endpoint 14 interrupt enable. 14 1 read-write EP13_IN_INT_EN Endpoint 13 interrupt enable. 13 1 read-write EP12_IN_INT_EN Endpoint 12 interrupt enable. 12 1 read-write EP11_IN_INT_EN Endpoint 11 interrupt enable. 11 1 read-write EP10_IN_INT_EN Endpoint 10 interrupt enable. 10 1 read-write EP9_IN_INT_EN Endpoint 9 interrupt enable. 9 1 read-write EP8_IN_INT_EN Endpoint 8 interrupt enable. 8 1 read-write EP7_IN_INT_EN Endpoint 7 interrupt enable. 7 1 read-write EP6_IN_INT_EN Endpoint 6 interrupt enable. 6 1 read-write EP5_IN_INT_EN Endpoint 5 interrupt enable. 5 1 read-write EP4_IN_INT_EN Endpoint 4 interrupt enable. 4 1 read-write EP3_IN_INT_EN Endpoint 3 interrupt enable. 3 1 read-write EP2_IN_INT_EN Endpoint 2 interrupt enable. 2 1 read-write EP1_IN_INT_EN Endpoint 1 interrupt enable. 1 1 read-write EP0_INT_EN Endpoint 0 interrupt enable. 0 1 read-write INTROUTEN Interrupt enable for OUT EP 1-15. 0x08 16 EP15_OUT_INT_EN Endpoint 15 interrupt. 15 1 read-write EP14_OUT_INT_EN Endpoint 14 interrupt. 14 1 read-write EP13_OUT_INT_EN Endpoint 13 interrupt. 13 1 read-write EP12_OUT_INT_EN Endpoint 12 interrupt. 12 1 read-write EP11_OUT_INT_EN Endpoint 11 interrupt. 11 1 read-write EP10_OUT_INT_EN Endpoint 10 interrupt. 10 1 read-write EP9_OUT_INT_EN Endpoint 9 interrupt. 9 1 read-write EP8_OUT_INT_EN Endpoint 8 interrupt. 8 1 read-write EP7_OUT_INT_EN Endpoint 7 interrupt. 7 1 read-write EP6_OUT_INT_EN Endpoint 6 interrupt. 6 1 read-write EP5_OUT_INT_EN Endpoint 5 interrupt. 5 1 read-write EP4_OUT_INT_EN Endpoint 4 interrupt. 4 1 read-write EP3_OUT_INT_EN Endpoint 3 interrupt. 3 1 read-write EP2_OUT_INT_EN Endpoint 2 interrupt. 2 1 read-write EP1_OUT_INT_EN Endpoint 1 interrupt. 1 1 read-write INTRUSB Interrupt register for common USB interrupts. 0x0A 8 SOF_INT Start of Frame. 3 1 read-only RESET_INT Bus reset detected. 2 1 read-only RESUME_INT Resume detected. 1 1 read-only SUSPEND_INT Suspend detected. 0 1 read-only INTRUSBEN Interrupt enable for common USB interrupts. 0x0B 8 SOF_INT_EN Start of Frame. 3 1 read-write RESET_INT_EN Bus reset detected. 2 1 read-write RESUME_INT_EN Resume detected. 1 1 read-write SUSPEND_INT_EN Suspend detected. 0 1 read-write FRAME Frame number. 0x0C 16 FRAMENUM Read the last received frame number, that is the 11-bit frame number received in the SOF packet. 0 11 read-only INDEX Index for banked registers. 0x0E 8 INDEX Index Register Access Selector. 0 4 read-write TESTMODE USB 2.0 test mode enable register. 0x0F 8 FORCE_FS Force USB to Full-speed after reset. 5 1 read-write FORCE_HS Force USB to High-speed after reset. 4 1 read-write TEST_PKT Transmit fixed test packet. 3 1 read-write TEST_K Force USB to continuous K state. 2 1 read-write TEST_J Force USB to continuous J state. 1 1 read-write TEST_SE0_NAK Respond to any valid IN token with NAK. 0 1 read-write INMAXP Maximum packet size for INx endpoint (x == INDEX). 0x10 16 MAXPACKETSIZE Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9 0 11 NUMPACKMINUS1 Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases. 11 5 CSR0 Control status register for EP 0 (when INDEX == 0). 0x12 8 SERV_SETUP_END Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set 7 1 read-write SERV_OUTPKTRDY Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set. 6 1 read-write SEND_STALL Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set. 5 1 read-write SETUP_END Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear. 4 1 read-only DATA_END Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet. 3 1 read-write SENT_STALL Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear. 2 1 read-write INPKTRDY EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared. 1 1 read-write OUTPKTRDY EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO. 0 1 read-only INCSRL Control status lower register for INx endpoint (x == INDEX). CSR0 0x12 8 INCOMPTX Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear. 7 1 read-write CLRDATATOG Write 1 to clear IN endpoint data-toggle to 0. 6 1 read-write SENTSTALL Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear. 5 1 read-write SENDSTALL Send STALL Handshake. 4 1 read-only terminate Terminate STALL handhsake 0 respond Respond to an IN token with a STALL handshake 1 FLUSHFIFO Flush Next Packet from IN FIFO. Write 1 to clear 3 1 read-write UNDERRUN Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear 2 1 read-write FIFONOTEMPTY Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear. 1 1 read-write INPKTRDY IN Packet Ready. Write a 1 to clear 0 1 read-only INCSRU Control status upper register for INx endpoint (x == INDEX). 0x13 8 AUTOSET Auto Set inpktrdy. 7 1 read-write set USBHS_INCSRL_inpktrdy must be set by firmware. 0 auto USBHS_INCSRL_inpktrdy is automatically set. 1 ISO Isochronous Transfer Enable 6 1 read-write interrupt Enable IN Bulk and IN interrupt transfers. 0 isochronous Enable IN Isochronous transfers. 1 MODE Endpoint Direction Mode. 5 1 read-write out Endpoint direction is OUT. 0 in Endpoint direction is IN. 1 FRCDATATOG Force In Data - Toggle 3 1 read-write received Toggle data-toglge only when an ACK is received. 0 dontcare Toggle data-toggle regardless of ACK. 1 DPKTBUFDIS Double Packet Buffering Disable 1 1 read-write en Enable Double packet buffering. 0 dis Disable Double Packet Buffering. 1 OUTMAXP Maximum packet size for OUTx endpoint (x == INDEX). 0x14 16 NUMPACKMINUS1 Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize. 11 5 MAXPACKETSIZE Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9. 0 11 OUTCSRL Control status lower register for OUTx endpoint (x == INDEX). 0x16 8 CLRDATATOG 7 1 read-write SENTSTALL 6 1 read-write SENDSTALL 5 1 read-write FLUSHFIFO 4 1 read-write DATAERROR 3 1 read-only OVERRUN 2 1 read-write FIFOFULL 1 1 read-only OUTPKTRDY 0 1 read-write OUTCSRU Control status upper register for OUTx endpoint (x == INDEX). 0x17 8 AUTOCLEAR 7 1 read-write ISO 6 1 read-write DISNYET 4 1 read-write DPKTBUFDIS 1 1 read-write INCOMPRX 0 1 read-only COUNT0 Number of received bytes in EP 0 FIFO (INDEX == 0). 0x18 16 COUNT0 Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1 0 7 read-only OUTCOUNT Number of received bytes in OUT EPx FIFO (x == INDEX). COUNT0 0x18 16 OUTCOUNT Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO. 0 13 read-only FIFO0 Read for OUT data FIFO, write for IN data FIFO. 0x20 USBHS_FIFO0 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO1 Read for OUT data FIFO, write for IN data FIFO. 0x24 USBHS_FIFO1 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO2 Read for OUT data FIFO, write for IN data FIFO. 0x28 USBHS_FIFO2 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO3 Read for OUT data FIFO, write for IN data FIFO. 0x2c USBHS_FIFO3 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO4 Read for OUT data FIFO, write for IN data FIFO. 0x30 USBHS_FIFO4 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO5 Read for OUT data FIFO, write for IN data FIFO. 0x34 USBHS_FIFO5 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO6 Read for OUT data FIFO, write for IN data FIFO. 0x38 USBHS_FIFO6 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO7 Read for OUT data FIFO, write for IN data FIFO. 0x3c USBHS_FIFO7 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO8 Read for OUT data FIFO, write for IN data FIFO. 0x40 USBHS_FIFO8 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO9 Read for OUT data FIFO, write for IN data FIFO. 0x44 USBHS_FIFO9 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO10 Read for OUT data FIFO, write for IN data FIFO. 0x48 USBHS_FIFO10 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO11 Read for OUT data FIFO, write for IN data FIFO. 0x4c USBHS_FIFO11 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO12 Read for OUT data FIFO, write for IN data FIFO. 0x50 USBHS_FIFO12 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO13 Read for OUT data FIFO, write for IN data FIFO. 0x54 USBHS_FIFO13 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO14 Read for OUT data FIFO, write for IN data FIFO. 0x58 USBHS_FIFO14 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO15 Read for OUT data FIFO, write for IN data FIFO. 0x5c USBHS_FIFO15 USBHS Endpoint FIFO Read/Write Register. 0 32 HWVERS HWVERS 0x6c 16 USBHS_HWVERS USBHS Register. 0 16 EPINFO Endpoint hardware information. 0x78 8 OUTENDPOINTS 4 4 read-only INTENDPOINTS 0 4 read-only RAMINFO RAM width information. 0x79 8 RAMBITS 0 4 read-only SOFTRESET Software reset register. 0x7A 8 RSTXS 1 1 read-write RSTS 0 1 read-write CTUCH Chirp timeout timer setting. 0x80 16 C_T_UCH HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host. 0 16 CTHSRTN Sets delay between HS resume to UTM normal operating mode. 0x82 16 C_T_HSTRN High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation. 0 16 MXM_USB_REG_00 MXM_USB_REG_00 0x400 M31_PHY_UTMI_RESET M31_PHY_UTMI_RESET 0x404 M31_PHY_UTMI_VCONTROL M31_PHY_UTMI_VCONTROL 0x408 M31_PHY_CLK_EN M31_PHY_CLK_EN 0x40C M31_PHY_PONRST M31_PHY_PONRST 0x410 M31_PHY_NONCRY_RSTB M31_PHY_NONCRY_RSTB 0x414 M31_PHY_NONCRY_EN M31_PHY_NONCRY_EN 0x418 M31_PHY_U2_COMPLIANCE_EN M31_PHY_U2_COMPLIANCE_EN 0x420 M31_PHY_U2_COMPLIANCE_DAC_ADJ M31_PHY_U2_COMPLIANCE_DAC_ADJ 0x424 M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN 0x428 M31_PHY_CLK_RDY M31_PHY_CLK_RDY 0x42C M31_PHY_PLL_EN M31_PHY_PLL_EN 0x430 M31_PHY_BIST_OK M31_PHY_BIST_OK 0x434 M31_PHY_DATA_OE M31_PHY_DATA_OE 0x438 M31_PHY_OSCOUTEN M31_PHY_OSCOUTEN 0x43C M31_PHY_LPM_ALIVE M31_PHY_LPM_ALIVE 0x440 M31_PHY_HS_BIST_MODE M31_PHY_HS_BIST_MODE 0x444 M31_PHY_CORECLKIN M31_PHY_CORECLKIN 0x448 M31_PHY_XTLSEL M31_PHY_XTLSEL 0x44C M31_PHY_LS_EN M31_PHY_LS_EN 0x450 M31_PHY_DEBUG_SEL M31_PHY_DEBUG_SEL 0x454 M31_PHY_DEBUG_OUT M31_PHY_DEBUG_OUT 0x458 M31_PHY_OUTCLKSEL M31_PHY_OUTCLKSEL 0x45C M31_PHY_XCFGI_31_0 M31_PHY_XCFGI_31_0 0x460 M31_PHY_XCFGI_63_32 M31_PHY_XCFGI_63_32 0x464 M31_PHY_XCFGI_95_64 M31_PHY_XCFGI_95_64 0x468 M31_PHY_XCFGI_127_96 M31_PHY_XCFGI_127_96 0x46C M31_PHY_XCFGI_137_128 M31_PHY_XCFGI_137_128 0x470 M31_PHY_XCFG_HS_COARSE_TUNE_NUM M31_PHY_XCFG_HS_COARSE_TUNE_NUM 0x474 M31_PHY_XCFG_HS_FINE_TUNE_NUM M31_PHY_XCFG_HS_FINE_TUNE_NUM 0x478 M31_PHY_XCFG_FS_COARSE_TUNE_NUM M31_PHY_XCFG_FS_COARSE_TUNE_NUM 0x47C M31_PHY_XCFG_FS_FINE_TUNE_NUM M31_PHY_XCFG_FS_FINE_TUNE_NUM 0x480 M31_PHY_XCFG_LOCK_RANGE_MAX M31_PHY_XCFG_LOCK_RANGE_MAX 0x484 M31_PHY_XCFGI_LOCK_RANGE_MIN M31_PHY_XCFGI_LOCK_RANGE_MIN 0x488 M31_PHY_XCFG_OB_RSEL M31_PHY_XCFG_OB_RSEL 0x48C M31_PHY_XCFG_OC_RSEL M31_PHY_XCFG_OC_RSEL 0x490 M31_PHY_XCFGO M31_PHY_XCFGO 0x494 MXM_INT USB Added Maxim Interrupt Flag Register. 0x498 VBUS VBUS 0 1 NOVBUS NOVBUS 1 1 MXM_INT_EN USB Added Maxim Interrupt Enable Register. 0x49C VBUS VBUS 0 1 NOVBUS NOVBUS 1 1 MXM_SUSPEND USB Added Maxim Suspend Register. 0x4A0 SEL Suspend register 0 1 MXM_REG_A4 USB Added Maxim Power Status Register 0x4A4 VRST_VDDB_N_A VRST_VDDB_N_A 0 1 WDT Windowed Watchdog Timer 0x40003000 0x00 0x0400 registers WWDT 1 CTRL Watchdog Timer Control Register. 0x00 read-write INT_LATE_VAL Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_LATE_VAL Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 4 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 EN Windowed Watchdog Timer Enable. 8 1 dis Disable. 0 en Enable. 1 INT_LATE Windowed Watchdog Timer Interrupt Flag Too Late. 9 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 WDT_INT_EN Windowed Watchdog Timer Interrupt Enable. 10 1 dis Disable. 0 en Enable. 1 WDT_RST_EN Windowed Watchdog Timer Reset Enable. 11 1 dis Disable. 0 en Enable. 1 INT_EARLY Windowed Watchdog Timer Interrupt Flag Too Soon. 12 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 INT_EARLY_VAL Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 16 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_EARLY_VAL Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 20 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 CLKRDY_IE Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock. 27 1 CLKRDY Clock Status. 28 1 WIN_EN Enables the Windowed Watchdog Function. 29 1 dis Windowed Mode Disabled (i.e. Compatibility Mode). 0 en Windowed Mode Enabled. 1 RST_EARLY Windowed Watchdog Timer Reset Flag Too Soon. 30 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST_LATE Windowed Watchdog Timer Reset Flag Too Late. 31 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST Windowed Watchdog Timer Reset Register. 0x04 write-only RESET Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled. 0 8 seq0 The first value to be written to reset the WDT. 0x000000A5 seq1 The second value to be written to reset the WDT. 0x0000005A CLKSEL Windowed Watchdog Timer Clock Select Register. 0x08 read-write SOURCE WWDT Clock Selection Register. 0 3 CNT Windowed Watchdog Timer Count Register. 0x0C read-only COUNT Current Value of the Windowed Watchdog Timer Counter. 0 32 WDT1 Windowed Watchdog Timer 1 0x40080800 WDT1 WDT1 IRQ 57 WUT Wake Up Timer 0x40006400 0x00 0x0400 registers WUT 53 CNT Wakeup Timer Count Register 0x0000 read-write COUNT Timer Count Value. 0 32 CMP Wakeup Timer Compare Register 0x0004 read-write COMPARE Timer Compare Value. 0 32 INTFL Wakeup Timer Interrupt Register 0x000C read-write IRQ_CLR Timer Interrupt. 0 1 CTRL Wakeup Timer Control Register 0x0010 read-write TMODE Timer Mode Select. 0 3 oneShot One Shot Mode. 0 continuous Continuous Mode. 1 counter Counter Mode. 2 pwm PWM Mode. 3 capture Capture Mode. 4 compare Compare Mode. 5 gated Gated Mode. 6 captureCompare Capture/Compare Mode. 7 PRES Timer Prescaler Select. 3 3 DIV1 0 DIV2 1 DIV4 2 DIV8 3 DIV16 4 DIV32 5 DIV64 6 DIV128 7 DIV256 0 DIV512 2 DIV1024 3 DIV2048 4 DIV4096 5 TPOL Timer pOLARITY. 6 1 TEN Timer Enable. 7 1 timer_dis 0 timer_en 1 PRES3 Timer Prescaler Select. 8 1 pres3_1 0 pres3_2 0 pres3_4 0 pres3_8 0 pres3_16 0 pres3_32 0 pres3_64 0 pres3_128 0 pres3_256 1 pres3_512 1 pres3_1024 1 pres3_2048 1 pres3_4096 1 NOLCMP Non Overlaping Compare Register 0x0014 read-write NOLLCMP Non Overlaping Low Compare. 0 8 NOLHCMP Non Overlaping High Compare. 8 8 PRESET Preset register. 0x0018 PRESET Preset Value. 0 32 RELOAD Reload register. 0x001C RELOAD Reload Value. 0 32 SNAPSHOT Snapshot register. 0x0020 SNAPSHOT Snapshot Value. 0 32