1<?xml version='1.0' encoding='utf-8'?> 2<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xsi:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <vendor>Maxim-Integrated</vendor> 4 <vendorID>Maxim</vendorID> 5 <name>max32572</name> 6 <series>ARMCM4</series> 7 <version>1.0</version> 8 <description>MAX32572 32-bit ARM Cortex-M4 microcontroller, 1024KB of flash, 760KB of system RAM, 128KB of Boot ROM.</description> 9 <cpu> 10 <name>CM4</name> 11 <revision>r2p1</revision> 12 <endian>little</endian> 13 <mpuPresent>true</mpuPresent> 14 <fpuPresent>true</fpuPresent> 15 <nvicPrioBits>3</nvicPrioBits> 16 <vendorSystickConfig>false</vendorSystickConfig> 17 </cpu> 18 <addressUnitBits>8</addressUnitBits> 19 <width>32</width> 20 <size>0x20</size> 21 <access>read-write</access> 22 <resetValue>0x00000000</resetValue> 23 <resetMask>0xFFFFFFFF</resetMask> 24 <peripherals> 25 <peripheral> 26 <name>ADC</name> 27 <description>10-bit Analog to Digital Converter</description> 28 <baseAddress>0x40034000</baseAddress> 29 <size>32</size> 30 <access>read-write</access> 31 <addressBlock> 32 <offset>0</offset> 33 <size>0x1000</size> 34 <usage>registers</usage> 35 </addressBlock> 36 <interrupt> 37 <name>ADC</name> 38 <description>ADC IRQ</description> 39 <value>20</value> 40 </interrupt> 41 <registers> 42 <register> 43 <name>CTRL</name> 44 <description>ADC Control</description> 45 <addressOffset>0x0000</addressOffset> 46 <access>read-write</access> 47 <fields> 48 <field> 49 <name>START</name> 50 <description>Start ADC Conversion</description> 51 <bitRange>[0:0]</bitRange> 52 <access>read-write</access> 53 </field> 54 <field> 55 <name>PWR</name> 56 <description>ADC Power Up</description> 57 <bitRange>[1:1]</bitRange> 58 <access>read-write</access> 59 </field> 60 <field> 61 <name>REBUF_PWR</name> 62 <description>ADC Reference Buffer Power Up</description> 63 <bitRange>[3:3]</bitRange> 64 <access>read-write</access> 65 </field> 66 <field> 67 <name>CHGPUMP_PWR</name> 68 <description>ADC Charge Pump Power Up</description> 69 <bitRange>[4:4]</bitRange> 70 <access>read-write</access> 71 </field> 72 <field> 73 <name>REF_SCALE</name> 74 <description>ADC Reference Scale</description> 75 <bitRange>[8:8]</bitRange> 76 <access>read-write</access> 77 </field> 78 <field> 79 <name>SCALE</name> 80 <description>ADC Scale</description> 81 <bitRange>[9:9]</bitRange> 82 <access>read-write</access> 83 </field> 84 <field> 85 <name>CLK_EN</name> 86 <description>ADC Clock Enable</description> 87 <bitRange>[11:11]</bitRange> 88 <access>read-write</access> 89 </field> 90 <field> 91 <name>CH_SEL</name> 92 <description>ADC Channel Select</description> 93 <bitRange>[16:12]</bitRange> 94 <access>read-write</access> 95 <enumeratedValues> 96 <enumeratedValue> 97 <name>AIN0</name> 98 <value>0</value> 99 </enumeratedValue> 100 <enumeratedValue> 101 <name>AIN1</name> 102 <value>1</value> 103 </enumeratedValue> 104 <enumeratedValue> 105 <name>AIN2</name> 106 <value>2</value> 107 </enumeratedValue> 108 <enumeratedValue> 109 <name>AIN3</name> 110 <value>3</value> 111 </enumeratedValue> 112 <enumeratedValue> 113 <name>AIN4</name> 114 <value>4</value> 115 </enumeratedValue> 116 <enumeratedValue> 117 <name>AIN5</name> 118 <value>5</value> 119 </enumeratedValue> 120 <enumeratedValue> 121 <name>AIN6</name> 122 <value>6</value> 123 </enumeratedValue> 124 <enumeratedValue> 125 <name>AIN7</name> 126 <value>7</value> 127 </enumeratedValue> 128 <enumeratedValue> 129 <name>VcoreA</name> 130 <value>8</value> 131 </enumeratedValue> 132 <enumeratedValue> 133 <name>VcoreB</name> 134 <value>9</value> 135 </enumeratedValue> 136 <enumeratedValue> 137 <name>Vrxout</name> 138 <value>10</value> 139 </enumeratedValue> 140 <enumeratedValue> 141 <name>Vtxout</name> 142 <value>11</value> 143 </enumeratedValue> 144 <enumeratedValue> 145 <name>VddA</name> 146 <value>12</value> 147 </enumeratedValue> 148 <enumeratedValue> 149 <name>VddB</name> 150 <description>VddB/4</description> 151 <value>13</value> 152 </enumeratedValue> 153 <enumeratedValue> 154 <name>Vddio</name> 155 <description>Vddio/4</description> 156 <value>14</value> 157 </enumeratedValue> 158 <enumeratedValue> 159 <name>Vddioh</name> 160 <description>Vddioh/4</description> 161 <value>15</value> 162 </enumeratedValue> 163 <enumeratedValue> 164 <name>VregI</name> 165 <description>VregI/4</description> 166 <value>16</value> 167 </enumeratedValue> 168 </enumeratedValues> 169 </field> 170 <field> 171 <name>DIVSEL</name> 172 <description>Scales the external inputs, all inputs are scaled the same</description> 173 <bitRange>[18:17]</bitRange> 174 <access>read-write</access> 175 <enumeratedValues> 176 <enumeratedValue> 177 <name>DIV1</name> 178 <value>0</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>DIV2</name> 182 <value>1</value> 183 </enumeratedValue> 184 <enumeratedValue> 185 <name>DIV3</name> 186 <value>2</value> 187 </enumeratedValue> 188 <enumeratedValue> 189 <name>DIV4</name> 190 <value>3</value> 191 </enumeratedValue> 192 </enumeratedValues> 193 </field> 194 <field> 195 <name>DATA_ALIGN</name> 196 <description>ADC Data Alignment Select</description> 197 <bitRange>[20:20]</bitRange> 198 <access>read-write</access> 199 </field> 200 </fields> 201 </register> 202 <register> 203 <name>STATUS</name> 204 <description>ADC Status</description> 205 <addressOffset>0x0004</addressOffset> 206 <access>read-write</access> 207 <fields> 208 <field> 209 <name>ACTIVE</name> 210 <description>ADC Conversion In Progress</description> 211 <bitRange>[0:0]</bitRange> 212 <access>read-only</access> 213 </field> 214 <field> 215 <name>AFE_PWR_UP_ACTIVE</name> 216 <description>AFE Power Up Delay Active</description> 217 <bitRange>[2:2]</bitRange> 218 <access>read-only</access> 219 </field> 220 <field> 221 <name>OVERFLOW</name> 222 <description>ADC Overflow</description> 223 <bitRange>[3:3]</bitRange> 224 <access>read-only</access> 225 </field> 226 </fields> 227 </register> 228 <register> 229 <name>DATA</name> 230 <description>ADC Output Data</description> 231 <addressOffset>0x0008</addressOffset> 232 <access>read-write</access> 233 <fields> 234 <field> 235 <name>DATA</name> 236 <description>ADC Converted Sample Data Output</description> 237 <bitRange>[15:0]</bitRange> 238 <access>read-only</access> 239 </field> 240 </fields> 241 </register> 242 <register> 243 <name>INTR</name> 244 <description>ADC Interrupt Control Register</description> 245 <addressOffset>0x000C</addressOffset> 246 <access>read-write</access> 247 <fields> 248 <field> 249 <name>DONE_IE</name> 250 <description>ADC Done Interrupt Enable</description> 251 <bitRange>[0:0]</bitRange> 252 <access>read-write</access> 253 </field> 254 <field> 255 <name>REF_READY_IE</name> 256 <description>ADC Reference Ready Interrupt Enable</description> 257 <bitRange>[1:1]</bitRange> 258 <access>read-write</access> 259 </field> 260 <field> 261 <name>HI_LIMIT_IE</name> 262 <description>ADC Hi Limit Monitor Interrupt Enable</description> 263 <bitRange>[2:2]</bitRange> 264 <access>read-write</access> 265 </field> 266 <field> 267 <name>LO_LIMIT_IE</name> 268 <description>ADC Lo Limit Monitor Interrupt Enable</description> 269 <bitRange>[3:3]</bitRange> 270 <access>read-write</access> 271 </field> 272 <field> 273 <name>OVERFLOW_IE</name> 274 <description>ADC Overflow Interrupt Enable</description> 275 <bitRange>[4:4]</bitRange> 276 <access>read-write</access> 277 </field> 278 <field> 279 <name>DONE_IF</name> 280 <description>ADC Done Interrupt Flag</description> 281 <bitRange>[16:16]</bitRange> 282 <access>read-write</access> 283 <modifiedWriteValues>oneToClear</modifiedWriteValues> 284 </field> 285 <field> 286 <name>REF_READY_IF</name> 287 <description>ADC Reference Ready Interrupt Flag</description> 288 <bitRange>[17:17]</bitRange> 289 <access>read-write</access> 290 <modifiedWriteValues>oneToClear</modifiedWriteValues> 291 </field> 292 <field> 293 <name>HI_LIMIT_IF</name> 294 <description>ADC Hi Limit Monitor Interrupt Flag</description> 295 <bitRange>[18:18]</bitRange> 296 <access>read-write</access> 297 <modifiedWriteValues>oneToClear</modifiedWriteValues> 298 </field> 299 <field> 300 <name>LO_LIMIT_IF</name> 301 <description>ADC Lo Limit Monitor Interrupt Flag</description> 302 <bitRange>[19:19]</bitRange> 303 <access>read-write</access> 304 <modifiedWriteValues>oneToClear</modifiedWriteValues> 305 </field> 306 <field> 307 <name>OVERFLOW_IF</name> 308 <description>ADC Overflow Interrupt Flag</description> 309 <bitRange>[20:20]</bitRange> 310 <access>read-write</access> 311 <modifiedWriteValues>oneToClear</modifiedWriteValues> 312 </field> 313 <field> 314 <name>PENDING</name> 315 <description>ADC Interrupt Pending Status</description> 316 <bitRange>[22:22]</bitRange> 317 <access>read-only</access> 318 </field> 319 </fields> 320 </register> 321 <register> 322 <dim>4</dim> 323 <dimIncrement>4</dimIncrement> 324 <name>LIMIT[%s]</name> 325 <description>ADC Limit</description> 326 <addressOffset>0x0010</addressOffset> 327 <access>read-write</access> 328 <fields> 329 <field> 330 <name>CH_LO_LIMIT</name> 331 <description>Low Limit Threshold</description> 332 <bitRange>[9:0]</bitRange> 333 <access>read-write</access> 334 </field> 335 <field> 336 <name>CH_HI_LIMIT</name> 337 <description>High Limit Threshold</description> 338 <bitRange>[21:12]</bitRange> 339 <access>read-write</access> 340 </field> 341 <field> 342 <name>CH_SEL</name> 343 <description>ADC Channel Select</description> 344 <bitRange>[27:24]</bitRange> 345 <access>read-write</access> 346 </field> 347 <field> 348 <name>CH_LO_LIMIT_EN</name> 349 <description>Low Limit Monitoring Enable</description> 350 <bitRange>[28:28]</bitRange> 351 <access>read-write</access> 352 </field> 353 <field> 354 <name>CH_HI_LIMIT_EN</name> 355 <description>High Limit Monitoring Enable</description> 356 <bitRange>[29:29]</bitRange> 357 <access>read-write</access> 358 </field> 359 </fields> 360 </register> 361 <register> 362 <name>DECCNT</name> 363 <description>ADC Decimation Count.</description> 364 <addressOffset>0x0020</addressOffset> 365 <access>read-write</access> 366 <fields> 367 <field> 368 <name>DELAY</name> 369 <description>Delay.</description> 370 <bitRange>[31:0]</bitRange> 371 <access>read-write</access> 372 </field> 373 </fields> 374 </register> 375 </registers> 376 </peripheral> 377<!--ADC 10-bit Analog to Digital Converter--> 378 <peripheral> 379 <name>AESKEYS</name> 380 <description>AES Key Registers.</description> 381 <baseAddress>0x40005000</baseAddress> 382 <addressBlock> 383 <offset>0x00</offset> 384 <size>0x400</size> 385 <usage>registers</usage> 386 </addressBlock> 387 <registers> 388 <register> 389 <dim>8</dim> 390 <dimIncrement>4</dimIncrement> 391 <name>MEU[%s]</name> 392 <description>AES-256 SRAM Encryption Key (MEU).</description> 393 <addressOffset>0x00</addressOffset> 394 <size>32</size> 395 <access>read-write</access> 396 </register> 397 <register> 398 <dim>4</dim> 399 <dimIncrement>4</dimIncrement> 400 <name>XIP[%s]</name> 401 <description>AES-128 QSPI Code Key (MEMPROT XIP).</description> 402 <addressOffset>0x20</addressOffset> 403 <size>32</size> 404 <access>read-write</access> 405 </register> 406 </registers> 407 </peripheral> 408<!--AESKEYS AES Key Registers.--> 409 <peripheral> 410 <name>MSRADC</name> 411 <description>Magnetic Strip Reader - 9 bit ADC</description> 412 <baseAddress>0x4002B000</baseAddress> 413 <size>32</size> 414 <access>read-write</access> 415 <addressBlock> 416 <offset>0</offset> 417 <size>0x1000</size> 418 <usage>registers</usage> 419 </addressBlock> 420 <interrupt> 421 <name>ADC9</name> 422 <description>ADC IRQ</description> 423 <value>22</value> 424 </interrupt> 425 <registers> 426 <register> 427 <name>CTRL</name> 428 <description>ADC Control</description> 429 <addressOffset>0x0000</addressOffset> 430 <access>read-write</access> 431 <fields> 432 <field> 433 <name>CLKDIV</name> 434 <description>ADC Clock Divider.</description> 435 <bitRange>[7:0]</bitRange> 436 <access>read-write</access> 437 </field> 438 <field> 439 <name>ACHSEL</name> 440 <description>A Channel ADC Input Pin Selection.</description> 441 <bitRange>[10:8]</bitRange> 442 <access>read-write</access> 443 <enumeratedValues> 444 <enumeratedValue> 445 <name>invalid</name> 446 <value>0</value> 447 </enumeratedValue> 448 <enumeratedValue> 449 <name>CH1_IN</name> 450 <value>1</value> 451 </enumeratedValue> 452 <enumeratedValue> 453 <name>CH2_IN</name> 454 <value>2</value> 455 </enumeratedValue> 456 <enumeratedValue> 457 <name>CH3_IN</name> 458 <value>3</value> 459 </enumeratedValue> 460 </enumeratedValues> 461 </field> 462 <field derivedFrom="ACHSEL"> 463 <name>BCHSEL</name> 464 <description>B Channel ADC Input Pin Selection.</description> 465 <bitRange>[13:11]</bitRange> 466 <access>read-write</access> 467 </field> 468 <field derivedFrom="ACHSEL"> 469 <name>CCHSEL</name> 470 <description>C Channel ADC Input Pin Selection.</description> 471 <bitRange>[16:14]</bitRange> 472 <access>read-write</access> 473 </field> 474 <field derivedFrom="ACHSEL"> 475 <name>DCHSEL</name> 476 <description>D Channel ADC Input Pin Selection.</description> 477 <bitRange>[19:17]</bitRange> 478 <access>read-write</access> 479 </field> 480 <field derivedFrom="ACHSEL"> 481 <name>ECHSEL</name> 482 <description>E Channel ADC Input Pin Selection.</description> 483 <bitRange>[22:20]</bitRange> 484 <access>read-write</access> 485 </field> 486 <field derivedFrom="ACHSEL"> 487 <name>FCHSEL</name> 488 <description>F Channel ADC Input Pin Selection.</description> 489 <bitRange>[25:23]</bitRange> 490 <access>read-write</access> 491 </field> 492 <field derivedFrom="ACHSEL"> 493 <name>GCHSEL</name> 494 <description>G Channel ADC Input Pin Selection.</description> 495 <bitRange>[28:26]</bitRange> 496 <access>read-write</access> 497 </field> 498 <field derivedFrom="ACHSEL"> 499 <name>HCHSEL</name> 500 <description>H Channel ADC Input Pin Selection.</description> 501 <bitRange>[31:29]</bitRange> 502 <access>read-write</access> 503 </field> 504 </fields> 505 </register> 506 <register> 507 <name>CMD</name> 508 <description>MSRADC Command</description> 509 <addressOffset>0x0004</addressOffset> 510 <access>read-write</access> 511 <fields> 512 <field> 513 <name>RST</name> 514 <description>ADC Reset.</description> 515 <bitRange>[0:0]</bitRange> 516 <access>read-write</access> 517 </field> 518 <field> 519 <name>SNGLSMPL</name> 520 <description>Single Sample Mode.</description> 521 <bitRange>[1:1]</bitRange> 522 <access>read-write</access> 523 </field> 524 <field> 525 <name>CONTSMPL</name> 526 <description>Continuous Sample Mode Enable.</description> 527 <bitRange>[2:2]</bitRange> 528 <access>read-write</access> 529 </field> 530 <field> 531 <name>ROTLIMIT</name> 532 <description>Rotation Limit.</description> 533 <bitRange>[6:4]</bitRange> 534 <access>read-write</access> 535 <enumeratedValues> 536 <enumeratedValue> 537 <name>1_channel</name> 538 <value>0</value> 539 </enumeratedValue> 540 <enumeratedValue> 541 <name>2_channels</name> 542 <value>1</value> 543 </enumeratedValue> 544 <enumeratedValue> 545 <name>3_channels</name> 546 <value>2</value> 547 </enumeratedValue> 548 <enumeratedValue> 549 <name>4_channels</name> 550 <value>3</value> 551 </enumeratedValue> 552 <enumeratedValue> 553 <name>5_channels</name> 554 <value>4</value> 555 </enumeratedValue> 556 <enumeratedValue> 557 <name>6_channels</name> 558 <value>5</value> 559 </enumeratedValue> 560 <enumeratedValue> 561 <name>7_channels</name> 562 <value>6</value> 563 </enumeratedValue> 564 <enumeratedValue> 565 <name>8_channels</name> 566 <value>7</value> 567 </enumeratedValue> 568 </enumeratedValues> 569 </field> 570 <field> 571 <name>CLKSEL</name> 572 <description>Clock Select.</description> 573 <bitRange>[10:8]</bitRange> 574 <access>read-write</access> 575 <enumeratedValues> 576 <enumeratedValue> 577 <name>3_samples</name> 578 <value>0</value> 579 </enumeratedValue> 580 <enumeratedValue> 581 <name>5_samples</name> 582 <value>1</value> 583 </enumeratedValue> 584 <enumeratedValue> 585 <name>4_samples</name> 586 <value>2</value> 587 </enumeratedValue> 588 <enumeratedValue> 589 <name>8_samples</name> 590 <value>3</value> 591 </enumeratedValue> 592 <enumeratedValue> 593 <name>16_samples</name> 594 <value>4</value> 595 </enumeratedValue> 596 <enumeratedValue> 597 <name>32_samples</name> 598 <value>5</value> 599 </enumeratedValue> 600 <enumeratedValue> 601 <name>64_samples</name> 602 <value>6</value> 603 </enumeratedValue> 604 <enumeratedValue> 605 <name>128_samples</name> 606 <value>7</value> 607 </enumeratedValue> 608 </enumeratedValues> 609 </field> 610 </fields> 611 </register> 612 <register> 613 <name>FIFO</name> 614 <description>ADC FIFO</description> 615 <addressOffset>0x0008</addressOffset> 616 <access>read-write</access> 617 <fields> 618 <field> 619 <name>SAMPLE</name> 620 <description>ADC Converted Sample Data Output</description> 621 <bitRange>[8:0]</bitRange> 622 <access>read-only</access> 623 </field> 624 <field> 625 <name>INPUT</name> 626 <description>ADC Sample Pin</description> 627 <bitRange>[11:9]</bitRange> 628 <access>read-only</access> 629 <enumeratedValues> 630 <enumeratedValue> 631 <name>invalid</name> 632 <value>0</value> 633 </enumeratedValue> 634 <enumeratedValue> 635 <name>CH1_IN</name> 636 <value>1</value> 637 </enumeratedValue> 638 <enumeratedValue> 639 <name>CH2_IN</name> 640 <value>2</value> 641 </enumeratedValue> 642 <enumeratedValue> 643 <name>CH3_IN</name> 644 <value>3</value> 645 </enumeratedValue> 646 <enumeratedValue> 647 <name>CH4_IN</name> 648 <value>4</value> 649 </enumeratedValue> 650 <enumeratedValue> 651 <name>CH5_IN</name> 652 <value>5</value> 653 </enumeratedValue> 654 <enumeratedValue> 655 <name>CH6_IN</name> 656 <value>6</value> 657 </enumeratedValue> 658 <enumeratedValue> 659 <name>CH7_IN</name> 660 <value>7</value> 661 </enumeratedValue> 662 </enumeratedValues> 663 </field> 664 <field> 665 <name>INCOMPLETE</name> 666 <description>ADC Incomplete.</description> 667 <bitRange>[12:12]</bitRange> 668 <access>read-only</access> 669 </field> 670 </fields> 671 </register> 672 <register> 673 <name>INTEN</name> 674 <description>ADC Interrupt Enable Register</description> 675 <addressOffset>0x000C</addressOffset> 676 <access>read-write</access> 677 <fields> 678 <field> 679 <name>SET_FIFOLVL</name> 680 <description>Set FIFO Interrupt Level.</description> 681 <bitRange>[4:0]</bitRange> 682 <access>read-write</access> 683 <enumeratedValues> 684 <enumeratedValue> 685 <name>at_least_1</name> 686 <value>0</value> 687 </enumeratedValue> 688 <enumeratedValue> 689 <name>at_least_2</name> 690 <value>1</value> 691 </enumeratedValue> 692 <enumeratedValue> 693 <name>at_least_3</name> 694 <value>2</value> 695 </enumeratedValue> 696 <enumeratedValue> 697 <name>at_least_4</name> 698 <value>3</value> 699 </enumeratedValue> 700 <enumeratedValue> 701 <name>at_least_5</name> 702 <value>4</value> 703 </enumeratedValue> 704 <enumeratedValue> 705 <name>at_least_6</name> 706 <value>5</value> 707 </enumeratedValue> 708 <enumeratedValue> 709 <name>at_least_7</name> 710 <value>6</value> 711 </enumeratedValue> 712 <enumeratedValue> 713 <name>at_least_8</name> 714 <value>7</value> 715 </enumeratedValue> 716 <enumeratedValue> 717 <name>at_least_9</name> 718 <value>8</value> 719 </enumeratedValue> 720 <enumeratedValue> 721 <name>at_least_10</name> 722 <value>9</value> 723 </enumeratedValue> 724 <enumeratedValue> 725 <name>at_least_11</name> 726 <value>10</value> 727 </enumeratedValue> 728 <enumeratedValue> 729 <name>at_least_12</name> 730 <value>11</value> 731 </enumeratedValue> 732 <enumeratedValue> 733 <name>at_least_13</name> 734 <value>12</value> 735 </enumeratedValue> 736 <enumeratedValue> 737 <name>at_least_14</name> 738 <value>13</value> 739 </enumeratedValue> 740 <enumeratedValue> 741 <name>at_least_15</name> 742 <value>14</value> 743 </enumeratedValue> 744 <enumeratedValue> 745 <name>at_least_16</name> 746 <value>15</value> 747 </enumeratedValue> 748 </enumeratedValues> 749 </field> 750 <field> 751 <name>DMAREQ</name> 752 <description>DMA Request Enable.</description> 753 <bitRange>[5:5]</bitRange> 754 <access>read-write</access> 755 </field> 756 <field> 757 <name>FIFO_OV</name> 758 <description>FIFO Overflow Interrupt Enable.</description> 759 <bitRange>[6:6]</bitRange> 760 <access>read-write</access> 761 </field> 762 <field> 763 <name>FIFO_UN</name> 764 <description>FIFO Underflow Interrupt Enable.</description> 765 <bitRange>[7:7]</bitRange> 766 <access>read-write</access> 767 </field> 768 <field> 769 <name>FIFO_LVL</name> 770 <description>FIFO Level Interrupt Enable.</description> 771 <bitRange>[8:8]</bitRange> 772 <access>read-write</access> 773 </field> 774 <field> 775 <name>GLOBAL</name> 776 <description>ADC Global Interrupt Enable.</description> 777 <bitRange>[9:9]</bitRange> 778 <access>read-write</access> 779 </field> 780 </fields> 781 </register> 782 <register> 783 <name>INTFL</name> 784 <description>ADC Interrupt Flag Register.</description> 785 <access>read-write</access> 786 <addressOffset>0x0010</addressOffset> 787 <fields> 788 <field> 789 <name>FIFOCNT</name> 790 <description>FIFO Count.</description> 791 <bitRange>[5:0]</bitRange> 792 <access>read-only</access> 793 </field> 794 <field> 795 <name>FIFO_FULL_ST</name> 796 <description>FIFO Full Status.</description> 797 <bitRange>[6:6]</bitRange> 798 <access>read-only</access> 799 </field> 800 <field> 801 <name>FIFO_EM_ST</name> 802 <description>FIFO Empty Status.</description> 803 <bitRange>[7:7]</bitRange> 804 <access>read-only</access> 805 </field> 806 <field> 807 <name>FIFO_OV</name> 808 <description>FIFO Overflow Status.</description> 809 <bitRange>[8:8]</bitRange> 810 <access>read-only</access> 811 </field> 812 <field> 813 <name>FIFO_UN</name> 814 <description>FIFO Underflow Status.</description> 815 <bitRange>[9:9]</bitRange> 816 <access>read-only</access> 817 </field> 818 <field> 819 <name>FIFO_LVL</name> 820 <description>FIFO Level Status.</description> 821 <bitRange>[10:10]</bitRange> 822 <access>read-only</access> 823 </field> 824 <field> 825 <name>GLOBAL</name> 826 <description>ADC Global Interrupt Flag.</description> 827 <bitRange>[11:11]</bitRange> 828 <access>read-only</access> 829 </field> 830 </fields> 831 </register> 832 </registers> 833 </peripheral> 834<!--MSRADC Magnetic Strip Reader - 9 bit ADC--> 835 <peripheral> 836 <name>FCR</name> 837 <description>Function Control Register.</description> 838 <baseAddress>0x40000800</baseAddress> 839 <addressBlock> 840 <offset>0x00</offset> 841 <size>0x400</size> 842 <usage>registers</usage> 843 </addressBlock> 844 <registers> 845 <register> 846 <name>FCTRL0</name> 847 <description>Register 0.</description> 848 <addressOffset>0x00</addressOffset> 849 <access>read-write</access> 850 <fields> 851 <field> 852 <name>USBCLKSEL</name> 853 <description>USB External Core Clock Select.</description> 854 <bitOffset>16</bitOffset> 855 <bitWidth>1</bitWidth> 856 <enumeratedValues> 857 <enumeratedValue> 858 <name>sys</name> 859 <description>Generated clock from system clock.</description> 860 <value>0</value> 861 </enumeratedValue> 862 <enumeratedValue> 863 <name>dig</name> 864 <description>Digital clock from a GPIO.</description> 865 <value>1</value> 866 </enumeratedValue> 867 </enumeratedValues> 868 </field> 869 <field> 870 <name>I2C0DGEN0</name> 871 <description>I2C0 SDA Glitch Filter Enable.</description> 872 <bitOffset>20</bitOffset> 873 <bitWidth>1</bitWidth> 874 <enumeratedValues> 875 <enumeratedValue> 876 <name>dis</name> 877 <description>Filter disabled.</description> 878 <value>0</value> 879 </enumeratedValue> 880 <enumeratedValue> 881 <name>en</name> 882 <description>Filter enabled.</description> 883 <value>1</value> 884 </enumeratedValue> 885 </enumeratedValues> 886 </field> 887 <field> 888 <name>I2C0DGEN1</name> 889 <description>I2C0 SCL Glitch Filter Enable.</description> 890 <bitOffset>21</bitOffset> 891 <bitWidth>1</bitWidth> 892 <enumeratedValues> 893 <enumeratedValue> 894 <name>dis</name> 895 <description>Filter disabled.</description> 896 <value>0</value> 897 </enumeratedValue> 898 <enumeratedValue> 899 <name>en</name> 900 <description>Filter enabled.</description> 901 <value>1</value> 902 </enumeratedValue> 903 </enumeratedValues> 904 </field> 905 <field> 906 <name>I2C1DGEN0</name> 907 <description>I2C1 SDA Glitch Filter Enable.</description> 908 <bitOffset>22</bitOffset> 909 <bitWidth>1</bitWidth> 910 <enumeratedValues> 911 <enumeratedValue> 912 <name>dis</name> 913 <description>Filter disabled.</description> 914 <value>0</value> 915 </enumeratedValue> 916 <enumeratedValue> 917 <name>en</name> 918 <description>Filter enabled.</description> 919 <value>1</value> 920 </enumeratedValue> 921 </enumeratedValues> 922 </field> 923 <field> 924 <name>I2C1DGEN1</name> 925 <description>I2C1 SCL Glitch Filter Enable.</description> 926 <bitOffset>23</bitOffset> 927 <bitWidth>1</bitWidth> 928 <enumeratedValues> 929 <enumeratedValue> 930 <name>dis</name> 931 <description>Filter disabled.</description> 932 <value>0</value> 933 </enumeratedValue> 934 <enumeratedValue> 935 <name>en</name> 936 <description>Filter enabled.</description> 937 <value>1</value> 938 </enumeratedValue> 939 </enumeratedValues> 940 </field> 941 </fields> 942 </register> 943 <register> 944 <name>FCTRL1</name> 945 <description>Register 1.</description> 946 <addressOffset>0x04</addressOffset> 947 <access>read-write</access> 948 <fields> 949 <field> 950 <name>AC_EN</name> 951 <description>Auto-calibration Enable.</description> 952 <bitOffset>0</bitOffset> 953 <bitWidth>1</bitWidth> 954 <enumeratedValues> 955 <enumeratedValue> 956 <name>dis</name> 957 <description>Disabled.</description> 958 <value>0</value> 959 </enumeratedValue> 960 <enumeratedValue> 961 <name>en</name> 962 <description>Enabled.</description> 963 <value>1</value> 964 </enumeratedValue> 965 </enumeratedValues> 966 </field> 967 <field> 968 <name>AC_RUN</name> 969 <description>Autocalibration Run.</description> 970 <bitOffset>1</bitOffset> 971 <bitWidth>1</bitWidth> 972 <enumeratedValues> 973 <enumeratedValue> 974 <name>not</name> 975 <description>Not Running.</description> 976 <value>0</value> 977 </enumeratedValue> 978 <enumeratedValue> 979 <name>run</name> 980 <description>Running.</description> 981 <value>1</value> 982 </enumeratedValue> 983 </enumeratedValues> 984 </field> 985 <field> 986 <name>LOAD</name> 987 <description>Load Trim.</description> 988 <bitOffset>2</bitOffset> 989 <bitWidth>1</bitWidth> 990 </field> 991 <field> 992 <name>INV_GAIN</name> 993 <description>Invert Gain.</description> 994 <bitOffset>3</bitOffset> 995 <bitWidth>1</bitWidth> 996 <enumeratedValues> 997 <enumeratedValue> 998 <name>not</name> 999 <description>Not Running.</description> 1000 <value>0</value> 1001 </enumeratedValue> 1002 <enumeratedValue> 1003 <name>run</name> 1004 <description>Running.</description> 1005 <value>1</value> 1006 </enumeratedValue> 1007 </enumeratedValues> 1008 </field> 1009 <field> 1010 <name>ATOMIC</name> 1011 <description>Atomic mode.</description> 1012 <bitOffset>4</bitOffset> 1013 <bitWidth>1</bitWidth> 1014 <enumeratedValues> 1015 <enumeratedValue> 1016 <name>not</name> 1017 <description>Not Running.</description> 1018 <value>0</value> 1019 </enumeratedValue> 1020 <enumeratedValue> 1021 <name>run</name> 1022 <description>Running.</description> 1023 <value>1</value> 1024 </enumeratedValue> 1025 </enumeratedValues> 1026 </field> 1027 <field> 1028 <name>MU</name> 1029 <description>MU value.</description> 1030 <bitOffset>8</bitOffset> 1031 <bitWidth>12</bitWidth> 1032 </field> 1033 <field> 1034 <name>AC_TRIM</name> 1035 <description>150MHz HFIO Auto Calibration Trim</description> 1036 <bitOffset>23</bitOffset> 1037 <bitWidth>9</bitWidth> 1038 </field> 1039 </fields> 1040 </register> 1041 <register> 1042 <name>FCTRL3</name> 1043 <description>Register 3.</description> 1044 <addressOffset>0x0C</addressOffset> 1045 <access>read-write</access> 1046 <fields> 1047 <field> 1048 <name>DONECNT</name> 1049 <description>Auto-calibration Done Counter Setting.</description> 1050 <bitOffset>0</bitOffset> 1051 <bitWidth>8</bitWidth> 1052 </field> 1053 </fields> 1054 </register> 1055 <register> 1056 <name>URVBOOTADDR</name> 1057 <description>Register 4.</description> 1058 <addressOffset>0x10</addressOffset> 1059 <access>read-write</access> 1060 <fields> 1061 <field> 1062 <name>BOOTADDR</name> 1063 <description>RISCV Boot Address.</description> 1064 <bitOffset>0</bitOffset> 1065 <bitWidth>32</bitWidth> 1066 </field> 1067 </fields> 1068 </register> 1069 <register> 1070 <name>URVCTRL</name> 1071 <description>Register 5.</description> 1072 <addressOffset>0x14</addressOffset> 1073 <access>read-write</access> 1074 <fields> 1075 <field> 1076 <name>SLEEP_REQ</name> 1077 <description>Sleep Request to RISCV.</description> 1078 <bitOffset>0</bitOffset> 1079 <bitWidth>1</bitWidth> 1080 </field> 1081 <field> 1082 <name>SLEEP_ACK</name> 1083 <description>Acknowledgement of Sleep Request for RISCV.</description> 1084 <bitOffset>1</bitOffset> 1085 <bitWidth>1</bitWidth> 1086 </field> 1087 </fields> 1088 </register> 1089 <register> 1090 <name>GP</name> 1091 <description>General Purpose Register.</description> 1092 <addressOffset>0x1C</addressOffset> 1093 <access>read-write</access> 1094 <fields> 1095 <field> 1096 <name>GP</name> 1097 <description>General Purpose.</description> 1098 <bitOffset>0</bitOffset> 1099 <bitWidth>32</bitWidth> 1100 </field> 1101 </fields> 1102 </register> 1103 <register> 1104 <name>TRIMCTRL</name> 1105 <description>MSR ADC Trim Register.</description> 1106 <addressOffset>0x20</addressOffset> 1107 <access>read-write</access> 1108 <fields> 1109 <field> 1110 <name>MSR_R1</name> 1111 <description>MSR R1</description> 1112 <bitOffset>0</bitOffset> 1113 <bitWidth>2</bitWidth> 1114 <enumeratedValues> 1115 <enumeratedValue> 1116 <name>0K</name> 1117 <description>0kOhm</description> 1118 <value>0</value> 1119 </enumeratedValue> 1120 <enumeratedValue> 1121 <name>1P2K</name> 1122 <description>1.2kOhm</description> 1123 <value>1</value> 1124 </enumeratedValue> 1125 <enumeratedValue> 1126 <name>2P4K</name> 1127 <description>2.4kOhm</description> 1128 <value>2</value> 1129 </enumeratedValue> 1130 <enumeratedValue> 1131 <name>4P8K</name> 1132 <description>4.8kOhm</description> 1133 <value>3</value> 1134 </enumeratedValue> 1135 </enumeratedValues> 1136 </field> 1137 <field> 1138 <name>MSR_R2</name> 1139 <description>MSR R2</description> 1140 <bitOffset>2</bitOffset> 1141 <bitWidth>3</bitWidth> 1142 <enumeratedValues> 1143 <enumeratedValue> 1144 <name>OPEN</name> 1145 <description>Open drain.</description> 1146 <value>0</value> 1147 </enumeratedValue> 1148 <enumeratedValue> 1149 <name>3K</name> 1150 <description>3kOhm</description> 1151 <value>4</value> 1152 </enumeratedValue> 1153 <enumeratedValue> 1154 <name>6K</name> 1155 <description>6kOhm</description> 1156 <value>5</value> 1157 </enumeratedValue> 1158 <enumeratedValue> 1159 <name>12K</name> 1160 <description>12kOhm</description> 1161 <value>6</value> 1162 </enumeratedValue> 1163 <enumeratedValue> 1164 <name>24K</name> 1165 <description>24kOhm</description> 1166 <value>7</value> 1167 </enumeratedValue> 1168 </enumeratedValues> 1169 </field> 1170 </fields> 1171 </register> 1172 <register> 1173 <name>ERFOKS</name> 1174 <description>ERFO Kick Start Register.</description> 1175 <addressOffset>0x24</addressOffset> 1176 <access>read-write</access> 1177 <fields> 1178 <field> 1179 <name>CTRL</name> 1180 <description>Kick Start Control.</description> 1181 <bitOffset>0</bitOffset> 1182 <bitWidth>16</bitWidth> 1183 </field> 1184 </fields> 1185 </register> 1186 </registers> 1187 </peripheral> 1188<!--FCR Function Control Register.--> 1189 <peripheral> 1190 <name>TRIMSIR</name> 1191 <description>Trim System Initilazation Registers</description> 1192 <baseAddress>0x40005400</baseAddress> 1193 <addressBlock> 1194 <offset>0x00</offset> 1195 <size>0x400</size> 1196 <usage>registers</usage> 1197 </addressBlock> 1198 <registers> 1199 <register> 1200 <name>BBSIR2</name> 1201 <description>System Init. Configuration Register 2.</description> 1202 <addressOffset>0x08</addressOffset> 1203 <access>read-only</access> 1204 </register> 1205 <register> 1206 <name>BBSIR3</name> 1207 <description>System Init. Configuration Register 3.</description> 1208 <addressOffset>0x0C</addressOffset> 1209 <access>read-only</access> 1210 </register> 1211 </registers> 1212 </peripheral> 1213<!--TRIMSIR Trim System Initilazation Registers--> 1214 <peripheral> 1215 <name>MCR</name> 1216 <description>Misc Control.</description> 1217 <baseAddress>0x40006C00</baseAddress> 1218 <addressBlock> 1219 <offset>0x00</offset> 1220 <size>0x400</size> 1221 <usage>registers</usage> 1222 </addressBlock> 1223 <registers> 1224 <register> 1225 <name>PDOWN</name> 1226 <description>PDOWN Drive Strength</description> 1227 <addressOffset>0x08</addressOffset> 1228 <fields> 1229 <field> 1230 <name>PDOWNDS</name> 1231 <description>PDOWN Drive Strength</description> 1232 <bitOffset>0</bitOffset> 1233 <bitWidth>2</bitWidth> 1234 </field> 1235 <field> 1236 <name>PDOWNVS</name> 1237 <description>PDOWN Voltage Select</description> 1238 <bitOffset>2</bitOffset> 1239 <bitWidth>1</bitWidth> 1240 </field> 1241 </fields> 1242 </register> 1243 <register> 1244 <name>CTRL</name> 1245 <description>Misc Power State Control Register</description> 1246 <addressOffset>0x10</addressOffset> 1247 <fields> 1248 <field> 1249 <name>VDDCSW</name> 1250 <description>Controls switching of VCORE</description> 1251 <bitOffset>1</bitOffset> 1252 <bitWidth>2</bitWidth> 1253 </field> 1254 <field> 1255 <name>USBSWEN_N</name> 1256 <description>USB Switch Control</description> 1257 <bitOffset>3</bitOffset> 1258 <bitWidth>1</bitWidth> 1259 <enumeratedValues> 1260 <enumeratedValue> 1261 <name>off</name> 1262 <description>USB SW off in LP modes</description> 1263 <value>1</value> 1264 </enumeratedValue> 1265 <enumeratedValue> 1266 <name>on</name> 1267 <description>USB SW On</description> 1268 <value>0</value> 1269 </enumeratedValue> 1270 </enumeratedValues> 1271 </field> 1272 <field> 1273 <name>P1M</name> 1274 <description>Enable the Reset Pad Pull Up Resistors</description> 1275 <bitOffset>9</bitOffset> 1276 <bitWidth>1</bitWidth> 1277 <enumeratedValues> 1278 <enumeratedValue> 1279 <name>1m</name> 1280 <description>1MOhm Pullup</description> 1281 <value>0</value> 1282 </enumeratedValue> 1283 <enumeratedValue> 1284 <name>25k</name> 1285 <description>25kOhm Pullup.</description> 1286 <value>1</value> 1287 </enumeratedValue> 1288 </enumeratedValues> 1289 </field> 1290 <field> 1291 <name>rstn_voltage_sel</name> 1292 <description>Error! Description not Found!</description> 1293 <bitOffset>10</bitOffset> 1294 <bitWidth>1</bitWidth> 1295 </field> 1296 </fields> 1297 </register> 1298 <register> 1299 <name>CLKCTRL</name> 1300 <description>Clock Control Register.</description> 1301 <addressOffset>0x14</addressOffset> 1302 <fields> 1303 <field> 1304 <name>ERTCO_PD</name> 1305 <description>32kHz Crystal Oscillator Power Down.</description> 1306 <bitOffset>16</bitOffset> 1307 <bitWidth>1</bitWidth> 1308 </field> 1309 <field> 1310 <name>ERTCO_EN</name> 1311 <description>32kHz Crystal Oscillator Enable.</description> 1312 <bitOffset>17</bitOffset> 1313 <bitWidth>1</bitWidth> 1314 </field> 1315 </fields> 1316 </register> 1317 <register> 1318 <name>RST</name> 1319 <description>Reset Register.</description> 1320 <addressOffset>0x18</addressOffset> 1321 <fields> 1322 <field> 1323 <name>RTC</name> 1324 <description>Real Time Cock Reset.</description> 1325 <bitOffset>0</bitOffset> 1326 <bitWidth>1</bitWidth> 1327 </field> 1328 </fields> 1329 </register> 1330 <register> 1331 <name>RTCTRIM</name> 1332 <description>RTC Trim Register.</description> 1333 <addressOffset>0x1C</addressOffset> 1334 <fields> 1335 <field> 1336 <name>TRIM_X1</name> 1337 <description>RTC Trim X1</description> 1338 <bitOffset>0</bitOffset> 1339 <bitWidth>5</bitWidth> 1340 </field> 1341 <field> 1342 <name>TRIM_X2</name> 1343 <description>RTC TRIM X2</description> 1344 <bitOffset>8</bitOffset> 1345 <bitWidth>5</bitWidth> 1346 </field> 1347 </fields> 1348 </register> 1349 <register> 1350 <name>LDOCTRL</name> 1351 <description>LDO Control Register.</description> 1352 <addressOffset>0x60</addressOffset> 1353 <fields> 1354 <field> 1355 <name>0P9V_EN</name> 1356 <description>LDO 0.9V Enable.</description> 1357 <bitOffset>0</bitOffset> 1358 <bitWidth>1</bitWidth> 1359 </field> 1360 </fields> 1361 </register> 1362 <register> 1363 <name>PWRMONST</name> 1364 <description>Power Monitor Statuses Register.</description> 1365 <addressOffset>0x64</addressOffset> 1366 <fields> 1367 <field> 1368 <name>PORZ_VLOSS</name> 1369 <description>Sticky bit indicating power on status of core power domains.</description> 1370 <bitOffset>0</bitOffset> 1371 <bitWidth>1</bitWidth> 1372 </field> 1373 <field> 1374 <name>PORZ_VBAT</name> 1375 <description>Sticky bit indicating power on status of the battery.</description> 1376 <bitOffset>1</bitOffset> 1377 <bitWidth>1</bitWidth> 1378 </field> 1379 <field> 1380 <name>PORZ_VRTC</name> 1381 <description>Sticky bit indicating power on status of the RTC.</description> 1382 <bitOffset>2</bitOffset> 1383 <bitWidth>1</bitWidth> 1384 </field> 1385 <field> 1386 <name>PORZ_VDDC</name> 1387 <description>Sticky bit indicating power on status of VCORE.</description> 1388 <bitOffset>5</bitOffset> 1389 <bitWidth>1</bitWidth> 1390 </field> 1391 <field> 1392 <name>PORZ_VDDA</name> 1393 <description>Sticky bit indicating power on status of VDDA.</description> 1394 <bitOffset>6</bitOffset> 1395 <bitWidth>1</bitWidth> 1396 </field> 1397 <field> 1398 <name>PORZ_VDDB</name> 1399 <description>Sticky bit indicating power on status of VDDB.</description> 1400 <bitOffset>7</bitOffset> 1401 <bitWidth>1</bitWidth> 1402 </field> 1403 <field> 1404 <name>RSTZ_VDDC</name> 1405 <description>Sticky bit indicating reset condition on VCORE.</description> 1406 <bitOffset>9</bitOffset> 1407 <bitWidth>1</bitWidth> 1408 </field> 1409 <field> 1410 <name>RSTZ_VDDA</name> 1411 <description>Sticky bit indicating reset condition on VDDA.</description> 1412 <bitOffset>10</bitOffset> 1413 <bitWidth>1</bitWidth> 1414 </field> 1415 <field> 1416 <name>RSTZ_VDDB</name> 1417 <description>Sticky bit indicating reset condition on VDDB.</description> 1418 <bitOffset>11</bitOffset> 1419 <bitWidth>1</bitWidth> 1420 </field> 1421 <field> 1422 <name>RSTZ_VDDIO</name> 1423 <description>Sticky bit indicating reset condition on VDDIO.</description> 1424 <bitOffset>12</bitOffset> 1425 <bitWidth>1</bitWidth> 1426 </field> 1427 <field> 1428 <name>RSTZ_VDDIOH</name> 1429 <description>Sticky bit indicating reset condition on VDDIOH.</description> 1430 <bitOffset>13</bitOffset> 1431 <bitWidth>1</bitWidth> 1432 </field> 1433 <field> 1434 <name>RSTZ_VRTC</name> 1435 <description>Sticky bit indicating reset condition on RTC.</description> 1436 <bitOffset>14</bitOffset> 1437 <bitWidth>1</bitWidth> 1438 </field> 1439 <field> 1440 <name>RSTZ_LDO_0P9V</name> 1441 <description>Non-sticky bit indicating reset condition on 0.9V USB supply.</description> 1442 <bitOffset>16</bitOffset> 1443 <bitWidth>1</bitWidth> 1444 </field> 1445 <field> 1446 <name>RSTZ_VDDCA</name> 1447 <description>Non-sticky bit indicating reset condition on VCORE in Analog supply.</description> 1448 <bitOffset>17</bitOffset> 1449 <bitWidth>1</bitWidth> 1450 </field> 1451 <field> 1452 <name>RSTZ_VCOREHV</name> 1453 <description>Non-sticky bit indicating high voltage reset condition on VCORE supply.</description> 1454 <bitOffset>18</bitOffset> 1455 <bitWidth>1</bitWidth> 1456 </field> 1457 <field> 1458 <name>RSTZ_VDDIOHV</name> 1459 <description>Non-sticky bit indicating high voltage reset condition on VDDIO supply.</description> 1460 <bitOffset>19</bitOffset> 1461 <bitWidth>1</bitWidth> 1462 </field> 1463 <field> 1464 <name>RSTZ_VDDIOHHV</name> 1465 <description>Non-sticky bit indicating high voltage reset condition on VDDIOH supply.</description> 1466 <bitOffset>20</bitOffset> 1467 <bitWidth>1</bitWidth> 1468 </field> 1469 </fields> 1470 </register> 1471 </registers> 1472 </peripheral> 1473<!--MCR Misc Control.--> 1474 <peripheral> 1475 <name>CTB</name> 1476 <description>The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security.</description> 1477 <baseAddress>0x40001000</baseAddress> 1478 <addressBlock> 1479 <offset>0x00</offset> 1480 <size>0x1000</size> 1481 <usage>registers</usage> 1482 </addressBlock> 1483 <interrupt> 1484 <name>Crypto_Engine</name> 1485 <description>Crypto Engine interrupt.</description> 1486 <value>27</value> 1487 </interrupt> 1488 <registers> 1489 <register> 1490 <name>CTRL</name> 1491 <description>Crypto Control Register.</description> 1492 <addressOffset>0x00</addressOffset> 1493 <resetValue>0xC0000000</resetValue> 1494 <fields> 1495 <field> 1496 <name>RST</name> 1497 <description>Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle.</description> 1498 <bitOffset>0</bitOffset> 1499 <bitWidth>1</bitWidth> 1500 <enumeratedValues> 1501 <name>reset_write</name> 1502 <usage>write</usage> 1503 <enumeratedValue> 1504 <name>reset</name> 1505 <description>Starts reset operation.</description> 1506 <value>1</value> 1507 </enumeratedValue> 1508 </enumeratedValues> 1509 <enumeratedValues> 1510 <name>reset_read</name> 1511 <usage>read</usage> 1512 <enumeratedValue> 1513 <name>reset_done</name> 1514 <description>Reset complete.</description> 1515 <value>0</value> 1516 </enumeratedValue> 1517 <enumeratedValue> 1518 <name>busy</name> 1519 <description>Reset in progress.</description> 1520 <value>1</value> 1521 </enumeratedValue> 1522 </enumeratedValues> 1523 </field> 1524 <field> 1525 <name>INTR</name> 1526 <description>Interrupt Enable. Generates an interrupt when done or error set.</description> 1527 <bitOffset>1</bitOffset> 1528 <bitWidth>1</bitWidth> 1529 <enumeratedValues> 1530 <enumeratedValue> 1531 <name>dis</name> 1532 <description>Disable</description> 1533 <value>0</value> 1534 </enumeratedValue> 1535 <enumeratedValue> 1536 <name>en</name> 1537 <description>Enable</description> 1538 <value>1</value> 1539 </enumeratedValue> 1540 </enumeratedValues> 1541 </field> 1542 <field> 1543 <name>SRC</name> 1544 <description>Source Select. This bit selects the hash function and CRC generator input source.</description> 1545 <bitOffset>2</bitOffset> 1546 <bitWidth>1</bitWidth> 1547 <enumeratedValues> 1548 <enumeratedValue> 1549 <name>inputFIFO</name> 1550 <description>Input FIFO</description> 1551 <value>0</value> 1552 </enumeratedValue> 1553 <enumeratedValue> 1554 <name>outputFIFO</name> 1555 <description>Output FIFO</description> 1556 <value>1</value> 1557 </enumeratedValue> 1558 </enumeratedValues> 1559 </field> 1560 <field derivedFrom="INTR"> 1561 <name>BSO</name> 1562 <description>Byte Swap Output. Note. No byte swap will occur if there is not a full word.</description> 1563 <bitOffset>4</bitOffset> 1564 <bitWidth>1</bitWidth> 1565 </field> 1566 <field derivedFrom="INTR"> 1567 <name>BSI</name> 1568 <description>Byte Swap Input. Note. No byte swap will occur if there is not a full word.</description> 1569 <bitOffset>5</bitOffset> 1570 <bitWidth>1</bitWidth> 1571 </field> 1572 <field derivedFrom="INTR"> 1573 <name>WAIT_EN</name> 1574 <description>Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready.</description> 1575 <bitOffset>6</bitOffset> 1576 <bitWidth>1</bitWidth> 1577 </field> 1578 <field> 1579 <name>WAIT_POL</name> 1580 <description>Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state.</description> 1581 <bitOffset>7</bitOffset> 1582 <bitWidth>1</bitWidth> 1583 <enumeratedValues> 1584 <enumeratedValue> 1585 <name>activeLo</name> 1586 <description>Active Low.</description> 1587 <value>0</value> 1588 </enumeratedValue> 1589 <enumeratedValue> 1590 <name>activeHi</name> 1591 <description>Active High.</description> 1592 <value>1</value> 1593 </enumeratedValue> 1594 </enumeratedValues> 1595 </field> 1596 <field> 1597 <name>WRSRC</name> 1598 <description>Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled.</description> 1599 <bitOffset>8</bitOffset> 1600 <bitWidth>2</bitWidth> 1601 <enumeratedValues> 1602 <enumeratedValue> 1603 <name>none</name> 1604 <description>None.</description> 1605 <value>0</value> 1606 </enumeratedValue> 1607 <enumeratedValue> 1608 <name>cipherOutput</name> 1609 <description>Cipher Output.</description> 1610 <value>1</value> 1611 </enumeratedValue> 1612 <enumeratedValue> 1613 <name>readFIFO</name> 1614 <description>Read FIFO.</description> 1615 <value>2</value> 1616 </enumeratedValue> 1617 </enumeratedValues> 1618 </field> 1619 <field> 1620 <name>RDSRC</name> 1621 <description>Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator.</description> 1622 <bitOffset>10</bitOffset> 1623 <bitWidth>2</bitWidth> 1624 <enumeratedValues> 1625 <enumeratedValue> 1626 <name>dmaDisabled</name> 1627 <description>DMA Disable.</description> 1628 <value>0</value> 1629 </enumeratedValue> 1630 <enumeratedValue> 1631 <name>dmaOrApb</name> 1632 <description>DMA Or APB.</description> 1633 <value>1</value> 1634 </enumeratedValue> 1635 <enumeratedValue> 1636 <name>rng</name> 1637 <description>RNG.</description> 1638 <value>2</value> 1639 </enumeratedValue> 1640 </enumeratedValues> 1641 </field> 1642 <field> 1643 <name>FLAG_MODE</name> 1644 <description>Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs.</description> 1645 <bitOffset>14</bitOffset> 1646 <bitWidth>1</bitWidth> 1647 <enumeratedValues> 1648 <enumeratedValue> 1649 <name>unres_wr</name> 1650 <description>Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags.</description> 1651 <value>0</value> 1652 </enumeratedValue> 1653 <enumeratedValue> 1654 <name>res_wr</name> 1655 <description>Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect.</description> 1656 <value>1</value> 1657 </enumeratedValue> 1658 </enumeratedValues> 1659 </field> 1660 <field> 1661 <name>DMADNEMSK</name> 1662 <description>DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA.</description> 1663 <bitOffset>15</bitOffset> 1664 <bitWidth>1</bitWidth> 1665 <enumeratedValues> 1666 <enumeratedValue> 1667 <name>not_used</name> 1668 <description>DMA_DONE not used in setting CRYPTO_CTRL.DONE bit.</description> 1669 <value>0</value> 1670 </enumeratedValue> 1671 <enumeratedValue> 1672 <name>used</name> 1673 <description>DMA_DONE used in setting CRYPTO_CTRL.DONE bit.</description> 1674 <value>1</value> 1675 </enumeratedValue> 1676 </enumeratedValues> 1677 </field> 1678 <field> 1679 <name>DMA_DONE</name> 1680 <description>DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation.</description> 1681 <bitOffset>24</bitOffset> 1682 <bitWidth>1</bitWidth> 1683 <enumeratedValues> 1684 <enumeratedValue> 1685 <name>notDone</name> 1686 <description>Not Done.</description> 1687 <value>0</value> 1688 </enumeratedValue> 1689 <enumeratedValue> 1690 <name>done</name> 1691 <description>Done.</description> 1692 <value>1</value> 1693 </enumeratedValue> 1694 </enumeratedValues> 1695 </field> 1696 <field derivedFrom="DMA_DONE"> 1697 <name>GLS_DONE</name> 1698 <description>Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator.</description> 1699 <bitOffset>25</bitOffset> 1700 <bitWidth>1</bitWidth> 1701 </field> 1702 <field derivedFrom="DMA_DONE"> 1703 <name>HSH_DONE</name> 1704 <description>Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation.</description> 1705 <bitOffset>26</bitOffset> 1706 <bitWidth>1</bitWidth> 1707 </field> 1708 <field derivedFrom="DMA_DONE"> 1709 <name>CPH_DONE</name> 1710 <description>Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation.</description> 1711 <bitOffset>27</bitOffset> 1712 <bitWidth>1</bitWidth> 1713 </field> 1714 <field> 1715 <name>ERR</name> 1716 <description>AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block.</description> 1717 <bitOffset>29</bitOffset> 1718 <bitWidth>1</bitWidth> 1719 <access>read-only</access> 1720 <enumeratedValues> 1721 <enumeratedValue> 1722 <name>noError</name> 1723 <description>No Error.</description> 1724 <value>0</value> 1725 </enumeratedValue> 1726 <enumeratedValue> 1727 <name>error</name> 1728 <description>Error.</description> 1729 <value>1</value> 1730 </enumeratedValue> 1731 </enumeratedValues> 1732 </field> 1733 <field> 1734 <name>RDY</name> 1735 <description>Ready. Crypto block ready for more data.</description> 1736 <bitOffset>30</bitOffset> 1737 <bitWidth>1</bitWidth> 1738 <access>read-only</access> 1739 <enumeratedValues> 1740 <enumeratedValue> 1741 <name>busy</name> 1742 <description>Busy.</description> 1743 <value>0</value> 1744 </enumeratedValue> 1745 <enumeratedValue> 1746 <name>ready</name> 1747 <description>Ready.</description> 1748 <value>1</value> 1749 </enumeratedValue> 1750 </enumeratedValues> 1751 </field> 1752 <field derivedFrom="DMA_DONE"> 1753 <name>DONE</name> 1754 <description>Done. One or more cryptographic calculations complete (logical OR of done flags).</description> 1755 <bitOffset>31</bitOffset> 1756 <bitWidth>1</bitWidth> 1757 <access>read-only</access> 1758 </field> 1759 </fields> 1760 </register> 1761 <register> 1762 <name>CIPHER_CTRL</name> 1763 <description>Cipher Control Register.</description> 1764 <addressOffset>0x04</addressOffset> 1765 <fields> 1766 <field> 1767 <name>ENC</name> 1768 <description>Encrypt. Select encryption or decryption of input data.</description> 1769 <bitOffset>0</bitOffset> 1770 <bitWidth>1</bitWidth> 1771 <enumeratedValues> 1772 <enumeratedValue> 1773 <name>encrypt</name> 1774 <description>Encrypt.</description> 1775 <value>0</value> 1776 </enumeratedValue> 1777 <enumeratedValue> 1778 <name>decrypt</name> 1779 <description>Decrypt.</description> 1780 <value>1</value> 1781 </enumeratedValue> 1782 </enumeratedValues> 1783 </field> 1784 <field> 1785 <name>KEY</name> 1786 <description>Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag.</description> 1787 <bitOffset>1</bitOffset> 1788 <bitWidth>1</bitWidth> 1789 <enumeratedValues> 1790 <enumeratedValue> 1791 <name>complete</name> 1792 <description>No operation/complete.</description> 1793 <value>0</value> 1794 </enumeratedValue> 1795 <enumeratedValue> 1796 <name>start</name> 1797 <description>Start operation.</description> 1798 <value>1</value> 1799 </enumeratedValue> 1800 </enumeratedValues> 1801 </field> 1802 <field> 1803 <name>SRC</name> 1804 <description>Source of Random key.</description> 1805 <bitOffset>2</bitOffset> 1806 <bitWidth>2</bitWidth> 1807 <enumeratedValues> 1808 <enumeratedValue> 1809 <name>cipherKey</name> 1810 <description>User cipher key (0x4000_1060).</description> 1811 <value>0</value> 1812 </enumeratedValue> 1813 <enumeratedValue> 1814 <name>regFile</name> 1815 <description>Key from battery-backed register file (0x4000_5000 to 0x4000_501F).</description> 1816 <value>2</value> 1817 </enumeratedValue> 1818 <enumeratedValue> 1819 <name>qspiKey_regFile</name> 1820 <description>Key from battery-backed register file (0x4000_5020 to 0x4000_502F).</description> 1821 <value>3</value> 1822 </enumeratedValue> 1823 </enumeratedValues> 1824 </field> 1825 <field> 1826 <name>CIPHER</name> 1827 <description>Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation.</description> 1828 <bitOffset>4</bitOffset> 1829 <bitWidth>3</bitWidth> 1830 <enumeratedValues> 1831 <enumeratedValue> 1832 <name>dis</name> 1833 <description>Disabled.</description> 1834 <value>0</value> 1835 </enumeratedValue> 1836 <enumeratedValue> 1837 <name>aes128</name> 1838 <description>AES 128.</description> 1839 <value>1</value> 1840 </enumeratedValue> 1841 <enumeratedValue> 1842 <name>aes192</name> 1843 <description>AES 192.</description> 1844 <value>2</value> 1845 </enumeratedValue> 1846 <enumeratedValue> 1847 <name>aes256</name> 1848 <description>AES 256.</description> 1849 <value>3</value> 1850 </enumeratedValue> 1851 <enumeratedValue> 1852 <name>des</name> 1853 <description>DES.</description> 1854 <value>4</value> 1855 </enumeratedValue> 1856 <enumeratedValue> 1857 <name>tdes</name> 1858 <description>Triple DES.</description> 1859 <value>5</value> 1860 </enumeratedValue> 1861 </enumeratedValues> 1862 </field> 1863 <field> 1864 <name>MODE</name> 1865 <description>Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes.</description> 1866 <bitOffset>8</bitOffset> 1867 <bitWidth>3</bitWidth> 1868 <enumeratedValues> 1869 <enumeratedValue> 1870 <name>ECB</name> 1871 <description>ECB Mode.</description> 1872 <value>0</value> 1873 </enumeratedValue> 1874 <enumeratedValue> 1875 <name>CBC</name> 1876 <description>CBC Mode.</description> 1877 <value>1</value> 1878 </enumeratedValue> 1879 <enumeratedValue> 1880 <name>CFB</name> 1881 <description>CFB (AES only).</description> 1882 <value>2</value> 1883 </enumeratedValue> 1884 <enumeratedValue> 1885 <name>OFB</name> 1886 <description>OFB (AES only).</description> 1887 <value>3</value> 1888 </enumeratedValue> 1889 <enumeratedValue> 1890 <name>CTR</name> 1891 <description>CTR (AES only).</description> 1892 <value>4</value> 1893 </enumeratedValue> 1894 </enumeratedValues> 1895 </field> 1896 <field> 1897 <name>HVC</name> 1898 <description>H Vector Computation.</description> 1899 <bitOffset>11</bitOffset> 1900 <bitWidth>1</bitWidth> 1901 <access>read-only</access> 1902 </field> 1903 <field> 1904 <name>DTYPE</name> 1905 <description>GCM/CCM data type.</description> 1906 <bitOffset>12</bitOffset> 1907 <bitWidth>1</bitWidth> 1908 <access>read-only</access> 1909 </field> 1910 <field> 1911 <name>CCMM</name> 1912 <description>CCM M Parameter.</description> 1913 <bitOffset>13</bitOffset> 1914 <bitWidth>3</bitWidth> 1915 <access>read-only</access> 1916 </field> 1917 <field> 1918 <name>CCML</name> 1919 <description>CCM L Parameter.</description> 1920 <bitOffset>16</bitOffset> 1921 <bitWidth>3</bitWidth> 1922 <access>read-only</access> 1923 </field> 1924 </fields> 1925 </register> 1926 <register> 1927 <name>HASH_CTRL</name> 1928 <description>HASH Control Register.</description> 1929 <addressOffset>0x08</addressOffset> 1930 <fields> 1931 <field> 1932 <name>INIT</name> 1933 <description>Initialize. Initializes hash registers with standard constants.</description> 1934 <bitOffset>0</bitOffset> 1935 <bitWidth>1</bitWidth> 1936 <enumeratedValues> 1937 <enumeratedValue> 1938 <name>nop</name> 1939 <description>No operation/complete.</description> 1940 <value>0</value> 1941 </enumeratedValue> 1942 <enumeratedValue> 1943 <name>start</name> 1944 <description>Start operation.</description> 1945 <value>1</value> 1946 </enumeratedValue> 1947 </enumeratedValues> 1948 </field> 1949 <field> 1950 <name>XOR</name> 1951 <description>XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad.</description> 1952 <bitOffset>1</bitOffset> 1953 <bitWidth>1</bitWidth> 1954 <enumeratedValues> 1955 <enumeratedValue> 1956 <name>dis</name> 1957 <description>Disable.</description> 1958 <value>0</value> 1959 </enumeratedValue> 1960 <enumeratedValue> 1961 <name>en</name> 1962 <description>Enable.</description> 1963 <value>1</value> 1964 </enumeratedValue> 1965 </enumeratedValues> 1966 </field> 1967 <field> 1968 <name>HASH</name> 1969 <description>Hash function selection.</description> 1970 <bitOffset>2</bitOffset> 1971 <bitWidth>3</bitWidth> 1972 <enumeratedValues> 1973 <enumeratedValue> 1974 <name>dis</name> 1975 <description>Disabled.</description> 1976 <value>0</value> 1977 </enumeratedValue> 1978 <enumeratedValue> 1979 <name>sha1</name> 1980 <description>SHA-1.</description> 1981 <value>1</value> 1982 </enumeratedValue> 1983 <enumeratedValue> 1984 <name>sha224</name> 1985 <description>SHA 224.</description> 1986 <value>2</value> 1987 </enumeratedValue> 1988 <enumeratedValue> 1989 <name>sha256</name> 1990 <description>SHA 256.</description> 1991 <value>3</value> 1992 </enumeratedValue> 1993 <enumeratedValue> 1994 <name>sha384</name> 1995 <description>SHA 384.</description> 1996 <value>4</value> 1997 </enumeratedValue> 1998 <enumeratedValue> 1999 <name>sha512</name> 2000 <description>SHA 512.</description> 2001 <value>5</value> 2002 </enumeratedValue> 2003 </enumeratedValues> 2004 </field> 2005 <field> 2006 <name>LAST</name> 2007 <description>Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash.</description> 2008 <bitOffset>5</bitOffset> 2009 <bitWidth>1</bitWidth> 2010 <enumeratedValues> 2011 <enumeratedValue> 2012 <name>noEffect</name> 2013 <description>No Effect.</description> 2014 <value>0</value> 2015 </enumeratedValue> 2016 <enumeratedValue> 2017 <name>lastMsgData</name> 2018 <description>Last Message Data.</description> 2019 <value>1</value> 2020 </enumeratedValue> 2021 </enumeratedValues> 2022 </field> 2023 </fields> 2024 </register> 2025 <register> 2026 <name>CRC_CTRL</name> 2027 <description>CRC Control Register.</description> 2028 <addressOffset>0x0C</addressOffset> 2029 <fields> 2030 <field> 2031 <name>CRC</name> 2032 <description>Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled.</description> 2033 <bitOffset>0</bitOffset> 2034 <bitWidth>1</bitWidth> 2035 <enumeratedValues> 2036 <enumeratedValue> 2037 <name>dis</name> 2038 <description>Disable.</description> 2039 <value>0</value> 2040 </enumeratedValue> 2041 <enumeratedValue> 2042 <name>en</name> 2043 <description>Enable.</description> 2044 <value>1</value> 2045 </enumeratedValue> 2046 </enumeratedValues> 2047 </field> 2048 <field> 2049 <name>MSB</name> 2050 <description>MSB select. This bit selects the order of calculating CRC on data.</description> 2051 <bitOffset>1</bitOffset> 2052 <bitWidth>1</bitWidth> 2053 <enumeratedValues> 2054 <enumeratedValue> 2055 <name>lsbFirst</name> 2056 <description>LSB First.</description> 2057 <value>0</value> 2058 </enumeratedValue> 2059 <enumeratedValue> 2060 <name>msbFirst</name> 2061 <description>MSB First.</description> 2062 <value>1</value> 2063 </enumeratedValue> 2064 </enumeratedValues> 2065 </field> 2066 <field derivedFrom="CRC"> 2067 <name>PRNG</name> 2068 <description>Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle.</description> 2069 <bitOffset>2</bitOffset> 2070 <bitWidth>1</bitWidth> 2071 </field> 2072 <field derivedFrom="CRC"> 2073 <name>ENT</name> 2074 <description>Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source.</description> 2075 <bitOffset>3</bitOffset> 2076 <bitWidth>1</bitWidth> 2077 </field> 2078 <field derivedFrom="CRC"> 2079 <name>HAM</name> 2080 <description>Hamming Code Enable. Enable hamming code calculation.</description> 2081 <bitOffset>4</bitOffset> 2082 <bitWidth>1</bitWidth> 2083 </field> 2084 <field> 2085 <name>HRST</name> 2086 <description>Hamming Reset. Reset Hamming code ECC generator for next block.</description> 2087 <bitOffset>5</bitOffset> 2088 <bitWidth>1</bitWidth> 2089 <access>write-only</access> 2090 <enumeratedValues> 2091 <usage>write</usage> 2092 <enumeratedValue> 2093 <name>reset</name> 2094 <description>Starts reset operation.</description> 2095 <value>1</value> 2096 </enumeratedValue> 2097 </enumeratedValues> 2098 </field> 2099 </fields> 2100 </register> 2101 <register> 2102 <name>DMA_SRC</name> 2103 <description>Crypto DMA Source Address.</description> 2104 <addressOffset>0x10</addressOffset> 2105 <fields> 2106 <field> 2107 <name>ADDR</name> 2108 <description>DMA Source Address.</description> 2109 <bitOffset>0</bitOffset> 2110 <bitWidth>32</bitWidth> 2111 </field> 2112 </fields> 2113 </register> 2114 <register> 2115 <name>DMA_DEST</name> 2116 <description>Crypto DMA Destination Address.</description> 2117 <addressOffset>0x14</addressOffset> 2118 <fields> 2119 <field> 2120 <name>ADDR</name> 2121 <description>DMA Destination Address.</description> 2122 <bitOffset>0</bitOffset> 2123 <bitWidth>32</bitWidth> 2124 </field> 2125 </fields> 2126 </register> 2127 <register> 2128 <name>DMA_CNT</name> 2129 <description>Crypto DMA Byte Count.</description> 2130 <addressOffset>0x18</addressOffset> 2131 <fields> 2132 <field> 2133 <name>ADDR</name> 2134 <description>DMA Byte Address.</description> 2135 <bitOffset>0</bitOffset> 2136 <bitWidth>32</bitWidth> 2137 </field> 2138 </fields> 2139 </register> 2140 <register> 2141 <name>MAA_CTRL</name> 2142 <description>MAA Control Register.</description> 2143 <addressOffset>0x1C</addressOffset> 2144 </register> 2145 <register> 2146 <dim>4</dim> 2147 <dimIncrement>4</dimIncrement> 2148 <name>DIN[%s]</name> 2149 <description>Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.</description> 2150 <addressOffset>0x20</addressOffset> 2151 <access>write-only</access> 2152 <fields> 2153 <field> 2154 <name>DATA</name> 2155 <description>Crypto Data Input. Input can be written to this register instead of using DMA.</description> 2156 <bitOffset>0</bitOffset> 2157 <bitWidth>32</bitWidth> 2158 </field> 2159 </fields> 2160 </register> 2161 <register> 2162 <dim>4</dim> 2163 <dimIncrement>4</dimIncrement> 2164 <name>DOUT[%s]</name> 2165 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.</description> 2166 <addressOffset>0x30</addressOffset> 2167 <access>read-only</access> 2168 <fields> 2169 <field> 2170 <name>DATA</name> 2171 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.</description> 2172 <bitOffset>0</bitOffset> 2173 <bitWidth>32</bitWidth> 2174 </field> 2175 </fields> 2176 </register> 2177 <register> 2178 <name>CRC_POLY</name> 2179 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 2180 <addressOffset>0x40</addressOffset> 2181 <resetValue>0xEDB88320</resetValue> 2182 <fields> 2183 <field> 2184 <name>POLY</name> 2185 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 2186 <bitOffset>0</bitOffset> 2187 <bitWidth>32</bitWidth> 2188 </field> 2189 </fields> 2190 </register> 2191 <register> 2192 <name>CRC_VAL</name> 2193 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit.</description> 2194 <addressOffset>0x44</addressOffset> 2195 <resetValue>0xFFFFFFFF</resetValue> 2196 <fields> 2197 <field> 2198 <name>VAL</name> 2199 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit.</description> 2200 <bitOffset>0</bitOffset> 2201 <bitWidth>32</bitWidth> 2202 </field> 2203 </fields> 2204 </register> 2205 <register> 2206 <name>CRC_PRNG</name> 2207 <description>CRC PRNG Register.</description> 2208 <addressOffset>0x48</addressOffset> 2209 <fields> 2210 <field> 2211 <name>PRNG</name> 2212 <description>PRNG</description> 2213 <bitOffset>0</bitOffset> 2214 <bitWidth>32</bitWidth> 2215 </field> 2216 </fields> 2217 </register> 2218 <register> 2219 <name>HAM_ECC</name> 2220 <description>Hamming ECC Register.</description> 2221 <addressOffset>0x4C</addressOffset> 2222 <fields> 2223 <field> 2224 <name>ECC</name> 2225 <description>Hamming ECC Value. These bits are the even parity of their corresponding bit groups.</description> 2226 <bitOffset>0</bitOffset> 2227 <bitWidth>16</bitWidth> 2228 </field> 2229 <field> 2230 <name>PAR</name> 2231 <description>Parity. This is the parity of the entire array.</description> 2232 <bitOffset>16</bitOffset> 2233 <bitWidth>1</bitWidth> 2234 <enumeratedValues> 2235 <enumeratedValue> 2236 <name>even</name> 2237 <description>Even.</description> 2238 <value>0</value> 2239 </enumeratedValue> 2240 <enumeratedValue> 2241 <name>odd</name> 2242 <description>Odd.</description> 2243 <value>1</value> 2244 </enumeratedValue> 2245 </enumeratedValues> 2246 </field> 2247 </fields> 2248 </register> 2249 <register> 2250 <dim>4</dim> 2251 <dimIncrement>4</dimIncrement> 2252 <name>CIPHER_INIT[%s]</name> 2253 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 2254 <addressOffset>0x50</addressOffset> 2255 <fields> 2256 <field> 2257 <name>IVEC</name> 2258 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 2259 <bitOffset>0</bitOffset> 2260 <bitWidth>32</bitWidth> 2261 </field> 2262 </fields> 2263 </register> 2264 <register> 2265 <dim>8</dim> 2266 <dimIncrement>4</dimIncrement> 2267 <name>CIPHER_KEY[%s]</name> 2268 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.</description> 2269 <addressOffset>0x60</addressOffset> 2270 <access>write-only</access> 2271 <fields> 2272 <field> 2273 <name>KEY</name> 2274 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.</description> 2275 <bitOffset>0</bitOffset> 2276 <bitWidth>32</bitWidth> 2277 </field> 2278 </fields> 2279 </register> 2280 <register> 2281 <dim>16</dim> 2282 <dimIncrement>4</dimIncrement> 2283 <name>HASH_DIGEST[%s]</name> 2284 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 2285 <addressOffset>0x80</addressOffset> 2286 <fields> 2287 <field> 2288 <name>HASH</name> 2289 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 2290 <bitOffset>0</bitOffset> 2291 <bitWidth>32</bitWidth> 2292 </field> 2293 </fields> 2294 </register> 2295 <register> 2296 <dim>4</dim> 2297 <dimIncrement>4</dimIncrement> 2298 <name>HASH_MSG_SZ[%s]</name> 2299 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 2300 <addressOffset>0xC0</addressOffset> 2301 <fields> 2302 <field> 2303 <name>MSGSZ</name> 2304 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 2305 <bitOffset>0</bitOffset> 2306 <bitWidth>32</bitWidth> 2307 </field> 2308 </fields> 2309 </register> 2310 <register> 2311 <dim>2</dim> 2312 <dimIncrement>4</dimIncrement> 2313 <name>AAD_LENGTH[%s]</name> 2314 <description>AAD Length Registers.</description> 2315 <addressOffset>0xD0</addressOffset> 2316 <resetValue>0x0</resetValue> 2317 <fields> 2318 <field> 2319 <name>LENGTH</name> 2320 <description>AAD length in bytes for AES GCM and CCM operations.</description> 2321 <bitOffset>0</bitOffset> 2322 <bitWidth>32</bitWidth> 2323 </field> 2324 </fields> 2325 </register> 2326 <register> 2327 <dim>2</dim> 2328 <dimIncrement>4</dimIncrement> 2329 <name>PLD_LENGTH[%s]</name> 2330 <description>PLD Length Registers.</description> 2331 <addressOffset>0xD8</addressOffset> 2332 <resetValue>0x0</resetValue> 2333 <fields> 2334 <field> 2335 <name>LENGTH</name> 2336 <description>PLD length in bytes for AES GCM and CCM operations.</description> 2337 <bitOffset>0</bitOffset> 2338 <bitWidth>32</bitWidth> 2339 </field> 2340 </fields> 2341 </register> 2342 <register> 2343 <dim>4</dim> 2344 <dimIncrement>4</dimIncrement> 2345 <name>TAGMIC[%s]</name> 2346 <description>TAG/MIC Registers.</description> 2347 <addressOffset>0xE0</addressOffset> 2348 <fields> 2349 <field> 2350 <name>LENGTH</name> 2351 <description>TAG/MIC output for AES GCM and CCM operations.</description> 2352 <bitOffset>0</bitOffset> 2353 <bitWidth>32</bitWidth> 2354 </field> 2355 </fields> 2356 </register> 2357 <register> 2358 <name>MAA_MAWS</name> 2359 <description>MAA Word Size Register.</description> 2360 <addressOffset>0xF0</addressOffset> 2361 <resetValue>0x0</resetValue> 2362 <fields> 2363 <field> 2364 <name>SIZE</name> 2365 <description>MAA Word Size.</description> 2366 <bitOffset>0</bitOffset> 2367 <bitWidth>32</bitWidth> 2368 </field> 2369 </fields> 2370 </register> 2371 <register> 2372 <name>SCA_CTRL0</name> 2373 <description>SCA Control 0 Register.</description> 2374 <addressOffset>0x700</addressOffset> 2375 <fields> 2376 <field> 2377 <name>STC</name> 2378 <description>Start Calculation.</description> 2379 <bitOffset>0</bitOffset> 2380 <bitWidth>1</bitWidth> 2381 </field> 2382 <field> 2383 <name>SCAIE</name> 2384 <description>SCA Interrupt Enable.</description> 2385 <bitOffset>1</bitOffset> 2386 <bitWidth>1</bitWidth> 2387 <enumeratedValues> 2388 <enumeratedValue> 2389 <name>disable</name> 2390 <description>Disable</description> 2391 <value>0</value> 2392 </enumeratedValue> 2393 <enumeratedValue> 2394 <name>enable</name> 2395 <description>Enable</description> 2396 <value>1</value> 2397 </enumeratedValue> 2398 </enumeratedValues> 2399 </field> 2400 <field> 2401 <name>ABORT</name> 2402 <description>Abort Operation.</description> 2403 <bitOffset>2</bitOffset> 2404 <bitWidth>1</bitWidth> 2405 </field> 2406 <field> 2407 <name>AFFJAC</name> 2408 <description>Select Affine or Jacobi Coordinates.</description> 2409 <bitOffset>3</bitOffset> 2410 <bitWidth>1</bitWidth> 2411 </field> 2412 <field> 2413 <name>ERMEM</name> 2414 <description>Erase Cryptographic Memory.</description> 2415 <bitOffset>4</bitOffset> 2416 <bitWidth>1</bitWidth> 2417 </field> 2418 <field> 2419 <name>MANPARAM</name> 2420 <description>ECC Parameter Source.</description> 2421 <bitOffset>5</bitOffset> 2422 <bitWidth>1</bitWidth> 2423 </field> 2424 <field> 2425 <name>HWKEY</name> 2426 <description>Hardware Key Select.</description> 2427 <bitOffset>6</bitOffset> 2428 <bitWidth>1</bitWidth> 2429 </field> 2430 <field> 2431 <name>OPCODE</name> 2432 <description>SCA Opcode.</description> 2433 <bitOffset>8</bitOffset> 2434 <bitWidth>5</bitWidth> 2435 </field> 2436 <field> 2437 <name>MODADDR</name> 2438 <description>MODULO Address Offset.</description> 2439 <bitOffset>16</bitOffset> 2440 <bitWidth>5</bitWidth> 2441 </field> 2442 <field> 2443 <name>ECCSIZE</name> 2444 <description>ECC Size.</description> 2445 <bitOffset>24</bitOffset> 2446 <bitWidth>2</bitWidth> 2447 </field> 2448 </fields> 2449 </register> 2450 <register> 2451 <name>SCA_CTRL1</name> 2452 <description>SCA Advanced Control Register.</description> 2453 <addressOffset>0x704</addressOffset> 2454 <fields> 2455 <field> 2456 <name>MAN</name> 2457 <description>SCA Mode.</description> 2458 <bitOffset>0</bitOffset> 2459 <bitWidth>1</bitWidth> 2460 <enumeratedValues> 2461 <enumeratedValue> 2462 <name>auto</name> 2463 <description>Auto Mode</description> 2464 <value>0</value> 2465 </enumeratedValue> 2466 <enumeratedValue> 2467 <name>manual</name> 2468 <description>Manual Mode</description> 2469 <value>1</value> 2470 </enumeratedValue> 2471 </enumeratedValues> 2472 </field> 2473 <field> 2474 <name>AUTOCARRY</name> 2475 <description>Automatically propagate the carry for the next operation.</description> 2476 <bitOffset>1</bitOffset> 2477 <bitWidth>1</bitWidth> 2478 </field> 2479 <field> 2480 <name>PLUSONE</name> 2481 <description>Enable Carry propagation for the next operation.</description> 2482 <bitOffset>2</bitOffset> 2483 <bitWidth>1</bitWidth> 2484 </field> 2485 <field> 2486 <name>RESSELECT</name> 2487 <description>ALU Selection.</description> 2488 <bitOffset>3</bitOffset> 2489 <bitWidth>2</bitWidth> 2490 </field> 2491 <field> 2492 <name>NRNG</name> 2493 <description>Enable NIST RNG.</description> 2494 <bitOffset>5</bitOffset> 2495 <bitWidth>1</bitWidth> 2496 </field> 2497 <field> 2498 <name>CARRYPOS</name> 2499 <description>To set Carry location.</description> 2500 <bitOffset>8</bitOffset> 2501 <bitWidth>10</bitWidth> 2502 </field> 2503 <field> 2504 <name>CM_EN</name> 2505 <description>Enable Countermeasure.</description> 2506 <bitOffset>20</bitOffset> 2507 <bitWidth>12</bitWidth> 2508 </field> 2509 </fields> 2510 </register> 2511 <register> 2512 <name>SCA_STAT</name> 2513 <description>SCA Status Register.</description> 2514 <addressOffset>0x708</addressOffset> 2515 <fields> 2516 <field> 2517 <name>BUSY</name> 2518 <description>SCA Busy.</description> 2519 <bitOffset>0</bitOffset> 2520 <bitWidth>1</bitWidth> 2521 </field> 2522 <field> 2523 <name>SCAIF</name> 2524 <description>SCA Interrupt Flag.</description> 2525 <bitOffset>1</bitOffset> 2526 <bitWidth>1</bitWidth> 2527 </field> 2528 <field> 2529 <name>PVF1</name> 2530 <description>Point 1 Verification Failed.</description> 2531 <bitOffset>2</bitOffset> 2532 <bitWidth>1</bitWidth> 2533 </field> 2534 <field> 2535 <name>PVF2</name> 2536 <description>Point 2 Verification Failed.</description> 2537 <bitOffset>3</bitOffset> 2538 <bitWidth>1</bitWidth> 2539 </field> 2540 <field> 2541 <name>FSMERR</name> 2542 <description>FSM Transition Error.</description> 2543 <bitOffset>4</bitOffset> 2544 <bitWidth>1</bitWidth> 2545 </field> 2546 <field> 2547 <name>COMPERR</name> 2548 <description>EC Computation Error.</description> 2549 <bitOffset>5</bitOffset> 2550 <bitWidth>1</bitWidth> 2551 </field> 2552 <field> 2553 <name>MEMERR</name> 2554 <description>SCA Memory Access Error.</description> 2555 <bitOffset>6</bitOffset> 2556 <bitWidth>1</bitWidth> 2557 </field> 2558 <field> 2559 <name>CARRY</name> 2560 <description>Carry on ongoing operation.</description> 2561 <bitOffset>8</bitOffset> 2562 <bitWidth>1</bitWidth> 2563 </field> 2564 <field> 2565 <name>GTE2I2</name> 2566 <description>Modulo 2x Result.</description> 2567 <bitOffset>9</bitOffset> 2568 <bitWidth>1</bitWidth> 2569 </field> 2570 <field> 2571 <name>ALUNEG1</name> 2572 <description>ALU 2 SubSign of the subtraction result for ALU_2.</description> 2573 <bitOffset>10</bitOffset> 2574 <bitWidth>1</bitWidth> 2575 </field> 2576 <field> 2577 <name>ALUNEG2</name> 2578 <description>ALU 2 SubSign of the subtraction result for ALU_2.</description> 2579 <bitOffset>11</bitOffset> 2580 <bitWidth>1</bitWidth> 2581 </field> 2582 </fields> 2583 </register> 2584 <register> 2585 <name>SCA_PPX_ADDR</name> 2586 <description>PPX Coordinate Data Pointer Register.</description> 2587 <addressOffset>0x70C</addressOffset> 2588 <resetValue>0x0</resetValue> 2589 <fields> 2590 <field> 2591 <name>ADDR</name> 2592 <description>Point P Coordinate Data Pointer.</description> 2593 <bitOffset>0</bitOffset> 2594 <bitWidth>32</bitWidth> 2595 </field> 2596 </fields> 2597 </register> 2598 <register> 2599 <name>SCA_PPY_ADDR</name> 2600 <description>PPY Coordinate Data Pointer Register.</description> 2601 <addressOffset>0x710</addressOffset> 2602 <resetValue>0x0</resetValue> 2603 <fields> 2604 <field> 2605 <name>ADDR</name> 2606 <description>Point P Coordinate Data Pointer.</description> 2607 <bitOffset>0</bitOffset> 2608 <bitWidth>32</bitWidth> 2609 </field> 2610 </fields> 2611 </register> 2612 <register> 2613 <name>SCA_PPZ_ADDR</name> 2614 <description>PPZ Coordinate Data Pointer Register.</description> 2615 <addressOffset>0x714</addressOffset> 2616 <resetValue>0x0</resetValue> 2617 <fields> 2618 <field> 2619 <name>ADDR</name> 2620 <description>Point P Coordinate Data Pointer.</description> 2621 <bitOffset>0</bitOffset> 2622 <bitWidth>32</bitWidth> 2623 </field> 2624 </fields> 2625 </register> 2626 <register> 2627 <name>SCA_PQX_ADDR</name> 2628 <description>PQX Coordinate Data Pointer Register.</description> 2629 <addressOffset>0x718</addressOffset> 2630 <resetValue>0x0</resetValue> 2631 <fields> 2632 <field> 2633 <name>ADDR</name> 2634 <description>Point Q Coordinate Data Pointer.</description> 2635 <bitOffset>0</bitOffset> 2636 <bitWidth>32</bitWidth> 2637 </field> 2638 </fields> 2639 </register> 2640 <register> 2641 <name>SCA_PQY_ADDR</name> 2642 <description>PQY Coordinate Data Pointer Register.</description> 2643 <addressOffset>0x71C</addressOffset> 2644 <resetValue>0x0</resetValue> 2645 <fields> 2646 <field> 2647 <name>ADDR</name> 2648 <description>Point Q Coordinate Data Pointer.</description> 2649 <bitOffset>0</bitOffset> 2650 <bitWidth>32</bitWidth> 2651 </field> 2652 </fields> 2653 </register> 2654 <register> 2655 <name>SCA_PQZ_ADDR</name> 2656 <description>PQZ Coordinate Data Pointer Register.</description> 2657 <addressOffset>0x720</addressOffset> 2658 <resetValue>0x0</resetValue> 2659 <fields> 2660 <field> 2661 <name>ADDR</name> 2662 <description>Point Q Coordinate Data Pointer.</description> 2663 <bitOffset>0</bitOffset> 2664 <bitWidth>32</bitWidth> 2665 </field> 2666 </fields> 2667 </register> 2668 <register> 2669 <name>SCA_RDSA_ADDR</name> 2670 <description>SCA RDSA Address Register.</description> 2671 <addressOffset>0x724</addressOffset> 2672 <resetValue>0x0</resetValue> 2673 <fields> 2674 <field> 2675 <name>ADDR</name> 2676 <description>The starting address of the R portion for R, S ECDSA signature.</description> 2677 <bitOffset>0</bitOffset> 2678 <bitWidth>32</bitWidth> 2679 </field> 2680 </fields> 2681 </register> 2682 <register> 2683 <name>SCA_RES_ADDR</name> 2684 <description>SCA Result Address Register.</description> 2685 <addressOffset>0x728</addressOffset> 2686 <resetValue>0x0</resetValue> 2687 <fields> 2688 <field> 2689 <name>ADDR</name> 2690 <description>Starting address of result storage.</description> 2691 <bitOffset>0</bitOffset> 2692 <bitWidth>32</bitWidth> 2693 </field> 2694 </fields> 2695 </register> 2696 <register> 2697 <name>SCA_OP_BUFF_ADDR</name> 2698 <description>SCA Operation Buffer Address Register.</description> 2699 <addressOffset>0x72C</addressOffset> 2700 <resetValue>0x0</resetValue> 2701 <fields> 2702 <field> 2703 <name>ADDR</name> 2704 <description>Starting address of operation buffer.</description> 2705 <bitOffset>0</bitOffset> 2706 <bitWidth>32</bitWidth> 2707 </field> 2708 </fields> 2709 </register> 2710 <register> 2711 <name>SCA_MODDATA</name> 2712 <description>SCA Modulo Data Input Register.</description> 2713 <addressOffset>0x730</addressOffset> 2714 <resetValue>0x0</resetValue> 2715 <fields> 2716 <field> 2717 <name>DATA</name> 2718 <description>Used to load the SCA modulo for modular operations.</description> 2719 <bitOffset>0</bitOffset> 2720 <bitWidth>32</bitWidth> 2721 </field> 2722 </fields> 2723 </register> 2724 <register> 2725 <name>SCA_NRNG</name> 2726 <description>SCA NIST RNG Address Register.</description> 2727 <addressOffset>0x734</addressOffset> 2728 <resetValue>0x0</resetValue> 2729 <fields> 2730 <field> 2731 <name>ADDR</name> 2732 <description>Starting SRAM address where up to 32 words of NIST washed RNG data is stored.</description> 2733 <bitOffset>0</bitOffset> 2734 <bitWidth>32</bitWidth> 2735 </field> 2736 </fields> 2737 </register> 2738 <register> 2739 <name>SCA_WASH</name> 2740 <description>SCA Wash Register.</description> 2741 <addressOffset>0x738</addressOffset> 2742 <resetValue>0x0</resetValue> 2743 <fields> 2744 <field> 2745 <name>ADDR</name> 2746 <description>Starting SRAM address where up to 1 word of random is stored for SRAM washing.</description> 2747 <bitOffset>0</bitOffset> 2748 <bitWidth>32</bitWidth> 2749 </field> 2750 </fields> 2751 </register> 2752 </registers> 2753 </peripheral> 2754<!--CTB The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security.--> 2755 <peripheral> 2756 <name>DMA</name> 2757 <description>DMA Controller Fully programmable, chaining capable DMA channels.</description> 2758 <baseAddress>0x40028000</baseAddress> 2759 <size>32</size> 2760 <addressBlock> 2761 <offset>0x00</offset> 2762 <size>0x1000</size> 2763 <usage>registers</usage> 2764 </addressBlock> 2765 <interrupt> 2766 <name>DMA0</name> 2767 <value>28</value> 2768 </interrupt> 2769 <interrupt> 2770 <name>DMA1</name> 2771 <value>29</value> 2772 </interrupt> 2773 <interrupt> 2774 <name>DMA2</name> 2775 <value>30</value> 2776 </interrupt> 2777 <interrupt> 2778 <name>DMA3</name> 2779 <value>31</value> 2780 </interrupt> 2781 <interrupt> 2782 <name>DMA4</name> 2783 <value>68</value> 2784 </interrupt> 2785 <interrupt> 2786 <name>DMA5</name> 2787 <value>69</value> 2788 </interrupt> 2789 <interrupt> 2790 <name>DMA6</name> 2791 <value>70</value> 2792 </interrupt> 2793 <interrupt> 2794 <name>DMA7</name> 2795 <value>71</value> 2796 </interrupt> 2797 <interrupt> 2798 <name>DMA8</name> 2799 <value>72</value> 2800 </interrupt> 2801 <interrupt> 2802 <name>DMA9</name> 2803 <value>73</value> 2804 </interrupt> 2805 <interrupt> 2806 <name>DMA10</name> 2807 <value>74</value> 2808 </interrupt> 2809 <interrupt> 2810 <name>DMA11</name> 2811 <value>75</value> 2812 </interrupt> 2813 <interrupt> 2814 <name>DMA12</name> 2815 <value>76</value> 2816 </interrupt> 2817 <interrupt> 2818 <name>DMA13</name> 2819 <value>77</value> 2820 </interrupt> 2821 <interrupt> 2822 <name>DMA14</name> 2823 <value>78</value> 2824 </interrupt> 2825 <interrupt> 2826 <name>DMA15</name> 2827 <value>79</value> 2828 </interrupt> 2829 <registers> 2830 <register> 2831 <name>INTEN</name> 2832 <description>DMA Interrupt Enable Register.</description> 2833 <addressOffset>0x000</addressOffset> 2834 <fields> 2835 <field> 2836 <name>CH0</name> 2837 <description>Channel 0 Interrupt Enable.</description> 2838 <bitOffset>0</bitOffset> 2839 <bitWidth>1</bitWidth> 2840 <enumeratedValues> 2841 <enumeratedValue> 2842 <name>dis</name> 2843 <description>Disable.</description> 2844 <value>0</value> 2845 </enumeratedValue> 2846 <enumeratedValue> 2847 <name>en</name> 2848 <description>Enable.</description> 2849 <value>1</value> 2850 </enumeratedValue> 2851 </enumeratedValues> 2852 </field> 2853 <field derivedFrom="CH0"> 2854 <name>CH1</name> 2855 <description>Channel 1 Interrupt Enable.</description> 2856 <bitOffset>1</bitOffset> 2857 <bitWidth>1</bitWidth> 2858 </field> 2859 <field derivedFrom="CH0"> 2860 <name>CH2</name> 2861 <description>Channel 2 Interrupt Enable.</description> 2862 <bitOffset>2</bitOffset> 2863 <bitWidth>1</bitWidth> 2864 </field> 2865 <field derivedFrom="CH0"> 2866 <name>CH3</name> 2867 <description>Channel 3 Interrupt Enable.</description> 2868 <bitOffset>3</bitOffset> 2869 <bitWidth>1</bitWidth> 2870 </field> 2871 <field derivedFrom="CH0"> 2872 <name>CH4</name> 2873 <description>Channel 4 Interrupt Enable.</description> 2874 <bitOffset>4</bitOffset> 2875 <bitWidth>1</bitWidth> 2876 </field> 2877 <field derivedFrom="CH0"> 2878 <name>CH5</name> 2879 <description>Channel 5 Interrupt Enable.</description> 2880 <bitOffset>5</bitOffset> 2881 <bitWidth>1</bitWidth> 2882 </field> 2883 <field derivedFrom="CH0"> 2884 <name>CH6</name> 2885 <description>Channel 6 Interrupt Enable.</description> 2886 <bitOffset>6</bitOffset> 2887 <bitWidth>1</bitWidth> 2888 </field> 2889 <field derivedFrom="CH0"> 2890 <name>CH7</name> 2891 <description>Channel 7 Interrupt Enable.</description> 2892 <bitOffset>7</bitOffset> 2893 <bitWidth>1</bitWidth> 2894 </field> 2895 <field derivedFrom="CH0"> 2896 <name>CH8</name> 2897 <description>Channel 8 Interrupt Enable.</description> 2898 <bitOffset>8</bitOffset> 2899 <bitWidth>1</bitWidth> 2900 </field> 2901 <field derivedFrom="CH0"> 2902 <name>CH9</name> 2903 <description>Channel 9 Interrupt Enable.</description> 2904 <bitOffset>9</bitOffset> 2905 <bitWidth>1</bitWidth> 2906 </field> 2907 <field derivedFrom="CH0"> 2908 <name>CH10</name> 2909 <description>Channel 10 Interrupt Enable.</description> 2910 <bitOffset>10</bitOffset> 2911 <bitWidth>1</bitWidth> 2912 </field> 2913 <field derivedFrom="CH0"> 2914 <name>CH11</name> 2915 <description>Channel 11 Interrupt Enable.</description> 2916 <bitOffset>11</bitOffset> 2917 <bitWidth>1</bitWidth> 2918 </field> 2919 <field derivedFrom="CH0"> 2920 <name>CH12</name> 2921 <description>Channel 12 Interrupt Enable.</description> 2922 <bitOffset>12</bitOffset> 2923 <bitWidth>1</bitWidth> 2924 </field> 2925 <field derivedFrom="CH0"> 2926 <name>CH13</name> 2927 <description>Channel 13 Interrupt Enable.</description> 2928 <bitOffset>13</bitOffset> 2929 <bitWidth>1</bitWidth> 2930 </field> 2931 <field derivedFrom="CH0"> 2932 <name>CH14</name> 2933 <description>Channel 14 Interrupt Enable.</description> 2934 <bitOffset>14</bitOffset> 2935 <bitWidth>1</bitWidth> 2936 </field> 2937 <field derivedFrom="CH0"> 2938 <name>CH15</name> 2939 <description>Channel 15 Interrupt Enable.</description> 2940 <bitOffset>15</bitOffset> 2941 <bitWidth>1</bitWidth> 2942 </field> 2943 </fields> 2944 </register> 2945 <register> 2946 <name>INTFL</name> 2947 <description>DMA Interrupt Flag Register.</description> 2948 <addressOffset>0x004</addressOffset> 2949 <access>read-only</access> 2950 <fields> 2951 <field> 2952 <name>CH0</name> 2953 <description>Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.</description> 2954 <bitOffset>0</bitOffset> 2955 <bitWidth>1</bitWidth> 2956 <enumeratedValues> 2957 <enumeratedValue> 2958 <name>inactive</name> 2959 <description>No interrupt is pending.</description> 2960 <value>0</value> 2961 </enumeratedValue> 2962 <enumeratedValue> 2963 <name>pending</name> 2964 <description>An interrupt is pending.</description> 2965 <value>1</value> 2966 </enumeratedValue> 2967 </enumeratedValues> 2968 </field> 2969 <field derivedFrom="CH0"> 2970 <name>CH1</name> 2971 <bitOffset>1</bitOffset> 2972 <bitWidth>1</bitWidth> 2973 </field> 2974 <field derivedFrom="CH0"> 2975 <name>CH2</name> 2976 <bitOffset>2</bitOffset> 2977 <bitWidth>1</bitWidth> 2978 </field> 2979 <field derivedFrom="CH0"> 2980 <name>CH3</name> 2981 <bitOffset>3</bitOffset> 2982 <bitWidth>1</bitWidth> 2983 </field> 2984 <field derivedFrom="CH0"> 2985 <name>CH4</name> 2986 <bitOffset>4</bitOffset> 2987 <bitWidth>1</bitWidth> 2988 </field> 2989 <field derivedFrom="CH0"> 2990 <name>CH5</name> 2991 <bitOffset>5</bitOffset> 2992 <bitWidth>1</bitWidth> 2993 </field> 2994 <field derivedFrom="CH0"> 2995 <name>CH6</name> 2996 <bitOffset>6</bitOffset> 2997 <bitWidth>1</bitWidth> 2998 </field> 2999 <field derivedFrom="CH0"> 3000 <name>CH7</name> 3001 <bitOffset>7</bitOffset> 3002 <bitWidth>1</bitWidth> 3003 </field> 3004 <field derivedFrom="CH0"> 3005 <name>CH8</name> 3006 <bitOffset>8</bitOffset> 3007 <bitWidth>1</bitWidth> 3008 </field> 3009 <field derivedFrom="CH0"> 3010 <name>CH9</name> 3011 <bitOffset>9</bitOffset> 3012 <bitWidth>1</bitWidth> 3013 </field> 3014 <field derivedFrom="CH0"> 3015 <name>CH10</name> 3016 <bitOffset>10</bitOffset> 3017 <bitWidth>1</bitWidth> 3018 </field> 3019 <field derivedFrom="CH0"> 3020 <name>CH11</name> 3021 <bitOffset>11</bitOffset> 3022 <bitWidth>1</bitWidth> 3023 </field> 3024 <field derivedFrom="CH0"> 3025 <name>CH12</name> 3026 <bitOffset>12</bitOffset> 3027 <bitWidth>1</bitWidth> 3028 </field> 3029 <field derivedFrom="CH0"> 3030 <name>CH13</name> 3031 <bitOffset>13</bitOffset> 3032 <bitWidth>1</bitWidth> 3033 </field> 3034 <field derivedFrom="CH0"> 3035 <name>CH14</name> 3036 <bitOffset>14</bitOffset> 3037 <bitWidth>1</bitWidth> 3038 </field> 3039 <field derivedFrom="CH0"> 3040 <name>CH15</name> 3041 <bitOffset>15</bitOffset> 3042 <bitWidth>1</bitWidth> 3043 </field> 3044 </fields> 3045 </register> 3046 <cluster> 3047 <dim>16</dim> 3048 <dimIncrement>0x20</dimIncrement> 3049 <name>CH[%s]</name> 3050 <description>DMA Channel registers.</description> 3051 <headerStructName>dma_ch</headerStructName> 3052 <addressOffset>0x100</addressOffset> 3053 <access>read-write</access> 3054 <register> 3055 <name>CTRL</name> 3056 <description>DMA Channel Control Register.</description> 3057 <addressOffset>0x000</addressOffset> 3058 <fields> 3059 <field> 3060 <name>EN</name> 3061 <description>Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.</description> 3062 <bitOffset>0</bitOffset> 3063 <bitWidth>1</bitWidth> 3064 <enumeratedValues> 3065 <enumeratedValue> 3066 <name>dis</name> 3067 <description>Disable.</description> 3068 <value>0</value> 3069 </enumeratedValue> 3070 <enumeratedValue> 3071 <name>en</name> 3072 <description>Enable.</description> 3073 <value>1</value> 3074 </enumeratedValue> 3075 </enumeratedValues> 3076 </field> 3077 <field> 3078 <name>RLDEN</name> 3079 <description>Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.</description> 3080 <bitOffset>1</bitOffset> 3081 <bitWidth>1</bitWidth> 3082 <enumeratedValues> 3083 <enumeratedValue> 3084 <name>dis</name> 3085 <description>Disable.</description> 3086 <value>0</value> 3087 </enumeratedValue> 3088 <enumeratedValue> 3089 <name>en</name> 3090 <description>Enable.</description> 3091 <value>1</value> 3092 </enumeratedValue> 3093 </enumeratedValues> 3094 </field> 3095 <field> 3096 <name>PRI</name> 3097 <description>DMA Priority.</description> 3098 <bitOffset>2</bitOffset> 3099 <bitWidth>2</bitWidth> 3100 <enumeratedValues> 3101 <enumeratedValue> 3102 <name>high</name> 3103 <description>Highest Priority.</description> 3104 <value>0</value> 3105 </enumeratedValue> 3106 <enumeratedValue> 3107 <name>medHigh</name> 3108 <description>Medium High Priority.</description> 3109 <value>1</value> 3110 </enumeratedValue> 3111 <enumeratedValue> 3112 <name>medLow</name> 3113 <description>Medium Low Priority.</description> 3114 <value>2</value> 3115 </enumeratedValue> 3116 <enumeratedValue> 3117 <name>low</name> 3118 <description>Lowest Priority.</description> 3119 <value>3</value> 3120 </enumeratedValue> 3121 </enumeratedValues> 3122 </field> 3123 <field> 3124 <name>REQUEST</name> 3125 <description>Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.</description> 3126 <bitOffset>4</bitOffset> 3127 <bitWidth>6</bitWidth> 3128 <enumeratedValues> 3129 <enumeratedValue> 3130 <name>MEMTOMEM</name> 3131 <description>Memory To Memory</description> 3132 <value>0x00</value> 3133 </enumeratedValue> 3134 <enumeratedValue> 3135 <name>SPI0RX</name> 3136 <description>SPI0 RX</description> 3137 <value>0x01</value> 3138 </enumeratedValue> 3139 <enumeratedValue> 3140 <name>SPI1RX</name> 3141 <description>SPI1 RX</description> 3142 <value>0x02</value> 3143 </enumeratedValue> 3144 <enumeratedValue> 3145 <name>UART0RX</name> 3146 <description>UART0 RX</description> 3147 <value>0x04</value> 3148 </enumeratedValue> 3149 <enumeratedValue> 3150 <name>UART1RX</name> 3151 <description>UART1 RX</description> 3152 <value>0x05</value> 3153 </enumeratedValue> 3154 <enumeratedValue> 3155 <name>SC0RX</name> 3156 <description>SC0 RX</description> 3157 <value>0x06</value> 3158 </enumeratedValue> 3159 <enumeratedValue> 3160 <name>I2C0RX</name> 3161 <description>I2C0 RX</description> 3162 <value>0x07</value> 3163 </enumeratedValue> 3164 <enumeratedValue> 3165 <name>I2C1RX</name> 3166 <description>I2C1 RX</description> 3167 <value>0x08</value> 3168 </enumeratedValue> 3169 <enumeratedValue> 3170 <name>ADC</name> 3171 <description>Analog-to-Digital Converter Channel</description> 3172 <value>0x09</value> 3173 </enumeratedValue> 3174 <enumeratedValue> 3175 <name>MSRADC</name> 3176 <description>MSR 9 bit ADC.</description> 3177 <value>0x0B</value> 3178 </enumeratedValue> 3179 <enumeratedValue> 3180 <name>UART2RX</name> 3181 <description>UART2 RX</description> 3182 <value>0x0E</value> 3183 </enumeratedValue> 3184 <enumeratedValue> 3185 <name>SPI3RX</name> 3186 <description>SPI3 RX</description> 3187 <value>0x0F</value> 3188 </enumeratedValue> 3189 <enumeratedValue> 3190 <name>USBRXEP1</name> 3191 <description>USB Endpoint 1 RX</description> 3192 <value>0x11</value> 3193 </enumeratedValue> 3194 <enumeratedValue> 3195 <name>USBRXEP2</name> 3196 <description>USB Endpoint 2 RX</description> 3197 <value>0x12</value> 3198 </enumeratedValue> 3199 <enumeratedValue> 3200 <name>USBRXEP3</name> 3201 <description>USB Endpoint 3 RX</description> 3202 <value>0x13</value> 3203 </enumeratedValue> 3204 <enumeratedValue> 3205 <name>USBRXEP4</name> 3206 <description>USB Endpoint 4 RX</description> 3207 <value>0x14</value> 3208 </enumeratedValue> 3209 <enumeratedValue> 3210 <name>USBRXEP5</name> 3211 <description>USB Endpoint 5 RX</description> 3212 <value>0x15</value> 3213 </enumeratedValue> 3214 <enumeratedValue> 3215 <name>USBRXEP6</name> 3216 <description>USB Endpoint 6 RX</description> 3217 <value>0x16</value> 3218 </enumeratedValue> 3219 <enumeratedValue> 3220 <name>USBRXEP7</name> 3221 <description>USB Endpoint 7 RX</description> 3222 <value>0x17</value> 3223 </enumeratedValue> 3224 <enumeratedValue> 3225 <name>USBRXEP8</name> 3226 <description>USB Endpoint 8 RX</description> 3227 <value>0x18</value> 3228 </enumeratedValue> 3229 <enumeratedValue> 3230 <name>USBRXEP9</name> 3231 <description>USB Endpoint 9 RX</description> 3232 <value>0x19</value> 3233 </enumeratedValue> 3234 <enumeratedValue> 3235 <name>USBRXEP10</name> 3236 <description>USB Endpoint 10 RX</description> 3237 <value>0x1A</value> 3238 </enumeratedValue> 3239 <enumeratedValue> 3240 <name>USBRXEP11</name> 3241 <description>USB Endpoint 11 RX</description> 3242 <value>0x1B</value> 3243 </enumeratedValue> 3244 <enumeratedValue> 3245 <name>UART3RX</name> 3246 <description>UART3 RX</description> 3247 <value>0x1C</value> 3248 </enumeratedValue> 3249 <enumeratedValue> 3250 <name>SPI0TX</name> 3251 <description>SPI0 TX</description> 3252 <value>0x21</value> 3253 </enumeratedValue> 3254 <enumeratedValue> 3255 <name>SPI1TX</name> 3256 <description>SPI1 TX</description> 3257 <value>0x22</value> 3258 </enumeratedValue> 3259 <enumeratedValue> 3260 <name>UART0TX</name> 3261 <description>UART0 TX</description> 3262 <value>0x24</value> 3263 </enumeratedValue> 3264 <enumeratedValue> 3265 <name>UART1TX</name> 3266 <description>UART1 TX</description> 3267 <value>0x25</value> 3268 </enumeratedValue> 3269 <enumeratedValue> 3270 <name>SC0TX</name> 3271 <description>SC0 TX</description> 3272 <value>0x26</value> 3273 </enumeratedValue> 3274 <enumeratedValue> 3275 <name>I2C0TX</name> 3276 <description>I2C0 TX</description> 3277 <value>0x27</value> 3278 </enumeratedValue> 3279 <enumeratedValue> 3280 <name>I2C1TX</name> 3281 <description>I2C1 TX</description> 3282 <value>0x28</value> 3283 </enumeratedValue> 3284 <enumeratedValue> 3285 <name>UART2TX</name> 3286 <description>UART2 TX</description> 3287 <value>0x2E</value> 3288 </enumeratedValue> 3289 <enumeratedValue> 3290 <name>SPI3TX</name> 3291 <description>SPI3 TX</description> 3292 <value>0x2F</value> 3293 </enumeratedValue> 3294 <enumeratedValue> 3295 <name>USBTXEP1</name> 3296 <description>USB Endpoint 1 TX</description> 3297 <value>0x31</value> 3298 </enumeratedValue> 3299 <enumeratedValue> 3300 <name>USBTXEP2</name> 3301 <description>USB Endpoint 2 TX</description> 3302 <value>0x32</value> 3303 </enumeratedValue> 3304 <enumeratedValue> 3305 <name>USBTXEP3</name> 3306 <description>USB Endpoint 3 TX</description> 3307 <value>0x33</value> 3308 </enumeratedValue> 3309 <enumeratedValue> 3310 <name>USBTXEP4</name> 3311 <description>USB Endpoint 4 TX</description> 3312 <value>0x34</value> 3313 </enumeratedValue> 3314 <enumeratedValue> 3315 <name>USBTXEP5</name> 3316 <description>USB Endpoint 5 TX</description> 3317 <value>0x35</value> 3318 </enumeratedValue> 3319 <enumeratedValue> 3320 <name>USBTXEP6</name> 3321 <description>USB Endpoint 6 TX</description> 3322 <value>0x36</value> 3323 </enumeratedValue> 3324 <enumeratedValue> 3325 <name>USBTXEP7</name> 3326 <description>USB Endpoint 7 TX</description> 3327 <value>0x37</value> 3328 </enumeratedValue> 3329 <enumeratedValue> 3330 <name>USBTXEP8</name> 3331 <description>USB Endpoint 8 TX</description> 3332 <value>0x38</value> 3333 </enumeratedValue> 3334 <enumeratedValue> 3335 <name>USBTXEP9</name> 3336 <description>USB Endpoint 9 TX</description> 3337 <value>0x39</value> 3338 </enumeratedValue> 3339 <enumeratedValue> 3340 <name>USBTXEP10</name> 3341 <description>USB Endpoint 10 TX</description> 3342 <value>0x3A</value> 3343 </enumeratedValue> 3344 <enumeratedValue> 3345 <name>USBTXEP11</name> 3346 <description>USB Endpoint 11 TX</description> 3347 <value>0x3B</value> 3348 </enumeratedValue> 3349 <enumeratedValue> 3350 <name>UART3TX</name> 3351 <description>UART3 TX</description> 3352 <value>0x3C</value> 3353 </enumeratedValue> 3354 </enumeratedValues> 3355 </field> 3356 <field> 3357 <name>TO_WAIT</name> 3358 <description>Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.</description> 3359 <bitOffset>10</bitOffset> 3360 <bitWidth>1</bitWidth> 3361 <enumeratedValues> 3362 <enumeratedValue> 3363 <name>dis</name> 3364 <description>Disable.</description> 3365 <value>0</value> 3366 </enumeratedValue> 3367 <enumeratedValue> 3368 <name>en</name> 3369 <description>Enable.</description> 3370 <value>1</value> 3371 </enumeratedValue> 3372 </enumeratedValues> 3373 </field> 3374 <field> 3375 <name>TO_PER</name> 3376 <description>Timeout Period Select.</description> 3377 <bitOffset>11</bitOffset> 3378 <bitWidth>3</bitWidth> 3379 <enumeratedValues> 3380 <enumeratedValue> 3381 <name>to4</name> 3382 <description>Timeout of 3 to 4 prescale clocks.</description> 3383 <value>0</value> 3384 </enumeratedValue> 3385 <enumeratedValue> 3386 <name>to8</name> 3387 <description>Timeout of 7 to 8 prescale clocks.</description> 3388 <value>1</value> 3389 </enumeratedValue> 3390 <enumeratedValue> 3391 <name>to16</name> 3392 <description>Timeout of 15 to 16 prescale clocks.</description> 3393 <value>2</value> 3394 </enumeratedValue> 3395 <enumeratedValue> 3396 <name>to32</name> 3397 <description>Timeout of 31 to 32 prescale clocks.</description> 3398 <value>3</value> 3399 </enumeratedValue> 3400 <enumeratedValue> 3401 <name>to64</name> 3402 <description>Timeout of 63 to 64 prescale clocks.</description> 3403 <value>4</value> 3404 </enumeratedValue> 3405 <enumeratedValue> 3406 <name>to128</name> 3407 <description>Timeout of 127 to 128 prescale clocks.</description> 3408 <value>5</value> 3409 </enumeratedValue> 3410 <enumeratedValue> 3411 <name>to256</name> 3412 <description>Timeout of 255 to 256 prescale clocks.</description> 3413 <value>6</value> 3414 </enumeratedValue> 3415 <enumeratedValue> 3416 <name>to512</name> 3417 <description>Timeout of 511 to 512 prescale clocks.</description> 3418 <value>7</value> 3419 </enumeratedValue> 3420 </enumeratedValues> 3421 </field> 3422 <field> 3423 <name>TO_CLKDIV</name> 3424 <description>Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.</description> 3425 <bitOffset>14</bitOffset> 3426 <bitWidth>2</bitWidth> 3427 <enumeratedValues> 3428 <enumeratedValue> 3429 <name>dis</name> 3430 <description>Disable timer.</description> 3431 <value>0</value> 3432 </enumeratedValue> 3433 <enumeratedValue> 3434 <name>div256</name> 3435 <description>hclk / 256.</description> 3436 <value>1</value> 3437 </enumeratedValue> 3438 <enumeratedValue> 3439 <name>div64k</name> 3440 <description>hclk / 64k.</description> 3441 <value>2</value> 3442 </enumeratedValue> 3443 <enumeratedValue> 3444 <name>div16M</name> 3445 <description>hclk / 16M.</description> 3446 <value>3</value> 3447 </enumeratedValue> 3448 </enumeratedValues> 3449 </field> 3450 <field> 3451 <name>SRCWD</name> 3452 <description>Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.</description> 3453 <bitOffset>16</bitOffset> 3454 <bitWidth>2</bitWidth> 3455 <enumeratedValues> 3456 <enumeratedValue> 3457 <name>byte</name> 3458 <description>Byte.</description> 3459 <value>0</value> 3460 </enumeratedValue> 3461 <enumeratedValue> 3462 <name>halfWord</name> 3463 <description>Halfword.</description> 3464 <value>1</value> 3465 </enumeratedValue> 3466 <enumeratedValue> 3467 <name>word</name> 3468 <description>Word.</description> 3469 <value>2</value> 3470 </enumeratedValue> 3471 </enumeratedValues> 3472 </field> 3473 <field> 3474 <name>SRCINC</name> 3475 <description>Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.</description> 3476 <bitOffset>18</bitOffset> 3477 <bitWidth>1</bitWidth> 3478 <enumeratedValues> 3479 <enumeratedValue> 3480 <name>dis</name> 3481 <description>Disable.</description> 3482 <value>0</value> 3483 </enumeratedValue> 3484 <enumeratedValue> 3485 <name>en</name> 3486 <description>Enable.</description> 3487 <value>1</value> 3488 </enumeratedValue> 3489 </enumeratedValues> 3490 </field> 3491 <field> 3492 <name>DSTWD</name> 3493 <description>Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).</description> 3494 <bitOffset>20</bitOffset> 3495 <bitWidth>2</bitWidth> 3496 <enumeratedValues> 3497 <enumeratedValue> 3498 <name>byte</name> 3499 <description>Byte.</description> 3500 <value>0</value> 3501 </enumeratedValue> 3502 <enumeratedValue> 3503 <name>halfWord</name> 3504 <description>Halfword.</description> 3505 <value>1</value> 3506 </enumeratedValue> 3507 <enumeratedValue> 3508 <name>word</name> 3509 <description>Word.</description> 3510 <value>2</value> 3511 </enumeratedValue> 3512 </enumeratedValues> 3513 </field> 3514 <field> 3515 <name>DSTINC</name> 3516 <description>Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.</description> 3517 <bitOffset>22</bitOffset> 3518 <bitWidth>1</bitWidth> 3519 <enumeratedValues> 3520 <enumeratedValue> 3521 <name>dis</name> 3522 <description>Disable.</description> 3523 <value>0</value> 3524 </enumeratedValue> 3525 <enumeratedValue> 3526 <name>en</name> 3527 <description>Enable.</description> 3528 <value>1</value> 3529 </enumeratedValue> 3530 </enumeratedValues> 3531 </field> 3532 <field> 3533 <name>BURST_SIZE</name> 3534 <description>Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.</description> 3535 <bitOffset>24</bitOffset> 3536 <bitWidth>5</bitWidth> 3537 </field> 3538 <field> 3539 <name>DIS_IE</name> 3540 <description>Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.</description> 3541 <bitOffset>30</bitOffset> 3542 <bitWidth>1</bitWidth> 3543 <enumeratedValues> 3544 <enumeratedValue> 3545 <name>dis</name> 3546 <description>Disable.</description> 3547 <value>0</value> 3548 </enumeratedValue> 3549 <enumeratedValue> 3550 <name>en</name> 3551 <description>Enable.</description> 3552 <value>1</value> 3553 </enumeratedValue> 3554 </enumeratedValues> 3555 </field> 3556 <field> 3557 <name>CTZ_IE</name> 3558 <description>Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.</description> 3559 <bitOffset>31</bitOffset> 3560 <bitWidth>1</bitWidth> 3561 <enumeratedValues> 3562 <enumeratedValue> 3563 <name>dis</name> 3564 <description>Disable.</description> 3565 <value>0</value> 3566 </enumeratedValue> 3567 <enumeratedValue> 3568 <name>en</name> 3569 <description>Enable.</description> 3570 <value>1</value> 3571 </enumeratedValue> 3572 </enumeratedValues> 3573 </field> 3574 </fields> 3575 </register> 3576 <register> 3577 <name>STATUS</name> 3578 <description>DMA Channel Status Register.</description> 3579 <addressOffset>0x004</addressOffset> 3580 <fields> 3581 <field> 3582 <name>STATUS</name> 3583 <description>Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).</description> 3584 <bitOffset>0</bitOffset> 3585 <bitWidth>1</bitWidth> 3586 <access>read-only</access> 3587 <enumeratedValues> 3588 <enumeratedValue> 3589 <name>dis</name> 3590 <description>Disable.</description> 3591 <value>0</value> 3592 </enumeratedValue> 3593 <enumeratedValue> 3594 <name>en</name> 3595 <description>Enable.</description> 3596 <value>1</value> 3597 </enumeratedValue> 3598 </enumeratedValues> 3599 </field> 3600 <field> 3601 <name>IPEND</name> 3602 <description>Channel Interrupt.</description> 3603 <bitOffset>1</bitOffset> 3604 <bitWidth>1</bitWidth> 3605 <access>read-only</access> 3606 <enumeratedValues> 3607 <enumeratedValue> 3608 <name>inactive</name> 3609 <description>No interrupt is pending.</description> 3610 <value>0</value> 3611 </enumeratedValue> 3612 <enumeratedValue> 3613 <name>pending</name> 3614 <description>An interrupt is pending.</description> 3615 <value>1</value> 3616 </enumeratedValue> 3617 </enumeratedValues> 3618 </field> 3619 <field> 3620 <name>CTZ_IF</name> 3621 <description>Count-to-Zero (CTZ) Event Interrupt Flag</description> 3622 <bitOffset>2</bitOffset> 3623 <bitWidth>1</bitWidth> 3624 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3625 </field> 3626 <field> 3627 <name>RLD_IF</name> 3628 <description>Reload Event Interrupt Flag.</description> 3629 <bitOffset>3</bitOffset> 3630 <bitWidth>1</bitWidth> 3631 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3632 </field> 3633 <field> 3634 <name>BUS_ERR</name> 3635 <description>Bus Error. Indicates that an AHB abort was received and the channel has been disabled.</description> 3636 <bitOffset>4</bitOffset> 3637 <bitWidth>1</bitWidth> 3638 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3639 </field> 3640 <field> 3641 <name>TO_IF</name> 3642 <description>Time-Out Event Interrupt Flag.</description> 3643 <bitOffset>6</bitOffset> 3644 <bitWidth>1</bitWidth> 3645 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3646 </field> 3647 </fields> 3648 </register> 3649 <register> 3650 <name>SRC</name> 3651 <description>Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.</description> 3652 <addressOffset>0x008</addressOffset> 3653 <fields> 3654 <field> 3655 <name>ADDR</name> 3656 <bitOffset>0</bitOffset> 3657 <bitWidth>32</bitWidth> 3658 </field> 3659 </fields> 3660 </register> 3661 <register> 3662 <name>DST</name> 3663 <description>Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.</description> 3664 <addressOffset>0x00C</addressOffset> 3665 <fields> 3666 <field> 3667 <name>ADDR</name> 3668 <bitOffset>0</bitOffset> 3669 <bitWidth>32</bitWidth> 3670 </field> 3671 </fields> 3672 </register> 3673 <register> 3674 <name>CNT</name> 3675 <description>DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.</description> 3676 <addressOffset>0x010</addressOffset> 3677 <fields> 3678 <field> 3679 <name>CNT</name> 3680 <description>DMA Counter.</description> 3681 <bitOffset>0</bitOffset> 3682 <bitWidth>24</bitWidth> 3683 </field> 3684 </fields> 3685 </register> 3686 <register> 3687 <name>SRCRLD</name> 3688 <description>Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.</description> 3689 <addressOffset>0x014</addressOffset> 3690 <fields> 3691 <field> 3692 <name>ADDR</name> 3693 <description>Source Address Reload Value.</description> 3694 <bitOffset>0</bitOffset> 3695 <bitWidth>31</bitWidth> 3696 </field> 3697 </fields> 3698 </register> 3699 <register> 3700 <name>DSTRLD</name> 3701 <description>Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.</description> 3702 <addressOffset>0x018</addressOffset> 3703 <fields> 3704 <field> 3705 <name>ADDR</name> 3706 <description>Destination Address Reload Value.</description> 3707 <bitOffset>0</bitOffset> 3708 <bitWidth>31</bitWidth> 3709 </field> 3710 </fields> 3711 </register> 3712 <register> 3713 <name>CNTRLD</name> 3714 <description>DMA Channel Count Reload Register.</description> 3715 <addressOffset>0x01C</addressOffset> 3716 <fields> 3717 <field> 3718 <name>CNT</name> 3719 <description>Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.</description> 3720 <bitOffset>0</bitOffset> 3721 <bitWidth>24</bitWidth> 3722 </field> 3723 <field> 3724 <name>EN</name> 3725 <description>Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.</description> 3726 <bitOffset>31</bitOffset> 3727 <bitWidth>1</bitWidth> 3728 <enumeratedValues> 3729 <enumeratedValue> 3730 <name>dis</name> 3731 <description>Disable.</description> 3732 <value>0</value> 3733 </enumeratedValue> 3734 <enumeratedValue> 3735 <name>en</name> 3736 <description>Enable.</description> 3737 <value>1</value> 3738 </enumeratedValue> 3739 </enumeratedValues> 3740 </field> 3741 </fields> 3742 </register> 3743 </cluster> 3744 </registers> 3745 </peripheral> 3746<!--DMA DMA Controller Fully programmable, chaining capable DMA channels.--> 3747 <peripheral> 3748 <name>GCR</name> 3749 <description>Global Control Registers.</description> 3750 <baseAddress>0x40000000</baseAddress> 3751 <addressBlock> 3752 <offset>0</offset> 3753 <size>0x400</size> 3754 <usage>registers</usage> 3755 </addressBlock> 3756 <registers> 3757 <register> 3758 <name>SYSCTRL</name> 3759 <description>System Control.</description> 3760 <addressOffset>0x00</addressOffset> 3761 <resetMask>0xFFFFFFFE</resetMask> 3762 <fields> 3763 <field> 3764 <name>BSTAPEN</name> 3765 <description>Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE.</description> 3766 <bitOffset>0</bitOffset> 3767 <bitWidth>1</bitWidth> 3768 <enumeratedValues> 3769 <enumeratedValue> 3770 <name>dis</name> 3771 <description>Boundary Scan TAP port disabled.</description> 3772 <value>0</value> 3773 </enumeratedValue> 3774 <enumeratedValue> 3775 <name>en</name> 3776 <description>Boundary Scan TAP port enabled.</description> 3777 <value>1</value> 3778 </enumeratedValue> 3779 </enumeratedValues> 3780 </field> 3781 <field> 3782 <name>SBUSARB</name> 3783 <description>System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.</description> 3784 <bitOffset>1</bitOffset> 3785 <bitWidth>2</bitWidth> 3786 <enumeratedValues> 3787 <enumeratedValue> 3788 <name>fix</name> 3789 <description>Fixed Burst abritration.</description> 3790 <value>0</value> 3791 </enumeratedValue> 3792 <enumeratedValue> 3793 <name>round</name> 3794 <description>Round-robin scheme.</description> 3795 <value>1</value> 3796 </enumeratedValue> 3797 </enumeratedValues> 3798 </field> 3799 <field> 3800 <name>FPU_DIS</name> 3801 <description>Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4.</description> 3802 <bitOffset>5</bitOffset> 3803 <bitWidth>1</bitWidth> 3804 </field> 3805 <field> 3806 <name>SFCC_FLUSH</name> 3807 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 3808 <bitOffset>6</bitOffset> 3809 <bitWidth>1</bitWidth> 3810 <enumeratedValues> 3811 <enumeratedValue> 3812 <name>normal</name> 3813 <description>Normal Code Cache Operation</description> 3814 <value>0</value> 3815 </enumeratedValue> 3816 <enumeratedValue> 3817 <name>flush</name> 3818 <description>Code Caches and CPU instruction buffer are flushed </description> 3819 <value>1</value> 3820 </enumeratedValue> 3821 </enumeratedValues> 3822 </field> 3823 <field> 3824 <name>CHKRES1</name> 3825 <description>Result of CPU1 ROM1 Checksum.</description> 3826 <bitOffset>11</bitOffset> 3827 <bitWidth>1</bitWidth> 3828 </field> 3829 <field> 3830 <name>CCHK1</name> 3831 <description>Compute CPU1 ROM1 Checksum</description> 3832 <bitOffset>12</bitOffset> 3833 <bitWidth>1</bitWidth> 3834 </field> 3835 <field> 3836 <name>CCHK0</name> 3837 <description>Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 3838 <bitOffset>13</bitOffset> 3839 <bitWidth>1</bitWidth> 3840 <enumeratedValues> 3841 <enumeratedValue> 3842 <name>complete</name> 3843 <description>No operation/complete.</description> 3844 <value>0</value> 3845 </enumeratedValue> 3846 <enumeratedValue> 3847 <name>start</name> 3848 <description>Start operation.</description> 3849 <value>1</value> 3850 </enumeratedValue> 3851 </enumeratedValues> 3852 </field> 3853 <field> 3854 <name>SWD_DIS</name> 3855 <description> Serial Wire Debug Disable.</description> 3856 <bitOffset>14</bitOffset> 3857 <bitWidth>1</bitWidth> 3858 </field> 3859 <field> 3860 <name>CHKRES0</name> 3861 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 3862 <bitOffset>15</bitOffset> 3863 <bitWidth>1</bitWidth> 3864 <enumeratedValues> 3865 <enumeratedValue> 3866 <name>pass</name> 3867 <description>ROM Checksum Correct.</description> 3868 <value>0</value> 3869 </enumeratedValue> 3870 <enumeratedValue> 3871 <name>fail</name> 3872 <description>ROM Checksum Fail.</description> 3873 <value>1</value> 3874 </enumeratedValue> 3875 </enumeratedValues> 3876 </field> 3877 </fields> 3878 </register> 3879 <register> 3880 <name>RST0</name> 3881 <description>Reset.</description> 3882 <addressOffset>0x04</addressOffset> 3883 <fields> 3884 <field> 3885 <name>DMA</name> 3886 <description>DMA Reset.</description> 3887 <bitOffset>0</bitOffset> 3888 <bitWidth>1</bitWidth> 3889 <enumeratedValues> 3890 <name>reset</name> 3891 <usage>read-write</usage> 3892 <enumeratedValue> 3893 <name>reset_done</name> 3894 <description>Reset complete.</description> 3895 <value>0</value> 3896 </enumeratedValue> 3897 <enumeratedValue> 3898 <name>busy</name> 3899 <description>Starts Reset or indicates reset in progress.</description> 3900 <value>1</value> 3901 </enumeratedValue> 3902 </enumeratedValues> 3903 </field> 3904 <field derivedFrom="DMA"> 3905 <name>WDT0</name> 3906 <description>Watchdog Timer 0 Reset.</description> 3907 <bitOffset>1</bitOffset> 3908 <bitWidth>1</bitWidth> 3909 </field> 3910 <field derivedFrom="DMA"> 3911 <name>GPIO0</name> 3912 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 3913 <bitOffset>2</bitOffset> 3914 <bitWidth>1</bitWidth> 3915 </field> 3916 <field derivedFrom="DMA"> 3917 <name>GPIO1</name> 3918 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 3919 <bitOffset>3</bitOffset> 3920 <bitWidth>1</bitWidth> 3921 </field> 3922 <field derivedFrom="DMA"> 3923 <name>TMR0</name> 3924 <description>Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 3925 <bitOffset>5</bitOffset> 3926 <bitWidth>1</bitWidth> 3927 </field> 3928 <field derivedFrom="DMA"> 3929 <name>TMR1</name> 3930 <description>Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 3931 <bitOffset>6</bitOffset> 3932 <bitWidth>1</bitWidth> 3933 </field> 3934 <field derivedFrom="DMA"> 3935 <name>TMR2</name> 3936 <description>Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 3937 <bitOffset>7</bitOffset> 3938 <bitWidth>1</bitWidth> 3939 </field> 3940 <field derivedFrom="DMA"> 3941 <name>TMR3</name> 3942 <description>Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 3943 <bitOffset>8</bitOffset> 3944 <bitWidth>1</bitWidth> 3945 </field> 3946 <field derivedFrom="DMA"> 3947 <name>TMR4</name> 3948 <description>Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks.</description> 3949 <bitOffset>9</bitOffset> 3950 <bitWidth>1</bitWidth> 3951 </field> 3952 <field derivedFrom="DMA"> 3953 <name>TMR5</name> 3954 <description>Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks.</description> 3955 <bitOffset>10</bitOffset> 3956 <bitWidth>1</bitWidth> 3957 </field> 3958 <field derivedFrom="DMA"> 3959 <name>UART0</name> 3960 <description>UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 3961 <bitOffset>11</bitOffset> 3962 <bitWidth>1</bitWidth> 3963 </field> 3964 <field derivedFrom="DMA"> 3965 <name>UART1</name> 3966 <description>UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 3967 <bitOffset>12</bitOffset> 3968 <bitWidth>1</bitWidth> 3969 </field> 3970 <field derivedFrom="DMA"> 3971 <name>SPI0</name> 3972 <description>SPI 0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 3973 <bitOffset>13</bitOffset> 3974 <bitWidth>1</bitWidth> 3975 </field> 3976 <field derivedFrom="DMA"> 3977 <name>SPI1</name> 3978 <description>SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 3979 <bitOffset>14</bitOffset> 3980 <bitWidth>1</bitWidth> 3981 </field> 3982 <field derivedFrom="DMA"> 3983 <name>I2C0</name> 3984 <description>I2C 0 Reset.</description> 3985 <bitOffset>16</bitOffset> 3986 <bitWidth>1</bitWidth> 3987 </field> 3988 <field derivedFrom="DMA"> 3989 <name>CRYPTO</name> 3990 <description>Crypto Reset.</description> 3991 <bitOffset>18</bitOffset> 3992 <bitWidth>1</bitWidth> 3993 </field> 3994 <field derivedFrom="DMA"> 3995 <name>USB</name> 3996 <description>USB Reset.</description> 3997 <bitOffset>23</bitOffset> 3998 <bitWidth>1</bitWidth> 3999 </field> 4000 <field derivedFrom="DMA"> 4001 <name>TRNG</name> 4002 <description>TRNG Reset.</description> 4003 <bitOffset>24</bitOffset> 4004 <bitWidth>1</bitWidth> 4005 </field> 4006 <field derivedFrom="DMA"> 4007 <name>ADC</name> 4008 <description>ADC Reset.</description> 4009 <bitOffset>26</bitOffset> 4010 <bitWidth>1</bitWidth> 4011 </field> 4012 <field derivedFrom="DMA"> 4013 <name>UART2</name> 4014 <description>UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.</description> 4015 <bitOffset>28</bitOffset> 4016 <bitWidth>1</bitWidth> 4017 </field> 4018 <field derivedFrom="DMA"> 4019 <name>SOFT</name> 4020 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 4021 <bitOffset>29</bitOffset> 4022 <bitWidth>1</bitWidth> 4023 </field> 4024 <field derivedFrom="DMA"> 4025 <name>PERIPH</name> 4026 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 4027 <bitOffset>30</bitOffset> 4028 <bitWidth>1</bitWidth> 4029 </field> 4030 <field derivedFrom="DMA"> 4031 <name>SYS</name> 4032 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 4033 <bitOffset>31</bitOffset> 4034 <bitWidth>1</bitWidth> 4035 </field> 4036 </fields> 4037 </register> 4038 <register> 4039 <name>CLKCTRL</name> 4040 <description>Clock Control.</description> 4041 <addressOffset>0x08</addressOffset> 4042 <resetValue>0x00000008</resetValue> 4043 <fields> 4044 <field> 4045 <name>PCLK_DIV</name> 4046 <description>PCLK Divider.</description> 4047 <bitOffset>3</bitOffset> 4048 <bitWidth>3</bitWidth> 4049 <enumeratedValues> 4050 <enumeratedValue> 4051 <name>div1</name> 4052 <description>Divide by 1.</description> 4053 <value>0</value> 4054 </enumeratedValue> 4055 <enumeratedValue> 4056 <name>div2</name> 4057 <description>Divide by 2.</description> 4058 <value>1</value> 4059 </enumeratedValue> 4060 <enumeratedValue> 4061 <name>div4</name> 4062 <description>Divide by 4.</description> 4063 <value>2</value> 4064 </enumeratedValue> 4065 <enumeratedValue> 4066 <name>div8</name> 4067 <description>Divide by 8.</description> 4068 <value>3</value> 4069 </enumeratedValue> 4070 </enumeratedValues> 4071 </field> 4072 <field> 4073 <name>SYSCLK_DIV</name> 4074 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 4075 <bitOffset>6</bitOffset> 4076 <bitWidth>3</bitWidth> 4077 <enumeratedValues> 4078 <enumeratedValue> 4079 <name>div1</name> 4080 <description>Divide by 1.</description> 4081 <value>0</value> 4082 </enumeratedValue> 4083 <enumeratedValue> 4084 <name>div2</name> 4085 <description>Divide by 2.</description> 4086 <value>1</value> 4087 </enumeratedValue> 4088 <enumeratedValue> 4089 <name>div4</name> 4090 <description>Divide by 4.</description> 4091 <value>2</value> 4092 </enumeratedValue> 4093 <enumeratedValue> 4094 <name>div8</name> 4095 <description>Divide by 8.</description> 4096 <value>3</value> 4097 </enumeratedValue> 4098 <enumeratedValue> 4099 <name>div16</name> 4100 <description>Divide by 16.</description> 4101 <value>4</value> 4102 </enumeratedValue> 4103 <enumeratedValue> 4104 <name>div32</name> 4105 <description>Divide by 32.</description> 4106 <value>5</value> 4107 </enumeratedValue> 4108 <enumeratedValue> 4109 <name>div64</name> 4110 <description>Divide by 64.</description> 4111 <value>6</value> 4112 </enumeratedValue> 4113 <enumeratedValue> 4114 <name>div128</name> 4115 <description>Divide by 128.</description> 4116 <value>7</value> 4117 </enumeratedValue> 4118 </enumeratedValues> 4119 </field> 4120 <field> 4121 <name>SYSCLK_SEL</name> 4122 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 4123 <bitOffset>9</bitOffset> 4124 <bitWidth>3</bitWidth> 4125 <enumeratedValues> 4126 <enumeratedValue> 4127 <name>ISO</name> 4128 <description>The internal 60 MHz oscillator is used for the system clock.</description> 4129 <value>0</value> 4130 </enumeratedValue> 4131 <enumeratedValue> 4132 <name>ERFO</name> 4133 <description>The external 32 MHz input is used for the system clock.</description> 4134 <value>2</value> 4135 </enumeratedValue> 4136 <enumeratedValue> 4137 <name>INRO</name> 4138 <description>8 kHz LIRC is used for the system clock.</description> 4139 <value>3</value> 4140 </enumeratedValue> 4141 <enumeratedValue> 4142 <name>IPO</name> 4143 <description>The internal 100 MHz oscillator is used for the system clock.</description> 4144 <value>4</value> 4145 </enumeratedValue> 4146 <enumeratedValue> 4147 <name>IBRO</name> 4148 <description>The internal 7.3725 MHz oscillator is used for the system clock.</description> 4149 <value>5</value> 4150 </enumeratedValue> 4151 <enumeratedValue> 4152 <name>ERTCO</name> 4153 <description>External 32 kHz input is used for the system clock.</description> 4154 <value>6</value> 4155 </enumeratedValue> 4156 </enumeratedValues> 4157 </field> 4158 <field> 4159 <name>CRYPTOCLK_DIV</name> 4160 <description>Cryptographic clock divider</description> 4161 <bitOffset>12</bitOffset> 4162 <bitWidth>1</bitWidth> 4163 <enumeratedValues> 4164 <enumeratedValue> 4165 <name>non_div</name> 4166 <description>The cryptographic accelerator clock is running in non-divided mode.</description> 4167 <value>0</value> 4168 </enumeratedValue> 4169 <enumeratedValue> 4170 <name>div</name> 4171 <description>The cryptographic accelerator clock is running in divided mode.</description> 4172 <value>1</value> 4173 </enumeratedValue> 4174 </enumeratedValues> 4175 </field> 4176 <field> 4177 <name>SYSCLK_RDY</name> 4178 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 4179 <bitOffset>13</bitOffset> 4180 <bitWidth>1</bitWidth> 4181 <access>read-only</access> 4182 <enumeratedValues> 4183 <enumeratedValue> 4184 <name>busy</name> 4185 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 4186 <value>0</value> 4187 </enumeratedValue> 4188 <enumeratedValue> 4189 <name>ready</name> 4190 <description>System clock running from CLKSEL clock source.</description> 4191 <value>1</value> 4192 </enumeratedValue> 4193 </enumeratedValues> 4194 </field> 4195 <field> 4196 <name>IPO_DIV</name> 4197 <description>IPO Divider.</description> 4198 <bitOffset>14</bitOffset> 4199 <bitWidth>2</bitWidth> 4200 <enumeratedValues> 4201 <enumeratedValue> 4202 <name>DIV1</name> 4203 <description>Divide by 1.</description> 4204 <value>0</value> 4205 </enumeratedValue> 4206 <enumeratedValue> 4207 <name>DIV2</name> 4208 <description>Divide by 2.</description> 4209 <value>1</value> 4210 </enumeratedValue> 4211 <enumeratedValue> 4212 <name>DIV4</name> 4213 <description>Divide by 4.</description> 4214 <value>2</value> 4215 </enumeratedValue> 4216 <enumeratedValue> 4217 <name>DIV8</name> 4218 <description>Divide by 8.</description> 4219 <value>3</value> 4220 </enumeratedValue> 4221 </enumeratedValues> 4222 </field> 4223 <field> 4224 <name>ERFO_EN</name> 4225 <description>27 MHz Crystal Oscillator Enable.</description> 4226 <bitOffset>16</bitOffset> 4227 <bitWidth>1</bitWidth> 4228 <enumeratedValues> 4229 <enumeratedValue> 4230 <name>dis</name> 4231 <description>Is Disabled.</description> 4232 <value>0</value> 4233 </enumeratedValue> 4234 <enumeratedValue> 4235 <name>en</name> 4236 <description>Is Enabled.</description> 4237 <value>1</value> 4238 </enumeratedValue> 4239 </enumeratedValues> 4240 </field> 4241 <field derivedFrom="ERFO_EN"> 4242 <name>ISO_EN</name> 4243 <description>60 MHz Internal Oscillator Enable.</description> 4244 <bitOffset>18</bitOffset> 4245 <bitWidth>1</bitWidth> 4246 </field> 4247 <field derivedFrom="ERFO_EN"> 4248 <name>IPO_EN</name> 4249 <description>100 MHz Clock Enable.</description> 4250 <bitOffset>19</bitOffset> 4251 <bitWidth>1</bitWidth> 4252 </field> 4253 <field derivedFrom="ERFO_EN"> 4254 <name>IBRO_EN</name> 4255 <description>7.3725 MHz Clock Enable.</description> 4256 <bitOffset>20</bitOffset> 4257 <bitWidth>1</bitWidth> 4258 </field> 4259 <field> 4260 <name>IBRO_VS</name> 4261 <description>7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO.</description> 4262 <bitOffset>21</bitOffset> 4263 <bitWidth>1</bitWidth> 4264 <enumeratedValues> 4265 <enumeratedValue> 4266 <name>Vcor</name> 4267 <description>VCore Supply</description> 4268 <value>0</value> 4269 </enumeratedValue> 4270 <enumeratedValue> 4271 <name>1V</name> 4272 <description>Dedicated 1V regulated supply.</description> 4273 <value>1</value> 4274 </enumeratedValue> 4275 </enumeratedValues> 4276 </field> 4277 <field> 4278 <name>ERFO_RDY</name> 4279 <description>32 MHz Oscillator Ready</description> 4280 <bitOffset>24</bitOffset> 4281 <bitWidth>1</bitWidth> 4282 <access>read-only</access> 4283 <enumeratedValues> 4284 <enumeratedValue> 4285 <name>not</name> 4286 <description>Is not Ready.</description> 4287 <value>0</value> 4288 </enumeratedValue> 4289 <enumeratedValue> 4290 <name>ready</name> 4291 <description>Is Ready.</description> 4292 <value>1</value> 4293 </enumeratedValue> 4294 </enumeratedValues> 4295 </field> 4296 <field derivedFrom="ERFO_RDY"> 4297 <name>ERTCO_RDY</name> 4298 <description>32 kHz Crystal Oscillator Ready</description> 4299 <bitOffset>25</bitOffset> 4300 <bitWidth>1</bitWidth> 4301 </field> 4302 <field derivedFrom="ERFO_RDY"> 4303 <name>ISO_RDY</name> 4304 <description>60 MHz Oscillator Ready.</description> 4305 <bitOffset>26</bitOffset> 4306 <bitWidth>1</bitWidth> 4307 </field> 4308 <field derivedFrom="ERFO_RDY"> 4309 <name>IPO_RDY</name> 4310 <description>100 MHz Clock Ready.</description> 4311 <bitOffset>27</bitOffset> 4312 <bitWidth>1</bitWidth> 4313 </field> 4314 <field derivedFrom="ERFO_RDY"> 4315 <name>IBRO_RDY</name> 4316 <description>7.3725 MHz HIRC Ready.</description> 4317 <bitOffset>28</bitOffset> 4318 <bitWidth>1</bitWidth> 4319 </field> 4320 <field derivedFrom="ERFO_RDY"> 4321 <name>INRO_RDY</name> 4322 <description>8 kHz Low Frequency Reference Clock Ready.</description> 4323 <bitOffset>29</bitOffset> 4324 <bitWidth>1</bitWidth> 4325 </field> 4326 </fields> 4327 </register> 4328 <register> 4329 <name>PM</name> 4330 <description>Power Management.</description> 4331 <addressOffset>0x0C</addressOffset> 4332 <fields> 4333 <field> 4334 <name>MODE</name> 4335 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 4336 <bitOffset>0</bitOffset> 4337 <bitWidth>3</bitWidth> 4338 <enumeratedValues> 4339 <enumeratedValue> 4340 <name>active</name> 4341 <description>Active Mode.</description> 4342 <value>0</value> 4343 </enumeratedValue> 4344 <enumeratedValue> 4345 <name>sleep</name> 4346 <description>Sleep Mode.</description> 4347 <value>1</value> 4348 </enumeratedValue> 4349 <enumeratedValue> 4350 <name>deepsleep</name> 4351 <description>DeepSleep Mode.</description> 4352 <value>2</value> 4353 </enumeratedValue> 4354 <enumeratedValue> 4355 <name>shutdown</name> 4356 <description>ShutDown Mode.</description> 4357 <value>3</value> 4358 </enumeratedValue> 4359 <enumeratedValue> 4360 <name>backup</name> 4361 <description>Backup Mode.</description> 4362 <value>4</value> 4363 </enumeratedValue> 4364 </enumeratedValues> 4365 </field> 4366 <field> 4367 <name>GPIO_WE</name> 4368 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 4369 <bitOffset>4</bitOffset> 4370 <bitWidth>1</bitWidth> 4371 <enumeratedValues> 4372 <enumeratedValue> 4373 <name>dis</name> 4374 <description>Wake Up Disable.</description> 4375 <value>0</value> 4376 </enumeratedValue> 4377 <enumeratedValue> 4378 <name>en</name> 4379 <description>Wake Up Enable.</description> 4380 <value>1</value> 4381 </enumeratedValue> 4382 </enumeratedValues> 4383 </field> 4384 <field derivedFrom="GPIO_WE"> 4385 <name>RTC_WE</name> 4386 <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description> 4387 <bitOffset>5</bitOffset> 4388 <bitWidth>1</bitWidth> 4389 </field> 4390 <field derivedFrom="GPIO_WE"> 4391 <name>USB_WE</name> 4392 <description>USB Wake Up Enable. This bit enables USB IRQ as wakeup source</description> 4393 <bitOffset>6</bitOffset> 4394 <bitWidth>1</bitWidth> 4395 </field> 4396 <field> 4397 <name>ERFO_PD</name> 4398 <description>27 MHz power down. This bit selects the 27 MHz clock power state in DEEPSLEEP mode.</description> 4399 <bitOffset>12</bitOffset> 4400 <bitWidth>1</bitWidth> 4401 <enumeratedValues> 4402 <enumeratedValue> 4403 <name>active</name> 4404 <description>Mode is Active.</description> 4405 <value>0</value> 4406 </enumeratedValue> 4407 <enumeratedValue> 4408 <name>deepsleep</name> 4409 <description>Powered down in DEEPSLEEP.</description> 4410 <value>1</value> 4411 </enumeratedValue> 4412 </enumeratedValues> 4413 </field> 4414 <field derivedFrom="ERFO_PD"> 4415 <name>ISO_PD</name> 4416 <description>60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode.</description> 4417 <bitOffset>15</bitOffset> 4418 <bitWidth>1</bitWidth> 4419 </field> 4420 <field derivedFrom="ERFO_PD"> 4421 <name>IPO_PD</name> 4422 <description>100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. </description> 4423 <bitOffset>16</bitOffset> 4424 <bitWidth>1</bitWidth> 4425 </field> 4426 <field derivedFrom="ERFO_PD"> 4427 <name>IBRO_PD</name> 4428 <description>7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. </description> 4429 <bitOffset>17</bitOffset> 4430 <bitWidth>1</bitWidth> 4431 </field> 4432 <field> 4433 <name>ERFO_BP</name> 4434 <description>27MHz Oscillator Bypass.</description> 4435 <bitOffset>20</bitOffset> 4436 <bitWidth>1</bitWidth> 4437 </field> 4438 </fields> 4439 </register> 4440 <register> 4441 <name>PCLKDIV</name> 4442 <description>Peripheral Clock Divider.</description> 4443 <addressOffset>0x18</addressOffset> 4444 <resetValue>0x00000001</resetValue> 4445 <fields> 4446 <field> 4447 <name>SKBDFRQ</name> 4448 <description>GCR Frequency Indicator for Secure Keyboard.</description> 4449 <bitOffset>0</bitOffset> 4450 <bitWidth>3</bitWidth> 4451 </field> 4452 <field> 4453 <name>ADCFRQ</name> 4454 <description>ADC clock Frequency. These bits define the ADC clock frequency. fADC = fPCLK / (ADCFRQ)</description> 4455 <bitOffset>10</bitOffset> 4456 <bitWidth>4</bitWidth> 4457 </field> 4458 <field> 4459 <name>AONCLKDIV</name> 4460 <description>AON Clock Divider. These bits define the AON Domain Clock Divider.</description> 4461 <bitOffset>14</bitOffset> 4462 <bitWidth>2</bitWidth> 4463 <enumeratedValues> 4464 <enumeratedValue> 4465 <name>div4</name> 4466 <value>0</value> 4467 </enumeratedValue> 4468 <enumeratedValue> 4469 <name>div8</name> 4470 <value>1</value> 4471 </enumeratedValue> 4472 <enumeratedValue> 4473 <name>div16</name> 4474 <value>2</value> 4475 </enumeratedValue> 4476 <enumeratedValue> 4477 <name>div32</name> 4478 <value>3</value> 4479 </enumeratedValue> 4480 </enumeratedValues> 4481 </field> 4482 </fields> 4483 </register> 4484 <register> 4485 <name>PCLKDIS0</name> 4486 <description>Peripheral Clock Disable.</description> 4487 <addressOffset>0x24</addressOffset> 4488 <fields> 4489 <field> 4490 <name>GPIO0</name> 4491 <description>GPIO0 Clock Disable.</description> 4492 <bitOffset>0</bitOffset> 4493 <bitWidth>1</bitWidth> 4494 <enumeratedValues> 4495 <enumeratedValue> 4496 <name>en</name> 4497 <description>enable it.</description> 4498 <value>0</value> 4499 </enumeratedValue> 4500 <enumeratedValue> 4501 <name>dis</name> 4502 <description>disable it.</description> 4503 <value>1</value> 4504 </enumeratedValue> 4505 </enumeratedValues> 4506 </field> 4507 <field derivedFrom="GPIO0"> 4508 <name>GPIO1</name> 4509 <description>GPIO1 Clock Disable.</description> 4510 <bitOffset>1</bitOffset> 4511 <bitWidth>1</bitWidth> 4512 </field> 4513 <field derivedFrom="GPIO0"> 4514 <name>USB</name> 4515 <description>USB Clock Disable.</description> 4516 <bitOffset>3</bitOffset> 4517 <bitWidth>1</bitWidth> 4518 </field> 4519 <field derivedFrom="GPIO0"> 4520 <name>DMA</name> 4521 <description>DMA Clock Disable.</description> 4522 <bitOffset>5</bitOffset> 4523 <bitWidth>1</bitWidth> 4524 </field> 4525 <field derivedFrom="GPIO0"> 4526 <name>SPI0</name> 4527 <description>SPI 0 Clock Disable.</description> 4528 <bitOffset>6</bitOffset> 4529 <bitWidth>1</bitWidth> 4530 </field> 4531 <field derivedFrom="GPIO0"> 4532 <name>SPI1</name> 4533 <description>SPI 1 Clock Disable.</description> 4534 <bitOffset>7</bitOffset> 4535 <bitWidth>1</bitWidth> 4536 </field> 4537 <field derivedFrom="GPIO0"> 4538 <name>UART0</name> 4539 <description>UART 0 Clock Disable.</description> 4540 <bitOffset>9</bitOffset> 4541 <bitWidth>1</bitWidth> 4542 </field> 4543 <field derivedFrom="GPIO0"> 4544 <name>UART1</name> 4545 <description>UART 1 Clock Disable.</description> 4546 <bitOffset>10</bitOffset> 4547 <bitWidth>1</bitWidth> 4548 </field> 4549 <field derivedFrom="GPIO0"> 4550 <name>I2C0</name> 4551 <description>I2C 0 Clock Disable.</description> 4552 <bitOffset>13</bitOffset> 4553 <bitWidth>1</bitWidth> 4554 </field> 4555 <field derivedFrom="GPIO0"> 4556 <name>CRYPTO</name> 4557 <description>Crypto Clock Disable.</description> 4558 <bitOffset>14</bitOffset> 4559 <bitWidth>1</bitWidth> 4560 </field> 4561 <field derivedFrom="GPIO0"> 4562 <name>TMR0</name> 4563 <description>Timer 0 Clock Disable.</description> 4564 <bitOffset>15</bitOffset> 4565 <bitWidth>1</bitWidth> 4566 </field> 4567 <field derivedFrom="GPIO0"> 4568 <name>TMR1</name> 4569 <description>Timer 1 Clock Disable.</description> 4570 <bitOffset>16</bitOffset> 4571 <bitWidth>1</bitWidth> 4572 </field> 4573 <field derivedFrom="GPIO0"> 4574 <name>TMR2</name> 4575 <description>Timer 2 Clock Disable.</description> 4576 <bitOffset>17</bitOffset> 4577 <bitWidth>1</bitWidth> 4578 </field> 4579 <field derivedFrom="GPIO0"> 4580 <name>TMR3</name> 4581 <description>Timer 3 Clock Disable.</description> 4582 <bitOffset>18</bitOffset> 4583 <bitWidth>1</bitWidth> 4584 </field> 4585 <field derivedFrom="GPIO0"> 4586 <name>TMR4</name> 4587 <description>Timer 4 Clock Disable.</description> 4588 <bitOffset>19</bitOffset> 4589 <bitWidth>1</bitWidth> 4590 </field> 4591 <field derivedFrom="GPIO0"> 4592 <name>TMR5</name> 4593 <description>Timer 5 Clock Disable.</description> 4594 <bitOffset>20</bitOffset> 4595 <bitWidth>1</bitWidth> 4596 </field> 4597 <field derivedFrom="GPIO0"> 4598 <name>SKBD</name> 4599 <description>Secure Keypad Clock Disable.</description> 4600 <bitOffset>22</bitOffset> 4601 <bitWidth>1</bitWidth> 4602 </field> 4603 <field derivedFrom="GPIO0"> 4604 <name>ADC</name> 4605 <description>ADC Clock Disable.</description> 4606 <bitOffset>23</bitOffset> 4607 <bitWidth>1</bitWidth> 4608 </field> 4609 <field derivedFrom="GPIO0"> 4610 <name>HTMR0</name> 4611 <description>High Speed Timer 0 Clock Disable.</description> 4612 <bitOffset>26</bitOffset> 4613 <bitWidth>1</bitWidth> 4614 </field> 4615 <field derivedFrom="GPIO0"> 4616 <name>HTMR1</name> 4617 <description>High Speed Timer 1 Clock Disable.</description> 4618 <bitOffset>27</bitOffset> 4619 <bitWidth>1</bitWidth> 4620 </field> 4621 <field derivedFrom="GPIO0"> 4622 <name>I2C1</name> 4623 <description>I2C 1 Clock Disable.</description> 4624 <bitOffset>28</bitOffset> 4625 <bitWidth>1</bitWidth> 4626 </field> 4627 <field derivedFrom="GPIO0"> 4628 <name>PT</name> 4629 <description>Pluse Train Clock Disable.</description> 4630 <bitOffset>29</bitOffset> 4631 <bitWidth>1</bitWidth> 4632 </field> 4633 <field derivedFrom="GPIO0"> 4634 <name>SPIXIP</name> 4635 <description>SPI XIP Clock Disable.</description> 4636 <bitOffset>30</bitOffset> 4637 <bitWidth>1</bitWidth> 4638 </field> 4639 <field derivedFrom="GPIO0"> 4640 <name>SPIXIPC</name> 4641 <description>SPI XIPC Clock Disable.</description> 4642 <bitOffset>31</bitOffset> 4643 <bitWidth>1</bitWidth> 4644 </field> 4645 </fields> 4646 </register> 4647 <register> 4648 <name>MEMCTRL</name> 4649 <description>Memory Clock Control Register.</description> 4650 <addressOffset>0x28</addressOffset> 4651 <fields> 4652 <field> 4653 <name>FWS</name> 4654 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 4655 <bitOffset>0</bitOffset> 4656 <bitWidth>3</bitWidth> 4657 </field> 4658 <field> 4659 <name>RAM4_WS</name> 4660 <description>System RAM4 WS Select.</description> 4661 <bitOffset>4</bitOffset> 4662 <bitWidth>1</bitWidth> 4663 </field> 4664 <field> 4665 <name>RAM5_WS</name> 4666 <description>System RAM5 WS Select.</description> 4667 <bitOffset>5</bitOffset> 4668 <bitWidth>1</bitWidth> 4669 </field> 4670 <field> 4671 <name>RAM6_WS</name> 4672 <description>System RAM6 WS Select.</description> 4673 <bitOffset>6</bitOffset> 4674 <bitWidth>1</bitWidth> 4675 </field> 4676 <field> 4677 <name>ROM1_WS</name> 4678 <description>ROM1 WS Select.</description> 4679 <bitOffset>7</bitOffset> 4680 <bitWidth>1</bitWidth> 4681 </field> 4682 <field> 4683 <name>RAM0LS_EN</name> 4684 <description>System RAM 0 Light Sleep Mode.</description> 4685 <bitOffset>16</bitOffset> 4686 <bitWidth>1</bitWidth> 4687 <enumeratedValues> 4688 <enumeratedValue> 4689 <name>active</name> 4690 <description>RAM is active.</description> 4691 <value>0</value> 4692 </enumeratedValue> 4693 <enumeratedValue> 4694 <name>light_sleep</name> 4695 <description>RAM is in Light Sleep mode.</description> 4696 <value>1</value> 4697 </enumeratedValue> 4698 </enumeratedValues> 4699 </field> 4700 <field derivedFrom="RAM0LS_EN"> 4701 <name>RAM1LS_EN</name> 4702 <description>System RAM 1 Light Sleep Mode.</description> 4703 <bitOffset>17</bitOffset> 4704 <bitWidth>1</bitWidth> 4705 </field> 4706 <field derivedFrom="RAM0LS_EN"> 4707 <name>RAM2LS_EN</name> 4708 <description>System RAM 2 Light Sleep Mode.</description> 4709 <bitOffset>18</bitOffset> 4710 <bitWidth>1</bitWidth> 4711 </field> 4712 <field derivedFrom="RAM0LS_EN"> 4713 <name>RAM3LS_EN</name> 4714 <description>System RAM 3 Light Sleep Mode.</description> 4715 <bitOffset>19</bitOffset> 4716 <bitWidth>1</bitWidth> 4717 </field> 4718 <field derivedFrom="RAM0LS_EN"> 4719 <name>RAM4LS_EN</name> 4720 <description>System RAM 4 Light Sleep Mode.</description> 4721 <bitOffset>20</bitOffset> 4722 <bitWidth>1</bitWidth> 4723 </field> 4724 <field derivedFrom="RAM0LS_EN"> 4725 <name>RAM5LS_EN</name> 4726 <description>System RAM 5 Light Sleep Mode.</description> 4727 <bitOffset>21</bitOffset> 4728 <bitWidth>1</bitWidth> 4729 </field> 4730 <field derivedFrom="RAM0LS_EN"> 4731 <name>RAM6LS_EN</name> 4732 <description>System RAM 6 Light Sleep Mode.</description> 4733 <bitOffset>22</bitOffset> 4734 <bitWidth>1</bitWidth> 4735 </field> 4736 <field derivedFrom="RAM0LS_EN"> 4737 <name>ICCXIPLS_EN</name> 4738 <description>ICACHE-XIP RAM Light Sleep Mode.</description> 4739 <bitOffset>25</bitOffset> 4740 <bitWidth>1</bitWidth> 4741 </field> 4742 <field derivedFrom="RAM0LS_EN"> 4743 <name>CRYPTOLS_EN</name> 4744 <description>MEU RAM Light Sleep Mode.</description> 4745 <bitOffset>27</bitOffset> 4746 <bitWidth>1</bitWidth> 4747 </field> 4748 <field derivedFrom="RAM0LS_EN"> 4749 <name>USBLS_EN</name> 4750 <description>USB FIFO Light Sleep Mode.</description> 4751 <bitOffset>28</bitOffset> 4752 <bitWidth>1</bitWidth> 4753 </field> 4754 <field derivedFrom="RAM0LS_EN"> 4755 <name>ROM0LS_EN</name> 4756 <description>ROM0 Light Sleep Mode.</description> 4757 <bitOffset>29</bitOffset> 4758 <bitWidth>1</bitWidth> 4759 </field> 4760 <field derivedFrom="RAM0LS_EN"> 4761 <name>ROM1LS_EN</name> 4762 <description>ROM1 Light Sleep Mode.</description> 4763 <bitOffset>30</bitOffset> 4764 <bitWidth>1</bitWidth> 4765 </field> 4766 <field derivedFrom="RAM0LS_EN"> 4767 <name>MAALS_EN</name> 4768 <description>MAA Light Sleep Mode.</description> 4769 <bitOffset>31</bitOffset> 4770 <bitWidth>1</bitWidth> 4771 </field> 4772 </fields> 4773 </register> 4774 <register> 4775 <name>MEMZ</name> 4776 <description>Memory Zeroize Control.</description> 4777 <addressOffset>0x2C</addressOffset> 4778 <fields> 4779 <field> 4780 <name>RAM0</name> 4781 <description>System RAM Block 0 Zeroization.</description> 4782 <bitOffset>0</bitOffset> 4783 <bitWidth>1</bitWidth> 4784 <enumeratedValues> 4785 <enumeratedValue> 4786 <name>nop</name> 4787 <description>No operation/complete.</description> 4788 <value>0</value> 4789 </enumeratedValue> 4790 <enumeratedValue> 4791 <name>start</name> 4792 <description>Start operation.</description> 4793 <value>1</value> 4794 </enumeratedValue> 4795 </enumeratedValues> 4796 </field> 4797 <field derivedFrom="RAM0"> 4798 <name>RAM1</name> 4799 <description>System RAM Block 1 Zeroization.</description> 4800 <bitOffset>1</bitOffset> 4801 <bitWidth>1</bitWidth> 4802 </field> 4803 <field derivedFrom="RAM0"> 4804 <name>RAM2</name> 4805 <description>System RAM Block 2 Zeroization.</description> 4806 <bitOffset>2</bitOffset> 4807 <bitWidth>1</bitWidth> 4808 </field> 4809 <field derivedFrom="RAM0"> 4810 <name>RAM3</name> 4811 <description>System RAM Block 3 Zeroization.</description> 4812 <bitOffset>3</bitOffset> 4813 <bitWidth>1</bitWidth> 4814 </field> 4815 <field derivedFrom="RAM0"> 4816 <name>RAM4</name> 4817 <description>System RAM Block 4 Zeroization.</description> 4818 <bitOffset>4</bitOffset> 4819 <bitWidth>1</bitWidth> 4820 </field> 4821 <field derivedFrom="RAM0"> 4822 <name>RAM5</name> 4823 <description>System RAM Block 5 Zeroization.</description> 4824 <bitOffset>5</bitOffset> 4825 <bitWidth>1</bitWidth> 4826 </field> 4827 <field derivedFrom="RAM0"> 4828 <name>RAM6</name> 4829 <description>System RAM Block 6 Zeroization.</description> 4830 <bitOffset>6</bitOffset> 4831 <bitWidth>1</bitWidth> 4832 </field> 4833 <field derivedFrom="RAM0"> 4834 <name>ICCXIP</name> 4835 <description>Internal ICC XIP Data and Tag RAM Zeroization.</description> 4836 <bitOffset>9</bitOffset> 4837 <bitWidth>1</bitWidth> 4838 </field> 4839 <field derivedFrom="RAM0"> 4840 <name>CRYPTO</name> 4841 <description>MEU Memory Zeroization.</description> 4842 <bitOffset>12</bitOffset> 4843 <bitWidth>1</bitWidth> 4844 </field> 4845 <field derivedFrom="RAM0"> 4846 <name>USBFIFO</name> 4847 <description>USB FIFO Zeroization.</description> 4848 <bitOffset>13</bitOffset> 4849 <bitWidth>1</bitWidth> 4850 </field> 4851 </fields> 4852 </register> 4853 <register> 4854 <name>SCCLKCTRL</name> 4855 <description>Smart Card Clock Control.</description> 4856 <addressOffset>0x34</addressOffset> 4857 <resetValue>0x00000000</resetValue> 4858 <fields> 4859 <field> 4860 <name>SC0CLK_DIV</name> 4861 <description>Smart Card0 Clock Divider</description> 4862 <bitOffset>0</bitOffset> 4863 <bitWidth>6</bitWidth> 4864 </field> 4865 <field> 4866 <name>SC1CLK_DIV</name> 4867 <description>Smart Card1 Clock Divider</description> 4868 <bitOffset>8</bitOffset> 4869 <bitWidth>6</bitWidth> 4870 </field> 4871 </fields> 4872 </register> 4873 <register> 4874 <name>SYSST</name> 4875 <description>System Status Register.</description> 4876 <addressOffset>0x40</addressOffset> 4877 <fields> 4878 <field> 4879 <name>ICELOCK</name> 4880 <description>ARM ICE Lock Status.</description> 4881 <bitOffset>0</bitOffset> 4882 <bitWidth>1</bitWidth> 4883 <enumeratedValues> 4884 <enumeratedValue> 4885 <name>unlocked</name> 4886 <description>ICE is unlocked.</description> 4887 <value>0</value> 4888 </enumeratedValue> 4889 <enumeratedValue> 4890 <name>locked</name> 4891 <description>ICE is locked.</description> 4892 <value>1</value> 4893 </enumeratedValue> 4894 </enumeratedValues> 4895 </field> 4896 <field> 4897 <name>CODEINTERR</name> 4898 <description>Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. </description> 4899 <bitOffset>1</bitOffset> 4900 <bitWidth>1</bitWidth> 4901 <enumeratedValues> 4902 <enumeratedValue> 4903 <name>norm</name> 4904 <description>Normal Operating Condition.</description> 4905 <value>0</value> 4906 </enumeratedValue> 4907 <enumeratedValue> 4908 <name>code</name> 4909 <description>Code Integrity Error.</description> 4910 <value>1</value> 4911 </enumeratedValue> 4912 </enumeratedValues> 4913 </field> 4914 <field> 4915 <name>SCMEMF</name> 4916 <description>System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.</description> 4917 <bitOffset>5</bitOffset> 4918 <bitWidth>1</bitWidth> 4919 <enumeratedValues> 4920 <enumeratedValue> 4921 <name>norm</name> 4922 <description>Normal Operating Condition.</description> 4923 <value>0</value> 4924 </enumeratedValue> 4925 <enumeratedValue> 4926 <name>memory</name> 4927 <description>Memory Fault.</description> 4928 <value>1</value> 4929 </enumeratedValue> 4930 </enumeratedValues> 4931 </field> 4932 </fields> 4933 </register> 4934 <register> 4935 <name>RST1</name> 4936 <description>Reset 1.</description> 4937 <addressOffset>0x44</addressOffset> 4938 <fields> 4939 <field> 4940 <name>I2C1</name> 4941 <description>I2C1 Reset.</description> 4942 <bitOffset>0</bitOffset> 4943 <bitWidth>1</bitWidth> 4944 <enumeratedValues> 4945 <name>reset_read</name> 4946 <usage>read</usage> 4947 <enumeratedValue> 4948 <name>reset_done</name> 4949 <description>Reset complete.</description> 4950 <value>0</value> 4951 </enumeratedValue> 4952 <enumeratedValue> 4953 <name>busy</name> 4954 <description>Starts reset or indicates reset in progress.</description> 4955 <value>1</value> 4956 </enumeratedValue> 4957 </enumeratedValues> 4958 </field> 4959 <field derivedFrom="I2C1"> 4960 <name>PT</name> 4961 <description>PT Reset.</description> 4962 <bitOffset>1</bitOffset> 4963 <bitWidth>1</bitWidth> 4964 </field> 4965 <field derivedFrom="I2C1"> 4966 <name>SPIXIP</name> 4967 <description>SPI XIPF Reset.</description> 4968 <bitOffset>3</bitOffset> 4969 <bitWidth>1</bitWidth> 4970 </field> 4971 <field derivedFrom="I2C1"> 4972 <name>SPIXIPM</name> 4973 <description>SPI XIP Master Reset.</description> 4974 <bitOffset>4</bitOffset> 4975 <bitWidth>1</bitWidth> 4976 </field> 4977 <field derivedFrom="I2C1"> 4978 <name>WDT1</name> 4979 <description>WDT1 Reset.</description> 4980 <bitOffset>8</bitOffset> 4981 <bitWidth>1</bitWidth> 4982 </field> 4983 <field derivedFrom="I2C1"> 4984 <name>SPI3</name> 4985 <description>SPI3 Reset.</description> 4986 <bitOffset>9</bitOffset> 4987 <bitWidth>1</bitWidth> 4988 </field> 4989 <field derivedFrom="I2C1"> 4990 <name>AC</name> 4991 <description>Auto-Cal Reset.</description> 4992 <bitOffset>14</bitOffset> 4993 <bitWidth>1</bitWidth> 4994 </field> 4995 <field derivedFrom="I2C1"> 4996 <name>SEMA</name> 4997 <description>Semaphore Reset.</description> 4998 <bitOffset>16</bitOffset> 4999 <bitWidth>1</bitWidth> 5000 </field> 5001 <field derivedFrom="I2C1"> 5002 <name>UART3</name> 5003 <description>UART3 Reset.</description> 5004 <bitOffset>18</bitOffset> 5005 <bitWidth>1</bitWidth> 5006 </field> 5007 <field derivedFrom="I2C1"> 5008 <name>SKBD</name> 5009 <description>SKBD Reset.</description> 5010 <bitOffset>21</bitOffset> 5011 <bitWidth>1</bitWidth> 5012 </field> 5013 <field derivedFrom="I2C1"> 5014 <name>MSRADC</name> 5015 <description>MSRADC Reset.</description> 5016 <bitOffset>22</bitOffset> 5017 <bitWidth>1</bitWidth> 5018 </field> 5019 <field derivedFrom="I2C1"> 5020 <name>SC0</name> 5021 <description>SC0 Reset.</description> 5022 <bitOffset>23</bitOffset> 5023 <bitWidth>1</bitWidth> 5024 </field> 5025 <field derivedFrom="I2C1"> 5026 <name>SC1</name> 5027 <description>SC1 Reset.</description> 5028 <bitOffset>24</bitOffset> 5029 <bitWidth>1</bitWidth> 5030 </field> 5031 <field derivedFrom="I2C1"> 5032 <name>HTMR0</name> 5033 <description>HTIMER0 Reset.</description> 5034 <bitOffset>28</bitOffset> 5035 <bitWidth>1</bitWidth> 5036 </field> 5037 <field derivedFrom="I2C1"> 5038 <name>HTMR1</name> 5039 <description>HTIMER1 Reset.</description> 5040 <bitOffset>29</bitOffset> 5041 <bitWidth>1</bitWidth> 5042 </field> 5043 <field derivedFrom="I2C1"> 5044 <name>CPU1</name> 5045 <description>CPU1 Reset.</description> 5046 <bitOffset>31</bitOffset> 5047 <bitWidth>1</bitWidth> 5048 </field> 5049 </fields> 5050 </register> 5051 <register> 5052 <name>PCLKDIS1</name> 5053 <description>Peripheral Clock Disable.</description> 5054 <addressOffset>0x48</addressOffset> 5055 <fields> 5056 <field> 5057 <name>UART2</name> 5058 <description>UART2 Clock Disable.</description> 5059 <bitOffset>1</bitOffset> 5060 <bitWidth>1</bitWidth> 5061 <enumeratedValues> 5062 <enumeratedValue> 5063 <name>en</name> 5064 <description>Clock enabled to the peripheral.</description> 5065 <value>0</value> 5066 </enumeratedValue> 5067 <enumeratedValue> 5068 <name>dis</name> 5069 <description>Clock disabled to the peripheral.</description> 5070 <value>1</value> 5071 </enumeratedValue> 5072 </enumeratedValues> 5073 </field> 5074 <field derivedFrom="UART2"> 5075 <name>TRNG</name> 5076 <description>TRNG Clock Disable.</description> 5077 <bitOffset>2</bitOffset> 5078 <bitWidth>1</bitWidth> 5079 </field> 5080 <field derivedFrom="UART2"> 5081 <name>OTP</name> 5082 <description>OTP Clock Disable.</description> 5083 <bitOffset>3</bitOffset> 5084 <bitWidth>1</bitWidth> 5085 </field> 5086 <field derivedFrom="UART2"> 5087 <name>WDT0</name> 5088 <description>Watchdog 0 Clock Disable.</description> 5089 <bitOffset>4</bitOffset> 5090 <bitWidth>1</bitWidth> 5091 </field> 5092 <field derivedFrom="UART2"> 5093 <name>WDT1</name> 5094 <description>Watchdog 1 Clock Disable.</description> 5095 <bitOffset>5</bitOffset> 5096 <bitWidth>1</bitWidth> 5097 </field> 5098 <field derivedFrom="UART2"> 5099 <name>SEMA</name> 5100 <description>Semaphore Disable.</description> 5101 <bitOffset>9</bitOffset> 5102 <bitWidth>1</bitWidth> 5103 </field> 5104 <field derivedFrom="UART2"> 5105 <name>SPI3</name> 5106 <description>SPI3 Clock Disable.</description> 5107 <bitOffset>14</bitOffset> 5108 <bitWidth>1</bitWidth> 5109 </field> 5110 <field derivedFrom="UART2"> 5111 <name>UART3</name> 5112 <description>UART3 Clock Disable.</description> 5113 <bitOffset>22</bitOffset> 5114 <bitWidth>1</bitWidth> 5115 </field> 5116 <field derivedFrom="UART2"> 5117 <name>MSRADC</name> 5118 <description>MSRADC Clock Disable.</description> 5119 <bitOffset>25</bitOffset> 5120 <bitWidth>1</bitWidth> 5121 </field> 5122 <field derivedFrom="UART2"> 5123 <name>SC0</name> 5124 <description>SC0 Clock Disable.</description> 5125 <bitOffset>26</bitOffset> 5126 <bitWidth>1</bitWidth> 5127 </field> 5128 <field derivedFrom="UART2"> 5129 <name>SC1</name> 5130 <description>SC1 Clock Disable.</description> 5131 <bitOffset>27</bitOffset> 5132 <bitWidth>1</bitWidth> 5133 </field> 5134 <field derivedFrom="UART2"> 5135 <name>CPU1</name> 5136 <description>CPU1 Clock Disable.</description> 5137 <bitOffset>31</bitOffset> 5138 <bitWidth>1</bitWidth> 5139 </field> 5140 </fields> 5141 </register> 5142 <register> 5143 <name>EVENTEN</name> 5144 <description>Event Enable Register.</description> 5145 <addressOffset>0x4C</addressOffset> 5146 <fields> 5147 <field> 5148 <name>DMA</name> 5149 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 5150 <bitOffset>0</bitOffset> 5151 <bitWidth>1</bitWidth> 5152 </field> 5153 <field> 5154 <name>RX</name> 5155 <description>Enable RXEV pin event. When this bit is set, RXEV event from the CPU is output to GPIO1.9.</description> 5156 <bitOffset>1</bitOffset> 5157 <bitWidth>1</bitWidth> 5158 </field> 5159 <field> 5160 <name>TX</name> 5161 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9.</description> 5162 <bitOffset>2</bitOffset> 5163 <bitWidth>1</bitWidth> 5164 </field> 5165 </fields> 5166 </register> 5167 <register> 5168 <name>REVISION</name> 5169 <description>Revision Register.</description> 5170 <addressOffset>0x50</addressOffset> 5171 <access>read-only</access> 5172 <fields> 5173 <field> 5174 <name>REVISION</name> 5175 <description>Manufacturer Chip Revision.</description> 5176 <bitOffset>0</bitOffset> 5177 <bitWidth>16</bitWidth> 5178 </field> 5179 </fields> 5180 </register> 5181 <register> 5182 <name>SYSIE</name> 5183 <description>System Status Interrupt Enable Register.</description> 5184 <addressOffset>0x54</addressOffset> 5185 <fields> 5186 <field> 5187 <name>ICEUNLOCK</name> 5188 <description>ARM ICE Unlock Interrupt Enable.</description> 5189 <bitOffset>0</bitOffset> 5190 <bitWidth>1</bitWidth> 5191 <enumeratedValues> 5192 <enumeratedValue> 5193 <name>dis</name> 5194 <description>disabled.</description> 5195 <value>0</value> 5196 </enumeratedValue> 5197 <enumeratedValue> 5198 <name>en</name> 5199 <description>enabled.</description> 5200 <value>1</value> 5201 </enumeratedValue> 5202 </enumeratedValues> 5203 </field> 5204 <field derivedFrom="ICEUNLOCK"> 5205 <name>CIE</name> 5206 <description>Code Integrity Error Interrupt Enable.</description> 5207 <bitOffset>1</bitOffset> 5208 <bitWidth>1</bitWidth> 5209 </field> 5210 <field derivedFrom="ICEUNLOCK"> 5211 <name>SCMF</name> 5212 <description>System Cache Memory Fault Interrupt Enable.</description> 5213 <bitOffset>5</bitOffset> 5214 <bitWidth>1</bitWidth> 5215 </field> 5216 </fields> 5217 </register> 5218 <register> 5219 <name>IPOCNT</name> 5220 <description>IPO Warmup Count Register.</description> 5221 <addressOffset>0x58</addressOffset> 5222 <fields> 5223 <field> 5224 <name>WMUPCNT</name> 5225 <description>TBD</description> 5226 <bitOffset>0</bitOffset> 5227 <bitWidth>10</bitWidth> 5228 </field> 5229 </fields> 5230 </register> 5231 </registers> 5232 </peripheral> 5233<!--GCR Global Control Registers.--> 5234 <peripheral> 5235 <name>GPIO0</name> 5236 <description>Individual I/O for each GPIO</description> 5237 <groupName>GPIO</groupName> 5238 <baseAddress>0x40008000</baseAddress> 5239 <addressBlock> 5240 <offset>0x00</offset> 5241 <size>0x1000</size> 5242 <usage>registers</usage> 5243 </addressBlock> 5244 <interrupt> 5245 <name>GPIO0</name> 5246 <description>GPIO0 interrupt.</description> 5247 <value>24</value> 5248 </interrupt> 5249 <registers> 5250 <register> 5251 <name>EN0</name> 5252 <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description> 5253 <addressOffset>0x00</addressOffset> 5254 <fields> 5255 <field> 5256 <name>ALL</name> 5257 <description>Mask of all of the pins on the port.</description> 5258 <bitOffset>0</bitOffset> 5259 <bitWidth>32</bitWidth> 5260 <enumeratedValues> 5261 <enumeratedValue> 5262 <name>ALTERNATE</name> 5263 <description>Alternate function enabled.</description> 5264 <value>0</value> 5265 </enumeratedValue> 5266 <enumeratedValue> 5267 <name>GPIO</name> 5268 <description>GPIO function is enabled.</description> 5269 <value>1</value> 5270 </enumeratedValue> 5271 </enumeratedValues> 5272 </field> 5273 </fields> 5274 </register> 5275 <register> 5276 <name>EN0_SET</name> 5277 <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description> 5278 <addressOffset>0x04</addressOffset> 5279 <fields> 5280 <field> 5281 <name>ALL</name> 5282 <description>Mask of all of the pins on the port.</description> 5283 <bitOffset>0</bitOffset> 5284 <bitWidth>32</bitWidth> 5285 </field> 5286 </fields> 5287 </register> 5288 <register> 5289 <name>EN0_CLR</name> 5290 <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description> 5291 <addressOffset>0x08</addressOffset> 5292 <fields> 5293 <field> 5294 <name>ALL</name> 5295 <description>Mask of all of the pins on the port.</description> 5296 <bitOffset>0</bitOffset> 5297 <bitWidth>32</bitWidth> 5298 </field> 5299 </fields> 5300 </register> 5301 <register> 5302 <name>OUTEN</name> 5303 <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description> 5304 <addressOffset>0x0C</addressOffset> 5305 <fields> 5306 <field> 5307 <name>ALL</name> 5308 <description>Mask of all of the pins on the port.</description> 5309 <bitOffset>0</bitOffset> 5310 <bitWidth>32</bitWidth> 5311 <enumeratedValues> 5312 <enumeratedValue> 5313 <name>dis</name> 5314 <description>GPIO Output Disable</description> 5315 <value>0</value> 5316 </enumeratedValue> 5317 <enumeratedValue> 5318 <name>en</name> 5319 <description>GPIO Output Enable</description> 5320 <value>1</value> 5321 </enumeratedValue> 5322 </enumeratedValues> 5323 </field> 5324 </fields> 5325 </register> 5326 <register> 5327 <name>OUTEN_SET</name> 5328 <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description> 5329 <addressOffset>0x10</addressOffset> 5330 <fields> 5331 <field> 5332 <name>ALL</name> 5333 <description>Mask of all of the pins on the port.</description> 5334 <bitOffset>0</bitOffset> 5335 <bitWidth>32</bitWidth> 5336 </field> 5337 </fields> 5338 </register> 5339 <register> 5340 <name>OUTEN_CLR</name> 5341 <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description> 5342 <addressOffset>0x14</addressOffset> 5343 <fields> 5344 <field> 5345 <name>ALL</name> 5346 <description>Mask of all of the pins on the port.</description> 5347 <bitOffset>0</bitOffset> 5348 <bitWidth>32</bitWidth> 5349 </field> 5350 </fields> 5351 </register> 5352 <register> 5353 <name>OUT</name> 5354 <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description> 5355 <addressOffset>0x18</addressOffset> 5356 <fields> 5357 <field> 5358 <name>ALL</name> 5359 <description>Mask of all of the pins on the port.</description> 5360 <bitOffset>0</bitOffset> 5361 <bitWidth>32</bitWidth> 5362 <enumeratedValues> 5363 <enumeratedValue> 5364 <name>low</name> 5365 <description>Drive Logic 0 (low) on GPIO output.</description> 5366 <value>0</value> 5367 </enumeratedValue> 5368 <enumeratedValue> 5369 <name>high</name> 5370 <description>Drive logic 1 (high) on GPIO output.</description> 5371 <value>1</value> 5372 </enumeratedValue> 5373 </enumeratedValues> 5374 </field> 5375 </fields> 5376 </register> 5377 <register> 5378 <name>OUT_SET</name> 5379 <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description> 5380 <addressOffset>0x1C</addressOffset> 5381 <access>write-only</access> 5382 <fields> 5383 <field> 5384 <name>ALL</name> 5385 <description>Mask of all of the pins on the port.</description> 5386 <bitOffset>0</bitOffset> 5387 <bitWidth>32</bitWidth> 5388 <enumeratedValues> 5389 <enumeratedValue> 5390 <name>no</name> 5391 <description>No Effect.</description> 5392 <value>0</value> 5393 </enumeratedValue> 5394 <enumeratedValue> 5395 <name>set</name> 5396 <description>Set GPIO_OUT bit in this position to '1'</description> 5397 <value>1</value> 5398 </enumeratedValue> 5399 </enumeratedValues> 5400 </field> 5401 </fields> 5402 </register> 5403 <register> 5404 <name>OUT_CLR</name> 5405 <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description> 5406 <addressOffset>0x20</addressOffset> 5407 <access>write-only</access> 5408 <fields> 5409 <field> 5410 <name>ALL</name> 5411 <description>Mask of all of the pins on the port.</description> 5412 <bitOffset>0</bitOffset> 5413 <bitWidth>32</bitWidth> 5414 </field> 5415 </fields> 5416 </register> 5417 <register> 5418 <name>IN</name> 5419 <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description> 5420 <addressOffset>0x24</addressOffset> 5421 <access>read-only</access> 5422 <fields> 5423 <field> 5424 <name>ALL</name> 5425 <description>Mask of all of the pins on the port.</description> 5426 <bitOffset>0</bitOffset> 5427 <bitWidth>32</bitWidth> 5428 </field> 5429 </fields> 5430 </register> 5431 <register> 5432 <name>INTMODE</name> 5433 <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description> 5434 <addressOffset>0x28</addressOffset> 5435 <fields> 5436 <field> 5437 <name>ALL</name> 5438 <description>Mask of all of the pins on the port.</description> 5439 <bitOffset>0</bitOffset> 5440 <bitWidth>32</bitWidth> 5441 <enumeratedValues> 5442 <enumeratedValue> 5443 <name>level</name> 5444 <description>Interrupts for this pin are level triggered.</description> 5445 <value>0</value> 5446 </enumeratedValue> 5447 <enumeratedValue> 5448 <name>edge</name> 5449 <description>Interrupts for this pin are edge triggered.</description> 5450 <value>1</value> 5451 </enumeratedValue> 5452 </enumeratedValues> 5453 </field> 5454 </fields> 5455 </register> 5456 <register> 5457 <name>INTPOL</name> 5458 <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description> 5459 <addressOffset>0x2C</addressOffset> 5460 <fields> 5461 <field> 5462 <name>ALL</name> 5463 <description>Mask of all of the pins on the port.</description> 5464 <bitOffset>0</bitOffset> 5465 <bitWidth>32</bitWidth> 5466 <enumeratedValues> 5467 <enumeratedValue> 5468 <name>falling</name> 5469 <description>Interrupts are latched on a falling edge or low level condition for this pin.</description> 5470 <value>0</value> 5471 </enumeratedValue> 5472 <enumeratedValue> 5473 <name>rising</name> 5474 <description>Interrupts are latched on a rising edge or high condition for this pin.</description> 5475 <value>1</value> 5476 </enumeratedValue> 5477 </enumeratedValues> 5478 </field> 5479 </fields> 5480 </register> 5481 <register> 5482 <name>INEN</name> 5483 <description>GPIO Input Enable</description> 5484 <addressOffset>0x30</addressOffset> 5485 </register> 5486 <register> 5487 <name>INTEN</name> 5488 <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description> 5489 <addressOffset>0x34</addressOffset> 5490 <fields> 5491 <field> 5492 <name>ALL</name> 5493 <description>Mask of all of the pins on the port.</description> 5494 <bitOffset>0</bitOffset> 5495 <bitWidth>32</bitWidth> 5496 <enumeratedValues> 5497 <enumeratedValue> 5498 <name>dis</name> 5499 <description>Interrupts are disabled for this GPIO pin.</description> 5500 <value>0</value> 5501 </enumeratedValue> 5502 <enumeratedValue> 5503 <name>en</name> 5504 <description>Interrupts are enabled for this GPIO pin.</description> 5505 <value>1</value> 5506 </enumeratedValue> 5507 </enumeratedValues> 5508 </field> 5509 </fields> 5510 </register> 5511 <register> 5512 <name>INTEN_SET</name> 5513 <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description> 5514 <addressOffset>0x38</addressOffset> 5515 <fields> 5516 <field> 5517 <name>ALL</name> 5518 <description>Mask of all of the pins on the port.</description> 5519 <bitOffset>0</bitOffset> 5520 <bitWidth>32</bitWidth> 5521 <enumeratedValues> 5522 <enumeratedValue> 5523 <name>no</name> 5524 <description>No effect.</description> 5525 <value>0</value> 5526 </enumeratedValue> 5527 <enumeratedValue> 5528 <name>set</name> 5529 <description>Set GPIO_INT_EN bit in this position to '1'</description> 5530 <value>1</value> 5531 </enumeratedValue> 5532 </enumeratedValues> 5533 </field> 5534 </fields> 5535 </register> 5536 <register> 5537 <name>INTEN_CLR</name> 5538 <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description> 5539 <addressOffset>0x3C</addressOffset> 5540 <fields> 5541 <field> 5542 <name>ALL</name> 5543 <description>Mask of all of the pins on the port.</description> 5544 <bitOffset>0</bitOffset> 5545 <bitWidth>32</bitWidth> 5546 <enumeratedValues> 5547 <enumeratedValue> 5548 <name>no</name> 5549 <description>No Effect.</description> 5550 <value>0</value> 5551 </enumeratedValue> 5552 <enumeratedValue> 5553 <name>clear</name> 5554 <description>Clear GPIO_INT_EN bit in this position to '0'</description> 5555 <value>1</value> 5556 </enumeratedValue> 5557 </enumeratedValues> 5558 </field> 5559 </fields> 5560 </register> 5561 <register> 5562 <name>INTFL</name> 5563 <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description> 5564 <addressOffset>0x40</addressOffset> 5565 <access>read-only</access> 5566 <fields> 5567 <field> 5568 <name>ALL</name> 5569 <description>Mask of all of the pins on the port.</description> 5570 <bitOffset>0</bitOffset> 5571 <bitWidth>32</bitWidth> 5572 <enumeratedValues> 5573 <enumeratedValue> 5574 <name>no</name> 5575 <description>No Interrupt is pending on this GPIO pin.</description> 5576 <value>0</value> 5577 </enumeratedValue> 5578 <enumeratedValue> 5579 <name>pending</name> 5580 <description>An Interrupt is pending on this GPIO pin.</description> 5581 <value>1</value> 5582 </enumeratedValue> 5583 </enumeratedValues> 5584 </field> 5585 </fields> 5586 </register> 5587 <register> 5588 <name>INTFL_CLR</name> 5589 <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description> 5590 <addressOffset>0x48</addressOffset> 5591 <fields> 5592 <field> 5593 <name>ALL</name> 5594 <description>Mask of all of the pins on the port.</description> 5595 <bitOffset>0</bitOffset> 5596 <bitWidth>32</bitWidth> 5597 </field> 5598 </fields> 5599 </register> 5600 <register> 5601 <name>WKEN</name> 5602 <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description> 5603 <addressOffset>0x4C</addressOffset> 5604 <fields> 5605 <field> 5606 <name>ALL</name> 5607 <description>Mask of all of the pins on the port.</description> 5608 <bitOffset>0</bitOffset> 5609 <bitWidth>32</bitWidth> 5610 <enumeratedValues> 5611 <enumeratedValue> 5612 <name>dis</name> 5613 <description>PMU wakeup for this GPIO is disabled.</description> 5614 <value>0</value> 5615 </enumeratedValue> 5616 <enumeratedValue> 5617 <name>en</name> 5618 <description>PMU wakeup for this GPIO is enabled.</description> 5619 <value>1</value> 5620 </enumeratedValue> 5621 </enumeratedValues> 5622 </field> 5623 </fields> 5624 </register> 5625 <register> 5626 <name>WKEN_SET</name> 5627 <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description> 5628 <addressOffset>0x50</addressOffset> 5629 <fields> 5630 <field> 5631 <name>ALL</name> 5632 <description>Mask of all of the pins on the port.</description> 5633 <bitOffset>0</bitOffset> 5634 <bitWidth>32</bitWidth> 5635 </field> 5636 </fields> 5637 </register> 5638 <register> 5639 <name>WKEN_CLR</name> 5640 <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description> 5641 <addressOffset>0x54</addressOffset> 5642 <fields> 5643 <field> 5644 <name>ALL</name> 5645 <description>Mask of all of the pins on the port.</description> 5646 <bitOffset>0</bitOffset> 5647 <bitWidth>32</bitWidth> 5648 </field> 5649 </fields> 5650 </register> 5651 <register> 5652 <name>DUALEDGE</name> 5653 <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description> 5654 <addressOffset>0x5C</addressOffset> 5655 <fields> 5656 <field> 5657 <name>ALL</name> 5658 <description>Mask of all of the pins on the port.</description> 5659 <bitOffset>0</bitOffset> 5660 <bitWidth>32</bitWidth> 5661 <enumeratedValues> 5662 <enumeratedValue> 5663 <name>no</name> 5664 <description>No Effect.</description> 5665 <value>0</value> 5666 </enumeratedValue> 5667 <enumeratedValue> 5668 <name>en</name> 5669 <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description> 5670 <value>1</value> 5671 </enumeratedValue> 5672 </enumeratedValues> 5673 </field> 5674 </fields> 5675 </register> 5676 <register> 5677 <name>PADCTRL0</name> 5678 <description>GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 5679 <addressOffset>0x60</addressOffset> 5680 <fields> 5681 <field> 5682 <name>ALL</name> 5683 <description>The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 5684 <bitOffset>0</bitOffset> 5685 <bitWidth>32</bitWidth> 5686 <enumeratedValues> 5687 <enumeratedValue> 5688 <name>impedance</name> 5689 <description>High Impedance.</description> 5690 <value>0</value> 5691 </enumeratedValue> 5692 <enumeratedValue> 5693 <name>pu</name> 5694 <description>Weak pull-up mode.</description> 5695 <value>1</value> 5696 </enumeratedValue> 5697 <enumeratedValue> 5698 <name>pd</name> 5699 <description>weak pull-down mode.</description> 5700 <value>2</value> 5701 </enumeratedValue> 5702 </enumeratedValues> 5703 </field> 5704 </fields> 5705 </register> 5706 <register> 5707 <name>PADCTRL1</name> 5708 <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 5709 <addressOffset>0x64</addressOffset> 5710 <fields> 5711 <field> 5712 <name>ALL</name> 5713 <description>The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 5714 <bitOffset>0</bitOffset> 5715 <bitWidth>32</bitWidth> 5716 <enumeratedValues> 5717 <enumeratedValue> 5718 <name>impedance</name> 5719 <description>High Impedance.</description> 5720 <value>0</value> 5721 </enumeratedValue> 5722 <enumeratedValue> 5723 <name>pu</name> 5724 <description>Weak pull-up mode.</description> 5725 <value>1</value> 5726 </enumeratedValue> 5727 <enumeratedValue> 5728 <name>pd</name> 5729 <description>weak pull-down mode.</description> 5730 <value>2</value> 5731 </enumeratedValue> 5732 </enumeratedValues> 5733 </field> 5734 </fields> 5735 </register> 5736 <register> 5737 <name>EN1</name> 5738 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 5739 <addressOffset>0x68</addressOffset> 5740 <fields> 5741 <field> 5742 <name>ALL</name> 5743 <description>Mask of all of the pins on the port.</description> 5744 <bitOffset>0</bitOffset> 5745 <bitWidth>32</bitWidth> 5746 <enumeratedValues> 5747 <enumeratedValue> 5748 <name>primary</name> 5749 <description>Primary function selected.</description> 5750 <value>0</value> 5751 </enumeratedValue> 5752 <enumeratedValue> 5753 <name>secondary</name> 5754 <description>Secondary function selected.</description> 5755 <value>1</value> 5756 </enumeratedValue> 5757 </enumeratedValues> 5758 </field> 5759 </fields> 5760 </register> 5761 <register> 5762 <name>EN1_SET</name> 5763 <description>GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description> 5764 <addressOffset>0x6C</addressOffset> 5765 <fields> 5766 <field> 5767 <name>ALL</name> 5768 <description>Mask of all of the pins on the port.</description> 5769 <bitOffset>0</bitOffset> 5770 <bitWidth>32</bitWidth> 5771 </field> 5772 </fields> 5773 </register> 5774 <register> 5775 <name>EN1_CLR</name> 5776 <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description> 5777 <addressOffset>0x70</addressOffset> 5778 <fields> 5779 <field> 5780 <name>ALL</name> 5781 <description>Mask of all of the pins on the port.</description> 5782 <bitOffset>0</bitOffset> 5783 <bitWidth>32</bitWidth> 5784 </field> 5785 </fields> 5786 </register> 5787 <register> 5788 <name>EN2</name> 5789 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 5790 <addressOffset>0x74</addressOffset> 5791 <fields> 5792 <field> 5793 <name>ALL</name> 5794 <description>Mask of all of the pins on the port.</description> 5795 <bitOffset>0</bitOffset> 5796 <bitWidth>32</bitWidth> 5797 <enumeratedValues> 5798 <enumeratedValue> 5799 <name>primary</name> 5800 <description>Primary function selected.</description> 5801 <value>0</value> 5802 </enumeratedValue> 5803 <enumeratedValue> 5804 <name>secondary</name> 5805 <description>Secondary function selected.</description> 5806 <value>1</value> 5807 </enumeratedValue> 5808 </enumeratedValues> 5809 </field> 5810 </fields> 5811 </register> 5812 <register> 5813 <name>EN2_SET</name> 5814 <description>GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.</description> 5815 <addressOffset>0x78</addressOffset> 5816 <fields> 5817 <field> 5818 <name>ALL</name> 5819 <description>Mask of all of the pins on the port.</description> 5820 <bitOffset>0</bitOffset> 5821 <bitWidth>32</bitWidth> 5822 </field> 5823 </fields> 5824 </register> 5825 <register> 5826 <name>EN2_CLR</name> 5827 <description>GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.</description> 5828 <addressOffset>0x7C</addressOffset> 5829 <fields> 5830 <field> 5831 <name>ALL</name> 5832 <description>Mask of all of the pins on the port.</description> 5833 <bitOffset>0</bitOffset> 5834 <bitWidth>32</bitWidth> 5835 </field> 5836 </fields> 5837 </register> 5838 <register> 5839 <name>HYSEN</name> 5840 <description>GPIO Input Hysteresis Enable.</description> 5841 <addressOffset>0xA8</addressOffset> 5842 <fields> 5843 <field> 5844 <name>ALL</name> 5845 <description>Mask of all of the pins on the port.</description> 5846 <bitOffset>0</bitOffset> 5847 <bitWidth>32</bitWidth> 5848 </field> 5849 </fields> 5850 </register> 5851 <register> 5852 <name>SRSEL</name> 5853 <description>GPIO Slew Rate Enable Register.</description> 5854 <addressOffset>0xAC</addressOffset> 5855 <fields> 5856 <field> 5857 <name>ALL</name> 5858 <description>Mask of all of the pins on the port.</description> 5859 <bitOffset>0</bitOffset> 5860 <bitWidth>32</bitWidth> 5861 <enumeratedValues> 5862 <enumeratedValue> 5863 <name>FAST</name> 5864 <description>Fast Slew Rate selected.</description> 5865 <value>0</value> 5866 </enumeratedValue> 5867 <enumeratedValue> 5868 <name>SLOW</name> 5869 <description>Slow Slew Rate selected.</description> 5870 <value>1</value> 5871 </enumeratedValue> 5872 </enumeratedValues> 5873 </field> 5874 </fields> 5875 </register> 5876 <register> 5877 <name>DS0</name> 5878 <description>GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 5879 <addressOffset>0xB0</addressOffset> 5880 <fields> 5881 <field> 5882 <name>ALL</name> 5883 <description>Mask of all of the pins on the port.</description> 5884 <bitOffset>0</bitOffset> 5885 <bitWidth>32</bitWidth> 5886 <enumeratedValues> 5887 <enumeratedValue> 5888 <name>ld</name> 5889 <description>GPIO port pin is in low-drive mode.</description> 5890 <value>0</value> 5891 </enumeratedValue> 5892 <enumeratedValue> 5893 <name>hd</name> 5894 <description>GPIO port pin is in high-drive mode.</description> 5895 <value>1</value> 5896 </enumeratedValue> 5897 </enumeratedValues> 5898 </field> 5899 </fields> 5900 </register> 5901 <register> 5902 <name>DS1</name> 5903 <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 5904 <addressOffset>0xB4</addressOffset> 5905 <fields> 5906 <field> 5907 <name>ALL</name> 5908 <description>Mask of all of the pins on the port.</description> 5909 <bitOffset>0</bitOffset> 5910 <bitWidth>32</bitWidth> 5911 </field> 5912 </fields> 5913 </register> 5914 <register> 5915 <name>PSSEL</name> 5916 <description>GPIO Pull Select Mode.</description> 5917 <addressOffset>0xB8</addressOffset> 5918 <fields> 5919 <field> 5920 <name>ALL</name> 5921 <description>Mask of all of the pins on the port.</description> 5922 <bitOffset>0</bitOffset> 5923 <bitWidth>32</bitWidth> 5924 </field> 5925 </fields> 5926 </register> 5927 <register> 5928 <name>VSSEL</name> 5929 <description>GPIO Voltage Select.</description> 5930 <addressOffset>0xC0</addressOffset> 5931 <fields> 5932 <field> 5933 <name>ALL</name> 5934 <description>Mask of all of the pins on the port.</description> 5935 <bitOffset>0</bitOffset> 5936 <bitWidth>32</bitWidth> 5937 </field> 5938 </fields> 5939 </register> 5940 </registers> 5941 </peripheral> 5942<!--GPIO0 Individual I/O for each GPIO--> 5943 <peripheral derivedFrom="GPIO0"> 5944 <name>GPIO1</name> 5945 <description>Individual I/O for each GPIO 1</description> 5946 <baseAddress>0x40009000</baseAddress> 5947 <interrupt> 5948 <name>GPIO1</name> 5949 <description>GPIO1 IRQ</description> 5950 <value>25</value> 5951 </interrupt> 5952 </peripheral> 5953<!--GPIO1 Individual I/O for each GPIO 1--> 5954 <peripheral> 5955 <name>HTMR</name> 5956 <description>High Speed Timer Module.</description> 5957 <baseAddress>0x4001B000</baseAddress> 5958 <addressBlock> 5959 <offset>0x00</offset> 5960 <size>0xFFF</size> 5961 <usage>registers</usage> 5962 </addressBlock> 5963 <interrupt> 5964 <name>HTimer</name> 5965 <description>HTimer interrupt.</description> 5966 <value>93</value> 5967 </interrupt> 5968 <registers> 5969 <register> 5970 <name>LNICNT</name> 5971 <description>HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter.</description> 5972 <addressOffset>0x00</addressOffset> 5973 <resetMask>0x00000000</resetMask> 5974 <fields> 5975 <field> 5976 <name>CNT</name> 5977 <description>HTimer Long Interval Counter.</description> 5978 <bitOffset>0</bitOffset> 5979 <bitWidth>32</bitWidth> 5980 </field> 5981 </fields> 5982 </register> 5983 <register> 5984 <name>SHICNT</name> 5985 <description>HTimer Short Interval Counter. This counter ticks every t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00.</description> 5986 <addressOffset>0x04</addressOffset> 5987 <resetMask>0x00000000</resetMask> 5988 <fields> 5989 <field> 5990 <name>CNT</name> 5991 <description>HTimer Short Interval Counter.</description> 5992 <bitOffset>0</bitOffset> 5993 <bitWidth>8</bitWidth> 5994 </field> 5995 </fields> 5996 </register> 5997 <register> 5998 <name>LNIALM</name> 5999 <description>HTimer Long Interval Alarm Value Register.</description> 6000 <addressOffset>0x08</addressOffset> 6001 <resetMask>0x00000000</resetMask> 6002 <fields> 6003 <field> 6004 <name>ALM</name> 6005 <description>HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0]</description> 6006 <bitOffset>0</bitOffset> 6007 <bitWidth>20</bitWidth> 6008 </field> 6009 </fields> 6010 </register> 6011 <register> 6012 <name>SHIALM</name> 6013 <description>HTimer Short Interval Alarm Value Register.</description> 6014 <addressOffset>0x0C</addressOffset> 6015 <resetMask>0x00000000</resetMask> 6016 <fields> 6017 <field> 6018 <name>ALM</name> 6019 <description>This register contains the reload value for the short interval alarm.</description> 6020 <bitOffset>0</bitOffset> 6021 <bitWidth>32</bitWidth> 6022 </field> 6023 </fields> 6024 </register> 6025 <register> 6026 <name>CTRL</name> 6027 <description>HTimer Control Register.</description> 6028 <addressOffset>0x10</addressOffset> 6029 <resetValue>0x00000008</resetValue> 6030 <resetMask>0xFFFFFF38</resetMask> 6031 <fields> 6032 <field> 6033 <name>EN</name> 6034 <description>HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 6035 <bitOffset>0</bitOffset> 6036 <bitWidth>1</bitWidth> 6037 <enumeratedValues> 6038 <enumeratedValue> 6039 <name>dis</name> 6040 <description>Disable.</description> 6041 <value>0</value> 6042 </enumeratedValue> 6043 <enumeratedValue> 6044 <name>en</name> 6045 <description>Enable.</description> 6046 <value>1</value> 6047 </enumeratedValue> 6048 </enumeratedValues> 6049 </field> 6050 <field> 6051 <name>LONG_ALM_IE</name> 6052 <description>Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 6053 <bitOffset>1</bitOffset> 6054 <bitWidth>1</bitWidth> 6055 <enumeratedValues> 6056 <enumeratedValue> 6057 <name>dis</name> 6058 <description>Disable.</description> 6059 <value>0</value> 6060 </enumeratedValue> 6061 <enumeratedValue> 6062 <name>en</name> 6063 <description>Enable.</description> 6064 <value>1</value> 6065 </enumeratedValue> 6066 </enumeratedValues> 6067 </field> 6068 <field> 6069 <name>SHORT_ALM_IE</name> 6070 <description>Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 6071 <bitOffset>2</bitOffset> 6072 <bitWidth>1</bitWidth> 6073 <enumeratedValues> 6074 <enumeratedValue> 6075 <name>dis</name> 6076 <description>Disable.</description> 6077 <value>0</value> 6078 </enumeratedValue> 6079 <enumeratedValue> 6080 <name>en</name> 6081 <description>Enable.</description> 6082 <value>1</value> 6083 </enumeratedValue> 6084 </enumeratedValues> 6085 </field> 6086 <field> 6087 <name>BUSY</name> 6088 <description>HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.</description> 6089 <bitOffset>3</bitOffset> 6090 <bitWidth>1</bitWidth> 6091 <access>read-only</access> 6092 <enumeratedValues> 6093 <enumeratedValue> 6094 <name>idle</name> 6095 <description>Idle.</description> 6096 <value>0</value> 6097 </enumeratedValue> 6098 <enumeratedValue> 6099 <name>busy</name> 6100 <description>Busy.</description> 6101 <value>1</value> 6102 </enumeratedValue> 6103 </enumeratedValues> 6104 </field> 6105 <field> 6106 <name>RDY</name> 6107 <description>HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register.</description> 6108 <bitOffset>4</bitOffset> 6109 <bitWidth>1</bitWidth> 6110 <enumeratedValues> 6111 <enumeratedValue> 6112 <name>busy</name> 6113 <description>Register has not updated.</description> 6114 <value>0</value> 6115 </enumeratedValue> 6116 <enumeratedValue> 6117 <name>ready</name> 6118 <description>Ready.</description> 6119 <value>1</value> 6120 </enumeratedValue> 6121 </enumeratedValues> 6122 </field> 6123 <field> 6124 <name>RDY_IE</name> 6125 <description>HTimer Ready Interrupt Enable.</description> 6126 <bitOffset>5</bitOffset> 6127 <bitWidth>1</bitWidth> 6128 <enumeratedValues> 6129 <enumeratedValue> 6130 <name>dis</name> 6131 <description>Disable.</description> 6132 <value>0</value> 6133 </enumeratedValue> 6134 <enumeratedValue> 6135 <name>en</name> 6136 <description>Enable.</description> 6137 <value>1</value> 6138 </enumeratedValue> 6139 </enumeratedValues> 6140 </field> 6141 <field> 6142 <name>LONG_ALM_IF</name> 6143 <description>Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 6144 <bitOffset>6</bitOffset> 6145 <bitWidth>1</bitWidth> 6146 <access>read-only</access> 6147 <enumeratedValues> 6148 <enumeratedValue> 6149 <name>inactive</name> 6150 <description>Not active.</description> 6151 <value>0</value> 6152 </enumeratedValue> 6153 <enumeratedValue> 6154 <name>pending</name> 6155 <description>Active.</description> 6156 <value>1</value> 6157 </enumeratedValue> 6158 </enumeratedValues> 6159 </field> 6160 <field> 6161 <name>SHORT_ALM_IF</name> 6162 <description>Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 6163 <bitOffset>7</bitOffset> 6164 <bitWidth>1</bitWidth> 6165 <access>read-only</access> 6166 <enumeratedValues> 6167 <enumeratedValue> 6168 <name>inactive</name> 6169 <description>Not active.</description> 6170 <value>0</value> 6171 </enumeratedValue> 6172 <enumeratedValue> 6173 <name>Pending</name> 6174 <description>Active.</description> 6175 <value>1</value> 6176 </enumeratedValue> 6177 </enumeratedValues> 6178 </field> 6179 <field> 6180 <name>WR_EN</name> 6181 <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits.</description> 6182 <bitOffset>15</bitOffset> 6183 <bitWidth>1</bitWidth> 6184 <enumeratedValues> 6185 <enumeratedValue> 6186 <name>dis</name> 6187 <description>Not active.</description> 6188 <value>0</value> 6189 </enumeratedValue> 6190 <enumeratedValue> 6191 <name>en</name> 6192 <description>.</description> 6193 <value>1</value> 6194 </enumeratedValue> 6195 </enumeratedValues> 6196 </field> 6197 </fields> 6198 </register> 6199 <register> 6200 <name>TRIM</name> 6201 <description>HTimer Trim Register.</description> 6202 <addressOffset>0x14</addressOffset> 6203 <resetMask>0x00000000</resetMask> 6204 <fields> 6205 <field> 6206 <name>TRIM</name> 6207 <description>HTimer Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.</description> 6208 <bitOffset>0</bitOffset> 6209 <bitWidth>8</bitWidth> 6210 </field> 6211 <field> 6212 <name>VBAT_TMR</name> 6213 <description>VBAT Timer Value. When HTimer is running off of VBAT, this field is incremented every 32 seconds.</description> 6214 <bitOffset>8</bitOffset> 6215 <bitWidth>24</bitWidth> 6216 </field> 6217 </fields> 6218 </register> 6219 <register> 6220 <name>OSCCTRL</name> 6221 <description>HTimer Oscillator Control Register.</description> 6222 <addressOffset>0x18</addressOffset> 6223 <resetMask>0x00000000</resetMask> 6224 <fields> 6225 <field> 6226 <name>FILTER_EN</name> 6227 <description>Enable Filter.</description> 6228 <bitOffset>0</bitOffset> 6229 <bitWidth>1</bitWidth> 6230 </field> 6231 <field> 6232 <name>IBIAS_SEL</name> 6233 <description>IBIAS Select.</description> 6234 <bitOffset>1</bitOffset> 6235 <bitWidth>1</bitWidth> 6236 <enumeratedValues> 6237 <enumeratedValue> 6238 <name>2x</name> 6239 <description>2x</description> 6240 <value>0</value> 6241 </enumeratedValue> 6242 <enumeratedValue> 6243 <name>4x</name> 6244 <description>4x</description> 6245 <value>1</value> 6246 </enumeratedValue> 6247 </enumeratedValues> 6248 </field> 6249 <field> 6250 <name>HYST_EN</name> 6251 <description>HTimer Hysteresis Enable.</description> 6252 <bitOffset>2</bitOffset> 6253 <bitWidth>1</bitWidth> 6254 </field> 6255 <field> 6256 <name>IBIAS_EN</name> 6257 <description>HTimer IBIAS Enable.</description> 6258 <bitOffset>3</bitOffset> 6259 <bitWidth>1</bitWidth> 6260 </field> 6261 <field> 6262 <name>BYPASS</name> 6263 <description>HTimer Crystal Bypass</description> 6264 <bitOffset>4</bitOffset> 6265 <bitWidth>1</bitWidth> 6266 <enumeratedValues> 6267 <enumeratedValue> 6268 <name>dis</name> 6269 <description>Disable.</description> 6270 <value>0</value> 6271 </enumeratedValue> 6272 <enumeratedValue> 6273 <name>en</name> 6274 <description>Enable.</description> 6275 <value>1</value> 6276 </enumeratedValue> 6277 </enumeratedValues> 6278 </field> 6279 <field> 6280 <name>SQW_32K</name> 6281 <description>HTimer 32kHz Square Wave Output</description> 6282 <bitOffset>5</bitOffset> 6283 <bitWidth>1</bitWidth> 6284 <enumeratedValues> 6285 <enumeratedValue> 6286 <name>dis</name> 6287 <description>Disable.</description> 6288 <value>0</value> 6289 </enumeratedValue> 6290 <enumeratedValue> 6291 <name>en</name> 6292 <description>Enable.</description> 6293 <value>1</value> 6294 </enumeratedValue> 6295 </enumeratedValues> 6296 </field> 6297 </fields> 6298 </register> 6299 </registers> 6300 </peripheral> 6301<!--HTMR High Speed Timer Module.--> 6302 <peripheral derivedFrom="HTMR"> 6303 <name>HTMR1</name> 6304 <description>High Speed Timer Module. 1</description> 6305 <baseAddress>0x4001C000</baseAddress> 6306 <interrupt> 6307 <name>HTMR1</name> 6308 <description>HTMR1 IRQ</description> 6309 <value>94</value> 6310 </interrupt> 6311 </peripheral> 6312<!--HTMR1 High Speed Timer Module. 1--> 6313 <peripheral> 6314 <name>I2C0</name> 6315 <description>Inter-Integrated Circuit.</description> 6316 <groupName>I2C</groupName> 6317 <baseAddress>0x4001D000</baseAddress> 6318 <size>32</size> 6319 <addressBlock> 6320 <offset>0x00</offset> 6321 <size>0x1000</size> 6322 <usage>registers</usage> 6323 </addressBlock> 6324 <interrupt> 6325 <name>I2C0</name> 6326 <description>I2C0 IRQ</description> 6327 <value>13</value> 6328 </interrupt> 6329 <registers> 6330 <register> 6331 <name>CTRL</name> 6332 <description>Control Register0.</description> 6333 <addressOffset>0x00</addressOffset> 6334 <fields> 6335 <field> 6336 <name>EN</name> 6337 <description>I2C Enable.</description> 6338 <bitRange>[0:0]</bitRange> 6339 <access>read-write</access> 6340 <enumeratedValues> 6341 <enumeratedValue> 6342 <name>dis</name> 6343 <description>Disable I2C.</description> 6344 <value>0</value> 6345 </enumeratedValue> 6346 <enumeratedValue> 6347 <name>en</name> 6348 <description>enable I2C.</description> 6349 <value>1</value> 6350 </enumeratedValue> 6351 </enumeratedValues> 6352 </field> 6353 <field> 6354 <name>MST_MODE</name> 6355 <description>Master Mode Enable.</description> 6356 <bitRange>[1:1]</bitRange> 6357 <access>read-write</access> 6358 <enumeratedValues> 6359 <enumeratedValue> 6360 <name>slave_mode</name> 6361 <description>Slave Mode.</description> 6362 <value>0</value> 6363 </enumeratedValue> 6364 <enumeratedValue> 6365 <name>master_mode</name> 6366 <description>Master Mode.</description> 6367 <value>1</value> 6368 </enumeratedValue> 6369 </enumeratedValues> 6370 </field> 6371 <field> 6372 <name>GC_ADDR_EN</name> 6373 <description>General Call Address Enable.</description> 6374 <bitRange>[2:2]</bitRange> 6375 <access>read-write</access> 6376 <enumeratedValues> 6377 <enumeratedValue> 6378 <name>dis</name> 6379 <description>Ignore Gneral Call Address.</description> 6380 <value>0</value> 6381 </enumeratedValue> 6382 <enumeratedValue> 6383 <name>en</name> 6384 <description>Acknowledge general call address.</description> 6385 <value>1</value> 6386 </enumeratedValue> 6387 </enumeratedValues> 6388 </field> 6389 <field> 6390 <name>IRXM_EN</name> 6391 <description>Interactive Receive Mode.</description> 6392 <bitRange>[3:3]</bitRange> 6393 <access>read-write</access> 6394 <enumeratedValues> 6395 <enumeratedValue> 6396 <name>dis</name> 6397 <description>Disable Interactive Receive Mode.</description> 6398 <value>0</value> 6399 </enumeratedValue> 6400 <enumeratedValue> 6401 <name>en</name> 6402 <description>Enable Interactive Receive Mode.</description> 6403 <value>1</value> 6404 </enumeratedValue> 6405 </enumeratedValues> 6406 </field> 6407 <field> 6408 <name>IRXM_ACK</name> 6409 <description>Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.</description> 6410 <bitRange>[4:4]</bitRange> 6411 <access>read-write</access> 6412 <enumeratedValues> 6413 <enumeratedValue> 6414 <name>ack</name> 6415 <description>return ACK (pulling SDA LOW).</description> 6416 <value>0</value> 6417 </enumeratedValue> 6418 <enumeratedValue> 6419 <name>nack</name> 6420 <description>return NACK (leaving SDA HIGH).</description> 6421 <value>1</value> 6422 </enumeratedValue> 6423 </enumeratedValues> 6424 </field> 6425 <field> 6426 <name>SCL_OUT</name> 6427 <description>SCL Output. This bits control SCL output when SWOE =1.</description> 6428 <bitRange>[6:6]</bitRange> 6429 <access>read-write</access> 6430 <enumeratedValues> 6431 <enumeratedValue> 6432 <name>drive_scl_low</name> 6433 <description>Drive SCL low. </description> 6434 <value>0</value> 6435 </enumeratedValue> 6436 <enumeratedValue> 6437 <name>release_scl</name> 6438 <description>Release SCL.</description> 6439 <value>1</value> 6440 </enumeratedValue> 6441 </enumeratedValues> 6442 </field> 6443 <field> 6444 <name>SDA_OUT</name> 6445 <description>SDA Output. This bits control SDA output when SWOE = 1. </description> 6446 <bitRange>[7:7]</bitRange> 6447 <access>read-write</access> 6448 <enumeratedValues> 6449 <enumeratedValue> 6450 <name>drive_sda_low</name> 6451 <description>Drive SDA low. </description> 6452 <value>0</value> 6453 </enumeratedValue> 6454 <enumeratedValue> 6455 <name>release_sda</name> 6456 <description>Release SDA.</description> 6457 <value>1</value> 6458 </enumeratedValue> 6459 </enumeratedValues> 6460 </field> 6461 <field> 6462 <name>SCL</name> 6463 <description>SCL status. This bit reflects the logic gate of SCL signal. </description> 6464 <bitRange>[8:8]</bitRange> 6465 <access>read-only</access> 6466 </field> 6467 <field> 6468 <name>SDA</name> 6469 <description>SDA status. THis bit reflects the logic gate of SDA signal.</description> 6470 <bitRange>[9:9]</bitRange> 6471 <access>read-only</access> 6472 </field> 6473 <field> 6474 <name>BB_EN</name> 6475 <description>Software Output Enable.</description> 6476 <bitRange>[10:10]</bitRange> 6477 <access>read-write</access> 6478 <enumeratedValues> 6479 <enumeratedValue> 6480 <name>outputs_disable</name> 6481 <description>I2C Outputs SCLO and SDAO disabled. </description> 6482 <value>0</value> 6483 </enumeratedValue> 6484 <enumeratedValue> 6485 <name>outputs_enable</name> 6486 <description>I2C Outputs SCLO and SDAO enabled.</description> 6487 <value>1</value> 6488 </enumeratedValue> 6489 </enumeratedValues> 6490 </field> 6491 <field> 6492 <name>READ</name> 6493 <description>Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.</description> 6494 <bitRange>[11:11]</bitRange> 6495 <access>read-only</access> 6496 <enumeratedValues> 6497 <enumeratedValue> 6498 <name>write</name> 6499 <description>Write.</description> 6500 <value>0</value> 6501 </enumeratedValue> 6502 <enumeratedValue> 6503 <name>read</name> 6504 <description>Read.</description> 6505 <value>1</value> 6506 </enumeratedValue> 6507 </enumeratedValues> 6508 </field> 6509 <field> 6510 <name>CLKSTR_DIS</name> 6511 <description>This bit will disable slave clock stretching when set.</description> 6512 <bitRange>[12:12]</bitRange> 6513 <access>read-write</access> 6514 <enumeratedValues> 6515 <enumeratedValue> 6516 <name>en</name> 6517 <description>Slave clock stretching enabled.</description> 6518 <value>0</value> 6519 </enumeratedValue> 6520 <enumeratedValue> 6521 <name>dis</name> 6522 <description>Slave clock stretching disabled.</description> 6523 <value>1</value> 6524 </enumeratedValue> 6525 </enumeratedValues> 6526 </field> 6527 <field> 6528 <name>ONE_MST_MODE</name> 6529 <description>SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. </description> 6530 <bitRange>[13:13]</bitRange> 6531 <access>read-write</access> 6532 <enumeratedValues> 6533 <enumeratedValue> 6534 <name>dis</name> 6535 <description>Standard open-drain operation: 6536 drive low for 0, Hi-Z for 1</description> 6537 <value>0</value> 6538 </enumeratedValue> 6539 <enumeratedValue> 6540 <name>en</name> 6541 <description>Non-standard push-pull operation: 6542 drive low for 0, drive high for 1</description> 6543 <value>1</value> 6544 </enumeratedValue> 6545 </enumeratedValues> 6546 </field> 6547 <field> 6548 <name>HS_EN</name> 6549 <description>High speed mode enable</description> 6550 <bitRange>[15:15]</bitRange> 6551 <access>read-write</access> 6552 </field> 6553 </fields> 6554 </register> 6555 <register> 6556 <name>STATUS</name> 6557 <description>Status Register.</description> 6558 <addressOffset>0x04</addressOffset> 6559 <fields> 6560 <field> 6561 <name>BUSY</name> 6562 <description>Bus Status.</description> 6563 <bitRange>[0:0]</bitRange> 6564 <access>read-only</access> 6565 <enumeratedValues> 6566 <enumeratedValue> 6567 <name>idle</name> 6568 <description>I2C Bus Idle.</description> 6569 <value>0</value> 6570 </enumeratedValue> 6571 <enumeratedValue> 6572 <name>busy</name> 6573 <description>I2C Bus Busy.</description> 6574 <value>1</value> 6575 </enumeratedValue> 6576 </enumeratedValues> 6577 </field> 6578 <field> 6579 <name>RX_EM</name> 6580 <description>RX empty.</description> 6581 <bitRange>[1:1]</bitRange> 6582 <access>read-only</access> 6583 <enumeratedValues> 6584 <enumeratedValue> 6585 <name>not_empty</name> 6586 <description>Not Empty.</description> 6587 <value>0</value> 6588 </enumeratedValue> 6589 <enumeratedValue> 6590 <name>empty</name> 6591 <description>Empty.</description> 6592 <value>1</value> 6593 </enumeratedValue> 6594 </enumeratedValues> 6595 </field> 6596 <field> 6597 <name>RX_FULL</name> 6598 <description>RX Full.</description> 6599 <bitRange>[2:2]</bitRange> 6600 <access>read-only</access> 6601 <enumeratedValues> 6602 <enumeratedValue> 6603 <name>not_full</name> 6604 <description>Not Full.</description> 6605 <value>0</value> 6606 </enumeratedValue> 6607 <enumeratedValue> 6608 <name>full</name> 6609 <description>Full.</description> 6610 <value>1</value> 6611 </enumeratedValue> 6612 </enumeratedValues> 6613 </field> 6614 <field> 6615 <name>TX_EM</name> 6616 <description>TX Empty.</description> 6617 <bitRange>[3:3]</bitRange> 6618 <enumeratedValues> 6619 <enumeratedValue> 6620 <name>not_empty</name> 6621 <description>Not Empty.</description> 6622 <value>0</value> 6623 </enumeratedValue> 6624 <enumeratedValue> 6625 <name>empty</name> 6626 <description>Empty.</description> 6627 <value>1</value> 6628 </enumeratedValue> 6629 </enumeratedValues> 6630 </field> 6631 <field> 6632 <name>TX_FULL</name> 6633 <description>TX Full.</description> 6634 <bitRange>[4:4]</bitRange> 6635 <enumeratedValues> 6636 <enumeratedValue> 6637 <name>not_empty</name> 6638 <description>Not Empty.</description> 6639 <value>0</value> 6640 </enumeratedValue> 6641 <enumeratedValue> 6642 <name>empty</name> 6643 <description>Empty.</description> 6644 <value>1</value> 6645 </enumeratedValue> 6646 </enumeratedValues> 6647 </field> 6648 <field> 6649 <name>MST_BUSY</name> 6650 <description>Clock Mode.</description> 6651 <bitRange>[5:5]</bitRange> 6652 <access>read-only</access> 6653 <enumeratedValues> 6654 <enumeratedValue> 6655 <name>not_actively_driving_scl_clock</name> 6656 <description>Device not actively driving SCL clock cycles.</description> 6657 <value>0</value> 6658 </enumeratedValue> 6659 <enumeratedValue> 6660 <name>actively_driving_scl_clock</name> 6661 <description>Device operating as master and actively driving SCL clock cycles.</description> 6662 <value>1</value> 6663 </enumeratedValue> 6664 </enumeratedValues> 6665 </field> 6666 </fields> 6667 </register> 6668 <register> 6669 <name>INTFL0</name> 6670 <description>Interrupt Status Register.</description> 6671 <addressOffset>0x08</addressOffset> 6672 <fields> 6673 <field> 6674 <name>DONE</name> 6675 <description>Transfer Done Interrupt.</description> 6676 <bitRange>[0:0]</bitRange> 6677 <enumeratedValues> 6678 <name>INT_FL0_Done</name> 6679 <enumeratedValue> 6680 <name>inactive</name> 6681 <description>No Interrupt is Pending.</description> 6682 <value>0</value> 6683 </enumeratedValue> 6684 <enumeratedValue> 6685 <name>pending</name> 6686 <description>An interrupt is pending.</description> 6687 <value>1</value> 6688 </enumeratedValue> 6689 </enumeratedValues> 6690 </field> 6691 <field> 6692 <name>IRXM</name> 6693 <description>Interactive Receive Interrupt.</description> 6694 <bitRange>[1:1]</bitRange> 6695 <enumeratedValues> 6696 <enumeratedValue> 6697 <name>inactive</name> 6698 <description>No Interrupt is Pending.</description> 6699 <value>0</value> 6700 </enumeratedValue> 6701 <enumeratedValue> 6702 <name>pending</name> 6703 <description>An interrupt is pending.</description> 6704 <value>1</value> 6705 </enumeratedValue> 6706 </enumeratedValues> 6707 </field> 6708 <field> 6709 <name>GC_ADDR_MATCH</name> 6710 <description>Slave General Call Address Match Interrupt.</description> 6711 <bitRange>[2:2]</bitRange> 6712 <enumeratedValues> 6713 <enumeratedValue> 6714 <name>inactive</name> 6715 <description>No Interrupt is Pending.</description> 6716 <value>0</value> 6717 </enumeratedValue> 6718 <enumeratedValue> 6719 <name>pending</name> 6720 <description>An interrupt is pending.</description> 6721 <value>1</value> 6722 </enumeratedValue> 6723 </enumeratedValues> 6724 </field> 6725 <field> 6726 <name>ADDR_MATCH</name> 6727 <description>Slave Address Match Interrupt.</description> 6728 <bitRange>[3:3]</bitRange> 6729 <enumeratedValues> 6730 <enumeratedValue> 6731 <name>inactive</name> 6732 <description>No Interrupt is Pending.</description> 6733 <value>0</value> 6734 </enumeratedValue> 6735 <enumeratedValue> 6736 <name>pending</name> 6737 <description>An interrupt is pending.</description> 6738 <value>1</value> 6739 </enumeratedValue> 6740 </enumeratedValues> 6741 </field> 6742 <field> 6743 <name>RX_THD</name> 6744 <description>Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.</description> 6745 <bitRange>[4:4]</bitRange> 6746 <enumeratedValues> 6747 <enumeratedValue> 6748 <name>inactive</name> 6749 <description>No interrupt is pending.</description> 6750 <value>0</value> 6751 </enumeratedValue> 6752 <enumeratedValue> 6753 <name>pending</name> 6754 <description>An interrupt is pending. RX_FIFO equal or more bytes than the threshold.</description> 6755 <value>1</value> 6756 </enumeratedValue> 6757 </enumeratedValues> 6758 </field> 6759 <field> 6760 <name>TX_THD</name> 6761 <description>Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.</description> 6762 <bitRange>[5:5]</bitRange> 6763 <enumeratedValues> 6764 <enumeratedValue> 6765 <name>inactive</name> 6766 <description>No interrupt is pending.</description> 6767 <value>0</value> 6768 </enumeratedValue> 6769 <enumeratedValue> 6770 <name>pending</name> 6771 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 6772 <value>1</value> 6773 </enumeratedValue> 6774 </enumeratedValues> 6775 </field> 6776 <field> 6777 <name>STOP</name> 6778 <description>STOP Interrupt.</description> 6779 <bitRange>[6:6]</bitRange> 6780 <enumeratedValues> 6781 <enumeratedValue> 6782 <name>inactive</name> 6783 <description>No interrupt is pending.</description> 6784 <value>0</value> 6785 </enumeratedValue> 6786 <enumeratedValue> 6787 <name>pending</name> 6788 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 6789 <value>1</value> 6790 </enumeratedValue> 6791 </enumeratedValues> 6792 </field> 6793 <field> 6794 <name>ADDR_ACK</name> 6795 <description>Address Acknowledge Interrupt.</description> 6796 <bitRange>[7:7]</bitRange> 6797 <enumeratedValues> 6798 <enumeratedValue> 6799 <name>inactive</name> 6800 <description>No Interrupt is Pending.</description> 6801 <value>0</value> 6802 </enumeratedValue> 6803 <enumeratedValue> 6804 <name>pending</name> 6805 <description>An interrupt is pending.</description> 6806 <value>1</value> 6807 </enumeratedValue> 6808 </enumeratedValues> 6809 </field> 6810 <field> 6811 <name>ARB_ERR</name> 6812 <description>Arbritation error Interrupt.</description> 6813 <bitRange>[8:8]</bitRange> 6814 <enumeratedValues> 6815 <enumeratedValue> 6816 <name>inactive</name> 6817 <description>No Interrupt is Pending.</description> 6818 <value>0</value> 6819 </enumeratedValue> 6820 <enumeratedValue> 6821 <name>pending</name> 6822 <description>An interrupt is pending.</description> 6823 <value>1</value> 6824 </enumeratedValue> 6825 </enumeratedValues> 6826 </field> 6827 <field> 6828 <name>TO_ERR</name> 6829 <description>timeout Error Interrupt.</description> 6830 <bitRange>[9:9]</bitRange> 6831 <enumeratedValues> 6832 <enumeratedValue> 6833 <name>inactive</name> 6834 <description>No Interrupt is Pending.</description> 6835 <value>0</value> 6836 </enumeratedValue> 6837 <enumeratedValue> 6838 <name>pending</name> 6839 <description>An interrupt is pending.</description> 6840 <value>1</value> 6841 </enumeratedValue> 6842 </enumeratedValues> 6843 </field> 6844 <field> 6845 <name>ADDR_NACK_ERR</name> 6846 <description>Address NACK Error Interrupt.</description> 6847 <bitRange>[10:10]</bitRange> 6848 <enumeratedValues> 6849 <enumeratedValue> 6850 <name>inactive</name> 6851 <description>No Interrupt is Pending.</description> 6852 <value>0</value> 6853 </enumeratedValue> 6854 <enumeratedValue> 6855 <name>pending</name> 6856 <description>An interrupt is pending.</description> 6857 <value>1</value> 6858 </enumeratedValue> 6859 </enumeratedValues> 6860 </field> 6861 <field> 6862 <name>DATA_ERR</name> 6863 <description>Data NACK Error Interrupt.</description> 6864 <bitRange>[11:11]</bitRange> 6865 <enumeratedValues> 6866 <enumeratedValue> 6867 <name>inactive</name> 6868 <description>No Interrupt is Pending.</description> 6869 <value>0</value> 6870 </enumeratedValue> 6871 <enumeratedValue> 6872 <name>pending</name> 6873 <description>An interrupt is pending.</description> 6874 <value>1</value> 6875 </enumeratedValue> 6876 </enumeratedValues> 6877 </field> 6878 <field> 6879 <name>DNR_ERR</name> 6880 <description>Do Not Respond Error Interrupt.</description> 6881 <bitRange>[12:12]</bitRange> 6882 <enumeratedValues> 6883 <enumeratedValue> 6884 <name>inactive</name> 6885 <description>No Interrupt is Pending.</description> 6886 <value>0</value> 6887 </enumeratedValue> 6888 <enumeratedValue> 6889 <name>pending</name> 6890 <description>An interrupt is pending.</description> 6891 <value>1</value> 6892 </enumeratedValue> 6893 </enumeratedValues> 6894 </field> 6895 <field> 6896 <name>START_ERR</name> 6897 <description>Start Error Interrupt.</description> 6898 <bitRange>[13:13]</bitRange> 6899 <enumeratedValues> 6900 <enumeratedValue> 6901 <name>inactive</name> 6902 <description>No Interrupt is Pending.</description> 6903 <value>0</value> 6904 </enumeratedValue> 6905 <enumeratedValue> 6906 <name>pending</name> 6907 <description>An interrupt is pending.</description> 6908 <value>1</value> 6909 </enumeratedValue> 6910 </enumeratedValues> 6911 </field> 6912 <field> 6913 <name>STOP_ERR</name> 6914 <description>Stop Error Interrupt.</description> 6915 <bitRange>[14:14]</bitRange> 6916 <enumeratedValues> 6917 <enumeratedValue> 6918 <name>inactive</name> 6919 <description>No Interrupt is Pending.</description> 6920 <value>0</value> 6921 </enumeratedValue> 6922 <enumeratedValue> 6923 <name>pending</name> 6924 <description>An interrupt is pending.</description> 6925 <value>1</value> 6926 </enumeratedValue> 6927 </enumeratedValues> 6928 </field> 6929 <field> 6930 <name>TX_LOCKOUT</name> 6931 <description>Transmit Lock Out Interrupt.</description> 6932 <bitRange>[15:15]</bitRange> 6933 </field> 6934 <field> 6935 <name>MAMI</name> 6936 <description>Multiple Address Match Interrupt</description> 6937 <bitRange>[21:16]</bitRange> 6938 </field> 6939 <field> 6940 <name>RD_ADDR_MATCH</name> 6941 <description>Slave Read Address Match Interrupt</description> 6942 <bitRange>[22:22]</bitRange> 6943 </field> 6944 <field> 6945 <name>WR_ADDR_MATCH</name> 6946 <description>Slave Write Address Match Interrupt</description> 6947 <bitRange>[23:23]</bitRange> 6948 </field> 6949 </fields> 6950 </register> 6951 <register> 6952 <name>INTEN0</name> 6953 <description>Interrupt Enable Register.</description> 6954 <addressOffset>0x0C</addressOffset> 6955 <access>read-write</access> 6956 <fields> 6957 <field> 6958 <name>DONE</name> 6959 <description>Transfer Done Interrupt Enable.</description> 6960 <bitRange>[0:0]</bitRange> 6961 <access>read-write</access> 6962 <enumeratedValues> 6963 <enumeratedValue> 6964 <name>dis</name> 6965 <description>Interrupt disabled.</description> 6966 <value>0</value> 6967 </enumeratedValue> 6968 <enumeratedValue> 6969 <name>en</name> 6970 <description>Interrupt enabled when DONE = 1.</description> 6971 <value>1</value> 6972 </enumeratedValue> 6973 </enumeratedValues> 6974 </field> 6975 <field> 6976 <name>IRXM</name> 6977 <description>Description not available.</description> 6978 <bitRange>[1:1]</bitRange> 6979 <access>read-write</access> 6980 <enumeratedValues> 6981 <enumeratedValue> 6982 <name>dis</name> 6983 <description>Interrupt disabled.</description> 6984 <value>0</value> 6985 </enumeratedValue> 6986 <enumeratedValue> 6987 <name>en</name> 6988 <description>Interrupt enabled when RX_MODE = 1.</description> 6989 <value>1</value> 6990 </enumeratedValue> 6991 </enumeratedValues> 6992 </field> 6993 <field> 6994 <name>GC_ADDR_MATCH</name> 6995 <description>Slave mode general call address match received input enable.</description> 6996 <bitRange>[2:2]</bitRange> 6997 <access>read-write</access> 6998 <enumeratedValues> 6999 <enumeratedValue> 7000 <name>dis</name> 7001 <description>Interrupt disabled.</description> 7002 <value>0</value> 7003 </enumeratedValue> 7004 <enumeratedValue> 7005 <name>en</name> 7006 <description>Interrupt enabled when GEN_CTRL_ADDR = 1.</description> 7007 <value>1</value> 7008 </enumeratedValue> 7009 </enumeratedValues> 7010 </field> 7011 <field> 7012 <name>ADDR_MATCH</name> 7013 <description>Slave mode incoming address match interrupt.</description> 7014 <bitRange>[3:3]</bitRange> 7015 <access>read-write</access> 7016 <enumeratedValues> 7017 <enumeratedValue> 7018 <name>dis</name> 7019 <description>Interrupt disabled.</description> 7020 <value>0</value> 7021 </enumeratedValue> 7022 <enumeratedValue> 7023 <name>en</name> 7024 <description>Interrupt enabled when ADDR_MATCH = 1.</description> 7025 <value>1</value> 7026 </enumeratedValue> 7027 </enumeratedValues> 7028 </field> 7029 <field> 7030 <name>RX_THD</name> 7031 <description>RX FIFO Above Treshold Level Interrupt Enable.</description> 7032 <bitRange>[4:4]</bitRange> 7033 <access>read-write</access> 7034 <enumeratedValues> 7035 <enumeratedValue> 7036 <name>dis</name> 7037 <description>Interrupt disabled.</description> 7038 <value>0</value> 7039 </enumeratedValue> 7040 <enumeratedValue> 7041 <name>en</name> 7042 <description>Interrupt enabled.</description> 7043 <value>1</value> 7044 </enumeratedValue> 7045 </enumeratedValues> 7046 </field> 7047 <field> 7048 <name>TX_THD</name> 7049 <description>TX FIFO Below Treshold Level Interrupt Enable.</description> 7050 <bitRange>[5:5]</bitRange> 7051 <enumeratedValues> 7052 <enumeratedValue> 7053 <name>dis</name> 7054 <description>Interrupt disabled.</description> 7055 <value>0</value> 7056 </enumeratedValue> 7057 <enumeratedValue> 7058 <name>en</name> 7059 <description>Interrupt enabled.</description> 7060 <value>1</value> 7061 </enumeratedValue> 7062 </enumeratedValues> 7063 </field> 7064 <field> 7065 <name>STOP</name> 7066 <description>Stop Interrupt Enable</description> 7067 <bitRange>[6:6]</bitRange> 7068 <access>read-write</access> 7069 <enumeratedValues> 7070 <enumeratedValue> 7071 <name>dis</name> 7072 <description>Interrupt disabled.</description> 7073 <value>0</value> 7074 </enumeratedValue> 7075 <enumeratedValue> 7076 <name>en</name> 7077 <description>Interrupt enabled when STOP = 1.</description> 7078 <value>1</value> 7079 </enumeratedValue> 7080 </enumeratedValues> 7081 </field> 7082 <field> 7083 <name>ADDR_ACK</name> 7084 <description>Received Address ACK from Slave Interrupt.</description> 7085 <bitRange>[7:7]</bitRange> 7086 <enumeratedValues> 7087 <enumeratedValue> 7088 <name>dis</name> 7089 <description>Interrupt disabled.</description> 7090 <value>0</value> 7091 </enumeratedValue> 7092 <enumeratedValue> 7093 <name>en</name> 7094 <description>Interrupt enabled.</description> 7095 <value>1</value> 7096 </enumeratedValue> 7097 </enumeratedValues> 7098 </field> 7099 <field> 7100 <name>ARB_ERR</name> 7101 <description>Master Mode Arbitration Lost Interrupt.</description> 7102 <bitRange>[8:8]</bitRange> 7103 <enumeratedValues> 7104 <enumeratedValue> 7105 <name>dis</name> 7106 <description>Interrupt disabled.</description> 7107 <value>0</value> 7108 </enumeratedValue> 7109 <enumeratedValue> 7110 <name>en</name> 7111 <description>Interrupt enabled.</description> 7112 <value>1</value> 7113 </enumeratedValue> 7114 </enumeratedValues> 7115 </field> 7116 <field> 7117 <name>TO_ERR</name> 7118 <description>Timeout Error Interrupt Enable.</description> 7119 <bitRange>[9:9]</bitRange> 7120 <enumeratedValues> 7121 <enumeratedValue> 7122 <name>dis</name> 7123 <description>Interrupt disabled.</description> 7124 <value>0</value> 7125 </enumeratedValue> 7126 <enumeratedValue> 7127 <name>en</name> 7128 <description>Interrupt enabled.</description> 7129 <value>1</value> 7130 </enumeratedValue> 7131 </enumeratedValues> 7132 </field> 7133 <field> 7134 <name>ADDR_NACK_ERR</name> 7135 <description>Master Mode Address NACK Received Interrupt.</description> 7136 <bitRange>[10:10]</bitRange> 7137 <enumeratedValues> 7138 <enumeratedValue> 7139 <name>dis</name> 7140 <description>Interrupt disabled.</description> 7141 <value>0</value> 7142 </enumeratedValue> 7143 <enumeratedValue> 7144 <name>en</name> 7145 <description>Interrupt enabled.</description> 7146 <value>1</value> 7147 </enumeratedValue> 7148 </enumeratedValues> 7149 </field> 7150 <field> 7151 <name>DATA_ERR</name> 7152 <description>Master Mode Data NACK Received Interrupt.</description> 7153 <bitRange>[11:11]</bitRange> 7154 <enumeratedValues> 7155 <enumeratedValue> 7156 <name>dis</name> 7157 <description>Interrupt disabled.</description> 7158 <value>0</value> 7159 </enumeratedValue> 7160 <enumeratedValue> 7161 <name>en</name> 7162 <description>Interrupt enabled.</description> 7163 <value>1</value> 7164 </enumeratedValue> 7165 </enumeratedValues> 7166 </field> 7167 <field> 7168 <name>DNR_ERR</name> 7169 <description>Slave Mode Do Not Respond Interrupt.</description> 7170 <bitRange>[12:12]</bitRange> 7171 <enumeratedValues> 7172 <enumeratedValue> 7173 <name>dis</name> 7174 <description>Interrupt disabled.</description> 7175 <value>0</value> 7176 </enumeratedValue> 7177 <enumeratedValue> 7178 <name>en</name> 7179 <description>Interrupt enabled.</description> 7180 <value>1</value> 7181 </enumeratedValue> 7182 </enumeratedValues> 7183 </field> 7184 <field> 7185 <name>START_ERR</name> 7186 <description>Out of Sequence START condition detected interrupt.</description> 7187 <bitRange>[13:13]</bitRange> 7188 <enumeratedValues> 7189 <enumeratedValue> 7190 <name>dis</name> 7191 <description>Interrupt disabled.</description> 7192 <value>0</value> 7193 </enumeratedValue> 7194 <enumeratedValue> 7195 <name>en</name> 7196 <description>Interrupt enabled.</description> 7197 <value>1</value> 7198 </enumeratedValue> 7199 </enumeratedValues> 7200 </field> 7201 <field> 7202 <name>STOP_ERR</name> 7203 <description>Out of Sequence STOP condition detected interrupt.</description> 7204 <bitRange>[14:14]</bitRange> 7205 <enumeratedValues> 7206 <enumeratedValue> 7207 <name>dis</name> 7208 <description>Interrupt disabled.</description> 7209 <value>0</value> 7210 </enumeratedValue> 7211 <enumeratedValue> 7212 <name>en</name> 7213 <description>Interrupt enabled.</description> 7214 <value>1</value> 7215 </enumeratedValue> 7216 </enumeratedValues> 7217 </field> 7218 <field> 7219 <name>TX_LOCKOUT</name> 7220 <description>TX FIFO Locked Out Interrupt.</description> 7221 <bitRange>[15:15]</bitRange> 7222 </field> 7223 <field> 7224 <name>MAMI</name> 7225 <description>Multiple Address Match Interrupt</description> 7226 <bitRange>[21:16]</bitRange> 7227 </field> 7228 <field> 7229 <name>RD_ADDR_MATCH</name> 7230 <description>Slave Read Address Match Interrupt</description> 7231 <bitRange>[22:22]</bitRange> 7232 </field> 7233 <field> 7234 <name>WR_ADDR_MATCH</name> 7235 <description>Slave Write Address Match Interrupt</description> 7236 <bitRange>[23:23]</bitRange> 7237 </field> 7238 </fields> 7239 </register> 7240 <register> 7241 <name>INTFL1</name> 7242 <description>Interrupt Status Register 1.</description> 7243 <addressOffset>0x10</addressOffset> 7244 <fields> 7245 <field> 7246 <name>RX_OV</name> 7247 <description>Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.</description> 7248 <bitRange>[0:0]</bitRange> 7249 <enumeratedValues> 7250 <enumeratedValue> 7251 <name>inactive</name> 7252 <description>No Interrupt is Pending.</description> 7253 <value>0</value> 7254 </enumeratedValue> 7255 <enumeratedValue> 7256 <name>pending</name> 7257 <description>An interrupt is pending.</description> 7258 <value>1</value> 7259 </enumeratedValue> 7260 </enumeratedValues> 7261 </field> 7262 <field> 7263 <name>TX_UN</name> 7264 <description>Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).</description> 7265 <bitRange>[1:1]</bitRange> 7266 <enumeratedValues> 7267 <enumeratedValue> 7268 <name>inactive</name> 7269 <description>No Interrupt is Pending.</description> 7270 <value>0</value> 7271 </enumeratedValue> 7272 <enumeratedValue> 7273 <name>pending</name> 7274 <description>An interrupt is pending.</description> 7275 <value>1</value> 7276 </enumeratedValue> 7277 </enumeratedValues> 7278 </field> 7279 <field> 7280 <name>START</name> 7281 <description>START Condition Status Flag.</description> 7282 <bitRange>[2:2]</bitRange> 7283 </field> 7284 </fields> 7285 </register> 7286 <register> 7287 <name>INTEN1</name> 7288 <description>Interrupt Staus Register 1.</description> 7289 <addressOffset>0x14</addressOffset> 7290 <access>read-write</access> 7291 <fields> 7292 <field> 7293 <name>RX_OV</name> 7294 <description>Receiver Overflow Interrupt Enable.</description> 7295 <bitRange>[0:0]</bitRange> 7296 <enumeratedValues> 7297 <enumeratedValue> 7298 <name>dis</name> 7299 <description>No Interrupt is Pending.</description> 7300 <value>0</value> 7301 </enumeratedValue> 7302 <enumeratedValue> 7303 <name>en</name> 7304 <description>An interrupt is pending.</description> 7305 <value>1</value> 7306 </enumeratedValue> 7307 </enumeratedValues> 7308 </field> 7309 <field> 7310 <name>TX_UN</name> 7311 <description>Transmit Underflow Interrupt Enable.</description> 7312 <bitRange>[1:1]</bitRange> 7313 <enumeratedValues> 7314 <enumeratedValue> 7315 <name>dis</name> 7316 <description>No Interrupt is Pending.</description> 7317 <value>0</value> 7318 </enumeratedValue> 7319 <enumeratedValue> 7320 <name>en</name> 7321 <description>An interrupt is pending.</description> 7322 <value>1</value> 7323 </enumeratedValue> 7324 </enumeratedValues> 7325 </field> 7326 <field> 7327 <name>START</name> 7328 <description>START Condition Interrupt Enable.</description> 7329 <bitRange>[2:2]</bitRange> 7330 </field> 7331 </fields> 7332 </register> 7333 <register> 7334 <name>FIFOLEN</name> 7335 <description>FIFO Configuration Register.</description> 7336 <addressOffset>0x18</addressOffset> 7337 <fields> 7338 <field> 7339 <name>RX_DEPTH</name> 7340 <description>Receive FIFO Length.</description> 7341 <bitRange>[7:0]</bitRange> 7342 <access>read-only</access> 7343 </field> 7344 <field> 7345 <name>TX_DEPTH</name> 7346 <description>Transmit FIFO Length.</description> 7347 <bitRange>[15:8]</bitRange> 7348 <access>read-only</access> 7349 </field> 7350 </fields> 7351 </register> 7352 <register> 7353 <name>RXCTRL0</name> 7354 <description>Receive Control Register 0.</description> 7355 <addressOffset>0x1C</addressOffset> 7356 <fields> 7357 <field> 7358 <name>DNR</name> 7359 <description>Do Not Respond.</description> 7360 <bitRange>[0:0]</bitRange> 7361 <enumeratedValues> 7362 <enumeratedValue> 7363 <name>respond</name> 7364 <description>Always respond to address match.</description> 7365 <value>0</value> 7366 </enumeratedValue> 7367 <enumeratedValue> 7368 <name>not_respond_rx_fifo_empty</name> 7369 <description>Do not respond to address match when RX_FIFO is not empty.</description> 7370 <value>1</value> 7371 </enumeratedValue> 7372 </enumeratedValues> 7373 </field> 7374 <field> 7375 <name>FLUSH</name> 7376 <description>Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.</description> 7377 <bitRange>[7:7]</bitRange> 7378 <enumeratedValues> 7379 <enumeratedValue> 7380 <name>not_flushed</name> 7381 <description>FIFO not flushed.</description> 7382 <value>0</value> 7383 </enumeratedValue> 7384 <enumeratedValue> 7385 <name>flush</name> 7386 <description>Flush RX_FIFO.</description> 7387 <value>1</value> 7388 </enumeratedValue> 7389 </enumeratedValues> 7390 </field> 7391 <field> 7392 <name>THD_LVL</name> 7393 <description>Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.</description> 7394 <bitRange>[11:8]</bitRange> 7395 </field> 7396 </fields> 7397 </register> 7398 <register> 7399 <name>RXCTRL1</name> 7400 <description>Receive Control Register 1.</description> 7401 <addressOffset>0x20</addressOffset> 7402 <fields> 7403 <field> 7404 <name>CNT</name> 7405 <description>Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.</description> 7406 <bitRange>[7:0]</bitRange> 7407 </field> 7408 <field> 7409 <name>LVL</name> 7410 <description>Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.</description> 7411 <bitRange>[11:8]</bitRange> 7412 <access>read-only</access> 7413 </field> 7414 </fields> 7415 </register> 7416 <register> 7417 <name>TXCTRL0</name> 7418 <description>Transmit Control Register 0.</description> 7419 <addressOffset>0x24</addressOffset> 7420 <fields> 7421 <field> 7422 <name>PRELOAD_MODE</name> 7423 <description>Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.</description> 7424 <bitRange>[0:0]</bitRange> 7425 </field> 7426 <field> 7427 <name>TX_READY_MODE</name> 7428 <description>Transmit FIFO Ready Manual Mode.</description> 7429 <bitRange>[1:1]</bitRange> 7430 <enumeratedValues> 7431 <enumeratedValue> 7432 <name>en</name> 7433 <description>HW control of I2CTXRDY enabled.</description> 7434 <value>0</value> 7435 </enumeratedValue> 7436 <enumeratedValue> 7437 <name>dis</name> 7438 <description>HW control of I2CTXRDY disabled.</description> 7439 <value>1</value> 7440 </enumeratedValue> 7441 </enumeratedValues> 7442 </field> 7443 <field> 7444 <name>GC_ADDR_FLUSH_DIS</name> 7445 <description>TX FIFO General Call Address Match Auto Flush Disable.</description> 7446 <bitRange>[2:2]</bitRange> 7447 <enumeratedValues> 7448 <enumeratedValue> 7449 <name>en</name> 7450 <description>Enabled.</description> 7451 <value>0</value> 7452 </enumeratedValue> 7453 <enumeratedValue> 7454 <name>dis</name> 7455 <description>Disabled.</description> 7456 <value>1</value> 7457 </enumeratedValue> 7458 </enumeratedValues> 7459 </field> 7460 <field> 7461 <name>WR_ADDR_FLUSH_DIS</name> 7462 <description>TX FIFO Slave Address Match Write Auto Flush Disable.</description> 7463 <bitRange>[3:3]</bitRange> 7464 <enumeratedValues> 7465 <enumeratedValue> 7466 <name>en</name> 7467 <description>Enabled.</description> 7468 <value>0</value> 7469 </enumeratedValue> 7470 <enumeratedValue> 7471 <name>dis</name> 7472 <description>Disabled.</description> 7473 <value>1</value> 7474 </enumeratedValue> 7475 </enumeratedValues> 7476 </field> 7477 <field> 7478 <name>RD_ADDR_FLUSH_DIS</name> 7479 <description>TX FIFO Slave Address Match Read Auto Flush Disable.</description> 7480 <bitRange>[4:4]</bitRange> 7481 <enumeratedValues> 7482 <enumeratedValue> 7483 <name>en</name> 7484 <description>Enabled.</description> 7485 <value>0</value> 7486 </enumeratedValue> 7487 <enumeratedValue> 7488 <name>dis</name> 7489 <description>Disabled.</description> 7490 <value>1</value> 7491 </enumeratedValue> 7492 </enumeratedValues> 7493 </field> 7494 <field> 7495 <name>NACK_FLUSH_DIS</name> 7496 <description>TX FIFO received NACK Auto Flush Disable.</description> 7497 <bitRange>[5:5]</bitRange> 7498 <enumeratedValues> 7499 <enumeratedValue> 7500 <name>en</name> 7501 <description>Enabled.</description> 7502 <value>0</value> 7503 </enumeratedValue> 7504 <enumeratedValue> 7505 <name>dis</name> 7506 <description>Disabled.</description> 7507 <value>1</value> 7508 </enumeratedValue> 7509 </enumeratedValues> 7510 </field> 7511 <field> 7512 <name>FLUSH</name> 7513 <description>Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.</description> 7514 <bitRange>[7:7]</bitRange> 7515 <enumeratedValues> 7516 <enumeratedValue> 7517 <name>not_flushed</name> 7518 <description>FIFO not flushed.</description> 7519 <value>0</value> 7520 </enumeratedValue> 7521 <enumeratedValue> 7522 <name>flush</name> 7523 <description>Flush TX_FIFO.</description> 7524 <value>1</value> 7525 </enumeratedValue> 7526 </enumeratedValues> 7527 </field> 7528 <field> 7529 <name>THD_VAL</name> 7530 <description>Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.</description> 7531 <bitRange>[11:8]</bitRange> 7532 </field> 7533 </fields> 7534 </register> 7535 <register> 7536 <name>TXCTRL1</name> 7537 <description>Transmit Control Register 1.</description> 7538 <addressOffset>0x28</addressOffset> 7539 <fields> 7540 <field> 7541 <name>PRELOAD_RDY</name> 7542 <description>Transmit FIFO Preload Ready.</description> 7543 <bitRange>[0:0]</bitRange> 7544 </field> 7545 <field> 7546 <name>LAST</name> 7547 <description>Transmit Last.</description> 7548 <bitRange>[1:1]</bitRange> 7549 </field> 7550 <field> 7551 <name>LVL</name> 7552 <description>Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.</description> 7553 <bitRange>[11:8]</bitRange> 7554 <access>read-only</access> 7555 </field> 7556 </fields> 7557 </register> 7558 <register> 7559 <name>FIFO</name> 7560 <description>Data Register.</description> 7561 <addressOffset>0x2C</addressOffset> 7562 <fields> 7563 <field> 7564 <name>DATA</name> 7565 <description>Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.</description> 7566 <bitOffset>0</bitOffset> 7567 <bitWidth>8</bitWidth> 7568 </field> 7569 </fields> 7570 </register> 7571 <register> 7572 <name>MSTCTRL</name> 7573 <description>Master Control Register.</description> 7574 <addressOffset>0x30</addressOffset> 7575 <fields> 7576 <field> 7577 <name>START</name> 7578 <description>Setting this bit to 1 will start a master transfer.</description> 7579 <bitRange>[0:0]</bitRange> 7580 </field> 7581 <field> 7582 <name>RESTART</name> 7583 <description>Setting this bit to 1 will generate a repeated START.</description> 7584 <bitRange>[1:1]</bitRange> 7585 </field> 7586 <field> 7587 <name>STOP</name> 7588 <description>Setting this bit to 1 will generate a STOP condition.</description> 7589 <bitRange>[2:2]</bitRange> 7590 </field> 7591 <field> 7592 <name>EX_ADDR_EN</name> 7593 <description>Slave Extend Address Select.</description> 7594 <bitRange>[7:7]</bitRange> 7595 <enumeratedValues> 7596 <enumeratedValue> 7597 <name>7_bits_address</name> 7598 <description>7-bit address.</description> 7599 <value>0</value> 7600 </enumeratedValue> 7601 <enumeratedValue> 7602 <name>10_bits_address</name> 7603 <description>10-bit address.</description> 7604 <value>1</value> 7605 </enumeratedValue> 7606 </enumeratedValues> 7607 </field> 7608 <field> 7609 <name>CODE</name> 7610 <description>Master Code.</description> 7611 <bitRange>[10:8]</bitRange> 7612 </field> 7613 <field> 7614 <name>IGN_ACK</name> 7615 <description>Master Ignore Acknowledge.</description> 7616 <bitRange>[12:12]</bitRange> 7617 </field> 7618 </fields> 7619 </register> 7620 <register> 7621 <name>CLKLO</name> 7622 <description>Clock Low Register.</description> 7623 <addressOffset>0x34</addressOffset> 7624 <fields> 7625 <field> 7626 <name>LO</name> 7627 <description>Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.</description> 7628 <bitRange>[8:0]</bitRange> 7629 </field> 7630 </fields> 7631 </register> 7632 <register> 7633 <name>CLKHI</name> 7634 <description>Clock high Register.</description> 7635 <addressOffset>0x38</addressOffset> 7636 <fields> 7637 <field> 7638 <name>HI</name> 7639 <description>Clock High. In master mode, these bits define the SCL high period.</description> 7640 <bitRange>[8:0]</bitRange> 7641 </field> 7642 </fields> 7643 </register> 7644 <register> 7645 <name>HSCLK</name> 7646 <description>Clock high Register.</description> 7647 <addressOffset>0x3C</addressOffset> 7648 <fields> 7649 <field> 7650 <name>LO</name> 7651 <description>Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA.</description> 7652 <bitRange>[7:0]</bitRange> 7653 </field> 7654 <field> 7655 <name>HI</name> 7656 <description>Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA</description> 7657 <bitRange>[15:8]</bitRange> 7658 </field> 7659 </fields> 7660 </register> 7661 <register> 7662 <name>TIMEOUT</name> 7663 <description>Timeout Register</description> 7664 <addressOffset>0x40</addressOffset> 7665 <fields> 7666 <field> 7667 <name>SCL_TO_VAL</name> 7668 <description>Timeout</description> 7669 <bitRange>[15:0]</bitRange> 7670 </field> 7671 </fields> 7672 </register> 7673 <register> 7674 <name>DMA</name> 7675 <description>DMA Register.</description> 7676 <addressOffset>0x48</addressOffset> 7677 <fields> 7678 <field> 7679 <name>TX_EN</name> 7680 <description>TX channel enable.</description> 7681 <bitRange>[0:0]</bitRange> 7682 <enumeratedValues> 7683 <enumeratedValue> 7684 <name>dis</name> 7685 <description>Disable.</description> 7686 <value>0</value> 7687 </enumeratedValue> 7688 <enumeratedValue> 7689 <name>en</name> 7690 <description>Enable.</description> 7691 <value>1</value> 7692 </enumeratedValue> 7693 </enumeratedValues> 7694 </field> 7695 <field> 7696 <name>RX_EN</name> 7697 <description>RX channel enable.</description> 7698 <bitRange>[1:1]</bitRange> 7699 <enumeratedValues> 7700 <enumeratedValue> 7701 <name>dis</name> 7702 <description>Disable.</description> 7703 <value>0</value> 7704 </enumeratedValue> 7705 <enumeratedValue> 7706 <name>en</name> 7707 <description>Enable.</description> 7708 <value>1</value> 7709 </enumeratedValue> 7710 </enumeratedValues> 7711 </field> 7712 </fields> 7713 </register> 7714 <register> 7715 <dim>4</dim> 7716 <dimIncrement>4</dimIncrement> 7717 <name>SLAVE_MULTI[%s]</name> 7718 <description>Slave Address Register.</description> 7719 <alternateRegister>SLAVE0</alternateRegister> 7720 <addressOffset>0x4C</addressOffset> 7721 <size>32</size> 7722 <access>read-write</access> 7723 <fields> 7724 <field> 7725 <name>ADDR</name> 7726 <description>Slave Address.</description> 7727 <bitRange>[9:0]</bitRange> 7728 </field> 7729 <field> 7730 <name>DIS</name> 7731 <description>Slave Disable.</description> 7732 <bitRange>[10:10]</bitRange> 7733 </field> 7734 <field> 7735 <name>EXT_ADDR_EN</name> 7736 <description>Extended Address Select.</description> 7737 <bitRange>[15:15]</bitRange> 7738 <enumeratedValues> 7739 <enumeratedValue> 7740 <name>7_bits_address</name> 7741 <description>7-bit address.</description> 7742 <value>0</value> 7743 </enumeratedValue> 7744 <enumeratedValue> 7745 <name>10_bits_address</name> 7746 <description>10-bit address.</description> 7747 <value>1</value> 7748 </enumeratedValue> 7749 </enumeratedValues> 7750 </field> 7751 </fields> 7752 </register> 7753 <register> 7754 <name>SLAVE0</name> 7755 <description>Slave Address Register.</description> 7756 <addressOffset>0x4C</addressOffset> 7757 </register> 7758 <register> 7759 <name>SLAVE1</name> 7760 <description>Slave Address Register.</description> 7761 <addressOffset>0x50</addressOffset> 7762 </register> 7763 <register> 7764 <name>SLAVE2</name> 7765 <description>Slave Address Register.</description> 7766 <addressOffset>0x54</addressOffset> 7767 </register> 7768 <register> 7769 <name>SLAVE3</name> 7770 <description>Slave Address Register.</description> 7771 <addressOffset>0x58</addressOffset> 7772 </register> 7773 </registers> 7774 </peripheral> 7775<!--I2C0 Inter-Integrated Circuit.--> 7776 <peripheral derivedFrom="I2C0"> 7777 <name>I2C1</name> 7778 <description>Inter-Integrated Circuit. 1</description> 7779 <baseAddress>0x4001E000</baseAddress> 7780 <interrupt> 7781 <name>I2C1</name> 7782 <description>I2C1 IRQ</description> 7783 <value>36</value> 7784 </interrupt> 7785 </peripheral> 7786<!--I2C1 Inter-Integrated Circuit. 1--> 7787 <peripheral derivedFrom="I2C0"> 7788 <name>I2C2</name> 7789 <description>Inter-Integrated Circuit. 2</description> 7790 <baseAddress>0x4001F000</baseAddress> 7791 <interrupt> 7792 <name>I2C2</name> 7793 <description>I2C2 IRQ</description> 7794 <value>62</value> 7795 </interrupt> 7796 </peripheral> 7797<!--I2C2 Inter-Integrated Circuit. 2--> 7798 <peripheral> 7799 <name>SFCC</name> 7800 <description>SPIXF Cache Controller Registers</description> 7801 <baseAddress>0x4002F000</baseAddress> 7802 <addressBlock> 7803 <offset>0x00</offset> 7804 <size>0x1000</size> 7805 <usage>registers</usage> 7806 </addressBlock> 7807 <registers> 7808 <register> 7809 <name>INFO</name> 7810 <description>Cache ID Register.</description> 7811 <addressOffset>0x0000</addressOffset> 7812 <access>read-only</access> 7813 <fields> 7814 <field> 7815 <name>RELNUM</name> 7816 <description>Release Number. Identifies the RTL release version.</description> 7817 <bitOffset>0</bitOffset> 7818 <bitWidth>6</bitWidth> 7819 </field> 7820 <field> 7821 <name>PARTNUM</name> 7822 <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description> 7823 <bitOffset>6</bitOffset> 7824 <bitWidth>4</bitWidth> 7825 </field> 7826 <field> 7827 <name>ID</name> 7828 <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description> 7829 <bitOffset>10</bitOffset> 7830 <bitWidth>6</bitWidth> 7831 </field> 7832 </fields> 7833 </register> 7834 <register> 7835 <name>SZ</name> 7836 <description>Memory Configuration Register.</description> 7837 <addressOffset>0x0004</addressOffset> 7838 <access>read-only</access> 7839 <resetValue>0x00080008</resetValue> 7840 <fields> 7841 <field> 7842 <name>CCH</name> 7843 <description>Cache Size. Indicates total size in Kbytes of cache.</description> 7844 <bitOffset>0</bitOffset> 7845 <bitWidth>16</bitWidth> 7846 </field> 7847 <field> 7848 <name>MEM</name> 7849 <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description> 7850 <bitOffset>16</bitOffset> 7851 <bitWidth>16</bitWidth> 7852 </field> 7853 </fields> 7854 </register> 7855 <register> 7856 <name>CTRL</name> 7857 <description>Cache Control and Status Register.</description> 7858 <addressOffset>0x0100</addressOffset> 7859 <fields> 7860 <field> 7861 <name>EN</name> 7862 <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description> 7863 <bitOffset>0</bitOffset> 7864 <bitWidth>1</bitWidth> 7865 <enumeratedValues> 7866 <enumeratedValue> 7867 <name>dis</name> 7868 <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description> 7869 <value>0</value> 7870 </enumeratedValue> 7871 <enumeratedValue> 7872 <name>en</name> 7873 <description>Cache Enabled.</description> 7874 <value>1</value> 7875 </enumeratedValue> 7876 </enumeratedValues> 7877 </field> 7878 <field> 7879 <name>RDY</name> 7880 <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description> 7881 <bitOffset>16</bitOffset> 7882 <bitWidth>1</bitWidth> 7883 <access>read-only</access> 7884 <enumeratedValues> 7885 <enumeratedValue> 7886 <name>notReady</name> 7887 <description>Not Ready.</description> 7888 <value>0</value> 7889 </enumeratedValue> 7890 <enumeratedValue> 7891 <name>ready</name> 7892 <description>Ready.</description> 7893 <value>1</value> 7894 </enumeratedValue> 7895 </enumeratedValues> 7896 </field> 7897 </fields> 7898 </register> 7899 <register> 7900 <name>INVALIDATE</name> 7901 <description>Invalidate All Registers.</description> 7902 <addressOffset>0x0700</addressOffset> 7903 <access>read-write</access> 7904 <fields> 7905 <field> 7906 <name>INVALID</name> 7907 <description>Invalidate.</description> 7908 <bitOffset>0</bitOffset> 7909 <bitWidth>32</bitWidth> 7910 </field> 7911 </fields> 7912 </register> 7913 </registers> 7914 </peripheral> 7915<!--SFCC SPIXF Cache Controller Registers--> 7916 <peripheral> 7917 <name>OTP</name> 7918 <description>One-Time Programmable (OTP) Memory Controller.</description> 7919 <groupName>OTP</groupName> 7920 <baseAddress>0x40041000</baseAddress> 7921 <addressBlock> 7922 <offset>0x00</offset> 7923 <size>0x1000</size> 7924 <usage>registers</usage> 7925 </addressBlock> 7926 <registers> 7927 <register> 7928 <name>CTRL</name> 7929 <description>OTP Control Register.</description> 7930 <addressOffset>0x00</addressOffset> 7931 <fields> 7932 <field> 7933 <name>ADDR</name> 7934 <description>Address of the OTP 32 bit value.</description> 7935 <bitOffset>0</bitOffset> 7936 <bitWidth>16</bitWidth> 7937 </field> 7938 <field> 7939 <name>READ</name> 7940 <description>Read Operation. Setting this bit starts a read operation from the OTP.</description> 7941 <bitOffset>24</bitOffset> 7942 <bitWidth>1</bitWidth> 7943 <enumeratedValues> 7944 <enumeratedValue> 7945 <name>no_op</name> 7946 <description>No operation.</description> 7947 <value>0</value> 7948 </enumeratedValue> 7949 <enumeratedValue> 7950 <name>start</name> 7951 <description>Initiate program operation.</description> 7952 <value>1</value> 7953 </enumeratedValue> 7954 </enumeratedValues> 7955 </field> 7956 <field> 7957 <name>WRITE</name> 7958 <description>Program Operation. Setting this bit starts a write operation from the OTP location specified in the ADDR field.</description> 7959 <bitOffset>25</bitOffset> 7960 <bitWidth>1</bitWidth> 7961 </field> 7962 </fields> 7963 </register> 7964 <register> 7965 <name>CLKDIV</name> 7966 <description>OTP Clock Divide Register.</description> 7967 <addressOffset>0x04</addressOffset> 7968 <fields> 7969 <field> 7970 <name>PCLKDIV</name> 7971 <description>Clock Divider. The input clock, PCLK, is divided for generating OTP timing signals.</description> 7972 <bitOffset>0</bitOffset> 7973 <bitWidth>6</bitWidth> 7974 <enumeratedValues> 7975 <enumeratedValue> 7976 <name>DIV2</name> 7977 <description>Divide by 2</description> 7978 <value>1</value> 7979 </enumeratedValue> 7980 <enumeratedValue> 7981 <name>DIV4</name> 7982 <description>Divide by 4</description> 7983 <value>3</value> 7984 </enumeratedValue> 7985 <enumeratedValue> 7986 <name>DIV8</name> 7987 <description>Divide by 8</description> 7988 <value>7</value> 7989 </enumeratedValue> 7990 <enumeratedValue> 7991 <name>DIV16</name> 7992 <description>Divide by 16</description> 7993 <value>15</value> 7994 </enumeratedValue> 7995 <enumeratedValue> 7996 <name>DIV32</name> 7997 <description>Divide by 32</description> 7998 <value>31</value> 7999 </enumeratedValue> 8000 </enumeratedValues> 8001 </field> 8002 <field> 8003 <name>SPWE</name> 8004 <description>Smart PWE. If programmed value is 1, don't assert PWE.</description> 8005 <bitOffset>8</bitOffset> 8006 <bitWidth>1</bitWidth> 8007 </field> 8008 <field> 8009 <name>PD</name> 8010 <description>Power Down OTP. OTP controller will generate power up and down signals for control pins.</description> 8011 <bitOffset>9</bitOffset> 8012 <bitWidth>1</bitWidth> 8013 </field> 8014 <field> 8015 <name>HCLKDIV</name> 8016 <description>Clock Divider. The input clock, HCLK, is divided for generating OTP pwr on and down timing signals.</description> 8017 <bitOffset>16</bitOffset> 8018 <bitWidth>6</bitWidth> 8019 </field> 8020 </fields> 8021 </register> 8022 <register> 8023 <name>RDATA</name> 8024 <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description> 8025 <addressOffset>0x08</addressOffset> 8026 <fields> 8027 <field> 8028 <name>DATA</name> 8029 <description>OTP Read Data.</description> 8030 <bitOffset>0</bitOffset> 8031 <bitWidth>32</bitWidth> 8032 </field> 8033 </fields> 8034 </register> 8035 <register> 8036 <name>STATUS</name> 8037 <description>OTP Status Register.</description> 8038 <addressOffset>0x0C</addressOffset> 8039 <fields> 8040 <field> 8041 <name>BUSY</name> 8042 <description>OTP Busy Flag. This bit indicates whether the OTP controller is working a read or write operation.</description> 8043 <bitOffset>0</bitOffset> 8044 <bitWidth>1</bitWidth> 8045 </field> 8046 <field> 8047 <name>FAIL</name> 8048 <description>OTP Failed Flag. This bit indicates whether OTP programming has failed. OTP programming fails if the controller accesses a 32 bit location that has not been previously programmed.</description> 8049 <bitOffset>1</bitOffset> 8050 <bitWidth>1</bitWidth> 8051 </field> 8052 <field> 8053 <name>UNLOCK1</name> 8054 <description>Unlock1 Flag. This bit indicates that 1st password was entered, and the user block is enabled for OTP programming.</description> 8055 <bitOffset>8</bitOffset> 8056 <bitWidth>1</bitWidth> 8057 </field> 8058 <field> 8059 <name>UNLOCK3</name> 8060 <description>Unlock3 Flag. This bit indicates that 3 words unlock process is complete.</description> 8061 <bitOffset>9</bitOffset> 8062 <bitWidth>1</bitWidth> 8063 </field> 8064 <field> 8065 <name>PWR_RDY</name> 8066 <description>OTP Power On Status.</description> 8067 <bitOffset>16</bitOffset> 8068 <bitWidth>1</bitWidth> 8069 </field> 8070 </fields> 8071 </register> 8072 <register> 8073 <name>WDATA</name> 8074 <description>OTP Write Data Register.</description> 8075 <addressOffset>0x30</addressOffset> 8076 <fields> 8077 <field> 8078 <name>DATA</name> 8079 <description>Write Data.</description> 8080 <bitOffset>0</bitOffset> 8081 <bitWidth>32</bitWidth> 8082 </field> 8083 </fields> 8084 </register> 8085 <register> 8086 <name>ACTRL0</name> 8087 <description>Access Control for user block.</description> 8088 <addressOffset>0x3C</addressOffset> 8089 <fields> 8090 <field> 8091 <name>ADATA</name> 8092 <description>User Block Access Control.</description> 8093 <bitOffset>0</bitOffset> 8094 <bitWidth>32</bitWidth> 8095 </field> 8096 </fields> 8097 </register> 8098 <register> 8099 <name>ACTRL1</name> 8100 <description>Access Control for sys and user block.</description> 8101 <addressOffset>0x40</addressOffset> 8102 <fields> 8103 <field> 8104 <name>ADATA</name> 8105 <description>System Info Block Access Data.</description> 8106 <bitOffset>0</bitOffset> 8107 <bitWidth>32</bitWidth> 8108 </field> 8109 </fields> 8110 </register> 8111 </registers> 8112 </peripheral> 8113<!--OTP One-Time Programmable (OTP) Memory Controller.--> 8114 <peripheral> 8115 <name>PT</name> 8116 <description>Pulse Train</description> 8117 <groupName>Pulse_Train</groupName> 8118 <baseAddress>0x4003C020</baseAddress> 8119 <size>32</size> 8120 <access>read-write</access> 8121 <addressBlock> 8122 <offset>0</offset> 8123 <size>0x0010</size> 8124 <usage>registers</usage> 8125 </addressBlock> 8126 <registers> 8127 <register> 8128 <name>RATE_LENGTH</name> 8129 <description>Pulse Train Configuration</description> 8130 <addressOffset>0x0000</addressOffset> 8131 <access>read-write</access> 8132 <fields> 8133 <field> 8134 <name>rate_control</name> 8135 <description>Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.</description> 8136 <bitOffset>0</bitOffset> 8137 <bitWidth>27</bitWidth> 8138 <access>read-write</access> 8139 </field> 8140 <field> 8141 <name>mode</name> 8142 <description>Pulse Train Output Mode/Train Length</description> 8143 <bitOffset>27</bitOffset> 8144 <bitWidth>5</bitWidth> 8145 <access>read-write</access> 8146 <enumeratedValues> 8147 <enumeratedValue> 8148 <name>32_BIT</name> 8149 <description>Pulse train, 32 bit pattern.</description> 8150 <value>0</value> 8151 </enumeratedValue> 8152 <enumeratedValue> 8153 <name>SQUARE_WAVE</name> 8154 <description>Square wave mode.</description> 8155 <value>1</value> 8156 </enumeratedValue> 8157 <enumeratedValue> 8158 <name>2_BIT</name> 8159 <description>Pulse train, 2 bit pattern.</description> 8160 <value>2</value> 8161 </enumeratedValue> 8162 <enumeratedValue> 8163 <name>3_BIT</name> 8164 <description>Pulse train, 3 bit pattern.</description> 8165 <value>3</value> 8166 </enumeratedValue> 8167 <enumeratedValue> 8168 <name>4_BIT</name> 8169 <description>Pulse train, 4 bit pattern.</description> 8170 <value>4</value> 8171 </enumeratedValue> 8172 <enumeratedValue> 8173 <name>5_BIT</name> 8174 <description>Pulse train, 5 bit pattern.</description> 8175 <value>5</value> 8176 </enumeratedValue> 8177 <enumeratedValue> 8178 <name>6_BIT</name> 8179 <description>Pulse train, 6 bit pattern.</description> 8180 <value>6</value> 8181 </enumeratedValue> 8182 <enumeratedValue> 8183 <name>7_BIT</name> 8184 <description>Pulse train, 7 bit pattern.</description> 8185 <value>7</value> 8186 </enumeratedValue> 8187 <enumeratedValue> 8188 <name>8_BIT</name> 8189 <description>Pulse train, 8 bit pattern.</description> 8190 <value>8</value> 8191 </enumeratedValue> 8192 <enumeratedValue> 8193 <name>9_BIT</name> 8194 <description>Pulse train, 9 bit pattern.</description> 8195 <value>9</value> 8196 </enumeratedValue> 8197 <enumeratedValue> 8198 <name>10_BIT</name> 8199 <description>Pulse train, 10 bit pattern.</description> 8200 <value>10</value> 8201 </enumeratedValue> 8202 <enumeratedValue> 8203 <name>11_BIT</name> 8204 <description>Pulse train, 11 bit pattern.</description> 8205 <value>11</value> 8206 </enumeratedValue> 8207 <enumeratedValue> 8208 <name>12_BIT</name> 8209 <description>Pulse train, 12 bit pattern.</description> 8210 <value>12</value> 8211 </enumeratedValue> 8212 <enumeratedValue> 8213 <name>13_BIT</name> 8214 <description>Pulse train, 13 bit pattern.</description> 8215 <value>13</value> 8216 </enumeratedValue> 8217 <enumeratedValue> 8218 <name>14_BIT</name> 8219 <description>Pulse train, 14 bit pattern.</description> 8220 <value>14</value> 8221 </enumeratedValue> 8222 <enumeratedValue> 8223 <name>15_BIT</name> 8224 <description>Pulse train, 15 bit pattern.</description> 8225 <value>15</value> 8226 </enumeratedValue> 8227 <enumeratedValue> 8228 <name>16_BIT</name> 8229 <description>Pulse train, 16 bit pattern.</description> 8230 <value>16</value> 8231 </enumeratedValue> 8232 <enumeratedValue> 8233 <name>17_BIT</name> 8234 <description>Pulse train, 17 bit pattern.</description> 8235 <value>17</value> 8236 </enumeratedValue> 8237 <enumeratedValue> 8238 <name>18_BIT</name> 8239 <description>Pulse train, 18 bit pattern.</description> 8240 <value>18</value> 8241 </enumeratedValue> 8242 <enumeratedValue> 8243 <name>19_BIT</name> 8244 <description>Pulse train, 19 bit pattern.</description> 8245 <value>19</value> 8246 </enumeratedValue> 8247 <enumeratedValue> 8248 <name>20_BIT</name> 8249 <description>Pulse train, 20 bit pattern.</description> 8250 <value>20</value> 8251 </enumeratedValue> 8252 <enumeratedValue> 8253 <name>21_BIT</name> 8254 <description>Pulse train, 21 bit pattern.</description> 8255 <value>21</value> 8256 </enumeratedValue> 8257 <enumeratedValue> 8258 <name>22_BIT</name> 8259 <description>Pulse train, 22 bit pattern.</description> 8260 <value>22</value> 8261 </enumeratedValue> 8262 <enumeratedValue> 8263 <name>23_BIT</name> 8264 <description>Pulse train, 23 bit pattern.</description> 8265 <value>23</value> 8266 </enumeratedValue> 8267 <enumeratedValue> 8268 <name>24_BIT</name> 8269 <description>Pulse train, 24 bit pattern.</description> 8270 <value>24</value> 8271 </enumeratedValue> 8272 <enumeratedValue> 8273 <name>25_BIT</name> 8274 <description>Pulse train, 25 bit pattern.</description> 8275 <value>25</value> 8276 </enumeratedValue> 8277 <enumeratedValue> 8278 <name>26_BIT</name> 8279 <description>Pulse train, 26 bit pattern.</description> 8280 <value>26</value> 8281 </enumeratedValue> 8282 <enumeratedValue> 8283 <name>27_BIT</name> 8284 <description>Pulse train, 27 bit pattern.</description> 8285 <value>27</value> 8286 </enumeratedValue> 8287 <enumeratedValue> 8288 <name>28_BIT</name> 8289 <description>Pulse train, 28 bit pattern.</description> 8290 <value>28</value> 8291 </enumeratedValue> 8292 <enumeratedValue> 8293 <name>29_BIT</name> 8294 <description>Pulse train, 29 bit pattern.</description> 8295 <value>29</value> 8296 </enumeratedValue> 8297 <enumeratedValue> 8298 <name>30_BIT</name> 8299 <description>Pulse train, 30 bit pattern.</description> 8300 <value>30</value> 8301 </enumeratedValue> 8302 <enumeratedValue> 8303 <name>31_BIT</name> 8304 <description>Pulse train, 31 bit pattern.</description> 8305 <value>31</value> 8306 </enumeratedValue> 8307 </enumeratedValues> 8308 </field> 8309 </fields> 8310 </register> 8311 <register> 8312 <name>TRAIN</name> 8313 <description>Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.</description> 8314 <addressOffset>0x0004</addressOffset> 8315 <access>read-write</access> 8316 </register> 8317 <register> 8318 <name>LOOP</name> 8319 <description>Pulse Train Loop Count</description> 8320 <addressOffset>0x0008</addressOffset> 8321 <access>read-write</access> 8322 <fields> 8323 <field> 8324 <name>count</name> 8325 <description>Number of loops for this pulse train to repeat.</description> 8326 <bitOffset>0</bitOffset> 8327 <bitWidth>16</bitWidth> 8328 <access>read-write</access> 8329 </field> 8330 <field> 8331 <name>delay</name> 8332 <description>Delay between loops of the Pulse Train in PT Peripheral Clock cycles</description> 8333 <bitOffset>16</bitOffset> 8334 <bitWidth>12</bitWidth> 8335 <access>read-write</access> 8336 </field> 8337 </fields> 8338 </register> 8339 <register> 8340 <name>RESTART</name> 8341 <description> Pulse Train Auto-Restart Configuration.</description> 8342 <addressOffset>0x000C</addressOffset> 8343 <access>read-write</access> 8344 <fields> 8345 <field> 8346 <name>pt_x_select</name> 8347 <description>Auto-Restart PT X Select</description> 8348 <bitOffset>0</bitOffset> 8349 <bitWidth>5</bitWidth> 8350 <access>read-write</access> 8351 </field> 8352 <field> 8353 <name>on_pt_x_loop_exit</name> 8354 <description>Enable Auto-Restart on PT X Loop Exit</description> 8355 <bitOffset>7</bitOffset> 8356 <bitWidth>1</bitWidth> 8357 <access>read-write</access> 8358 </field> 8359 <field> 8360 <name>pt_y_select</name> 8361 <description>Auto-Restart PT Y Select</description> 8362 <bitOffset>8</bitOffset> 8363 <bitWidth>5</bitWidth> 8364 <access>read-write</access> 8365 </field> 8366 <field> 8367 <name>on_pt_y_loop_exit</name> 8368 <description>Enable Auto-Restart on PT Y Loop Exit</description> 8369 <bitOffset>15</bitOffset> 8370 <bitWidth>1</bitWidth> 8371 <access>read-write</access> 8372 </field> 8373 </fields> 8374 </register> 8375 </registers> 8376 </peripheral> 8377<!--PT Pulse Train--> 8378 <peripheral derivedFrom="PT"> 8379 <name>PT1</name> 8380 <description>Pulse Train 1</description> 8381 <baseAddress>0x4003C030</baseAddress> 8382 </peripheral> 8383<!--PT1 Pulse Train 1--> 8384 <peripheral derivedFrom="PT"> 8385 <name>PT2</name> 8386 <description>Pulse Train 2</description> 8387 <baseAddress>0x4003C040</baseAddress> 8388 </peripheral> 8389<!--PT2 Pulse Train 2--> 8390 <peripheral derivedFrom="PT"> 8391 <name>PT3</name> 8392 <description>Pulse Train 3</description> 8393 <baseAddress>0x4003C050</baseAddress> 8394 </peripheral> 8395<!--PT3 Pulse Train 3--> 8396 <peripheral derivedFrom="PT"> 8397 <name>PT4</name> 8398 <description>Pulse Train 4</description> 8399 <baseAddress>0x4003C060</baseAddress> 8400 </peripheral> 8401<!--PT4 Pulse Train 4--> 8402 <peripheral derivedFrom="PT"> 8403 <name>PT5</name> 8404 <description>Pulse Train 5</description> 8405 <baseAddress>0x4003C070</baseAddress> 8406 </peripheral> 8407<!--PT5 Pulse Train 5--> 8408 <peripheral derivedFrom="PT"> 8409 <name>PT6</name> 8410 <description>Pulse Train 6</description> 8411 <baseAddress>0x4003C080</baseAddress> 8412 </peripheral> 8413<!--PT6 Pulse Train 6--> 8414 <peripheral derivedFrom="PT"> 8415 <name>PT7</name> 8416 <description>Pulse Train 7</description> 8417 <baseAddress>0x4003C090</baseAddress> 8418 </peripheral> 8419<!--PT7 Pulse Train 7--> 8420 <peripheral derivedFrom="PT"> 8421 <name>PT8</name> 8422 <description>Pulse Train 8</description> 8423 <baseAddress /> 8424 </peripheral> 8425<!--PT8 Pulse Train 8--> 8426 <peripheral> 8427 <name>PTG</name> 8428 <description>Pulse Train Generation</description> 8429 <groupName>Pulse_Train</groupName> 8430 <baseAddress>0x4003C000</baseAddress> 8431 <size>32</size> 8432 <access>read-write</access> 8433 <addressBlock> 8434 <offset>0</offset> 8435 <size>0x0020</size> 8436 <usage>registers</usage> 8437 </addressBlock> 8438 <interrupt> 8439 <name>PT</name> 8440 <description>Pulse Train IRQ</description> 8441 <value>59</value> 8442 </interrupt> 8443 <registers> 8444 <register> 8445 <name>ENABLE</name> 8446 <description>Global Enable/Disable Controls for All Pulse Trains</description> 8447 <addressOffset>0x0000</addressOffset> 8448 <access>read-write</access> 8449 <fields> 8450 <field> 8451 <name>pt0</name> 8452 <description>Enable/Disable control for PT0</description> 8453 <bitOffset>0</bitOffset> 8454 <bitWidth>1</bitWidth> 8455 <access>read-write</access> 8456 </field> 8457 <field> 8458 <name>pt1</name> 8459 <description>Enable/Disable control for PT1</description> 8460 <bitOffset>1</bitOffset> 8461 <bitWidth>1</bitWidth> 8462 <access>read-write</access> 8463 </field> 8464 <field> 8465 <name>pt2</name> 8466 <description>Enable/Disable control for PT2</description> 8467 <bitOffset>2</bitOffset> 8468 <bitWidth>1</bitWidth> 8469 <access>read-write</access> 8470 </field> 8471 <field> 8472 <name>pt3</name> 8473 <description>Enable/Disable control for PT3</description> 8474 <bitOffset>3</bitOffset> 8475 <bitWidth>1</bitWidth> 8476 <access>read-write</access> 8477 </field> 8478 <field> 8479 <name>pt4</name> 8480 <description>Enable/Disable control for PT4</description> 8481 <bitOffset>4</bitOffset> 8482 <bitWidth>1</bitWidth> 8483 <access>read-write</access> 8484 </field> 8485 <field> 8486 <name>pt5</name> 8487 <description>Enable/Disable control for PT5</description> 8488 <bitOffset>5</bitOffset> 8489 <bitWidth>1</bitWidth> 8490 <access>read-write</access> 8491 </field> 8492 <field> 8493 <name>pt6</name> 8494 <description>Enable/Disable control for PT6</description> 8495 <bitOffset>6</bitOffset> 8496 <bitWidth>1</bitWidth> 8497 <access>read-write</access> 8498 </field> 8499 <field> 8500 <name>pt7</name> 8501 <description>Enable/Disable control for PT7</description> 8502 <bitOffset>7</bitOffset> 8503 <bitWidth>1</bitWidth> 8504 <access>read-write</access> 8505 </field> 8506 </fields> 8507 </register> 8508 <register> 8509 <name>RESYNC</name> 8510 <description>Global Resync (All Pulse Trains) Control</description> 8511 <addressOffset>0x0004</addressOffset> 8512 <access>read-write</access> 8513 <fields> 8514 <field> 8515 <name>pt0</name> 8516 <description>Resync control for PT0</description> 8517 <bitOffset>0</bitOffset> 8518 <bitWidth>1</bitWidth> 8519 <access>read-write</access> 8520 </field> 8521 <field> 8522 <name>pt1</name> 8523 <description>Resync control for PT1</description> 8524 <bitOffset>1</bitOffset> 8525 <bitWidth>1</bitWidth> 8526 <access>read-write</access> 8527 </field> 8528 <field> 8529 <name>pt2</name> 8530 <description>Resync control for PT2</description> 8531 <bitOffset>2</bitOffset> 8532 <bitWidth>1</bitWidth> 8533 <access>read-write</access> 8534 </field> 8535 <field> 8536 <name>pt3</name> 8537 <description>Resync control for PT3</description> 8538 <bitOffset>3</bitOffset> 8539 <bitWidth>1</bitWidth> 8540 <access>read-write</access> 8541 </field> 8542 <field> 8543 <name>pt4</name> 8544 <description>Resync control for PT4</description> 8545 <bitOffset>4</bitOffset> 8546 <bitWidth>1</bitWidth> 8547 <access>read-write</access> 8548 </field> 8549 <field> 8550 <name>pt5</name> 8551 <description>Resync control for PT5</description> 8552 <bitOffset>5</bitOffset> 8553 <bitWidth>1</bitWidth> 8554 <access>read-write</access> 8555 </field> 8556 <field> 8557 <name>pt6</name> 8558 <description>Resync control for PT6</description> 8559 <bitOffset>6</bitOffset> 8560 <bitWidth>1</bitWidth> 8561 <access>read-write</access> 8562 </field> 8563 <field> 8564 <name>pt7</name> 8565 <description>Resync control for PT7</description> 8566 <bitOffset>7</bitOffset> 8567 <bitWidth>1</bitWidth> 8568 <access>read-write</access> 8569 </field> 8570 </fields> 8571 </register> 8572 <register> 8573 <name>STOP_INTFL</name> 8574 <description>Pulse Train Stop Interrupt Flags</description> 8575 <addressOffset>0x0008</addressOffset> 8576 <access>read-write</access> 8577 <fields> 8578 <field> 8579 <name>pt0</name> 8580 <description>Pulse Train 0 Stopped Interrupt Flag</description> 8581 <bitOffset>0</bitOffset> 8582 <bitWidth>1</bitWidth> 8583 <access>read-write</access> 8584 </field> 8585 <field> 8586 <name>pt1</name> 8587 <description>Pulse Train 1 Stopped Interrupt Flag</description> 8588 <bitOffset>1</bitOffset> 8589 <bitWidth>1</bitWidth> 8590 <access>read-write</access> 8591 </field> 8592 <field> 8593 <name>pt2</name> 8594 <description>Pulse Train 2 Stopped Interrupt Flag</description> 8595 <bitOffset>2</bitOffset> 8596 <bitWidth>1</bitWidth> 8597 <access>read-write</access> 8598 </field> 8599 <field> 8600 <name>pt3</name> 8601 <description>Pulse Train 3 Stopped Interrupt Flag</description> 8602 <bitOffset>3</bitOffset> 8603 <bitWidth>1</bitWidth> 8604 <access>read-write</access> 8605 </field> 8606 <field> 8607 <name>pt4</name> 8608 <description>Pulse Train 4 Stopped Interrupt Flag</description> 8609 <bitOffset>4</bitOffset> 8610 <bitWidth>1</bitWidth> 8611 <access>read-write</access> 8612 </field> 8613 <field> 8614 <name>pt5</name> 8615 <description>Pulse Train 5 Stopped Interrupt Flag</description> 8616 <bitOffset>5</bitOffset> 8617 <bitWidth>1</bitWidth> 8618 <access>read-write</access> 8619 </field> 8620 <field> 8621 <name>pt6</name> 8622 <description>Pulse Train 6 Stopped Interrupt Flag</description> 8623 <bitOffset>6</bitOffset> 8624 <bitWidth>1</bitWidth> 8625 <access>read-write</access> 8626 </field> 8627 <field> 8628 <name>pt7</name> 8629 <description>Pulse Train 7 Stopped Interrupt Flag</description> 8630 <bitOffset>7</bitOffset> 8631 <bitWidth>1</bitWidth> 8632 <access>read-write</access> 8633 </field> 8634 </fields> 8635 </register> 8636 <register> 8637 <name>STOP_INTEN</name> 8638 <description>Pulse Train Stop Interrupt Enable/Disable</description> 8639 <addressOffset>0x000C</addressOffset> 8640 <access>read-write</access> 8641 <fields> 8642 <field> 8643 <name>pt0</name> 8644 <description>Pulse Train 0 Stopped Interrupt Enable/Disable</description> 8645 <bitOffset>0</bitOffset> 8646 <bitWidth>1</bitWidth> 8647 <access>read-write</access> 8648 </field> 8649 <field> 8650 <name>pt1</name> 8651 <description>Pulse Train 1 Stopped Interrupt Enable/Disable</description> 8652 <bitOffset>1</bitOffset> 8653 <bitWidth>1</bitWidth> 8654 <access>read-write</access> 8655 </field> 8656 <field> 8657 <name>pt2</name> 8658 <description>Pulse Train 2 Stopped Interrupt Enable/Disable</description> 8659 <bitOffset>2</bitOffset> 8660 <bitWidth>1</bitWidth> 8661 <access>read-write</access> 8662 </field> 8663 <field> 8664 <name>pt3</name> 8665 <description>Pulse Train 3 Stopped Interrupt Enable/Disable</description> 8666 <bitOffset>3</bitOffset> 8667 <bitWidth>1</bitWidth> 8668 <access>read-write</access> 8669 </field> 8670 <field> 8671 <name>pt4</name> 8672 <description>Pulse Train 4 Stopped Interrupt Enable/Disable</description> 8673 <bitOffset>4</bitOffset> 8674 <bitWidth>1</bitWidth> 8675 <access>read-write</access> 8676 </field> 8677 <field> 8678 <name>pt5</name> 8679 <description>Pulse Train 5 Stopped Interrupt Enable/Disable</description> 8680 <bitOffset>5</bitOffset> 8681 <bitWidth>1</bitWidth> 8682 <access>read-write</access> 8683 </field> 8684 <field> 8685 <name>pt6</name> 8686 <description>Pulse Train 6 Stopped Interrupt Enable/Disable</description> 8687 <bitOffset>6</bitOffset> 8688 <bitWidth>1</bitWidth> 8689 <access>read-write</access> 8690 </field> 8691 <field> 8692 <name>pt7</name> 8693 <description>Pulse Train 7 Stopped Interrupt Enable/Disable</description> 8694 <bitOffset>7</bitOffset> 8695 <bitWidth>1</bitWidth> 8696 <access>read-write</access> 8697 </field> 8698 </fields> 8699 </register> 8700 <register> 8701 <name>SAFE_EN</name> 8702 <description>Pulse Train Global Safe Enable.</description> 8703 <addressOffset>0x0010</addressOffset> 8704 <access>write-only</access> 8705 <fields> 8706 <field> 8707 <name>PT0</name> 8708 <bitOffset>0</bitOffset> 8709 <bitWidth>1</bitWidth> 8710 <access>write-only</access> 8711 </field> 8712 <field> 8713 <name>PT1</name> 8714 <bitOffset>1</bitOffset> 8715 <bitWidth>1</bitWidth> 8716 <access>write-only</access> 8717 </field> 8718 <field> 8719 <name>PT2</name> 8720 <bitOffset>2</bitOffset> 8721 <bitWidth>1</bitWidth> 8722 <access>write-only</access> 8723 </field> 8724 <field> 8725 <name>PT3</name> 8726 <bitOffset>3</bitOffset> 8727 <bitWidth>1</bitWidth> 8728 <access>write-only</access> 8729 </field> 8730 <field> 8731 <name>PT4</name> 8732 <bitOffset>4</bitOffset> 8733 <bitWidth>1</bitWidth> 8734 <access>write-only</access> 8735 </field> 8736 <field> 8737 <name>PT5</name> 8738 <bitOffset>5</bitOffset> 8739 <bitWidth>1</bitWidth> 8740 <access>write-only</access> 8741 </field> 8742 <field> 8743 <name>PT6</name> 8744 <bitOffset>6</bitOffset> 8745 <bitWidth>1</bitWidth> 8746 <access>write-only</access> 8747 </field> 8748 <field> 8749 <name>PT7</name> 8750 <bitOffset>7</bitOffset> 8751 <bitWidth>1</bitWidth> 8752 <access>write-only</access> 8753 </field> 8754 </fields> 8755 </register> 8756 <register> 8757 <name>SAFE_DIS</name> 8758 <description>Pulse Train Global Safe Disable.</description> 8759 <addressOffset>0x0014</addressOffset> 8760 <access>write-only</access> 8761 <fields> 8762 <field> 8763 <name>PT0</name> 8764 <bitOffset>0</bitOffset> 8765 <bitWidth>1</bitWidth> 8766 <access>write-only</access> 8767 </field> 8768 <field> 8769 <name>PT1</name> 8770 <bitOffset>1</bitOffset> 8771 <bitWidth>1</bitWidth> 8772 <access>write-only</access> 8773 </field> 8774 <field> 8775 <name>PT2</name> 8776 <bitOffset>2</bitOffset> 8777 <bitWidth>1</bitWidth> 8778 <access>write-only</access> 8779 </field> 8780 <field> 8781 <name>PT3</name> 8782 <bitOffset>3</bitOffset> 8783 <bitWidth>1</bitWidth> 8784 <access>write-only</access> 8785 </field> 8786 <field> 8787 <name>PT4</name> 8788 <bitOffset>4</bitOffset> 8789 <bitWidth>1</bitWidth> 8790 <access>write-only</access> 8791 </field> 8792 <field> 8793 <name>PT5</name> 8794 <bitOffset>5</bitOffset> 8795 <bitWidth>1</bitWidth> 8796 <access>write-only</access> 8797 </field> 8798 <field> 8799 <name>PT6</name> 8800 <bitOffset>6</bitOffset> 8801 <bitWidth>1</bitWidth> 8802 <access>write-only</access> 8803 </field> 8804 <field> 8805 <name>PT7</name> 8806 <bitOffset>7</bitOffset> 8807 <bitWidth>1</bitWidth> 8808 <access>write-only</access> 8809 </field> 8810 </fields> 8811 </register> 8812 <register> 8813 <name>READY_INTFL</name> 8814 <description>Pulse Train Ready Interrupt Flags</description> 8815 <addressOffset>0x0018</addressOffset> 8816 <access>read-write</access> 8817 <fields> 8818 <field> 8819 <name>pt0</name> 8820 <description>Pulse Train 0 Ready Interrupt Flag</description> 8821 <bitOffset>0</bitOffset> 8822 <bitWidth>1</bitWidth> 8823 <access>read-write</access> 8824 </field> 8825 <field> 8826 <name>pt1</name> 8827 <description>Pulse Train 1 Ready Interrupt Flag</description> 8828 <bitOffset>1</bitOffset> 8829 <bitWidth>1</bitWidth> 8830 <access>read-write</access> 8831 </field> 8832 <field> 8833 <name>pt2</name> 8834 <description>Pulse Train 2 Ready Interrupt Flag</description> 8835 <bitOffset>2</bitOffset> 8836 <bitWidth>1</bitWidth> 8837 <access>read-write</access> 8838 </field> 8839 <field> 8840 <name>pt3</name> 8841 <description>Pulse Train 3 Ready Interrupt Flag</description> 8842 <bitOffset>3</bitOffset> 8843 <bitWidth>1</bitWidth> 8844 <access>read-write</access> 8845 </field> 8846 <field> 8847 <name>pt4</name> 8848 <description>Pulse Train 4 Ready Interrupt Flag</description> 8849 <bitOffset>4</bitOffset> 8850 <bitWidth>1</bitWidth> 8851 <access>read-write</access> 8852 </field> 8853 <field> 8854 <name>pt5</name> 8855 <description>Pulse Train 5 Ready Interrupt Flag</description> 8856 <bitOffset>5</bitOffset> 8857 <bitWidth>1</bitWidth> 8858 <access>read-write</access> 8859 </field> 8860 <field> 8861 <name>pt6</name> 8862 <description>Pulse Train 6 Ready Interrupt Flag</description> 8863 <bitOffset>6</bitOffset> 8864 <bitWidth>1</bitWidth> 8865 <access>read-write</access> 8866 </field> 8867 <field> 8868 <name>pt7</name> 8869 <description>Pulse Train 7 Ready Interrupt Flag</description> 8870 <bitOffset>7</bitOffset> 8871 <bitWidth>1</bitWidth> 8872 <access>read-write</access> 8873 </field> 8874 </fields> 8875 </register> 8876 <register> 8877 <name>READY_INTEN</name> 8878 <description>Pulse Train Ready Interrupt Enable/Disable</description> 8879 <addressOffset>0x001C</addressOffset> 8880 <access>read-write</access> 8881 <fields> 8882 <field> 8883 <name>pt0</name> 8884 <description>Pulse Train 0 Ready Interrupt Enable/Disable</description> 8885 <bitOffset>0</bitOffset> 8886 <bitWidth>1</bitWidth> 8887 <access>read-write</access> 8888 </field> 8889 <field> 8890 <name>pt1</name> 8891 <description>Pulse Train 1 Ready Interrupt Enable/Disable</description> 8892 <bitOffset>1</bitOffset> 8893 <bitWidth>1</bitWidth> 8894 <access>read-write</access> 8895 </field> 8896 <field> 8897 <name>pt2</name> 8898 <description>Pulse Train 2 Ready Interrupt Enable/Disable</description> 8899 <bitOffset>2</bitOffset> 8900 <bitWidth>1</bitWidth> 8901 <access>read-write</access> 8902 </field> 8903 <field> 8904 <name>pt3</name> 8905 <description>Pulse Train 3 Ready Interrupt Enable/Disable</description> 8906 <bitOffset>3</bitOffset> 8907 <bitWidth>1</bitWidth> 8908 <access>read-write</access> 8909 </field> 8910 <field> 8911 <name>pt4</name> 8912 <description>Pulse Train 4 Ready Interrupt Enable/Disable</description> 8913 <bitOffset>4</bitOffset> 8914 <bitWidth>1</bitWidth> 8915 <access>read-write</access> 8916 </field> 8917 <field> 8918 <name>pt5</name> 8919 <description>Pulse Train 5 Ready Interrupt Enable/Disable</description> 8920 <bitOffset>5</bitOffset> 8921 <bitWidth>1</bitWidth> 8922 <access>read-write</access> 8923 </field> 8924 <field> 8925 <name>pt6</name> 8926 <description>Pulse Train 6 Ready Interrupt Enable/Disable</description> 8927 <bitOffset>6</bitOffset> 8928 <bitWidth>1</bitWidth> 8929 <access>read-write</access> 8930 </field> 8931 <field> 8932 <name>pt7</name> 8933 <description>Pulse Train 7 Ready Interrupt Enable/Disable</description> 8934 <bitOffset>7</bitOffset> 8935 <bitWidth>1</bitWidth> 8936 <access>read-write</access> 8937 </field> 8938 </fields> 8939 </register> 8940 </registers> 8941 </peripheral> 8942<!--PTG Pulse Train Generation--> 8943 <peripheral> 8944 <name>PWRSEQ</name> 8945 <description>Power Sequencer / Low Power Control Register.</description> 8946 <baseAddress>0x40006800</baseAddress> 8947 <addressBlock> 8948 <offset>0x00</offset> 8949 <size>0x400</size> 8950 <usage>registers</usage> 8951 </addressBlock> 8952 <registers> 8953 <register> 8954 <name>LPCTRL</name> 8955 <description>Low Power Control Register.</description> 8956 <addressOffset>0x00</addressOffset> 8957 <fields> 8958 <field> 8959 <name>RAMRET_EN</name> 8960 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 8961 <bitOffset>0</bitOffset> 8962 <bitWidth>4</bitWidth> 8963 </field> 8964 <field> 8965 <name>OVR</name> 8966 <description>Operating Voltage Range</description> 8967 <bitOffset>4</bitOffset> 8968 <bitWidth>2</bitWidth> 8969 <enumeratedValues> 8970 <enumeratedValue> 8971 <name>1_1V</name> 8972 <description>1.1V</description> 8973 <value>2</value> 8974 </enumeratedValue> 8975 </enumeratedValues> 8976 </field> 8977 <field> 8978 <name>RETREG_EN</name> 8979 <description>Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. </description> 8980 <bitOffset>8</bitOffset> 8981 <bitWidth>1</bitWidth> 8982 <enumeratedValues> 8983 <enumeratedValue> 8984 <name>dis</name> 8985 <description>Disabled.</description> 8986 <value>0</value> 8987 </enumeratedValue> 8988 <enumeratedValue> 8989 <name>en</name> 8990 <description>Enabled.</description> 8991 <value>1</value> 8992 </enumeratedValue> 8993 </enumeratedValues> 8994 </field> 8995 <field> 8996 <name>FASTWK_EN</name> 8997 <description>Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). </description> 8998 <bitOffset>10</bitOffset> 8999 <bitWidth>1</bitWidth> 9000 <enumeratedValues> 9001 <enumeratedValue> 9002 <name>dis</name> 9003 <description>Disabled.</description> 9004 <value>0</value> 9005 </enumeratedValue> 9006 <enumeratedValue> 9007 <name>en</name> 9008 <description>Enabled.</description> 9009 <value>1</value> 9010 </enumeratedValue> 9011 </enumeratedValues> 9012 </field> 9013 <field> 9014 <name>BGOFF</name> 9015 <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description> 9016 <bitOffset>11</bitOffset> 9017 <bitWidth>1</bitWidth> 9018 <enumeratedValues> 9019 <enumeratedValue> 9020 <name>on</name> 9021 <description>Bandgap is always ON.</description> 9022 <value>0</value> 9023 </enumeratedValue> 9024 <enumeratedValue> 9025 <name>off</name> 9026 <description>Bandgap is OFF in DeepSleep mode (default).</description> 9027 <value>1</value> 9028 </enumeratedValue> 9029 </enumeratedValues> 9030 </field> 9031 <field> 9032 <name>VCOREPOR_DIS</name> 9033 <description>VCore Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode.</description> 9034 <bitOffset>12</bitOffset> 9035 <bitWidth>1</bitWidth> 9036 <enumeratedValues> 9037 <enumeratedValue> 9038 <name>dis</name> 9039 <description>Disabled.</description> 9040 <value>0</value> 9041 </enumeratedValue> 9042 <enumeratedValue> 9043 <name>en</name> 9044 <description>Enabled.</description> 9045 <value>1</value> 9046 </enumeratedValue> 9047 </enumeratedValues> 9048 </field> 9049 <field> 9050 <name>VDDIOHHVMON_DIS</name> 9051 <description>VDDIOH High Voltage Monitor Disable.</description> 9052 <bitOffset>17</bitOffset> 9053 <bitWidth>1</bitWidth> 9054 <enumeratedValues> 9055 <enumeratedValue> 9056 <name>en</name> 9057 <description>Enable if Bandgap is ON (default) </description> 9058 <value>0</value> 9059 </enumeratedValue> 9060 <enumeratedValue> 9061 <name>dis</name> 9062 <description>Disabled.</description> 9063 <value>1</value> 9064 </enumeratedValue> 9065 </enumeratedValues> 9066 </field> 9067 <field> 9068 <name>VDDIOHVMON_DIS</name> 9069 <description>VDDIO High Voltage Monitor Disable.</description> 9070 <bitOffset>18</bitOffset> 9071 <bitWidth>1</bitWidth> 9072 <enumeratedValues> 9073 <enumeratedValue> 9074 <name>en</name> 9075 <description>Enable if Bandgap is ON (default) </description> 9076 <value>0</value> 9077 </enumeratedValue> 9078 <enumeratedValue> 9079 <name>dis</name> 9080 <description>Disabled.</description> 9081 <value>1</value> 9082 </enumeratedValue> 9083 </enumeratedValues> 9084 </field> 9085 <field> 9086 <name>VCOREHVMON_DIS</name> 9087 <description>VCORE High Voltage Monitor Disable.</description> 9088 <bitOffset>19</bitOffset> 9089 <bitWidth>1</bitWidth> 9090 <enumeratedValues> 9091 <enumeratedValue> 9092 <name>en</name> 9093 <description>Enable if Bandgap is ON (default) </description> 9094 <value>0</value> 9095 </enumeratedValue> 9096 <enumeratedValue> 9097 <name>dis</name> 9098 <description>Disabled.</description> 9099 <value>1</value> 9100 </enumeratedValue> 9101 </enumeratedValues> 9102 </field> 9103 <field> 9104 <name>VCOREMON_DIS</name> 9105 <description>Vcore Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.</description> 9106 <bitOffset>20</bitOffset> 9107 <bitWidth>1</bitWidth> 9108 <enumeratedValues> 9109 <enumeratedValue> 9110 <name>en</name> 9111 <description>Enable if Bandgap is ON (default) </description> 9112 <value>0</value> 9113 </enumeratedValue> 9114 <enumeratedValue> 9115 <name>dis</name> 9116 <description>Disabled.</description> 9117 <value>1</value> 9118 </enumeratedValue> 9119 </enumeratedValues> 9120 </field> 9121 <field> 9122 <name>VRTCMON_DIS</name> 9123 <description>VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes.</description> 9124 <bitOffset>21</bitOffset> 9125 <bitWidth>1</bitWidth> 9126 <enumeratedValues> 9127 <enumeratedValue> 9128 <name>en</name> 9129 <description>Enable if Bandgap is ON (default) </description> 9130 <value>0</value> 9131 </enumeratedValue> 9132 <enumeratedValue> 9133 <name>dis</name> 9134 <description>Disabled.</description> 9135 <value>1</value> 9136 </enumeratedValue> 9137 </enumeratedValues> 9138 </field> 9139 <field> 9140 <name>VDDAMON_DIS</name> 9141 <description>VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 9142 <bitOffset>22</bitOffset> 9143 <bitWidth>1</bitWidth> 9144 <enumeratedValues> 9145 <enumeratedValue> 9146 <name>en</name> 9147 <description>Enable if Bandgap is ON (default) </description> 9148 <value>0</value> 9149 </enumeratedValue> 9150 <enumeratedValue> 9151 <name>dis</name> 9152 <description>Disabled.</description> 9153 <value>1</value> 9154 </enumeratedValue> 9155 </enumeratedValues> 9156 </field> 9157 <field> 9158 <name>VDDIOMON_DIS</name> 9159 <description>VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 9160 <bitOffset>23</bitOffset> 9161 <bitWidth>1</bitWidth> 9162 <enumeratedValues> 9163 <enumeratedValue> 9164 <name>en</name> 9165 <description>Enable if Bandgap is ON (default) </description> 9166 <value>0</value> 9167 </enumeratedValue> 9168 <enumeratedValue> 9169 <name>dis</name> 9170 <description>Disabled.</description> 9171 <value>1</value> 9172 </enumeratedValue> 9173 </enumeratedValues> 9174 </field> 9175 <field> 9176 <name>VDDIOHMON_DIS</name> 9177 <description>VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 9178 <bitOffset>24</bitOffset> 9179 <bitWidth>1</bitWidth> 9180 <enumeratedValues> 9181 <enumeratedValue> 9182 <name>en</name> 9183 <description>Enable if Bandgap is ON (default) </description> 9184 <value>0</value> 9185 </enumeratedValue> 9186 <enumeratedValue> 9187 <name>dis</name> 9188 <description>Disabled.</description> 9189 <value>1</value> 9190 </enumeratedValue> 9191 </enumeratedValues> 9192 </field> 9193 <field> 9194 <name>VDDBMON_DIS</name> 9195 <description>VDDB Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods.</description> 9196 <bitOffset>27</bitOffset> 9197 <bitWidth>1</bitWidth> 9198 <enumeratedValues> 9199 <enumeratedValue> 9200 <name>dis</name> 9201 <description>Disabled.</description> 9202 <value>0</value> 9203 </enumeratedValue> 9204 <enumeratedValue> 9205 <name>en</name> 9206 <description>Enabled.</description> 9207 <value>1</value> 9208 </enumeratedValue> 9209 </enumeratedValues> 9210 </field> 9211 <field> 9212 <name>DEEPSLEEP_PDOUT_DIS</name> 9213 <description>PDOWN out enable in DEEPSLEEP mode.</description> 9214 <bitOffset>30</bitOffset> 9215 <bitWidth>1</bitWidth> 9216 </field> 9217 </fields> 9218 </register> 9219 <register> 9220 <name>LPWKFL0</name> 9221 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 9222 <addressOffset>0x04</addressOffset> 9223 <fields> 9224 <field> 9225 <name>WAKEST</name> 9226 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 9227 <bitOffset>0</bitOffset> 9228 <bitWidth>1</bitWidth> 9229 </field> 9230 </fields> 9231 </register> 9232 <register> 9233 <name>LPWKEN0</name> 9234 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 9235 <addressOffset>0x08</addressOffset> 9236 <fields> 9237 <field> 9238 <name>WAKEEN</name> 9239 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 9240 <bitOffset>0</bitOffset> 9241 <bitWidth>31</bitWidth> 9242 </field> 9243 </fields> 9244 </register> 9245 <register derivedFrom="LPWKFL0"> 9246 <name>LPWKFL1</name> 9247 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 9248 <addressOffset>0x0C</addressOffset> 9249 </register> 9250 <register derivedFrom="LPWKEN0"> 9251 <name>LPWKEN1</name> 9252 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 9253 <addressOffset>0x10</addressOffset> 9254 </register> 9255 <register derivedFrom="LPWKFL0"> 9256 <name>LPWKFL2</name> 9257 <description>Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.</description> 9258 <addressOffset>0x14</addressOffset> 9259 </register> 9260 <register derivedFrom="LPWKEN0"> 9261 <name>LPWKEN2</name> 9262 <description>Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.</description> 9263 <addressOffset>0x18</addressOffset> 9264 </register> 9265 <register derivedFrom="LPWKFL0"> 9266 <name>LPWKFL3</name> 9267 <description>Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.</description> 9268 <addressOffset>0x1C</addressOffset> 9269 </register> 9270 <register derivedFrom="LPWKEN0"> 9271 <name>LPWKEN3</name> 9272 <description>Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.</description> 9273 <addressOffset>0x20</addressOffset> 9274 </register> 9275 <register> 9276 <name>LPPWKFL</name> 9277 <description>Low Power Peripheral Wakeup Status Register.</description> 9278 <addressOffset>0x30</addressOffset> 9279 <fields> 9280 <field> 9281 <name>USBLS</name> 9282 <description>USB UTMI Linestate Detect Wakeup Flag (write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN.</description> 9283 <bitOffset>0</bitOffset> 9284 <bitWidth>2</bitWidth> 9285 </field> 9286 <field> 9287 <name>USBVBUS</name> 9288 <description>USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off.</description> 9289 <bitOffset>2</bitOffset> 9290 <bitWidth>1</bitWidth> 9291 </field> 9292 <field> 9293 <name>CPU1</name> 9294 <description>CPU1 Detect Wakeup Flag (wite one to clear). This bit will be set when the SDMA IRQ transitions from low to high, or high to low.</description> 9295 <bitOffset>3</bitOffset> 9296 <bitWidth>1</bitWidth> 9297 </field> 9298 <field> 9299 <name>BACKUP</name> 9300 <description>Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode.</description> 9301 <bitOffset>16</bitOffset> 9302 <bitWidth>1</bitWidth> 9303 </field> 9304 <field> 9305 <name>RESET</name> 9306 <description>Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup</description> 9307 <bitOffset>17</bitOffset> 9308 <bitWidth>1</bitWidth> 9309 </field> 9310 <field> 9311 <name>DRS_EVT</name> 9312 <description>Tamper Detext Status. Can only be cleared with a system reset.</description> 9313 <bitOffset>19</bitOffset> 9314 <bitWidth>1</bitWidth> 9315 </field> 9316 </fields> 9317 </register> 9318 <register> 9319 <name>LPPWKEN</name> 9320 <description>Low Power Peripheral Wakeup Enable Register.</description> 9321 <addressOffset>0x34</addressOffset> 9322 <fields> 9323 <field> 9324 <name>USBLS</name> 9325 <description>USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal (s) on transition (s) from low to high or high to low when PM.USBWKEN is set.</description> 9326 <bitOffset>0</bitOffset> 9327 <bitWidth>2</bitWidth> 9328 </field> 9329 <field> 9330 <name>USBVBUS</name> 9331 <description>USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status.</description> 9332 <bitOffset>2</bitOffset> 9333 <bitWidth>1</bitWidth> 9334 </field> 9335 <field> 9336 <name>CPU1</name> 9337 <description>CPU1 Wakeup Enable.</description> 9338 <bitOffset>3</bitOffset> 9339 <bitWidth>1</bitWidth> 9340 </field> 9341 </fields> 9342 </register> 9343 <register> 9344 <name>LPMEMSD</name> 9345 <description>Low Power Memory Shutdown Control.</description> 9346 <addressOffset>0x40</addressOffset> 9347 <fields> 9348 <field> 9349 <name>RAM0</name> 9350 <description>System RAM block 0 Shut Down.</description> 9351 <bitOffset>0</bitOffset> 9352 <bitWidth>1</bitWidth> 9353 <enumeratedValues> 9354 <enumeratedValue> 9355 <name>normal</name> 9356 <description>Normal Operating Mode.</description> 9357 <value>0</value> 9358 </enumeratedValue> 9359 <enumeratedValue> 9360 <name>shutdown</name> 9361 <description>Shutdown Mode.</description> 9362 <value>1</value> 9363 </enumeratedValue> 9364 </enumeratedValues> 9365 </field> 9366 <field> 9367 <name>RAM1</name> 9368 <description>System RAM block 1 Shut Down.</description> 9369 <bitOffset>1</bitOffset> 9370 <bitWidth>1</bitWidth> 9371 <enumeratedValues> 9372 <enumeratedValue> 9373 <name>normal</name> 9374 <description>Normal Operating Mode.</description> 9375 <value>0</value> 9376 </enumeratedValue> 9377 <enumeratedValue> 9378 <name>shutdown</name> 9379 <description>Shutdown Mode.</description> 9380 <value>1</value> 9381 </enumeratedValue> 9382 </enumeratedValues> 9383 </field> 9384 <field> 9385 <name>RAM2</name> 9386 <description>System RAM block 2 Shut Down.</description> 9387 <bitOffset>2</bitOffset> 9388 <bitWidth>1</bitWidth> 9389 <enumeratedValues> 9390 <enumeratedValue> 9391 <name>normal</name> 9392 <description>Normal Operating Mode.</description> 9393 <value>0</value> 9394 </enumeratedValue> 9395 <enumeratedValue> 9396 <name>shutdown</name> 9397 <description>Shutdown Mode.</description> 9398 <value>1</value> 9399 </enumeratedValue> 9400 </enumeratedValues> 9401 </field> 9402 <field> 9403 <name>RAM3</name> 9404 <description>System RAM block 3 Shut Down.</description> 9405 <bitOffset>3</bitOffset> 9406 <bitWidth>1</bitWidth> 9407 <enumeratedValues> 9408 <enumeratedValue> 9409 <name>normal</name> 9410 <description>Normal Operating Mode.</description> 9411 <value>0</value> 9412 </enumeratedValue> 9413 <enumeratedValue> 9414 <name>shutdown</name> 9415 <description>Shutdown Mode.</description> 9416 <value>1</value> 9417 </enumeratedValue> 9418 </enumeratedValues> 9419 </field> 9420 <field> 9421 <name>RAM4</name> 9422 <description>System RAM block 4 Shut Down.</description> 9423 <bitOffset>4</bitOffset> 9424 <bitWidth>1</bitWidth> 9425 <enumeratedValues> 9426 <enumeratedValue> 9427 <name>normal</name> 9428 <description>Normal Operating Mode.</description> 9429 <value>0</value> 9430 </enumeratedValue> 9431 <enumeratedValue> 9432 <name>shutdown</name> 9433 <description>Shutdown Mode.</description> 9434 <value>1</value> 9435 </enumeratedValue> 9436 </enumeratedValues> 9437 </field> 9438 <field> 9439 <name>RAM5</name> 9440 <description>System RAM block 5 Shut Down.</description> 9441 <bitOffset>5</bitOffset> 9442 <bitWidth>1</bitWidth> 9443 <enumeratedValues> 9444 <enumeratedValue> 9445 <name>normal</name> 9446 <description>Normal Operating Mode.</description> 9447 <value>0</value> 9448 </enumeratedValue> 9449 <enumeratedValue> 9450 <name>shutdown</name> 9451 <description>Shutdown Mode.</description> 9452 <value>1</value> 9453 </enumeratedValue> 9454 </enumeratedValues> 9455 </field> 9456 <field> 9457 <name>RAM6</name> 9458 <description>System RAM block 6 Shut Down.</description> 9459 <bitOffset>6</bitOffset> 9460 <bitWidth>1</bitWidth> 9461 <enumeratedValues> 9462 <enumeratedValue> 9463 <name>normal</name> 9464 <description>Normal Operating Mode.</description> 9465 <value>0</value> 9466 </enumeratedValue> 9467 <enumeratedValue> 9468 <name>shutdown</name> 9469 <description>Shutdown Mode.</description> 9470 <value>1</value> 9471 </enumeratedValue> 9472 </enumeratedValues> 9473 </field> 9474 <field> 9475 <name>ICCXIP</name> 9476 <description>XiP Instruction Cache RAM Shut Down.</description> 9477 <bitOffset>8</bitOffset> 9478 <bitWidth>1</bitWidth> 9479 <enumeratedValues> 9480 <enumeratedValue> 9481 <name>normal</name> 9482 <description>Normal Operating Mode.</description> 9483 <value>0</value> 9484 </enumeratedValue> 9485 <enumeratedValue> 9486 <name>shutdown</name> 9487 <description>Shutdown Mode.</description> 9488 <value>1</value> 9489 </enumeratedValue> 9490 </enumeratedValues> 9491 </field> 9492 <field> 9493 <name>CRYPTO</name> 9494 <description>MAA memory Shut Down.</description> 9495 <bitOffset>10</bitOffset> 9496 <bitWidth>1</bitWidth> 9497 <enumeratedValues> 9498 <enumeratedValue> 9499 <name>normal</name> 9500 <description>Normal Operating Mode.</description> 9501 <value>0</value> 9502 </enumeratedValue> 9503 <enumeratedValue> 9504 <name>shutdown</name> 9505 <description>Shutdown Mode.</description> 9506 <value>1</value> 9507 </enumeratedValue> 9508 </enumeratedValues> 9509 </field> 9510 <field> 9511 <name>USBFIFO</name> 9512 <description>USB FIFO Shut Down.</description> 9513 <bitOffset>11</bitOffset> 9514 <bitWidth>1</bitWidth> 9515 <enumeratedValues> 9516 <enumeratedValue> 9517 <name>normal</name> 9518 <description>Normal Operating Mode.</description> 9519 <value>0</value> 9520 </enumeratedValue> 9521 <enumeratedValue> 9522 <name>shutdown</name> 9523 <description>Shutdown Mode.</description> 9524 <value>1</value> 9525 </enumeratedValue> 9526 </enumeratedValues> 9527 </field> 9528 <field> 9529 <name>ROM0</name> 9530 <description>ROM0 Shut Down.</description> 9531 <bitOffset>12</bitOffset> 9532 <bitWidth>1</bitWidth> 9533 <enumeratedValues> 9534 <enumeratedValue> 9535 <name>normal</name> 9536 <description>Normal Operating Mode.</description> 9537 <value>0</value> 9538 </enumeratedValue> 9539 <enumeratedValue> 9540 <name>shutdown</name> 9541 <description>Shutdown Mode.</description> 9542 <value>1</value> 9543 </enumeratedValue> 9544 </enumeratedValues> 9545 </field> 9546 <field> 9547 <name>MEUMEM</name> 9548 <description>MEU memory Shut Down.</description> 9549 <bitOffset>13</bitOffset> 9550 <bitWidth>1</bitWidth> 9551 <enumeratedValues> 9552 <enumeratedValue> 9553 <name>normal</name> 9554 <description>Normal Operating Mode.</description> 9555 <value>0</value> 9556 </enumeratedValue> 9557 <enumeratedValue> 9558 <name>shutdown</name> 9559 <description>Shutdown Mode.</description> 9560 <value>1</value> 9561 </enumeratedValue> 9562 </enumeratedValues> 9563 </field> 9564 <field> 9565 <name>ROM1</name> 9566 <description>ROM1 Shut Down.</description> 9567 <bitOffset>15</bitOffset> 9568 <bitWidth>1</bitWidth> 9569 <enumeratedValues> 9570 <enumeratedValue> 9571 <name>normal</name> 9572 <description>Normal Operating Mode.</description> 9573 <value>0</value> 9574 </enumeratedValue> 9575 <enumeratedValue> 9576 <name>shutdown</name> 9577 <description>Shutdown Mode.</description> 9578 <value>1</value> 9579 </enumeratedValue> 9580 </enumeratedValues> 9581 </field> 9582 </fields> 9583 </register> 9584 <register> 9585 <name>LPVDDPD</name> 9586 <description>Low Power VDD Domain Power Down Control.</description> 9587 <addressOffset>0x44</addressOffset> 9588 </register> 9589 <register> 9590 <name>GP0</name> 9591 <description>General Purpose Register 0</description> 9592 <addressOffset>0x48</addressOffset> 9593 </register> 9594 <register> 9595 <name>GP1</name> 9596 <description>General Purpose Register 1</description> 9597 <addressOffset>0x4C</addressOffset> 9598 </register> 9599 </registers> 9600 </peripheral> 9601<!--PWRSEQ Power Sequencer / Low Power Control Register.--> 9602 <peripheral> 9603 <name>RTC</name> 9604 <description>Real Time Clock and Alarm.</description> 9605 <baseAddress>0x40006000</baseAddress> 9606 <addressBlock> 9607 <offset>0x00</offset> 9608 <size>0x400</size> 9609 <usage>registers</usage> 9610 </addressBlock> 9611 <interrupt> 9612 <name>RTC</name> 9613 <description>RTC interrupt.</description> 9614 <value>3</value> 9615 </interrupt> 9616 <registers> 9617 <register> 9618 <name>SEC</name> 9619 <description>RTC Second Counter. This register contains the 32-bit second counter.</description> 9620 <addressOffset>0x00</addressOffset> 9621 <resetMask>0x00000000</resetMask> 9622 <fields> 9623 <field> 9624 <name>SEC</name> 9625 <description>Seconds Counter.</description> 9626 <bitOffset>0</bitOffset> 9627 <bitWidth>32</bitWidth> 9628 </field> 9629 </fields> 9630 </register> 9631 <register> 9632 <name>SSEC</name> 9633 <description>RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.</description> 9634 <addressOffset>0x04</addressOffset> 9635 <resetMask>0x00000000</resetMask> 9636 <fields> 9637 <field> 9638 <name>SSEC</name> 9639 <description>Sub-Seconds Counter (12-bit).</description> 9640 <bitOffset>0</bitOffset> 9641 <bitWidth>12</bitWidth> 9642 </field> 9643 </fields> 9644 </register> 9645 <register> 9646 <name>TODA</name> 9647 <description>Time-of-day Alarm.</description> 9648 <addressOffset>0x08</addressOffset> 9649 <resetMask>0x00000000</resetMask> 9650 <fields> 9651 <field> 9652 <name>TOD_ALARM</name> 9653 <description>Time-of-day Alarm.</description> 9654 <bitOffset>0</bitOffset> 9655 <bitWidth>20</bitWidth> 9656 </field> 9657 </fields> 9658 </register> 9659 <register> 9660 <name>SSECA</name> 9661 <description>RTC sub-second alarm. This register contains the reload value for the sub-second alarm.</description> 9662 <addressOffset>0x0C</addressOffset> 9663 <resetMask>0x00000000</resetMask> 9664 <fields> 9665 <field> 9666 <name>SSEC_ALARM</name> 9667 <description>This register contains the reload value for the sub-second alarm.</description> 9668 <bitOffset>0</bitOffset> 9669 <bitWidth>32</bitWidth> 9670 </field> 9671 </fields> 9672 </register> 9673 <register> 9674 <name>CTRL</name> 9675 <description>RTC Control Register.</description> 9676 <addressOffset>0x10</addressOffset> 9677 <resetValue>0x00000008</resetValue> 9678 <resetMask>0xFFFFFF38</resetMask> 9679 <fields> 9680 <field> 9681 <name>EN</name> 9682 <description>Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 9683 <bitOffset>0</bitOffset> 9684 <bitWidth>1</bitWidth> 9685 <enumeratedValues> 9686 <enumeratedValue> 9687 <name>dis</name> 9688 <description>Disable.</description> 9689 <value>0</value> 9690 </enumeratedValue> 9691 <enumeratedValue> 9692 <name>en</name> 9693 <description>Enable.</description> 9694 <value>1</value> 9695 </enumeratedValue> 9696 </enumeratedValues> 9697 </field> 9698 <field> 9699 <name>TOD_ALARM_IE</name> 9700 <description>Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 9701 <bitOffset>1</bitOffset> 9702 <bitWidth>1</bitWidth> 9703 <enumeratedValues> 9704 <enumeratedValue> 9705 <name>dis</name> 9706 <description>Disable.</description> 9707 <value>0</value> 9708 </enumeratedValue> 9709 <enumeratedValue> 9710 <name>en</name> 9711 <description>Enable.</description> 9712 <value>1</value> 9713 </enumeratedValue> 9714 </enumeratedValues> 9715 </field> 9716 <field> 9717 <name>SSEC_ALARM_IE</name> 9718 <description>Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 9719 <bitOffset>2</bitOffset> 9720 <bitWidth>1</bitWidth> 9721 <enumeratedValues> 9722 <enumeratedValue> 9723 <name>dis</name> 9724 <description>Disable.</description> 9725 <value>0</value> 9726 </enumeratedValue> 9727 <enumeratedValue> 9728 <name>en</name> 9729 <description>Enable.</description> 9730 <value>1</value> 9731 </enumeratedValue> 9732 </enumeratedValues> 9733 </field> 9734 <field> 9735 <name>BUSY</name> 9736 <description>RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.</description> 9737 <bitOffset>3</bitOffset> 9738 <bitWidth>1</bitWidth> 9739 <access>read-only</access> 9740 <enumeratedValues> 9741 <enumeratedValue> 9742 <name>idle</name> 9743 <description>Idle.</description> 9744 <value>0</value> 9745 </enumeratedValue> 9746 <enumeratedValue> 9747 <name>busy</name> 9748 <description>Busy.</description> 9749 <value>1</value> 9750 </enumeratedValue> 9751 </enumeratedValues> 9752 </field> 9753 <field> 9754 <name>RDY</name> 9755 <description>RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.</description> 9756 <bitOffset>4</bitOffset> 9757 <bitWidth>1</bitWidth> 9758 <enumeratedValues> 9759 <enumeratedValue> 9760 <name>busy</name> 9761 <description>Register has not updated.</description> 9762 <value>0</value> 9763 </enumeratedValue> 9764 <enumeratedValue> 9765 <name>ready</name> 9766 <description>Ready.</description> 9767 <value>1</value> 9768 </enumeratedValue> 9769 </enumeratedValues> 9770 </field> 9771 <field> 9772 <name>RDY_IE</name> 9773 <description>RTC Ready Interrupt Enable.</description> 9774 <bitOffset>5</bitOffset> 9775 <bitWidth>1</bitWidth> 9776 <enumeratedValues> 9777 <enumeratedValue> 9778 <name>dis</name> 9779 <description>Disable.</description> 9780 <value>0</value> 9781 </enumeratedValue> 9782 <enumeratedValue> 9783 <name>en</name> 9784 <description>Enable.</description> 9785 <value>1</value> 9786 </enumeratedValue> 9787 </enumeratedValues> 9788 </field> 9789 <field> 9790 <name>TOD_ALARM_IF</name> 9791 <description>Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 9792 <bitOffset>6</bitOffset> 9793 <bitWidth>1</bitWidth> 9794 <access>read-only</access> 9795 <enumeratedValues> 9796 <enumeratedValue> 9797 <name>inactive</name> 9798 <description>Not active.</description> 9799 <value>0</value> 9800 </enumeratedValue> 9801 <enumeratedValue> 9802 <name>pending</name> 9803 <description>Active.</description> 9804 <value>1</value> 9805 </enumeratedValue> 9806 </enumeratedValues> 9807 </field> 9808 <field> 9809 <name>SSEC_ALARM_IF</name> 9810 <description>Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 9811 <bitOffset>7</bitOffset> 9812 <bitWidth>1</bitWidth> 9813 <access>read-only</access> 9814 <enumeratedValues> 9815 <enumeratedValue> 9816 <name>inactive</name> 9817 <description>Not active.</description> 9818 <value>0</value> 9819 </enumeratedValue> 9820 <enumeratedValue> 9821 <name>pending</name> 9822 <description>Active.</description> 9823 <value>1</value> 9824 </enumeratedValue> 9825 </enumeratedValues> 9826 </field> 9827 <field> 9828 <name>SQW_EN</name> 9829 <description>Square Wave Output Enable.</description> 9830 <bitOffset>8</bitOffset> 9831 <bitWidth>1</bitWidth> 9832 <enumeratedValues> 9833 <enumeratedValue> 9834 <name>dis</name> 9835 <description>Disable.</description> 9836 <value>0</value> 9837 </enumeratedValue> 9838 <enumeratedValue> 9839 <name>en</name> 9840 <description>Enable.</description> 9841 <value>1</value> 9842 </enumeratedValue> 9843 </enumeratedValues> 9844 </field> 9845 <field> 9846 <name>SQW_SEL</name> 9847 <description>Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.</description> 9848 <bitOffset>9</bitOffset> 9849 <bitWidth>2</bitWidth> 9850 <enumeratedValues> 9851 <enumeratedValue> 9852 <name>freq1Hz</name> 9853 <description>1 Hz (Compensated).</description> 9854 <value>0</value> 9855 </enumeratedValue> 9856 <enumeratedValue> 9857 <name>freq512Hz</name> 9858 <description>512 Hz (Compensated).</description> 9859 <value>1</value> 9860 </enumeratedValue> 9861 <enumeratedValue> 9862 <name>freq4KHz</name> 9863 <description>4 KHz.</description> 9864 <value>2</value> 9865 </enumeratedValue> 9866 <enumeratedValue> 9867 <name>clkDiv8</name> 9868 <description>RTC Input Clock / 8.</description> 9869 <value>3</value> 9870 </enumeratedValue> 9871 </enumeratedValues> 9872 </field> 9873 <field> 9874 <name>RD_EN</name> 9875 <description>Asynchronous Counter Read Enable.</description> 9876 <bitOffset>14</bitOffset> 9877 <bitWidth>1</bitWidth> 9878 <enumeratedValues> 9879 <enumeratedValue> 9880 <name>sync</name> 9881 <description>Synchronous.</description> 9882 <value>0</value> 9883 </enumeratedValue> 9884 <enumeratedValue> 9885 <name>async</name> 9886 <description>Asynchronous.</description> 9887 <value>1</value> 9888 </enumeratedValue> 9889 </enumeratedValues> 9890 </field> 9891 <field> 9892 <name>WR_EN</name> 9893 <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.</description> 9894 <bitOffset>15</bitOffset> 9895 <bitWidth>1</bitWidth> 9896 <enumeratedValues> 9897 <enumeratedValue> 9898 <name>ignore</name> 9899 <description>Ignored.</description> 9900 <value>0</value> 9901 </enumeratedValue> 9902 <enumeratedValue> 9903 <name>allow</name> 9904 <description>Allowed.</description> 9905 <value>1</value> 9906 </enumeratedValue> 9907 </enumeratedValues> 9908 </field> 9909 </fields> 9910 </register> 9911 <register> 9912 <name>TRIM</name> 9913 <description>RTC Trim Register.</description> 9914 <addressOffset>0x14</addressOffset> 9915 <resetMask>0x00000000</resetMask> 9916 <fields> 9917 <field> 9918 <name>TRIM</name> 9919 <description>RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.</description> 9920 <bitOffset>0</bitOffset> 9921 <bitWidth>8</bitWidth> 9922 </field> 9923 <field> 9924 <name>VBAT_TMR</name> 9925 <description>VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.</description> 9926 <bitOffset>8</bitOffset> 9927 <bitWidth>24</bitWidth> 9928 </field> 9929 </fields> 9930 </register> 9931 <register> 9932 <name>OSCCTRL</name> 9933 <description>RTC Oscillator Control Register.</description> 9934 <addressOffset>0x18</addressOffset> 9935 <resetMask>0x00000000</resetMask> 9936 <fields> 9937 <field> 9938 <name>FILTER_EN</name> 9939 <description>Enable Filter.</description> 9940 <bitOffset>0</bitOffset> 9941 <bitWidth>1</bitWidth> 9942 </field> 9943 <field> 9944 <name>IBIAS_SEL</name> 9945 <description>IBIAS Select.</description> 9946 <bitOffset>1</bitOffset> 9947 <bitWidth>1</bitWidth> 9948 <enumeratedValues> 9949 <enumeratedValue> 9950 <name>2x</name> 9951 <description>2x</description> 9952 <value>0</value> 9953 </enumeratedValue> 9954 <enumeratedValue> 9955 <name>4x</name> 9956 <description>4x</description> 9957 <value>1</value> 9958 </enumeratedValue> 9959 </enumeratedValues> 9960 </field> 9961 <field> 9962 <name>HYST_EN</name> 9963 <description>RTC Hysteresis Enable.</description> 9964 <bitOffset>2</bitOffset> 9965 <bitWidth>1</bitWidth> 9966 </field> 9967 <field> 9968 <name>IBIAS_EN</name> 9969 <description>RTC IBIAS Enable.</description> 9970 <bitOffset>3</bitOffset> 9971 <bitWidth>1</bitWidth> 9972 </field> 9973 <field> 9974 <name>BYPASS</name> 9975 <description>RTC Crystal Bypass</description> 9976 <bitOffset>4</bitOffset> 9977 <bitWidth>1</bitWidth> 9978 <enumeratedValues> 9979 <enumeratedValue> 9980 <name>dis</name> 9981 <description>Disable.</description> 9982 <value>0</value> 9983 </enumeratedValue> 9984 <enumeratedValue> 9985 <name>en</name> 9986 <description>Enable.</description> 9987 <value>1</value> 9988 </enumeratedValue> 9989 </enumeratedValues> 9990 </field> 9991 <field> 9992 <name>SQW_32K</name> 9993 <description>RTC 32kHz Square Wave Output</description> 9994 <bitOffset>5</bitOffset> 9995 <bitWidth>1</bitWidth> 9996 <enumeratedValues> 9997 <enumeratedValue> 9998 <name>dis</name> 9999 <description>Disable.</description> 10000 <value>0</value> 10001 </enumeratedValue> 10002 <enumeratedValue> 10003 <name>en</name> 10004 <description>Enable.</description> 10005 <value>1</value> 10006 </enumeratedValue> 10007 </enumeratedValues> 10008 </field> 10009 </fields> 10010 </register> 10011 </registers> 10012 </peripheral> 10013<!--RTC Real Time Clock and Alarm.--> 10014 <peripheral> 10015 <name>SIR</name> 10016 <description>System Initialization Registers.</description> 10017 <baseAddress>0x40000400</baseAddress> 10018 <access>read-only</access> 10019 <addressBlock> 10020 <offset>0x00</offset> 10021 <size>0x400</size> 10022 <usage>registers</usage> 10023 </addressBlock> 10024 <registers> 10025 <register> 10026 <name>SISTAT</name> 10027 <description>System Initialization Status Register.</description> 10028 <addressOffset>0x00</addressOffset> 10029 <access>read-only</access> 10030 <fields> 10031 <field> 10032 <name>MAGIC</name> 10033 <description>Magic Word Validation. This bit is set by the system initialization block following power-up.</description> 10034 <bitOffset>0</bitOffset> 10035 <bitWidth>1</bitWidth> 10036 <access>read-only</access> 10037 <enumeratedValues> 10038 <usage>read</usage> 10039 <enumeratedValue> 10040 <name>magicNotSet</name> 10041 <description>Magic word was not set (OTP has not been initialized properly).</description> 10042 <value>0</value> 10043 </enumeratedValue> 10044 <enumeratedValue> 10045 <name>magicSet</name> 10046 <description>Magic word was set (OTP contains valid settings).</description> 10047 <value>1</value> 10048 </enumeratedValue> 10049 </enumeratedValues> 10050 </field> 10051 <field> 10052 <name>CRCERR</name> 10053 <description>CRC Error Status. This bit is set by the system initialization block following power-up.</description> 10054 <bitOffset>1</bitOffset> 10055 <bitWidth>1</bitWidth> 10056 <access>read-only</access> 10057 <enumeratedValues> 10058 <usage>read</usage> 10059 <enumeratedValue> 10060 <name>noError</name> 10061 <description>No CRC errors occurred during the read of the OTP memory block.</description> 10062 <value>0</value> 10063 </enumeratedValue> 10064 <enumeratedValue> 10065 <name>error</name> 10066 <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description> 10067 <value>1</value> 10068 </enumeratedValue> 10069 </enumeratedValues> 10070 </field> 10071 </fields> 10072 </register> 10073 <register> 10074 <name>SIADDR</name> 10075 <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> 10076 <addressOffset>0x04</addressOffset> 10077 <access>read-only</access> 10078 <fields> 10079 <field> 10080 <name>ERRADDR</name> 10081 <bitOffset>0</bitOffset> 10082 <bitWidth>32</bitWidth> 10083 </field> 10084 </fields> 10085 </register> 10086 <register> 10087 <name>FSTAT</name> 10088 <description>funcstat register.</description> 10089 <addressOffset>0x100</addressOffset> 10090 <access>read-only</access> 10091 <fields> 10092 <field> 10093 <name>FPU</name> 10094 <description>FPU Function.</description> 10095 <bitOffset>0</bitOffset> 10096 <bitWidth>1</bitWidth> 10097 <enumeratedValues> 10098 <enumeratedValue> 10099 <name>no</name> 10100 <value>0</value> 10101 </enumeratedValue> 10102 <enumeratedValue> 10103 <name>yes</name> 10104 <value>1</value> 10105 </enumeratedValue> 10106 </enumeratedValues> 10107 </field> 10108 <field> 10109 <name>USB</name> 10110 <description>USB Device.</description> 10111 <bitOffset>1</bitOffset> 10112 <bitWidth>1</bitWidth> 10113 <enumeratedValues> 10114 <enumeratedValue> 10115 <name>no</name> 10116 <value>0</value> 10117 </enumeratedValue> 10118 <enumeratedValue> 10119 <name>yes</name> 10120 <value>1</value> 10121 </enumeratedValue> 10122 </enumeratedValues> 10123 </field> 10124 <field> 10125 <name>ADC</name> 10126 <description>10-bit Sigma Delta ADC.</description> 10127 <bitOffset>2</bitOffset> 10128 <bitWidth>1</bitWidth> 10129 <enumeratedValues> 10130 <enumeratedValue> 10131 <name>no</name> 10132 <value>0</value> 10133 </enumeratedValue> 10134 <enumeratedValue> 10135 <name>yes</name> 10136 <value>1</value> 10137 </enumeratedValue> 10138 </enumeratedValues> 10139 </field> 10140 <field> 10141 <name>SPIXIP</name> 10142 <description>SPIXIPffunction.</description> 10143 <bitOffset>3</bitOffset> 10144 <bitWidth>1</bitWidth> 10145 <enumeratedValues> 10146 <enumeratedValue> 10147 <name>no</name> 10148 <value>0</value> 10149 </enumeratedValue> 10150 <enumeratedValue> 10151 <name>yes</name> 10152 <value>1</value> 10153 </enumeratedValue> 10154 </enumeratedValues> 10155 </field> 10156 <field> 10157 <name>ADC9</name> 10158 <description>ADC9 function.</description> 10159 <bitOffset>9</bitOffset> 10160 <bitWidth>1</bitWidth> 10161 <enumeratedValues> 10162 <enumeratedValue> 10163 <name>no</name> 10164 <value>0</value> 10165 </enumeratedValue> 10166 <enumeratedValue> 10167 <name>yes</name> 10168 <value>1</value> 10169 </enumeratedValue> 10170 </enumeratedValues> 10171 </field> 10172 <field> 10173 <name>SC</name> 10174 <description>SC function.</description> 10175 <bitOffset>10</bitOffset> 10176 <bitWidth>1</bitWidth> 10177 <enumeratedValues> 10178 <enumeratedValue> 10179 <name>no</name> 10180 <value>0</value> 10181 </enumeratedValue> 10182 <enumeratedValue> 10183 <name>yes</name> 10184 <value>1</value> 10185 </enumeratedValue> 10186 </enumeratedValues> 10187 </field> 10188 <field> 10189 <name>NMI</name> 10190 <description>NMI function.</description> 10191 <bitOffset>12</bitOffset> 10192 <bitWidth>1</bitWidth> 10193 <enumeratedValues> 10194 <enumeratedValue> 10195 <name>no</name> 10196 <value>0</value> 10197 </enumeratedValue> 10198 <enumeratedValue> 10199 <name>yes</name> 10200 <value>1</value> 10201 </enumeratedValue> 10202 </enumeratedValues> 10203 </field> 10204 </fields> 10205 </register> 10206 <register> 10207 <name>SFSTAT</name> 10208 <description>Security Function </description> 10209 <addressOffset>0x104</addressOffset> 10210 <access>read-only</access> 10211 <fields> 10212 <field> 10213 <name>SECBOOT</name> 10214 <description>Secure Boot Disable.</description> 10215 <bitOffset>0</bitOffset> 10216 <bitWidth>1</bitWidth> 10217 <enumeratedValues> 10218 <enumeratedValue> 10219 <name>no</name> 10220 <value>0</value> 10221 </enumeratedValue> 10222 <enumeratedValue> 10223 <name>yes</name> 10224 <value>1</value> 10225 </enumeratedValue> 10226 </enumeratedValues> 10227 </field> 10228 <field> 10229 <name>SERLOAD</name> 10230 <description>Serial Load Disable function.</description> 10231 <bitOffset>1</bitOffset> 10232 <bitWidth>1</bitWidth> 10233 <enumeratedValues> 10234 <enumeratedValue> 10235 <name>no</name> 10236 <value>0</value> 10237 </enumeratedValue> 10238 <enumeratedValue> 10239 <name>yes</name> 10240 <value>1</value> 10241 </enumeratedValue> 10242 </enumeratedValues> 10243 </field> 10244 <field> 10245 <name>TRNG</name> 10246 <description>TRNG function.</description> 10247 <bitOffset>2</bitOffset> 10248 <bitWidth>1</bitWidth> 10249 <enumeratedValues> 10250 <enumeratedValue> 10251 <name>no</name> 10252 <value>0</value> 10253 </enumeratedValue> 10254 <enumeratedValue> 10255 <name>yes</name> 10256 <value>1</value> 10257 </enumeratedValue> 10258 </enumeratedValues> 10259 </field> 10260 <field> 10261 <name>AES</name> 10262 <description>AES function.</description> 10263 <bitOffset>3</bitOffset> 10264 <bitWidth>1</bitWidth> 10265 <enumeratedValues> 10266 <enumeratedValue> 10267 <name>no</name> 10268 <value>0</value> 10269 </enumeratedValue> 10270 <enumeratedValue> 10271 <name>yes</name> 10272 <value>1</value> 10273 </enumeratedValue> 10274 </enumeratedValues> 10275 </field> 10276 <field> 10277 <name>SHA</name> 10278 <description>SHA function.</description> 10279 <bitOffset>4</bitOffset> 10280 <bitWidth>1</bitWidth> 10281 <enumeratedValues> 10282 <enumeratedValue> 10283 <name>no</name> 10284 <value>0</value> 10285 </enumeratedValue> 10286 <enumeratedValue> 10287 <name>yes</name> 10288 <value>1</value> 10289 </enumeratedValue> 10290 </enumeratedValues> 10291 </field> 10292 <field> 10293 <name>SECMODE</name> 10294 <description>Security Mode Disable.</description> 10295 <bitOffset>7</bitOffset> 10296 <bitWidth>1</bitWidth> 10297 <enumeratedValues> 10298 <enumeratedValue> 10299 <name>no</name> 10300 <value>0</value> 10301 </enumeratedValue> 10302 <enumeratedValue> 10303 <name>yes</name> 10304 <value>1</value> 10305 </enumeratedValue> 10306 </enumeratedValues> 10307 </field> 10308 </fields> 10309 </register> 10310 </registers> 10311 </peripheral> 10312<!--SIR System Initialization Registers.--> 10313 <peripheral> 10314 <name>SMON</name> 10315 <description>The Security Monitor block used to monitor system threat conditions.</description> 10316 <baseAddress>0x40004000</baseAddress> 10317 <addressBlock> 10318 <offset>0x00</offset> 10319 <size>0x400</size> 10320 <usage>registers</usage> 10321 </addressBlock> 10322 <registers> 10323 <register> 10324 <name>EXTSCTRL</name> 10325 <description>External Sensor Control Register.</description> 10326 <addressOffset>0x00</addressOffset> 10327 <resetMask>0x3800FFC0</resetMask> 10328 <fields> 10329 <field> 10330 <name>EXTS_EN0</name> 10331 <description>External Sensor Enable for input/output pair 0.</description> 10332 <bitOffset>0</bitOffset> 10333 <bitWidth>1</bitWidth> 10334 <enumeratedValues> 10335 <enumeratedValue> 10336 <name>dis</name> 10337 <description>Disable.</description> 10338 <value>0</value> 10339 </enumeratedValue> 10340 <enumeratedValue> 10341 <name>en</name> 10342 <description>Enable.</description> 10343 <value>1</value> 10344 </enumeratedValue> 10345 </enumeratedValues> 10346 </field> 10347 <field> 10348 <name>EXTS_EN1</name> 10349 <description>External Sensor Enable for input/output pair 1.</description> 10350 <bitOffset>1</bitOffset> 10351 <bitWidth>1</bitWidth> 10352 <enumeratedValues> 10353 <enumeratedValue> 10354 <name>dis</name> 10355 <description>Disable.</description> 10356 <value>0</value> 10357 </enumeratedValue> 10358 <enumeratedValue> 10359 <name>en</name> 10360 <description>Enable.</description> 10361 <value>1</value> 10362 </enumeratedValue> 10363 </enumeratedValues> 10364 </field> 10365 <field> 10366 <name>EXTS_EN2</name> 10367 <description>External Sensor Enable for input/output pair 2.</description> 10368 <bitOffset>2</bitOffset> 10369 <bitWidth>1</bitWidth> 10370 <enumeratedValues> 10371 <enumeratedValue> 10372 <name>dis</name> 10373 <description>Disable.</description> 10374 <value>0</value> 10375 </enumeratedValue> 10376 <enumeratedValue> 10377 <name>en</name> 10378 <description>Enable.</description> 10379 <value>1</value> 10380 </enumeratedValue> 10381 </enumeratedValues> 10382 </field> 10383 <field> 10384 <name>EXTS_EN3</name> 10385 <description>External Sensor Enable for input/output pair 3.</description> 10386 <bitOffset>3</bitOffset> 10387 <bitWidth>1</bitWidth> 10388 <enumeratedValues> 10389 <enumeratedValue> 10390 <name>dis</name> 10391 <description>Disable.</description> 10392 <value>0</value> 10393 </enumeratedValue> 10394 <enumeratedValue> 10395 <name>en</name> 10396 <description>Enable.</description> 10397 <value>1</value> 10398 </enumeratedValue> 10399 </enumeratedValues> 10400 </field> 10401 <field> 10402 <name>EXTS_EN4</name> 10403 <description>External Sensor Enable for input/output pair 4.</description> 10404 <bitOffset>4</bitOffset> 10405 <bitWidth>1</bitWidth> 10406 <enumeratedValues> 10407 <enumeratedValue> 10408 <name>dis</name> 10409 <description>Disable.</description> 10410 <value>0</value> 10411 </enumeratedValue> 10412 <enumeratedValue> 10413 <name>en</name> 10414 <description>Enable.</description> 10415 <value>1</value> 10416 </enumeratedValue> 10417 </enumeratedValues> 10418 </field> 10419 <field> 10420 <name>EXTS_EN5</name> 10421 <description>External Sensor Enable for input/output pair 5.</description> 10422 <bitOffset>5</bitOffset> 10423 <bitWidth>1</bitWidth> 10424 <enumeratedValues> 10425 <enumeratedValue> 10426 <name>dis</name> 10427 <description>Disable.</description> 10428 <value>0</value> 10429 </enumeratedValue> 10430 <enumeratedValue> 10431 <name>en</name> 10432 <description>Enable.</description> 10433 <value>1</value> 10434 </enumeratedValue> 10435 </enumeratedValues> 10436 </field> 10437 <field> 10438 <name>EXTCNT</name> 10439 <description>External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered.</description> 10440 <bitOffset>16</bitOffset> 10441 <bitWidth>5</bitWidth> 10442 </field> 10443 <field> 10444 <name>EXTFRQ</name> 10445 <description>External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.</description> 10446 <bitOffset>21</bitOffset> 10447 <bitWidth>3</bitWidth> 10448 <enumeratedValues> 10449 <enumeratedValue> 10450 <name>freq2000Hz</name> 10451 <description>Div 4 (2000Hz).</description> 10452 <value>0</value> 10453 </enumeratedValue> 10454 <enumeratedValue> 10455 <name>freq1000Hz</name> 10456 <description>Div 8 (1000Hz).</description> 10457 <value>1</value> 10458 </enumeratedValue> 10459 <enumeratedValue> 10460 <name>freq500Hz</name> 10461 <description>Div 16 (500Hz).</description> 10462 <value>2</value> 10463 </enumeratedValue> 10464 <enumeratedValue> 10465 <name>freq250Hz</name> 10466 <description>Div 32 (250Hz).</description> 10467 <value>3</value> 10468 </enumeratedValue> 10469 <enumeratedValue> 10470 <name>freq125Hz</name> 10471 <description>Div 64 (125Hz).</description> 10472 <value>4</value> 10473 </enumeratedValue> 10474 <enumeratedValue> 10475 <name>freq63Hz</name> 10476 <description>Div 128 (63Hz).</description> 10477 <value>5</value> 10478 </enumeratedValue> 10479 <enumeratedValue> 10480 <name>freq31Hz</name> 10481 <description>Div 256 (31Hz).</description> 10482 <value>6</value> 10483 </enumeratedValue> 10484 <enumeratedValue> 10485 <name>RFU</name> 10486 <description>Reserved. Do not use.</description> 10487 <value>7</value> 10488 </enumeratedValue> 10489 </enumeratedValues> 10490 </field> 10491 <field> 10492 <name>CLKDIV</name> 10493 <description>Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: 10494 If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.</description> 10495 <bitOffset>24</bitOffset> 10496 <bitWidth>3</bitWidth> 10497 <enumeratedValues> 10498 <enumeratedValue> 10499 <name>div1</name> 10500 <description>Divide by 1 (8000 Hz).</description> 10501 <value>0</value> 10502 </enumeratedValue> 10503 <enumeratedValue> 10504 <name>div2</name> 10505 <description>Divide by 2 (4000 Hz).</description> 10506 <value>1</value> 10507 </enumeratedValue> 10508 <enumeratedValue> 10509 <name>div4</name> 10510 <description>Divide by 4 (2000 Hz).</description> 10511 <value>2</value> 10512 </enumeratedValue> 10513 <enumeratedValue> 10514 <name>div8</name> 10515 <description>Divide by 8 (1000 Hz).</description> 10516 <value>3</value> 10517 </enumeratedValue> 10518 <enumeratedValue> 10519 <name>div16</name> 10520 <description>Divide by 16 (500 Hz).</description> 10521 <value>4</value> 10522 </enumeratedValue> 10523 <enumeratedValue> 10524 <name>div32</name> 10525 <description>Divide by 32 (250 Hz).</description> 10526 <value>5</value> 10527 </enumeratedValue> 10528 <enumeratedValue> 10529 <name>div64</name> 10530 <description>Divide by 64 (125 Hz).</description> 10531 <value>6</value> 10532 </enumeratedValue> 10533 </enumeratedValues> 10534 </field> 10535 <field> 10536 <name>BUSY</name> 10537 <description>Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.</description> 10538 <bitOffset>30</bitOffset> 10539 <bitWidth>1</bitWidth> 10540 <access>read-only</access> 10541 <enumeratedValues> 10542 <enumeratedValue> 10543 <name>idle</name> 10544 <description>Idle.</description> 10545 <value>0</value> 10546 </enumeratedValue> 10547 <enumeratedValue> 10548 <name>busy</name> 10549 <description>Update in Progress.</description> 10550 <value>1</value> 10551 </enumeratedValue> 10552 </enumeratedValues> 10553 </field> 10554 <field> 10555 <name>LOCK</name> 10556 <description>Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.</description> 10557 <bitOffset>31</bitOffset> 10558 <bitWidth>1</bitWidth> 10559 <enumeratedValues> 10560 <enumeratedValue> 10561 <name>unlocked</name> 10562 <description>Unlocked.</description> 10563 <value>0</value> 10564 </enumeratedValue> 10565 <enumeratedValue> 10566 <name>locked</name> 10567 <description>Locked.</description> 10568 <value>1</value> 10569 </enumeratedValue> 10570 </enumeratedValues> 10571 </field> 10572 </fields> 10573 </register> 10574 <register> 10575 <name>INTSCTRL</name> 10576 <description>Internal Sensor Control Register.</description> 10577 <addressOffset>0x04</addressOffset> 10578 <resetMask>0x7F00FFF7</resetMask> 10579 <fields> 10580 <field> 10581 <name>SHIELD_EN</name> 10582 <description>Die Shield Enable.</description> 10583 <bitOffset>0</bitOffset> 10584 <bitWidth>1</bitWidth> 10585 <enumeratedValues> 10586 <enumeratedValue> 10587 <name>dis</name> 10588 <description>Disable.</description> 10589 <value>0</value> 10590 </enumeratedValue> 10591 <enumeratedValue> 10592 <name>en</name> 10593 <description>Enable.</description> 10594 <value>1</value> 10595 </enumeratedValue> 10596 </enumeratedValues> 10597 </field> 10598 <field> 10599 <name>TEMP_EN</name> 10600 <description>Temperature Sensor Enable.</description> 10601 <bitOffset>1</bitOffset> 10602 <bitWidth>1</bitWidth> 10603 <enumeratedValues> 10604 <enumeratedValue> 10605 <name>dis</name> 10606 <description>Disable.</description> 10607 <value>0</value> 10608 </enumeratedValue> 10609 <enumeratedValue> 10610 <name>en</name> 10611 <description>Enable.</description> 10612 <value>1</value> 10613 </enumeratedValue> 10614 </enumeratedValues> 10615 </field> 10616 <field> 10617 <name>VBAT_EN</name> 10618 <description>Battery Monitor Enable.</description> 10619 <bitOffset>2</bitOffset> 10620 <bitWidth>1</bitWidth> 10621 <enumeratedValues> 10622 <enumeratedValue> 10623 <name>dis</name> 10624 <description>Disable.</description> 10625 <value>0</value> 10626 </enumeratedValue> 10627 <enumeratedValue> 10628 <name>en</name> 10629 <description>Enable.</description> 10630 <value>1</value> 10631 </enumeratedValue> 10632 </enumeratedValues> 10633 </field> 10634 <field> 10635 <name>DFD_EN</name> 10636 <description>Digital Fault Dector Enable</description> 10637 <bitOffset>3</bitOffset> 10638 <bitWidth>1</bitWidth> 10639 </field> 10640 <field> 10641 <name>DFD_NMI_EN</name> 10642 <description>Digital Fault NMI Enable</description> 10643 <bitOffset>4</bitOffset> 10644 <bitWidth>1</bitWidth> 10645 </field> 10646 <field> 10647 <name>TAMPOUT_EN</name> 10648 <description>Tamper Output Enable.</description> 10649 <bitOffset>7</bitOffset> 10650 <bitWidth>1</bitWidth> 10651 </field> 10652 <field> 10653 <name>LOTEMP_SEL</name> 10654 <description>Low Temperature Detection Select.</description> 10655 <bitOffset>16</bitOffset> 10656 <bitWidth>1</bitWidth> 10657 <enumeratedValues> 10658 <enumeratedValue> 10659 <name>neg50C</name> 10660 <description>-50 degrees C.</description> 10661 <value>0</value> 10662 </enumeratedValue> 10663 <enumeratedValue> 10664 <name>neg30C</name> 10665 <description>-30 degrees C.</description> 10666 <value>1</value> 10667 </enumeratedValue> 10668 </enumeratedValues> 10669 </field> 10670 <field> 10671 <name>HITEMP_SEL</name> 10672 <description>High Temperature Detection Select.</description> 10673 <bitOffset>17</bitOffset> 10674 <bitWidth>1</bitWidth> 10675 </field> 10676 <field> 10677 <name>VCORELO_EN</name> 10678 <description>VCORE Undervoltage Detect Enable.</description> 10679 <bitOffset>18</bitOffset> 10680 <bitWidth>1</bitWidth> 10681 <enumeratedValues> 10682 <enumeratedValue> 10683 <name>dis</name> 10684 <description>Disable.</description> 10685 <value>0</value> 10686 </enumeratedValue> 10687 <enumeratedValue> 10688 <name>en</name> 10689 <description>Enable.</description> 10690 <value>1</value> 10691 </enumeratedValue> 10692 </enumeratedValues> 10693 </field> 10694 <field> 10695 <name>VCOREHI_EN</name> 10696 <description>VCORE Overvoltage Detect Enable.</description> 10697 <bitOffset>19</bitOffset> 10698 <bitWidth>1</bitWidth> 10699 <enumeratedValues> 10700 <enumeratedValue> 10701 <name>dis</name> 10702 <description>Disable.</description> 10703 <value>0</value> 10704 </enumeratedValue> 10705 <enumeratedValue> 10706 <name>en</name> 10707 <description>Enable.</description> 10708 <value>1</value> 10709 </enumeratedValue> 10710 </enumeratedValues> 10711 </field> 10712 <field> 10713 <name>VDDLO_EN</name> 10714 <description>VDD Undervoltage Detect Enable.</description> 10715 <bitOffset>20</bitOffset> 10716 <bitWidth>1</bitWidth> 10717 <enumeratedValues> 10718 <enumeratedValue> 10719 <name>dis</name> 10720 <description>Disable.</description> 10721 <value>0</value> 10722 </enumeratedValue> 10723 <enumeratedValue> 10724 <name>en</name> 10725 <description>Enable.</description> 10726 <value>1</value> 10727 </enumeratedValue> 10728 </enumeratedValues> 10729 </field> 10730 <field> 10731 <name>VDDHI_EN</name> 10732 <description>VDD Overvoltage Detect Enable.</description> 10733 <bitOffset>21</bitOffset> 10734 <bitWidth>1</bitWidth> 10735 <enumeratedValues> 10736 <enumeratedValue> 10737 <name>dis</name> 10738 <description>Disable.</description> 10739 <value>0</value> 10740 </enumeratedValue> 10741 <enumeratedValue> 10742 <name>en</name> 10743 <description>Enable.</description> 10744 <value>1</value> 10745 </enumeratedValue> 10746 </enumeratedValues> 10747 </field> 10748 <field> 10749 <name>VGL_EN</name> 10750 <description>Voltage Glitch Detection Enable.</description> 10751 <bitOffset>22</bitOffset> 10752 <bitWidth>1</bitWidth> 10753 <enumeratedValues> 10754 <enumeratedValue> 10755 <name>dis</name> 10756 <description>Disable.</description> 10757 <value>0</value> 10758 </enumeratedValue> 10759 <enumeratedValue> 10760 <name>en</name> 10761 <description>Enable.</description> 10762 <value>1</value> 10763 </enumeratedValue> 10764 </enumeratedValues> 10765 </field> 10766 <field> 10767 <name>LOCK</name> 10768 <description>Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.</description> 10769 <bitOffset>31</bitOffset> 10770 <bitWidth>1</bitWidth> 10771 <enumeratedValues> 10772 <enumeratedValue> 10773 <name>unlocked</name> 10774 <description>Unlocked.</description> 10775 <value>0</value> 10776 </enumeratedValue> 10777 <enumeratedValue> 10778 <name>locked</name> 10779 <description>Locked.</description> 10780 <value>1</value> 10781 </enumeratedValue> 10782 </enumeratedValues> 10783 </field> 10784 </fields> 10785 </register> 10786 <register> 10787 <name>SECALM</name> 10788 <description>Security Alarm Register.</description> 10789 <addressOffset>0x08</addressOffset> 10790 <resetValue>0x00000000</resetValue> 10791 <resetMask>0x00000000</resetMask> 10792 <fields> 10793 <field> 10794 <name>DRS</name> 10795 <description>Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware.</description> 10796 <bitOffset>0</bitOffset> 10797 <bitWidth>1</bitWidth> 10798 <enumeratedValues> 10799 <enumeratedValue> 10800 <name>complete</name> 10801 <description>No operation/complete.</description> 10802 <value>0</value> 10803 </enumeratedValue> 10804 <enumeratedValue> 10805 <name>start</name> 10806 <description>Start operation.</description> 10807 <value>1</value> 10808 </enumeratedValue> 10809 </enumeratedValues> 10810 </field> 10811 <field> 10812 <name>KEYWIPE</name> 10813 <description>Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped.</description> 10814 <bitOffset>1</bitOffset> 10815 <bitWidth>1</bitWidth> 10816 <enumeratedValues> 10817 <enumeratedValue> 10818 <name>complete</name> 10819 <description>No operation/complete.</description> 10820 <value>0</value> 10821 </enumeratedValue> 10822 <enumeratedValue> 10823 <name>start</name> 10824 <description>Start operation.</description> 10825 <value>1</value> 10826 </enumeratedValue> 10827 </enumeratedValues> 10828 </field> 10829 <field> 10830 <name>SHIELD_FL</name> 10831 <description>Die Shield Flag.</description> 10832 <bitOffset>2</bitOffset> 10833 <bitWidth>1</bitWidth> 10834 <enumeratedValues> 10835 <enumeratedValue> 10836 <name>noEvent</name> 10837 <description>The event has not occurred.</description> 10838 <value>0</value> 10839 </enumeratedValue> 10840 <enumeratedValue> 10841 <name>occurred</name> 10842 <description>The event has occurred.</description> 10843 <value>1</value> 10844 </enumeratedValue> 10845 </enumeratedValues> 10846 </field> 10847 <field> 10848 <name>LOTEMP_FL</name> 10849 <description>Low Temperature Detect.</description> 10850 <bitOffset>3</bitOffset> 10851 <bitWidth>1</bitWidth> 10852 <enumeratedValues> 10853 <enumeratedValue> 10854 <name>noEvent</name> 10855 <description>The event has not occurred.</description> 10856 <value>0</value> 10857 </enumeratedValue> 10858 <enumeratedValue> 10859 <name>occurred</name> 10860 <description>The event has occurred.</description> 10861 <value>1</value> 10862 </enumeratedValue> 10863 </enumeratedValues> 10864 </field> 10865 <field> 10866 <name>HITEMP_FL</name> 10867 <description>High Temperature Detect.</description> 10868 <bitOffset>4</bitOffset> 10869 <bitWidth>1</bitWidth> 10870 <enumeratedValues> 10871 <enumeratedValue> 10872 <name>noEvent</name> 10873 <description>The event has not occurred.</description> 10874 <value>0</value> 10875 </enumeratedValue> 10876 <enumeratedValue> 10877 <name>occurred</name> 10878 <description>The event has occurred.</description> 10879 <value>1</value> 10880 </enumeratedValue> 10881 </enumeratedValues> 10882 </field> 10883 <field> 10884 <name>BATLO_FL</name> 10885 <description>Battery Undervoltage Detect.</description> 10886 <bitOffset>5</bitOffset> 10887 <bitWidth>1</bitWidth> 10888 <enumeratedValues> 10889 <enumeratedValue> 10890 <name>noEvent</name> 10891 <description>The event has not occurred.</description> 10892 <value>0</value> 10893 </enumeratedValue> 10894 <enumeratedValue> 10895 <name>occurred</name> 10896 <description>The event has occurred.</description> 10897 <value>1</value> 10898 </enumeratedValue> 10899 </enumeratedValues> 10900 </field> 10901 <field> 10902 <name>BATHI_FL</name> 10903 <description>Battery Overvoltage Detect.</description> 10904 <bitOffset>6</bitOffset> 10905 <bitWidth>1</bitWidth> 10906 <enumeratedValues> 10907 <enumeratedValue> 10908 <name>noEvent</name> 10909 <description>The event has not occurred.</description> 10910 <value>0</value> 10911 </enumeratedValue> 10912 <enumeratedValue> 10913 <name>occurred</name> 10914 <description>The event has occurred.</description> 10915 <value>1</value> 10916 </enumeratedValue> 10917 </enumeratedValues> 10918 </field> 10919 <field> 10920 <name>EXTS_FL</name> 10921 <description>External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.</description> 10922 <bitOffset>7</bitOffset> 10923 <bitWidth>1</bitWidth> 10924 <enumeratedValues> 10925 <enumeratedValue> 10926 <name>noEvent</name> 10927 <description>The event has not occurred.</description> 10928 <value>0</value> 10929 </enumeratedValue> 10930 <enumeratedValue> 10931 <name>occurred</name> 10932 <description>The event has occurred.</description> 10933 <value>1</value> 10934 </enumeratedValue> 10935 </enumeratedValues> 10936 </field> 10937 <field> 10938 <name>DFD_FL</name> 10939 <description>Digital Fault Detector.</description> 10940 <bitOffset>8</bitOffset> 10941 <bitWidth>1</bitWidth> 10942 <enumeratedValues> 10943 <enumeratedValue> 10944 <name>noEvent</name> 10945 <description>The event has not occurred.</description> 10946 <value>0</value> 10947 </enumeratedValue> 10948 <enumeratedValue> 10949 <name>occurred</name> 10950 <description>The event has occurred.</description> 10951 <value>1</value> 10952 </enumeratedValue> 10953 </enumeratedValues> 10954 </field> 10955 <field> 10956 <name>VMAINPF_FL</name> 10957 <description>VMAIN Power Fail Flag.</description> 10958 <bitOffset>9</bitOffset> 10959 <bitWidth>1</bitWidth> 10960 <enumeratedValues> 10961 <enumeratedValue> 10962 <name>noEvent</name> 10963 <description>The event has not occurred.</description> 10964 <value>0</value> 10965 </enumeratedValue> 10966 <enumeratedValue> 10967 <name>occurred</name> 10968 <description>The event has occurred.</description> 10969 <value>1</value> 10970 </enumeratedValue> 10971 </enumeratedValues> 10972 </field> 10973 <field> 10974 <name>VCOREHI_FL</name> 10975 <description>VCORE Overvoltage Detect Flag.</description> 10976 <bitOffset>10</bitOffset> 10977 <bitWidth>1</bitWidth> 10978 <enumeratedValues> 10979 <enumeratedValue> 10980 <name>noEvent</name> 10981 <description>The event has not occurred.</description> 10982 <value>0</value> 10983 </enumeratedValue> 10984 <enumeratedValue> 10985 <name>occurred</name> 10986 <description>The event has occurred.</description> 10987 <value>1</value> 10988 </enumeratedValue> 10989 </enumeratedValues> 10990 </field> 10991 <field> 10992 <name>VDDHI_FL</name> 10993 <description>VDD Overvoltage Flag.</description> 10994 <bitOffset>11</bitOffset> 10995 <bitWidth>1</bitWidth> 10996 <enumeratedValues> 10997 <enumeratedValue> 10998 <name>noEvent</name> 10999 <description>The event has not occurred.</description> 11000 <value>0</value> 11001 </enumeratedValue> 11002 <enumeratedValue> 11003 <name>occurred</name> 11004 <description>The event has occurred.</description> 11005 <value>1</value> 11006 </enumeratedValue> 11007 </enumeratedValues> 11008 </field> 11009 <field> 11010 <name>VGL_FL</name> 11011 <description>Voltage Glitch Detection Flag.</description> 11012 <bitOffset>12</bitOffset> 11013 <bitWidth>1</bitWidth> 11014 <enumeratedValues> 11015 <enumeratedValue> 11016 <name>noEvent</name> 11017 <description>The event has not occurred.</description> 11018 <value>0</value> 11019 </enumeratedValue> 11020 <enumeratedValue> 11021 <name>occurred</name> 11022 <description>The event has occurred.</description> 11023 <value>1</value> 11024 </enumeratedValue> 11025 </enumeratedValues> 11026 </field> 11027 <field> 11028 <name>EXTSTAT0_FL</name> 11029 <description>External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 11030 <bitOffset>16</bitOffset> 11031 <bitWidth>1</bitWidth> 11032 <enumeratedValues> 11033 <enumeratedValue> 11034 <name>noEvent</name> 11035 <description>The event has not occurred.</description> 11036 <value>0</value> 11037 </enumeratedValue> 11038 <enumeratedValue> 11039 <name>occurred</name> 11040 <description>The event has occurred.</description> 11041 <value>1</value> 11042 </enumeratedValue> 11043 </enumeratedValues> 11044 </field> 11045 <field> 11046 <name>EXTSTAT1_FL</name> 11047 <description>External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 11048 <bitOffset>17</bitOffset> 11049 <bitWidth>1</bitWidth> 11050 <enumeratedValues> 11051 <enumeratedValue> 11052 <name>noEvent</name> 11053 <description>The event has not occurred.</description> 11054 <value>0</value> 11055 </enumeratedValue> 11056 <enumeratedValue> 11057 <name>occurred</name> 11058 <description>The event has occurred.</description> 11059 <value>1</value> 11060 </enumeratedValue> 11061 </enumeratedValues> 11062 </field> 11063 <field> 11064 <name>EXTSTAT2_FL</name> 11065 <description>External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 11066 <bitOffset>18</bitOffset> 11067 <bitWidth>1</bitWidth> 11068 <enumeratedValues> 11069 <enumeratedValue> 11070 <name>noEvent</name> 11071 <description>The event has not occurred.</description> 11072 <value>0</value> 11073 </enumeratedValue> 11074 <enumeratedValue> 11075 <name>occurred</name> 11076 <description>The event has occurred.</description> 11077 <value>1</value> 11078 </enumeratedValue> 11079 </enumeratedValues> 11080 </field> 11081 <field> 11082 <name>EXTSTAT3_FL</name> 11083 <description>External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 11084 <bitOffset>19</bitOffset> 11085 <bitWidth>1</bitWidth> 11086 <enumeratedValues> 11087 <enumeratedValue> 11088 <name>noEvent</name> 11089 <description>The event has not occurred.</description> 11090 <value>0</value> 11091 </enumeratedValue> 11092 <enumeratedValue> 11093 <name>occurred</name> 11094 <description>The event has occurred.</description> 11095 <value>1</value> 11096 </enumeratedValue> 11097 </enumeratedValues> 11098 </field> 11099 <field> 11100 <name>EXTSTAT4_FL</name> 11101 <description>External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 11102 <bitOffset>20</bitOffset> 11103 <bitWidth>1</bitWidth> 11104 <enumeratedValues> 11105 <enumeratedValue> 11106 <name>noEvent</name> 11107 <description>The event has not occurred.</description> 11108 <value>0</value> 11109 </enumeratedValue> 11110 <enumeratedValue> 11111 <name>occurred</name> 11112 <description>The event has occurred.</description> 11113 <value>1</value> 11114 </enumeratedValue> 11115 </enumeratedValues> 11116 </field> 11117 <field> 11118 <name>EXTSTAT5_FL</name> 11119 <description>External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 11120 <bitOffset>21</bitOffset> 11121 <bitWidth>1</bitWidth> 11122 <enumeratedValues> 11123 <enumeratedValue> 11124 <name>noEvent</name> 11125 <description>The event has not occurred.</description> 11126 <value>0</value> 11127 </enumeratedValue> 11128 <enumeratedValue> 11129 <name>occurred</name> 11130 <description>The event has occurred.</description> 11131 <value>1</value> 11132 </enumeratedValue> 11133 </enumeratedValues> 11134 </field> 11135 <field> 11136 <name>EXTSWARN0_FL</name> 11137 <description>External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 11138 <bitOffset>24</bitOffset> 11139 <bitWidth>1</bitWidth> 11140 <enumeratedValues> 11141 <enumeratedValue> 11142 <name>noEvent</name> 11143 <description>The event has not occurred.</description> 11144 <value>0</value> 11145 </enumeratedValue> 11146 <enumeratedValue> 11147 <name>occurred</name> 11148 <description>The event has occurred.</description> 11149 <value>1</value> 11150 </enumeratedValue> 11151 </enumeratedValues> 11152 </field> 11153 <field> 11154 <name>EXTSWARN1_FL</name> 11155 <description>External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 11156 <bitOffset>25</bitOffset> 11157 <bitWidth>1</bitWidth> 11158 <enumeratedValues> 11159 <enumeratedValue> 11160 <name>noEvent</name> 11161 <description>The event has not occurred.</description> 11162 <value>0</value> 11163 </enumeratedValue> 11164 <enumeratedValue> 11165 <name>occurred</name> 11166 <description>The event has occurred.</description> 11167 <value>1</value> 11168 </enumeratedValue> 11169 </enumeratedValues> 11170 </field> 11171 <field> 11172 <name>EXTSWARN2_FL</name> 11173 <description>External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 11174 <bitOffset>26</bitOffset> 11175 <bitWidth>1</bitWidth> 11176 <enumeratedValues> 11177 <enumeratedValue> 11178 <name>noEvent</name> 11179 <description>The event has not occurred.</description> 11180 <value>0</value> 11181 </enumeratedValue> 11182 <enumeratedValue> 11183 <name>occurred</name> 11184 <description>The event has occurred.</description> 11185 <value>1</value> 11186 </enumeratedValue> 11187 </enumeratedValues> 11188 </field> 11189 <field> 11190 <name>EXTSWARN3_FL</name> 11191 <description>External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 11192 <bitOffset>27</bitOffset> 11193 <bitWidth>1</bitWidth> 11194 <enumeratedValues> 11195 <enumeratedValue> 11196 <name>noEvent</name> 11197 <description>The event has not occurred.</description> 11198 <value>0</value> 11199 </enumeratedValue> 11200 <enumeratedValue> 11201 <name>occurred</name> 11202 <description>The event has occurred.</description> 11203 <value>1</value> 11204 </enumeratedValue> 11205 </enumeratedValues> 11206 </field> 11207 <field> 11208 <name>EXTSWARN4_FL</name> 11209 <description>External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 11210 <bitOffset>28</bitOffset> 11211 <bitWidth>1</bitWidth> 11212 <enumeratedValues> 11213 <enumeratedValue> 11214 <name>noEvent</name> 11215 <description>The event has not occurred.</description> 11216 <value>0</value> 11217 </enumeratedValue> 11218 <enumeratedValue> 11219 <name>occurred</name> 11220 <description>The event has occurred.</description> 11221 <value>1</value> 11222 </enumeratedValue> 11223 </enumeratedValues> 11224 </field> 11225 <field> 11226 <name>EXTSWARN5_FL</name> 11227 <description>External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 11228 <bitOffset>29</bitOffset> 11229 <bitWidth>1</bitWidth> 11230 <enumeratedValues> 11231 <enumeratedValue> 11232 <name>noEvent</name> 11233 <description>The event has not occurred.</description> 11234 <value>0</value> 11235 </enumeratedValue> 11236 <enumeratedValue> 11237 <name>occurred</name> 11238 <description>The event has occurred.</description> 11239 <value>1</value> 11240 </enumeratedValue> 11241 </enumeratedValues> 11242 </field> 11243 </fields> 11244 </register> 11245 <register> 11246 <name>SECDIAG</name> 11247 <description>Security Diagnostic Register.</description> 11248 <addressOffset>0x0C</addressOffset> 11249 <access>read-write</access> 11250 <resetValue>0x00000001</resetValue> 11251 <resetMask>0xFFC0FE02</resetMask> 11252 <fields> 11253 <field> 11254 <name>POR_FL</name> 11255 <description>Power-On-Reset Flag. This bit is set once the power supply is conneted.</description> 11256 <bitOffset>0</bitOffset> 11257 <bitWidth>1</bitWidth> 11258 <enumeratedValues> 11259 <enumeratedValue> 11260 <name>noEvent</name> 11261 <description>The event has not occurred.</description> 11262 <value>0</value> 11263 </enumeratedValue> 11264 <enumeratedValue> 11265 <name>occurred</name> 11266 <description>The event has occurred.</description> 11267 <value>1</value> 11268 </enumeratedValue> 11269 </enumeratedValues> 11270 </field> 11271 <field> 11272 <name>SHIELD_FL</name> 11273 <description>Die Shield Flag.</description> 11274 <bitOffset>2</bitOffset> 11275 <bitWidth>1</bitWidth> 11276 <enumeratedValues> 11277 <enumeratedValue> 11278 <name>noEvent</name> 11279 <description>The event has not occurred.</description> 11280 <value>0</value> 11281 </enumeratedValue> 11282 <enumeratedValue> 11283 <name>occurred</name> 11284 <description>The event has occurred.</description> 11285 <value>1</value> 11286 </enumeratedValue> 11287 </enumeratedValues> 11288 </field> 11289 <field> 11290 <name>LOTEMP_FL</name> 11291 <description>Low Temperature Detect.</description> 11292 <bitOffset>3</bitOffset> 11293 <bitWidth>1</bitWidth> 11294 <enumeratedValues> 11295 <enumeratedValue> 11296 <name>noEvent</name> 11297 <description>The event has not occurred.</description> 11298 <value>0</value> 11299 </enumeratedValue> 11300 <enumeratedValue> 11301 <name>occurred</name> 11302 <description>The event has occurred.</description> 11303 <value>1</value> 11304 </enumeratedValue> 11305 </enumeratedValues> 11306 </field> 11307 <field> 11308 <name>HITEMP_FL</name> 11309 <description>High Temperature Detect.</description> 11310 <bitOffset>4</bitOffset> 11311 <bitWidth>1</bitWidth> 11312 <enumeratedValues> 11313 <enumeratedValue> 11314 <name>noEvent</name> 11315 <description>The event has not occurred.</description> 11316 <value>0</value> 11317 </enumeratedValue> 11318 <enumeratedValue> 11319 <name>occurred</name> 11320 <description>The event has occurred.</description> 11321 <value>1</value> 11322 </enumeratedValue> 11323 </enumeratedValues> 11324 </field> 11325 <field> 11326 <name>BATLO_FL</name> 11327 <description>Battery Undervoltage Detect.</description> 11328 <bitOffset>5</bitOffset> 11329 <bitWidth>1</bitWidth> 11330 <enumeratedValues> 11331 <enumeratedValue> 11332 <name>noEvent</name> 11333 <description>The event has not occurred.</description> 11334 <value>0</value> 11335 </enumeratedValue> 11336 <enumeratedValue> 11337 <name>occurred</name> 11338 <description>The event has occurred.</description> 11339 <value>1</value> 11340 </enumeratedValue> 11341 </enumeratedValues> 11342 </field> 11343 <field> 11344 <name>BATHI_FL</name> 11345 <description>Battery Overvoltage Detect.</description> 11346 <bitOffset>6</bitOffset> 11347 <bitWidth>1</bitWidth> 11348 <enumeratedValues> 11349 <enumeratedValue> 11350 <name>noEvent</name> 11351 <description>The event has not occurred.</description> 11352 <value>0</value> 11353 </enumeratedValue> 11354 <enumeratedValue> 11355 <name>occurred</name> 11356 <description>The event has occurred.</description> 11357 <value>1</value> 11358 </enumeratedValue> 11359 </enumeratedValues> 11360 </field> 11361 <field> 11362 <name>DYNS_FL</name> 11363 <description>Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.</description> 11364 <bitOffset>7</bitOffset> 11365 <bitWidth>1</bitWidth> 11366 <enumeratedValues> 11367 <enumeratedValue> 11368 <name>noEvent</name> 11369 <description>The event has not occurred.</description> 11370 <value>0</value> 11371 </enumeratedValue> 11372 <enumeratedValue> 11373 <name>occurred</name> 11374 <description>The event has occurred.</description> 11375 <value>1</value> 11376 </enumeratedValue> 11377 </enumeratedValues> 11378 </field> 11379 <field> 11380 <name>AESKT_MEU</name> 11381 <description>AES Key Transfer. This bit is set to 1 when the NVSRAM 256 bit AES key is generated by the TRNG and loaded to the AES KEY NVSRAM Encryption registers. This bit is reset by a POR or DRS.</description> 11382 <bitOffset>8</bitOffset> 11383 <bitWidth>1</bitWidth> 11384 <enumeratedValues> 11385 <enumeratedValue> 11386 <name>incomplete</name> 11387 <description>Key has not been transferred.</description> 11388 <value>0</value> 11389 </enumeratedValue> 11390 <enumeratedValue> 11391 <name>complete</name> 11392 <description>Key has been transferred.</description> 11393 <value>1</value> 11394 </enumeratedValue> 11395 </enumeratedValues> 11396 </field> 11397 <field> 11398 <name>AESKT_MEMPROT_XIP</name> 11399 <description>AES Key Transfer. This bit is set to 1 when AES MDU Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR.</description> 11400 <bitOffset>9</bitOffset> 11401 <bitWidth>1</bitWidth> 11402 <enumeratedValues> 11403 <enumeratedValue> 11404 <name>incomplete</name> 11405 <description>Key has not been transferred.</description> 11406 <value>0</value> 11407 </enumeratedValue> 11408 <enumeratedValue> 11409 <name>complete</name> 11410 <description>Key has been transferred.</description> 11411 <value>1</value> 11412 </enumeratedValue> 11413 </enumeratedValues> 11414 </field> 11415 <field> 11416 <name>KEY0_ZERO</name> 11417 <description>Key0 Cleared.</description> 11418 <bitOffset>10</bitOffset> 11419 <bitWidth>1</bitWidth> 11420 <enumeratedValues> 11421 <enumeratedValue> 11422 <name>incomplete</name> 11423 <description>Key has not been transferred.</description> 11424 <value>0</value> 11425 </enumeratedValue> 11426 <enumeratedValue> 11427 <name>complete</name> 11428 <description>Key has been transferred.</description> 11429 <value>1</value> 11430 </enumeratedValue> 11431 </enumeratedValues> 11432 </field> 11433 <field> 11434 <name>KEY1_ZERO</name> 11435 <description>Key1 Cleared.</description> 11436 <bitOffset>11</bitOffset> 11437 <bitWidth>1</bitWidth> 11438 <enumeratedValues> 11439 <enumeratedValue> 11440 <name>incomplete</name> 11441 <description>Key has not been transferred.</description> 11442 <value>0</value> 11443 </enumeratedValue> 11444 <enumeratedValue> 11445 <name>complete</name> 11446 <description>Key has been transferred.</description> 11447 <value>1</value> 11448 </enumeratedValue> 11449 </enumeratedValues> 11450 </field> 11451 <field> 11452 <name>DFD_FL</name> 11453 <description>Digital Fault Detector Flag.</description> 11454 <bitOffset>15</bitOffset> 11455 <bitWidth>1</bitWidth> 11456 <enumeratedValues> 11457 <enumeratedValue> 11458 <name>noEvent</name> 11459 <description>The event has not occurred.</description> 11460 <value>0</value> 11461 </enumeratedValue> 11462 <enumeratedValue> 11463 <name>occurred</name> 11464 <description>The event has occurred.</description> 11465 <value>1</value> 11466 </enumeratedValue> 11467 </enumeratedValues> 11468 </field> 11469 <field> 11470 <name>EXTS0_FL</name> 11471 <description>External Sensor 0 Detect.</description> 11472 <bitOffset>16</bitOffset> 11473 <bitWidth>1</bitWidth> 11474 <enumeratedValues> 11475 <enumeratedValue> 11476 <name>noEvent</name> 11477 <description>The event has not occurred.</description> 11478 <value>0</value> 11479 </enumeratedValue> 11480 <enumeratedValue> 11481 <name>occurred</name> 11482 <description>The event has occurred.</description> 11483 <value>1</value> 11484 </enumeratedValue> 11485 </enumeratedValues> 11486 </field> 11487 <field> 11488 <name>EXTS1_FL</name> 11489 <description>External Sensor 1 Detect.</description> 11490 <bitOffset>17</bitOffset> 11491 <bitWidth>1</bitWidth> 11492 <enumeratedValues> 11493 <enumeratedValue> 11494 <name>noEvent</name> 11495 <description>The event has not occurred.</description> 11496 <value>0</value> 11497 </enumeratedValue> 11498 <enumeratedValue> 11499 <name>occurred</name> 11500 <description>The event has occurred.</description> 11501 <value>1</value> 11502 </enumeratedValue> 11503 </enumeratedValues> 11504 </field> 11505 <field> 11506 <name>EXTS2_FL</name> 11507 <description>External Sensor 2 Detect.</description> 11508 <bitOffset>18</bitOffset> 11509 <bitWidth>1</bitWidth> 11510 <enumeratedValues> 11511 <enumeratedValue> 11512 <name>noEvent</name> 11513 <description>The event has not occurred.</description> 11514 <value>0</value> 11515 </enumeratedValue> 11516 <enumeratedValue> 11517 <name>occurred</name> 11518 <description>The event has occurred.</description> 11519 <value>1</value> 11520 </enumeratedValue> 11521 </enumeratedValues> 11522 </field> 11523 <field> 11524 <name>EXTS3_FL</name> 11525 <description>External Sensor 3 Detect.</description> 11526 <bitOffset>19</bitOffset> 11527 <bitWidth>1</bitWidth> 11528 <enumeratedValues> 11529 <enumeratedValue> 11530 <name>noEvent</name> 11531 <description>The event has not occurred.</description> 11532 <value>0</value> 11533 </enumeratedValue> 11534 <enumeratedValue> 11535 <name>occurred</name> 11536 <description>The event has occurred.</description> 11537 <value>1</value> 11538 </enumeratedValue> 11539 </enumeratedValues> 11540 </field> 11541 <field> 11542 <name>EXTS4_FL</name> 11543 <description>External Sensor 4 Detect.</description> 11544 <bitOffset>20</bitOffset> 11545 <bitWidth>1</bitWidth> 11546 <enumeratedValues> 11547 <enumeratedValue> 11548 <name>noEvent</name> 11549 <description>The event has not occurred.</description> 11550 <value>0</value> 11551 </enumeratedValue> 11552 <enumeratedValue> 11553 <name>occurred</name> 11554 <description>The event has occurred.</description> 11555 <value>1</value> 11556 </enumeratedValue> 11557 </enumeratedValues> 11558 </field> 11559 <field> 11560 <name>EXTS5_FL</name> 11561 <description>External Sensor 5 Detect.</description> 11562 <bitOffset>21</bitOffset> 11563 <bitWidth>1</bitWidth> 11564 <enumeratedValues> 11565 <enumeratedValue> 11566 <name>noEvent</name> 11567 <description>The event has not occurred.</description> 11568 <value>0</value> 11569 </enumeratedValue> 11570 <enumeratedValue> 11571 <name>occurred</name> 11572 <description>The event has occurred.</description> 11573 <value>1</value> 11574 </enumeratedValue> 11575 </enumeratedValues> 11576 </field> 11577 </fields> 11578 </register> 11579 <register> 11580 <name>DLRTC</name> 11581 <description>DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred.</description> 11582 <addressOffset>0x10</addressOffset> 11583 <access>read-only</access> 11584 <resetMask>0x00000000</resetMask> 11585 <fields> 11586 <field> 11587 <name>DLRTC</name> 11588 <description>DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured.</description> 11589 <bitOffset>0</bitOffset> 11590 <bitWidth>32</bitWidth> 11591 </field> 11592 </fields> 11593 </register> 11594 <register> 11595 <name>MEUCTRL</name> 11596 <description>MEU Configuration</description> 11597 <addressOffset>0x24</addressOffset> 11598 <resetMask>0x00000000</resetMask> 11599 <fields> 11600 <field> 11601 <name>ENC_EN</name> 11602 <description>Configuration plain/encrypted area of the backed NVSRAM.</description> 11603 <bitOffset>0</bitOffset> 11604 <bitWidth>7</bitWidth> 11605 </field> 11606 <field> 11607 <name>LOCK</name> 11608 <description>Lock.</description> 11609 <bitOffset>31</bitOffset> 11610 <bitWidth>1</bitWidth> 11611 </field> 11612 </fields> 11613 </register> 11614 <register> 11615 <name>SECST</name> 11616 <description>Security Monitor Status Register.</description> 11617 <addressOffset>0x34</addressOffset> 11618 <access>read-only</access> 11619 <fields> 11620 <field> 11621 <name>EXTSCTRL</name> 11622 <description>External Sensor Control Register Status.</description> 11623 <bitOffset>0</bitOffset> 11624 <bitWidth>1</bitWidth> 11625 <enumeratedValues> 11626 <enumeratedValue> 11627 <name>allowed</name> 11628 <description>Access authorized.</description> 11629 <value>0</value> 11630 </enumeratedValue> 11631 <enumeratedValue> 11632 <name>notAllowed</name> 11633 <description>Access not authorized.</description> 11634 <value>1</value> 11635 </enumeratedValue> 11636 </enumeratedValues> 11637 </field> 11638 <field> 11639 <name>INTSCTRL</name> 11640 <description>Internal Sensor Control Register Status.</description> 11641 <bitOffset>1</bitOffset> 11642 <bitWidth>1</bitWidth> 11643 <enumeratedValues> 11644 <enumeratedValue> 11645 <name>allowed</name> 11646 <description>Access authorized.</description> 11647 <value>0</value> 11648 </enumeratedValue> 11649 <enumeratedValue> 11650 <name>notAllowed</name> 11651 <description>Access not authorized.</description> 11652 <value>1</value> 11653 </enumeratedValue> 11654 </enumeratedValues> 11655 </field> 11656 <field> 11657 <name>SECALM</name> 11658 <description>Security Alarm Register Status.</description> 11659 <bitOffset>2</bitOffset> 11660 <bitWidth>1</bitWidth> 11661 <enumeratedValues> 11662 <enumeratedValue> 11663 <name>allowed</name> 11664 <description>Access authorized.</description> 11665 <value>0</value> 11666 </enumeratedValue> 11667 <enumeratedValue> 11668 <name>notAllowed</name> 11669 <description>Access not authorized.</description> 11670 <value>1</value> 11671 </enumeratedValue> 11672 </enumeratedValues> 11673 </field> 11674 <field> 11675 <name>MEUCTRL</name> 11676 <description>Security Alarm Register Status.</description> 11677 <bitOffset>7</bitOffset> 11678 <bitWidth>1</bitWidth> 11679 <enumeratedValues> 11680 <enumeratedValue> 11681 <name>allowed</name> 11682 <description>Access authorized.</description> 11683 <value>0</value> 11684 </enumeratedValue> 11685 <enumeratedValue> 11686 <name>notAllowed</name> 11687 <description>Access not authorized.</description> 11688 <value>1</value> 11689 </enumeratedValue> 11690 </enumeratedValues> 11691 </field> 11692 </fields> 11693 </register> 11694 <register> 11695 <name>SDBE</name> 11696 <description>Security Monitor Self Destruct Byte.</description> 11697 <addressOffset>0x38</addressOffset> 11698 <fields> 11699 <field> 11700 <name>SDBYTE</name> 11701 <description>Self Destruct Byte</description> 11702 <bitOffset>0</bitOffset> 11703 <bitWidth>8</bitWidth> 11704 </field> 11705 <field> 11706 <name>SDBYTE_EN</name> 11707 <description>Self-Destruct Byte Enable.</description> 11708 <bitOffset>31</bitOffset> 11709 <bitWidth>1</bitWidth> 11710 </field> 11711 </fields> 11712 </register> 11713 </registers> 11714 </peripheral> 11715<!--SMON The Security Monitor block used to monitor system threat conditions.--> 11716 <peripheral> 11717 <name>SPIXFC</name> 11718 <description>SPI XiP Flash Configuration Controller</description> 11719 <baseAddress>0x40027000</baseAddress> 11720 <addressBlock> 11721 <offset>0</offset> 11722 <size>0x1000</size> 11723 <usage>registers</usage> 11724 </addressBlock> 11725 <interrupt> 11726 <name>SPIXFC</name> 11727 <description>SPIXFC IRQ</description> 11728 <value>38</value> 11729 </interrupt> 11730 <registers> 11731 <register> 11732 <name>CTRL0</name> 11733 <description>Control Register.</description> 11734 <addressOffset>0x00</addressOffset> 11735 <fields> 11736 <field> 11737 <name>SSEL</name> 11738 <description>Slaves Select.</description> 11739 <bitOffset>0</bitOffset> 11740 <bitWidth>3</bitWidth> 11741 <enumeratedValues> 11742 <enumeratedValue> 11743 <name>Slave_0</name> 11744 <description>Slave 0 is selected.</description> 11745 <value>0</value> 11746 </enumeratedValue> 11747 <enumeratedValue> 11748 <name>Slave_1</name> 11749 <description>Slave 1 is selected.</description> 11750 <value>1</value> 11751 </enumeratedValue> 11752 </enumeratedValues> 11753 </field> 11754 <field> 11755 <name>THREE_WIRE</name> 11756 <description>Three Wire Mode.</description> 11757 <bitOffset>3</bitOffset> 11758 <bitWidth>1</bitWidth> 11759 </field> 11760 <field> 11761 <name>MODE</name> 11762 <description>Defines SPI Mode, Only valid values are 0 and 3.</description> 11763 <bitOffset>4</bitOffset> 11764 <bitWidth>2</bitWidth> 11765 <enumeratedValues> 11766 <enumeratedValue> 11767 <name>SPI_Mode_0</name> 11768 <description>SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0.</description> 11769 <value>0</value> 11770 </enumeratedValue> 11771 <enumeratedValue> 11772 <name>SPI_Mode_3</name> 11773 <description>SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1.</description> 11774 <value>3</value> 11775 </enumeratedValue> 11776 </enumeratedValues> 11777 </field> 11778 <field> 11779 <name>PGSZ</name> 11780 <description>Page Size.</description> 11781 <bitOffset>6</bitOffset> 11782 <bitWidth>2</bitWidth> 11783 <enumeratedValues> 11784 <enumeratedValue> 11785 <name>4_bytes</name> 11786 <description>4 bytes.</description> 11787 <value>0</value> 11788 </enumeratedValue> 11789 <enumeratedValue> 11790 <name>8_bytes</name> 11791 <description>8 bytes.</description> 11792 <value>1</value> 11793 </enumeratedValue> 11794 <enumeratedValue> 11795 <name>16_bytes</name> 11796 <description>16 bytes.</description> 11797 <value>2</value> 11798 </enumeratedValue> 11799 <enumeratedValue> 11800 <name>32_bytes</name> 11801 <description>32 bytes.</description> 11802 <value>3</value> 11803 </enumeratedValue> 11804 </enumeratedValues> 11805 </field> 11806 <field> 11807 <name>HICLK</name> 11808 <description>SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high.</description> 11809 <bitOffset>8</bitOffset> 11810 <bitWidth>4</bitWidth> 11811 <enumeratedValues> 11812 <enumeratedValue> 11813 <name>16_SCLK</name> 11814 <description>16 system clocks.</description> 11815 <value>0</value> 11816 </enumeratedValue> 11817 </enumeratedValues> 11818 </field> 11819 <field> 11820 <name>LOCLK</name> 11821 <description>SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low.</description> 11822 <bitOffset>12</bitOffset> 11823 <bitWidth>4</bitWidth> 11824 <enumeratedValues> 11825 <enumeratedValue> 11826 <name>16_SCLK</name> 11827 <description>16 system clocks.</description> 11828 <value>0</value> 11829 </enumeratedValue> 11830 </enumeratedValues> 11831 </field> 11832 <field> 11833 <name>SSACT</name> 11834 <description>Slaves Select Activate Timing.</description> 11835 <bitOffset>16</bitOffset> 11836 <bitWidth>2</bitWidth> 11837 <enumeratedValues> 11838 <enumeratedValue> 11839 <name>0_CLKS</name> 11840 <description>0 sytem clocks.</description> 11841 <value>0</value> 11842 </enumeratedValue> 11843 <enumeratedValue> 11844 <name>2_CLKS</name> 11845 <description>2 sytem clocks.</description> 11846 <value>1</value> 11847 </enumeratedValue> 11848 <enumeratedValue> 11849 <name>4_CLKS</name> 11850 <description>4 sytem clocks.</description> 11851 <value>2</value> 11852 </enumeratedValue> 11853 <enumeratedValue> 11854 <name>8_CLKS</name> 11855 <description>8 sytem clocks.</description> 11856 <value>3</value> 11857 </enumeratedValue> 11858 </enumeratedValues> 11859 </field> 11860 <field> 11861 <name>SSINACT</name> 11862 <description>Slaves Select Inactive Timing.</description> 11863 <bitOffset>18</bitOffset> 11864 <bitWidth>2</bitWidth> 11865 <enumeratedValues> 11866 <enumeratedValue> 11867 <name>4_CLKS</name> 11868 <description>4 sytem clocks.</description> 11869 <value>0</value> 11870 </enumeratedValue> 11871 <enumeratedValue> 11872 <name>6_CLKS</name> 11873 <description>6 sytem clocks.</description> 11874 <value>1</value> 11875 </enumeratedValue> 11876 <enumeratedValue> 11877 <name>8_CLKS</name> 11878 <description>8 sytem clocks.</description> 11879 <value>2</value> 11880 </enumeratedValue> 11881 <enumeratedValue> 11882 <name>12_CLKS</name> 11883 <description>12 sytem clocks.</description> 11884 <value>3</value> 11885 </enumeratedValue> 11886 </enumeratedValues> 11887 </field> 11888 <field> 11889 <name>IOSMPL</name> 11890 <description>Sample Delay</description> 11891 <bitOffset>20</bitOffset> 11892 <bitWidth>4</bitWidth> 11893 </field> 11894 </fields> 11895 </register> 11896 <register> 11897 <name>SSPOL</name> 11898 <description>SPIX Controller Slave Select Polarity Register.</description> 11899 <addressOffset>0x04</addressOffset> 11900 <fields> 11901 <field> 11902 <name>SSPOL</name> 11903 <description>Slave Select Polarity.</description> 11904 <bitOffset>0</bitOffset> 11905 <bitWidth>1</bitWidth> 11906 <enumeratedValues> 11907 <enumeratedValue> 11908 <name>lo</name> 11909 <description>Active Low.</description> 11910 <value>0</value> 11911 </enumeratedValue> 11912 <enumeratedValue> 11913 <name>hi</name> 11914 <description>Active High.</description> 11915 <value>1</value> 11916 </enumeratedValue> 11917 </enumeratedValues> 11918 </field> 11919 <field> 11920 <name>FCPOL</name> 11921 <description>FC Polarity.</description> 11922 <bitOffset>8</bitOffset> 11923 <bitWidth>1</bitWidth> 11924 <enumeratedValues> 11925 <enumeratedValue> 11926 <name>lo</name> 11927 <description>Active Low.</description> 11928 <value>0</value> 11929 </enumeratedValue> 11930 <enumeratedValue> 11931 <name>hi</name> 11932 <description>Active High.</description> 11933 <value>1</value> 11934 </enumeratedValue> 11935 </enumeratedValues> 11936 </field> 11937 </fields> 11938 </register> 11939 <register> 11940 <name>CTRL1</name> 11941 <description>SPIX Controller General Controller Register.</description> 11942 <addressOffset>0x08</addressOffset> 11943 <fields> 11944 <field> 11945 <name>EN</name> 11946 <description>SPI Master enable.</description> 11947 <bitOffset>0</bitOffset> 11948 <bitWidth>1</bitWidth> 11949 <enumeratedValues> 11950 <enumeratedValue> 11951 <name>dis</name> 11952 <description>Disable SPI Master, putting a reset state.</description> 11953 <value>0</value> 11954 </enumeratedValue> 11955 <enumeratedValue> 11956 <name>en</name> 11957 <description>Enable SPI Master for processing transactions.</description> 11958 <value>1</value> 11959 </enumeratedValue> 11960 </enumeratedValues> 11961 </field> 11962 <field> 11963 <name>TX_FIFO_EN</name> 11964 <description>Transaction FIFO Enable.</description> 11965 <bitOffset>1</bitOffset> 11966 <bitWidth>1</bitWidth> 11967 <enumeratedValues> 11968 <enumeratedValue> 11969 <name>dis_txfifo</name> 11970 <description>Disable Transaction FIFO.</description> 11971 <value>0</value> 11972 </enumeratedValue> 11973 <enumeratedValue> 11974 <name>en_txfifo</name> 11975 <description>Enable Transaction FIFO.</description> 11976 <value>1</value> 11977 </enumeratedValue> 11978 </enumeratedValues> 11979 </field> 11980 <field> 11981 <name>RX_FIFO_EN</name> 11982 <description>Result FIFO Enable.</description> 11983 <bitOffset>2</bitOffset> 11984 <bitWidth>1</bitWidth> 11985 <enumeratedValues> 11986 <enumeratedValue> 11987 <name>DIS_RXFIFO</name> 11988 <description>Disable Result FIFO.</description> 11989 <value>0</value> 11990 </enumeratedValue> 11991 <enumeratedValue> 11992 <name>EN_RXFIFO</name> 11993 <description>Enable Result FIFO.</description> 11994 <value>1</value> 11995 </enumeratedValue> 11996 </enumeratedValues> 11997 </field> 11998 <field> 11999 <name>BB_EN</name> 12000 <description>Bit-Bang Mode.</description> 12001 <bitOffset>3</bitOffset> 12002 <bitWidth>1</bitWidth> 12003 <enumeratedValues> 12004 <enumeratedValue> 12005 <name>dis</name> 12006 <description>Disable Bit-Bang Mode.</description> 12007 <value>0</value> 12008 </enumeratedValue> 12009 <enumeratedValue> 12010 <name>en</name> 12011 <description>Enable Bit-Bang Mode.</description> 12012 <value>1</value> 12013 </enumeratedValue> 12014 </enumeratedValues> 12015 </field> 12016 <field> 12017 <name>SSDR</name> 12018 <description>This bits reflects the state of the currently selected slave select.</description> 12019 <bitOffset>4</bitOffset> 12020 <bitWidth>1</bitWidth> 12021 <enumeratedValues> 12022 <enumeratedValue> 12023 <name>output0</name> 12024 <description>Selected Slave select output = 0.</description> 12025 <value>0</value> 12026 </enumeratedValue> 12027 <enumeratedValue> 12028 <name>output1</name> 12029 <description>Selected Slave select output = 1.</description> 12030 <value>1</value> 12031 </enumeratedValue> 12032 </enumeratedValues> 12033 </field> 12034 <field> 12035 <name>FCDR</name> 12036 <description>This bits reflects the state of the selected FC.</description> 12037 <bitOffset>5</bitOffset> 12038 <bitWidth>1</bitWidth> 12039 </field> 12040 <field> 12041 <name>SCLKDR</name> 12042 <description>SCLK Drive and State.</description> 12043 <bitOffset>6</bitOffset> 12044 <bitWidth>1</bitWidth> 12045 <enumeratedValues> 12046 <enumeratedValue> 12047 <name>SCLK_0</name> 12048 <description>SCLK is 0.</description> 12049 <value>0</value> 12050 </enumeratedValue> 12051 <enumeratedValue> 12052 <name>SCLK_1</name> 12053 <description>SCLK is 1.</description> 12054 <value>1</value> 12055 </enumeratedValue> 12056 </enumeratedValues> 12057 </field> 12058 <field> 12059 <name>SDIO_DATA_IN</name> 12060 <description>SDIO Input Data Value.</description> 12061 <bitOffset>8</bitOffset> 12062 <bitWidth>4</bitWidth> 12063 <enumeratedValues> 12064 <enumeratedValue> 12065 <name>SDIO0</name> 12066 <description>SDIO[0]</description> 12067 <value>0</value> 12068 </enumeratedValue> 12069 <enumeratedValue> 12070 <name>SDIO1</name> 12071 <description>SDIO[1]</description> 12072 <value>1</value> 12073 </enumeratedValue> 12074 <enumeratedValue> 12075 <name>SDIO2</name> 12076 <description>SDIO[2]</description> 12077 <value>2</value> 12078 </enumeratedValue> 12079 <enumeratedValue> 12080 <name>SDIO3</name> 12081 <description>SDIO[3]</description> 12082 <value>3</value> 12083 </enumeratedValue> 12084 </enumeratedValues> 12085 </field> 12086 <field> 12087 <name>BB_DATA_OUT</name> 12088 <description>Bit Bang SDIO Output.</description> 12089 <bitOffset>12</bitOffset> 12090 <bitWidth>4</bitWidth> 12091 <enumeratedValues> 12092 <enumeratedValue> 12093 <name>SDIO0</name> 12094 <description>SDIO[0]</description> 12095 <value>0</value> 12096 </enumeratedValue> 12097 <enumeratedValue> 12098 <name>SDIO1</name> 12099 <description>SDIO[1]</description> 12100 <value>1</value> 12101 </enumeratedValue> 12102 <enumeratedValue> 12103 <name>SDIO2</name> 12104 <description>SDIO[2]</description> 12105 <value>2</value> 12106 </enumeratedValue> 12107 <enumeratedValue> 12108 <name>SDIO3</name> 12109 <description>SDIO[3]</description> 12110 <value>3</value> 12111 </enumeratedValue> 12112 </enumeratedValues> 12113 </field> 12114 <field> 12115 <name>BB_DATA_OUT_EN</name> 12116 <description>Bit Bang SDIO Output Enable.</description> 12117 <bitOffset>16</bitOffset> 12118 <bitWidth>4</bitWidth> 12119 <enumeratedValues> 12120 <enumeratedValue> 12121 <name>SDIO0</name> 12122 <description>SDIO[0]</description> 12123 <value>0</value> 12124 </enumeratedValue> 12125 <enumeratedValue> 12126 <name>SDIO1</name> 12127 <description>SDIO[1]</description> 12128 <value>1</value> 12129 </enumeratedValue> 12130 <enumeratedValue> 12131 <name>SDIO2</name> 12132 <description>SDIO[2]</description> 12133 <value>2</value> 12134 </enumeratedValue> 12135 <enumeratedValue> 12136 <name>SDIO3</name> 12137 <description>SDIO[3]</description> 12138 <value>3</value> 12139 </enumeratedValue> 12140 </enumeratedValues> 12141 </field> 12142 <field> 12143 <name>SIMPLE_EN</name> 12144 <description>Simple Mode Enable.</description> 12145 <bitOffset>20</bitOffset> 12146 <bitWidth>1</bitWidth> 12147 </field> 12148 <field> 12149 <name>SIMPLE_RX</name> 12150 <description>Simple Receive Enable.</description> 12151 <bitOffset>21</bitOffset> 12152 <bitWidth>1</bitWidth> 12153 </field> 12154 <field> 12155 <name>SIMPLE_SS</name> 12156 <description>Simple Mode Slave Select.</description> 12157 <bitOffset>22</bitOffset> 12158 <bitWidth>1</bitWidth> 12159 </field> 12160 <field> 12161 <name>SCLK_FB</name> 12162 <description>Enable SCLK Feedback Mode.</description> 12163 <bitOffset>24</bitOffset> 12164 <bitWidth>1</bitWidth> 12165 <enumeratedValues> 12166 <enumeratedValue> 12167 <name>Dis</name> 12168 <value>0</value> 12169 </enumeratedValue> 12170 <enumeratedValue> 12171 <name>En</name> 12172 <value>1</value> 12173 </enumeratedValue> 12174 </enumeratedValues> 12175 </field> 12176 <field> 12177 <name>SCLK_FB_INV</name> 12178 <description>SCK Invert.</description> 12179 <bitOffset>25</bitOffset> 12180 <bitWidth>1</bitWidth> 12181 </field> 12182 </fields> 12183 </register> 12184 <register> 12185 <name>CTRL2</name> 12186 <description>SPIX Controller FIFO Control and Status Register.</description> 12187 <addressOffset>0x0C</addressOffset> 12188 <fields> 12189 <field> 12190 <name>TX_AE_LVL</name> 12191 <description>Transaction FIFO Almost Empty Level.</description> 12192 <bitOffset>0</bitOffset> 12193 <bitWidth>4</bitWidth> 12194 </field> 12195 <field> 12196 <name>TX_CNT</name> 12197 <description>Transaction FIFO Used.</description> 12198 <bitOffset>8</bitOffset> 12199 <bitWidth>5</bitWidth> 12200 </field> 12201 <field> 12202 <name>RX_AF_LVL</name> 12203 <description>Results FIFO Almost Full Level.</description> 12204 <bitOffset>16</bitOffset> 12205 <bitWidth>5</bitWidth> 12206 </field> 12207 <field> 12208 <name>RX_CNT</name> 12209 <description>Result FIFO Used.</description> 12210 <bitOffset>24</bitOffset> 12211 <bitWidth>6</bitWidth> 12212 </field> 12213 </fields> 12214 </register> 12215 <register> 12216 <name>CTRL3</name> 12217 <description>SPIX Controller Special Control Register.</description> 12218 <addressOffset>0x10</addressOffset> 12219 <fields> 12220 <field> 12221 <name>SAMPLE</name> 12222 <description>Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must 12223 only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the 12224 next slave select assertion.</description> 12225 <bitOffset>0</bitOffset> 12226 <bitWidth>1</bitWidth> 12227 </field> 12228 <field> 12229 <name>MISO_FC_EN</name> 12230 <description>MISO FC Enable.</description> 12231 <bitOffset>1</bitOffset> 12232 <bitWidth>1</bitWidth> 12233 </field> 12234 <field> 12235 <name>SDIO_OUT_VAL</name> 12236 <description>SDIO Output Value Sample Mode</description> 12237 <bitOffset>4</bitOffset> 12238 <bitWidth>4</bitWidth> 12239 </field> 12240 <field> 12241 <name>SDIO_OUT_EN</name> 12242 <description>SDIO Output Enable Sample Mode</description> 12243 <bitOffset>8</bitOffset> 12244 <bitWidth>4</bitWidth> 12245 </field> 12246 <field> 12247 <name>SCLKINH3</name> 12248 <description>SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams.</description> 12249 <bitOffset>16</bitOffset> 12250 <bitWidth>1</bitWidth> 12251 <enumeratedValues> 12252 <enumeratedValue> 12253 <name>EN</name> 12254 <description>Allow trailing SCLK low pulse prior to Slave Select de-assertion.</description> 12255 <value>0</value> 12256 </enumeratedValue> 12257 <enumeratedValue> 12258 <name>DIS</name> 12259 <description>Inhibit trailing SCLK low pulse prior to Slave Select de-assertion.</description> 12260 <value>1</value> 12261 </enumeratedValue> 12262 </enumeratedValues> 12263 </field> 12264 </fields> 12265 </register> 12266 <register> 12267 <name>INTFL</name> 12268 <description>SPIX Controller Interrupt Status Register.</description> 12269 <addressOffset>0x14</addressOffset> 12270 <fields> 12271 <field> 12272 <name>TX_STALLED</name> 12273 <description>Transaction Stalled Interrupt Flag.</description> 12274 <bitOffset>0</bitOffset> 12275 <bitWidth>1</bitWidth> 12276 <enumeratedValues> 12277 <enumeratedValue> 12278 <name>CLR</name> 12279 <description>Normal FIFO Transaction.</description> 12280 <value>0</value> 12281 </enumeratedValue> 12282 <enumeratedValue> 12283 <name>SET</name> 12284 <description>Stalled FIFO Transaction.</description> 12285 <value>1</value> 12286 </enumeratedValue> 12287 </enumeratedValues> 12288 </field> 12289 <field> 12290 <name>RX_STALLED</name> 12291 <description>Results Stalled Interrupt Flag.</description> 12292 <bitOffset>1</bitOffset> 12293 <bitWidth>1</bitWidth> 12294 <enumeratedValues> 12295 <enumeratedValue> 12296 <name>CLR</name> 12297 <description>Normal FIFO Operation.</description> 12298 <value>0</value> 12299 </enumeratedValue> 12300 <enumeratedValue> 12301 <name>SET</name> 12302 <description>Stalled FIFO.</description> 12303 <value>1</value> 12304 </enumeratedValue> 12305 </enumeratedValues> 12306 </field> 12307 <field> 12308 <name>TX_RDY</name> 12309 <description>Transaction Ready Interrupt Status.</description> 12310 <bitOffset>2</bitOffset> 12311 <bitWidth>1</bitWidth> 12312 <enumeratedValues> 12313 <enumeratedValue> 12314 <name>CLR</name> 12315 <description>FIFO Transaction not ready.</description> 12316 <value>0</value> 12317 </enumeratedValue> 12318 <enumeratedValue> 12319 <name>SET</name> 12320 <description>FIFO Transaction ready.</description> 12321 <value>1</value> 12322 </enumeratedValue> 12323 </enumeratedValues> 12324 </field> 12325 <field> 12326 <name>RX_DONE</name> 12327 <description>Results Done Interrupt Status.</description> 12328 <bitOffset>3</bitOffset> 12329 <bitWidth>1</bitWidth> 12330 <enumeratedValues> 12331 <enumeratedValue> 12332 <name>CLR</name> 12333 <description>Results FIFO ready.</description> 12334 <value>0</value> 12335 </enumeratedValue> 12336 <enumeratedValue> 12337 <name>SET</name> 12338 <description>Results FIFO Not ready.</description> 12339 <value>1</value> 12340 </enumeratedValue> 12341 </enumeratedValues> 12342 </field> 12343 <field> 12344 <name>TX_AE</name> 12345 <description>Transaction FIFO Almost Empty Flag.</description> 12346 <bitOffset>4</bitOffset> 12347 <bitWidth>1</bitWidth> 12348 <enumeratedValues> 12349 <enumeratedValue> 12350 <name>CLR</name> 12351 <description>Transaction FIFO not Almost Empty.</description> 12352 <value>0</value> 12353 </enumeratedValue> 12354 <enumeratedValue> 12355 <name>SET</name> 12356 <description>Transaction FIFO Almost Empty.</description> 12357 <value>1</value> 12358 </enumeratedValue> 12359 </enumeratedValues> 12360 </field> 12361 <field> 12362 <name>RX_AF</name> 12363 <description>Results FIFO Almost Full Flag.</description> 12364 <bitOffset>5</bitOffset> 12365 <bitWidth>1</bitWidth> 12366 <enumeratedValues> 12367 <enumeratedValue> 12368 <name>CLR</name> 12369 <description>Results FIFO level below the Almost Full level.</description> 12370 <value>0</value> 12371 </enumeratedValue> 12372 <enumeratedValue> 12373 <name>SET</name> 12374 <description>Results FIFO level at Almost Full level.</description> 12375 <value>1</value> 12376 </enumeratedValue> 12377 </enumeratedValues> 12378 </field> 12379 </fields> 12380 </register> 12381 <register> 12382 <name>INTEN</name> 12383 <description>SPIX Controller Interrupt Enable Register.</description> 12384 <addressOffset>0x18</addressOffset> 12385 <fields> 12386 <field> 12387 <name>TX_STALLED</name> 12388 <description>Transaction Stalled Interrupt Enable.</description> 12389 <bitOffset>0</bitOffset> 12390 <bitWidth>1</bitWidth> 12391 <enumeratedValues> 12392 <enumeratedValue> 12393 <name>EN</name> 12394 <description>Disable Transaction Stalled Interrupt.</description> 12395 <value>0</value> 12396 </enumeratedValue> 12397 <enumeratedValue> 12398 <name>DIS</name> 12399 <description>Enable Transaction Stalled Interrupt.</description> 12400 <value>1</value> 12401 </enumeratedValue> 12402 </enumeratedValues> 12403 </field> 12404 <field> 12405 <name>RX_STALLED</name> 12406 <description>Results Stalled Interrupt Enable.</description> 12407 <bitOffset>1</bitOffset> 12408 <bitWidth>1</bitWidth> 12409 <enumeratedValues> 12410 <enumeratedValue> 12411 <name>EN</name> 12412 <description>Disable Results Stalled Interrupt.</description> 12413 <value>0</value> 12414 </enumeratedValue> 12415 <enumeratedValue> 12416 <name>DIS</name> 12417 <description>Enable Results Stalled Interrupt.</description> 12418 <value>1</value> 12419 </enumeratedValue> 12420 </enumeratedValues> 12421 </field> 12422 <field> 12423 <name>TX_RDY</name> 12424 <description>Transaction Ready Interrupt Enable.</description> 12425 <bitOffset>2</bitOffset> 12426 <bitWidth>1</bitWidth> 12427 <enumeratedValues> 12428 <enumeratedValue> 12429 <name>EN</name> 12430 <description>Disable FIFO Transaction Ready Interrupt.</description> 12431 <value>0</value> 12432 </enumeratedValue> 12433 <enumeratedValue> 12434 <name>DIS</name> 12435 <description>Enable FIFO Transaction Ready Interrupt.</description> 12436 <value>1</value> 12437 </enumeratedValue> 12438 </enumeratedValues> 12439 </field> 12440 <field> 12441 <name>RX_DONE</name> 12442 <description>Results Done Interrupt Enable.</description> 12443 <bitOffset>3</bitOffset> 12444 <bitWidth>1</bitWidth> 12445 <enumeratedValues> 12446 <enumeratedValue> 12447 <name>EN</name> 12448 <description>Disable Results Done Interrupt.</description> 12449 <value>0</value> 12450 </enumeratedValue> 12451 <enumeratedValue> 12452 <name>DIS</name> 12453 <description>Enable Results Done Interrupt.</description> 12454 <value>1</value> 12455 </enumeratedValue> 12456 </enumeratedValues> 12457 </field> 12458 <field> 12459 <name>TX_AE</name> 12460 <description>Transaction FIFO Almost Empty Interrupt Enable.</description> 12461 <bitOffset>4</bitOffset> 12462 <bitWidth>1</bitWidth> 12463 <enumeratedValues> 12464 <enumeratedValue> 12465 <name>EN</name> 12466 <description>Disable Transaction FIFO Almost Empty Interrupt.</description> 12467 <value>0</value> 12468 </enumeratedValue> 12469 <enumeratedValue> 12470 <name>DIS</name> 12471 <description>Enable Transaction FIFO Almost Empty Interrupt.</description> 12472 <value>1</value> 12473 </enumeratedValue> 12474 </enumeratedValues> 12475 </field> 12476 <field> 12477 <name>RX_AF</name> 12478 <description>Results FIFO Almost Full Interrupt Enable.</description> 12479 <bitOffset>5</bitOffset> 12480 <bitWidth>1</bitWidth> 12481 <enumeratedValues> 12482 <enumeratedValue> 12483 <name>EN</name> 12484 <description>Disable Results FIFO Almost Full Interrupt.</description> 12485 <value>0</value> 12486 </enumeratedValue> 12487 <enumeratedValue> 12488 <name>DIS</name> 12489 <description>Enable Results FIFO Almost Full Interrupt.</description> 12490 <value>1</value> 12491 </enumeratedValue> 12492 </enumeratedValues> 12493 </field> 12494 </fields> 12495 </register> 12496 <register> 12497 <name>HEADER</name> 12498 <description>Simple Header</description> 12499 <addressOffset>0x1C</addressOffset> 12500 <fields> 12501 <field> 12502 <name>TX_BIDIR</name> 12503 <description>TX Bdirectional Header.</description> 12504 <bitOffset>0</bitOffset> 12505 <bitWidth>14</bitWidth> 12506 </field> 12507 <field> 12508 <name>RX_ONLY</name> 12509 <description>RX Only Header.</description> 12510 <bitOffset>16</bitOffset> 12511 <bitWidth>14</bitWidth> 12512 </field> 12513 </fields> 12514 </register> 12515 <register> 12516 <name>AUTOCTRL</name> 12517 <description>Auto Control Register.</description> 12518 <addressOffset>0x20</addressOffset> 12519 </register> 12520 <register> 12521 <name>AUTOCMD</name> 12522 <description>Auto Command Register.</description> 12523 <addressOffset>0x24</addressOffset> 12524 </register> 12525 </registers> 12526 </peripheral> 12527<!--SPIXFC SPI XiP Flash Configuration Controller--> 12528 <peripheral> 12529 <name>SPIXFC_FIFO</name> 12530 <description>SPI XiP Master Controller FIFO.</description> 12531 <baseAddress>0x400BC000</baseAddress> 12532 <addressBlock> 12533 <offset>0</offset> 12534 <size>0x1000</size> 12535 <usage>registers</usage> 12536 </addressBlock> 12537 <registers> 12538 <register> 12539 <name>TX_8</name> 12540 <description>SPI TX FIFO 8-Bit Write</description> 12541 <addressOffset>0x00</addressOffset> 12542 <size>8</size> 12543 <dataType>uint8_t</dataType> 12544 </register> 12545 <register> 12546 <name>TX_16</name> 12547 <description>SPI TX FIFO 16-Bit Write</description> 12548 <alternateRegister>TX_8</alternateRegister> 12549 <addressOffset>0x00</addressOffset> 12550 <size>16</size> 12551 <dataType>uint16_t</dataType> 12552 </register> 12553 <register> 12554 <name>TX_32</name> 12555 <description>SPI TX FIFO 32-Bit Write</description> 12556 <alternateRegister>TX_8</alternateRegister> 12557 <addressOffset>0x00</addressOffset> 12558 <size>32</size> 12559 <dataType>uint32_t</dataType> 12560 </register> 12561 <register> 12562 <name>RX_8</name> 12563 <description>SPI RX FIFO 8-Bit Access</description> 12564 <addressOffset>0x04</addressOffset> 12565 <size>8</size> 12566 <dataType>uint8_t</dataType> 12567 </register> 12568 <register> 12569 <name>RX_16</name> 12570 <description>SPI RX FIFO 16-Bit Access</description> 12571 <alternateRegister>RX_8</alternateRegister> 12572 <addressOffset>0x04</addressOffset> 12573 <size>16</size> 12574 <dataType>uint16_t</dataType> 12575 </register> 12576 <register> 12577 <name>RX_32</name> 12578 <description>SPI RX FIFO 32-Bit Access</description> 12579 <alternateRegister>RX_8</alternateRegister> 12580 <addressOffset>0x04</addressOffset> 12581 <size>32</size> 12582 <dataType>uint32_t</dataType> 12583 </register> 12584 </registers> 12585 </peripheral> 12586<!--SPIXFC_FIFO SPI XiP Master Controller FIFO.--> 12587 <peripheral> 12588 <name>SPIXFM</name> 12589 <description>SPIXF Master</description> 12590 <baseAddress>0x40026000</baseAddress> 12591 <addressBlock> 12592 <offset>0x00</offset> 12593 <size>0x1000</size> 12594 <usage>registers</usage> 12595 </addressBlock> 12596 <registers> 12597 <register> 12598 <name>CTRL</name> 12599 <description>SPIX Control Register.</description> 12600 <addressOffset>0x00</addressOffset> 12601 <fields> 12602 <field> 12603 <name>MODE</name> 12604 <description>Defines SPI Mode, Only valid values are 0 and 3.</description> 12605 <bitOffset>0</bitOffset> 12606 <bitWidth>2</bitWidth> 12607 <enumeratedValues> 12608 <enumeratedValue> 12609 <name>SCLK_HI_SAMPLE_RISING</name> 12610 <description>Description not available.</description> 12611 <value>0</value> 12612 </enumeratedValue> 12613 <enumeratedValue> 12614 <name>SCLK_LO_SAMPLE_FAILLING</name> 12615 <description>Description not available.</description> 12616 <value>3</value> 12617 </enumeratedValue> 12618 </enumeratedValues> 12619 </field> 12620 <field> 12621 <name>SSPOL</name> 12622 <description>Slave Select Polarity.</description> 12623 <bitOffset>2</bitOffset> 12624 <bitWidth>1</bitWidth> 12625 <enumeratedValues> 12626 <enumeratedValue> 12627 <name>ACTIVE_HIGH</name> 12628 <description>Slave Select is Active High.</description> 12629 <value>0</value> 12630 </enumeratedValue> 12631 <enumeratedValue> 12632 <name>ACTIVE_LOW</name> 12633 <description>Slave Select is Active Low.</description> 12634 <value>1</value> 12635 </enumeratedValue> 12636 </enumeratedValues> 12637 </field> 12638 <field> 12639 <name>SSEL</name> 12640 <description>Slave Select. Only valid value is zero.</description> 12641 <bitOffset>4</bitOffset> 12642 <bitWidth>3</bitWidth> 12643 </field> 12644 <field> 12645 <name>LOCLK</name> 12646 <description>Number of system clocks that SCLK will be low when SCLK pulses are generated.</description> 12647 <bitOffset>8</bitOffset> 12648 <bitWidth>4</bitWidth> 12649 </field> 12650 <field> 12651 <name>HICLK</name> 12652 <description>Number of system clocks that SCLK will be high when SCLK pulses are generated.</description> 12653 <bitOffset>12</bitOffset> 12654 <bitWidth>4</bitWidth> 12655 </field> 12656 <field> 12657 <name>SSACT</name> 12658 <description>Slave Select Active Timing.</description> 12659 <bitOffset>16</bitOffset> 12660 <bitWidth>2</bitWidth> 12661 <enumeratedValues> 12662 <enumeratedValue> 12663 <name>off</name> 12664 <description>0 system clocks.</description> 12665 <value>0</value> 12666 </enumeratedValue> 12667 <enumeratedValue> 12668 <name>for_2_mod_clk</name> 12669 <description>2 System clocks.</description> 12670 <value>1</value> 12671 </enumeratedValue> 12672 <enumeratedValue> 12673 <name>for_4_mod_clk</name> 12674 <description>4 System clocks.</description> 12675 <value>2</value> 12676 </enumeratedValue> 12677 <enumeratedValue> 12678 <name>for_8_mod_clk</name> 12679 <description>8 System clocks.</description> 12680 <value>3</value> 12681 </enumeratedValue> 12682 </enumeratedValues> 12683 </field> 12684 <field> 12685 <name>SSINACT</name> 12686 <description>Slave Select Inactive Timing.</description> 12687 <bitOffset>18</bitOffset> 12688 <bitWidth>2</bitWidth> 12689 <enumeratedValues> 12690 <enumeratedValue> 12691 <name>for_1_mod_clk</name> 12692 <description>1 system clocks.</description> 12693 <value>0</value> 12694 </enumeratedValue> 12695 <enumeratedValue> 12696 <name>for_3_mod_clk</name> 12697 <description>3 System clocks.</description> 12698 <value>1</value> 12699 </enumeratedValue> 12700 <enumeratedValue> 12701 <name>for_5_mod_clk</name> 12702 <description>5 System clocks.</description> 12703 <value>2</value> 12704 </enumeratedValue> 12705 <enumeratedValue> 12706 <name>for_9_mod_clk</name> 12707 <description>9 System clocks.</description> 12708 <value>3</value> 12709 </enumeratedValue> 12710 </enumeratedValues> 12711 </field> 12712 </fields> 12713 </register> 12714 <register> 12715 <name>FETCHCTRL</name> 12716 <description>SPIX Fetch Control Register.</description> 12717 <addressOffset>0x04</addressOffset> 12718 <fields> 12719 <field> 12720 <name>CMD_VAL</name> 12721 <description>Command Value sent to target to initiate fetching from SPI flash.</description> 12722 <bitOffset>0</bitOffset> 12723 <bitWidth>8</bitWidth> 12724 </field> 12725 <field> 12726 <name>CMD_WDTH</name> 12727 <description>Command Width. Number of data I/O used to send commands.</description> 12728 <bitOffset>8</bitOffset> 12729 <bitWidth>2</bitWidth> 12730 <enumeratedValues> 12731 <enumeratedValue> 12732 <name>Single</name> 12733 <description>Single SDIO.</description> 12734 <value>0</value> 12735 </enumeratedValue> 12736 <enumeratedValue> 12737 <name>Dual_IO</name> 12738 <description>Dual SDIO.</description> 12739 <value>1</value> 12740 </enumeratedValue> 12741 <enumeratedValue> 12742 <name>Quad_IO</name> 12743 <description>Quad SDIO.</description> 12744 <value>2</value> 12745 </enumeratedValue> 12746 <enumeratedValue> 12747 <name>Invalid</name> 12748 <description>Invalid.</description> 12749 <value>3</value> 12750 </enumeratedValue> 12751 </enumeratedValues> 12752 </field> 12753 <field> 12754 <name>ADDR_WDTH</name> 12755 <description>Address Width. Number of data I/O used to send address, and mode/dummy clocks.</description> 12756 <bitOffset>10</bitOffset> 12757 <bitWidth>2</bitWidth> 12758 <enumeratedValues> 12759 <enumeratedValue> 12760 <name>Single</name> 12761 <description>Single SDIO.</description> 12762 <value>0</value> 12763 </enumeratedValue> 12764 <enumeratedValue> 12765 <name>Dual_IO</name> 12766 <description>Dual SDIO.</description> 12767 <value>1</value> 12768 </enumeratedValue> 12769 <enumeratedValue> 12770 <name>Quad_IO</name> 12771 <description>Quad SDIO.</description> 12772 <value>2</value> 12773 </enumeratedValue> 12774 <enumeratedValue> 12775 <name>Invalid</name> 12776 <description>Invalid.</description> 12777 <value>3</value> 12778 </enumeratedValue> 12779 </enumeratedValues> 12780 </field> 12781 <field> 12782 <name>DATA_WDTH</name> 12783 <description>Data Width. Number of data I/O used to receive data.</description> 12784 <bitOffset>12</bitOffset> 12785 <bitWidth>2</bitWidth> 12786 <enumeratedValues> 12787 <enumeratedValue> 12788 <name>Single</name> 12789 <description>Single SDIO.</description> 12790 <value>0</value> 12791 </enumeratedValue> 12792 <enumeratedValue> 12793 <name>Dual_IO</name> 12794 <description>Dual SDIO.</description> 12795 <value>1</value> 12796 </enumeratedValue> 12797 <enumeratedValue> 12798 <name>Quad_IO</name> 12799 <description>Quad SDIO.</description> 12800 <value>2</value> 12801 </enumeratedValue> 12802 <enumeratedValue> 12803 <name>Invalid</name> 12804 <description>Invalid.</description> 12805 <value>3</value> 12806 </enumeratedValue> 12807 </enumeratedValues> 12808 </field> 12809 <field> 12810 <name>4BADDR</name> 12811 <description>Four Byte Address Mode. Enables 4-byte Flash Address Mode.</description> 12812 <bitOffset>16</bitOffset> 12813 <bitWidth>1</bitWidth> 12814 <enumeratedValues> 12815 <enumeratedValue> 12816 <name>3</name> 12817 <description>3 Byte Address Mode.</description> 12818 <value>0</value> 12819 </enumeratedValue> 12820 <enumeratedValue> 12821 <name>4</name> 12822 <description>4 Byte Address Mode.</description> 12823 <value>1</value> 12824 </enumeratedValue> 12825 </enumeratedValues> 12826 </field> 12827 </fields> 12828 </register> 12829 <register> 12830 <name>MODECTRL</name> 12831 <description>SPIX Mode Control Register.</description> 12832 <addressOffset>0x08</addressOffset> 12833 <fields> 12834 <field> 12835 <name>MDCLK</name> 12836 <description>Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch.</description> 12837 <bitOffset>0</bitOffset> 12838 <bitWidth>4</bitWidth> 12839 </field> 12840 <field> 12841 <name>NOCMD</name> 12842 <description>No Command Mode.</description> 12843 <bitOffset>8</bitOffset> 12844 <bitWidth>1</bitWidth> 12845 <enumeratedValues> 12846 <enumeratedValue> 12847 <name>always</name> 12848 <description>Send read command every time SPI transaction is initiated.</description> 12849 <value>0</value> 12850 </enumeratedValue> 12851 <enumeratedValue> 12852 <name>once</name> 12853 <description>Send read command only once. NO read command in subsequent SPI transactions.</description> 12854 <value>1</value> 12855 </enumeratedValue> 12856 </enumeratedValues> 12857 </field> 12858 <field> 12859 <name>EXIT_NOCMD</name> 12860 <description>Mode Send.</description> 12861 <bitOffset>9</bitOffset> 12862 <bitWidth>1</bitWidth> 12863 </field> 12864 </fields> 12865 </register> 12866 <register> 12867 <name>MODEDATA</name> 12868 <description>SPIX Mode Data Register.</description> 12869 <addressOffset>0x0C</addressOffset> 12870 <fields> 12871 <field> 12872 <name>DATA</name> 12873 <description>Mode Data. Specifies the data to send with the Dummy/Mode clocks.</description> 12874 <bitOffset>0</bitOffset> 12875 <bitWidth>16</bitWidth> 12876 </field> 12877 <field> 12878 <name>OUT_EN</name> 12879 <description>Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA.</description> 12880 <bitOffset>16</bitOffset> 12881 <bitWidth>16</bitWidth> 12882 </field> 12883 </fields> 12884 </register> 12885 <register> 12886 <name>FBCTRL</name> 12887 <description>SPIX Feedback Control Register.</description> 12888 <addressOffset>0x10</addressOffset> 12889 <fields> 12890 <field> 12891 <name>EN</name> 12892 <description>Enable SCLK feedback mode.</description> 12893 <bitOffset>0</bitOffset> 12894 <bitWidth>1</bitWidth> 12895 <enumeratedValues> 12896 <enumeratedValue> 12897 <name>dis</name> 12898 <description>Disable SCLK feedback mode.</description> 12899 <value>0</value> 12900 </enumeratedValue> 12901 <enumeratedValue> 12902 <name>en</name> 12903 <description>Enable SCLK feedback mode.</description> 12904 <value>1</value> 12905 </enumeratedValue> 12906 </enumeratedValues> 12907 </field> 12908 <field> 12909 <name>INVERT</name> 12910 <description>Invert SCLK in feedback mode.</description> 12911 <bitOffset>1</bitOffset> 12912 <bitWidth>1</bitWidth> 12913 <enumeratedValues> 12914 <enumeratedValue> 12915 <name>dis</name> 12916 <description>Disable Invert SCLK feedback mode.</description> 12917 <value>0</value> 12918 </enumeratedValue> 12919 <enumeratedValue> 12920 <name>en</name> 12921 <description>Enable Invert SCLK feedback mode.</description> 12922 <value>1</value> 12923 </enumeratedValue> 12924 </enumeratedValues> 12925 </field> 12926 </fields> 12927 </register> 12928 <register> 12929 <name>IOCTRL</name> 12930 <description>SPIX IO Control Register.</description> 12931 <addressOffset>0x1C</addressOffset> 12932 <fields> 12933 <field> 12934 <name>SCLK_DS</name> 12935 <description>SCLK drive Strength. This bit controls the drive strength on the SCLK pin.</description> 12936 <bitOffset>0</bitOffset> 12937 <bitWidth>1</bitWidth> 12938 <enumeratedValues> 12939 <enumeratedValue> 12940 <name>Low</name> 12941 <description>Low drive strength.</description> 12942 <value>0</value> 12943 </enumeratedValue> 12944 <enumeratedValue> 12945 <name>High</name> 12946 <description>High drive strength.</description> 12947 <value>1</value> 12948 </enumeratedValue> 12949 </enumeratedValues> 12950 </field> 12951 <field> 12952 <name>SS_DS</name> 12953 <description>Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin.</description> 12954 <bitOffset>1</bitOffset> 12955 <bitWidth>1</bitWidth> 12956 <enumeratedValues> 12957 <enumeratedValue> 12958 <name>Low</name> 12959 <description>Low drive strength.</description> 12960 <value>0</value> 12961 </enumeratedValue> 12962 <enumeratedValue> 12963 <name>High</name> 12964 <description>High drive strength.</description> 12965 <value>1</value> 12966 </enumeratedValue> 12967 </enumeratedValues> 12968 </field> 12969 <field> 12970 <name>SDIO_DS</name> 12971 <description>SDIO Drive Strength. This bit controls the drive strength of all SDIO pins.</description> 12972 <bitOffset>2</bitOffset> 12973 <bitWidth>1</bitWidth> 12974 <enumeratedValues> 12975 <enumeratedValue> 12976 <name>Low</name> 12977 <description>Low drive strength.</description> 12978 <value>0</value> 12979 </enumeratedValue> 12980 <enumeratedValue> 12981 <name>High</name> 12982 <description>High drive strength.</description> 12983 <value>1</value> 12984 </enumeratedValue> 12985 </enumeratedValues> 12986 </field> 12987 <field> 12988 <name>PADCTRL</name> 12989 <description>IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins.</description> 12990 <bitOffset>3</bitOffset> 12991 <bitWidth>2</bitWidth> 12992 <enumeratedValues> 12993 <enumeratedValue> 12994 <name>tri_state</name> 12995 <description>Tristate.</description> 12996 <value>0</value> 12997 </enumeratedValue> 12998 <enumeratedValue> 12999 <name>Pull_Up</name> 13000 <description>Pull-Up.</description> 13001 <value>1</value> 13002 </enumeratedValue> 13003 <enumeratedValue> 13004 <name>Pull_down</name> 13005 <description>Pull-Down.</description> 13006 <value>2</value> 13007 </enumeratedValue> 13008 </enumeratedValues> 13009 </field> 13010 </fields> 13011 </register> 13012 <register> 13013 <name>MEMSECCTRL</name> 13014 <description>SPIX Memory Security Control Register.</description> 13015 <addressOffset>0x20</addressOffset> 13016 <fields> 13017 <field> 13018 <name>DEC_EN</name> 13019 <description>Decryption Enable.</description> 13020 <bitOffset>0</bitOffset> 13021 <bitWidth>1</bitWidth> 13022 <enumeratedValues> 13023 <enumeratedValue> 13024 <name>dis</name> 13025 <description>Disable decryption of SPIX data.</description> 13026 <value>0</value> 13027 </enumeratedValue> 13028 <enumeratedValue> 13029 <name>en</name> 13030 <description>Enable decryption of SPIX data.</description> 13031 <value>1</value> 13032 </enumeratedValue> 13033 </enumeratedValues> 13034 </field> 13035 <field> 13036 <name>AUTH_DIS</name> 13037 <description>Integrity Enable.</description> 13038 <bitOffset>1</bitOffset> 13039 <bitWidth>1</bitWidth> 13040 <enumeratedValues> 13041 <enumeratedValue> 13042 <name>en</name> 13043 <description>Integrity checking enabled.</description> 13044 <value>0</value> 13045 </enumeratedValue> 13046 <enumeratedValue> 13047 <name>dis</name> 13048 <description>Integrity checking disabled.</description> 13049 <value>1</value> 13050 </enumeratedValue> 13051 </enumeratedValues> 13052 </field> 13053 <field> 13054 <name>CNTOPT_EN</name> 13055 <description>Enable counters optimization (when authentication is enabled).</description> 13056 <bitOffset>2</bitOffset> 13057 <bitWidth>1</bitWidth> 13058 <enumeratedValues> 13059 <enumeratedValue> 13060 <name>dis</name> 13061 <description>Disable counter optimization.</description> 13062 <value>0</value> 13063 </enumeratedValue> 13064 <enumeratedValue> 13065 <name>en</name> 13066 <description>Enable counter optimization.</description> 13067 <value>1</value> 13068 </enumeratedValue> 13069 </enumeratedValues> 13070 </field> 13071 <field> 13072 <name>INTERL_DIS</name> 13073 <description>Disable authenticity interleaving (when authentication is enabled)</description> 13074 <bitOffset>3</bitOffset> 13075 <bitWidth>1</bitWidth> 13076 <enumeratedValues> 13077 <enumeratedValue> 13078 <name>dis</name> 13079 <description>Disable interleaving of SPIX data.</description> 13080 <value>1</value> 13081 </enumeratedValue> 13082 <enumeratedValue> 13083 <name>en</name> 13084 <description>Enable interleaving of SPIX data.</description> 13085 <value>0</value> 13086 </enumeratedValue> 13087 </enumeratedValues> 13088 </field> 13089 <field> 13090 <name>AUTHERR_FL</name> 13091 <description>Authentication Error Flag Bit.</description> 13092 <bitOffset>4</bitOffset> 13093 <bitWidth>1</bitWidth> 13094 </field> 13095 </fields> 13096 </register> 13097 <register> 13098 <name>BUSIDLE</name> 13099 <description>Bus Idle</description> 13100 <addressOffset>0x24</addressOffset> 13101 <fields> 13102 <field> 13103 <name>BUSIDLE</name> 13104 <description>A 16-bit timer will be triggered for each external access. The timer will be 13105 restarted if another access is performed before the timer expires. When the 13106 timer expires, slave select will be deactivated.</description> 13107 <bitOffset>0</bitOffset> 13108 <bitWidth>16</bitWidth> 13109 </field> 13110 </fields> 13111 </register> 13112 <register> 13113 <name>AUTHOFFSET</name> 13114 <description>Auth Offset</description> 13115 <addressOffset>0x28</addressOffset> 13116 </register> 13117 <register> 13118 <name>BYPASS_MODE</name> 13119 <description>Bypass Mode Register.</description> 13120 <addressOffset>0x2C</addressOffset> 13121 <fields> 13122 <field> 13123 <name>EN</name> 13124 <description>Enable bypass.</description> 13125 <bitOffset>0</bitOffset> 13126 <bitWidth>1</bitWidth> 13127 </field> 13128 <field> 13129 <name>FCLK_DELAY</name> 13130 <description>FCLK Delay.</description> 13131 <bitOffset>1</bitOffset> 13132 <bitWidth>3</bitWidth> 13133 <enumeratedValues> 13134 <enumeratedValue> 13135 <name>0_NS</name> 13136 <description>0ns</description> 13137 <value>0</value> 13138 </enumeratedValue> 13139 <enumeratedValue> 13140 <name>0P5_NS</name> 13141 <description>0.5ns</description> 13142 <value>1</value> 13143 </enumeratedValue> 13144 <enumeratedValue> 13145 <name>1P0_NS</name> 13146 <description>1.0ns</description> 13147 <value>2</value> 13148 </enumeratedValue> 13149 <enumeratedValue> 13150 <name>1P5_NS</name> 13151 <description>1.5ns</description> 13152 <value>3</value> 13153 </enumeratedValue> 13154 <enumeratedValue> 13155 <name>2P0_NS</name> 13156 <description>2.0ns</description> 13157 <value>4</value> 13158 </enumeratedValue> 13159 <enumeratedValue> 13160 <name>2P5_NS</name> 13161 <description>2.5ns</description> 13162 <value>5</value> 13163 </enumeratedValue> 13164 <enumeratedValue> 13165 <name>3P0_NS</name> 13166 <description>3.0ns</description> 13167 <value>6</value> 13168 </enumeratedValue> 13169 <enumeratedValue> 13170 <name>3P5_NS</name> 13171 <description>3.0ns</description> 13172 <value>7</value> 13173 </enumeratedValue> 13174 </enumeratedValues> 13175 </field> 13176 <field> 13177 <name>SCLK_DELAY</name> 13178 <description>SCLK Delay.</description> 13179 <bitOffset>4</bitOffset> 13180 <bitWidth>3</bitWidth> 13181 <enumeratedValues> 13182 <enumeratedValue> 13183 <name>0_NS</name> 13184 <description>0ns</description> 13185 <value>0</value> 13186 </enumeratedValue> 13187 <enumeratedValue> 13188 <name>0P5_NS</name> 13189 <description>0.5ns</description> 13190 <value>1</value> 13191 </enumeratedValue> 13192 <enumeratedValue> 13193 <name>1P0_NS</name> 13194 <description>1.0ns</description> 13195 <value>2</value> 13196 </enumeratedValue> 13197 <enumeratedValue> 13198 <name>1P5_NS</name> 13199 <description>1.5ns</description> 13200 <value>3</value> 13201 </enumeratedValue> 13202 <enumeratedValue> 13203 <name>2P0_NS</name> 13204 <description>2.0ns</description> 13205 <value>4</value> 13206 </enumeratedValue> 13207 <enumeratedValue> 13208 <name>2P5_NS</name> 13209 <description>2.5ns</description> 13210 <value>5</value> 13211 </enumeratedValue> 13212 <enumeratedValue> 13213 <name>3P0_NS</name> 13214 <description>3.0ns</description> 13215 <value>6</value> 13216 </enumeratedValue> 13217 <enumeratedValue> 13218 <name>3P5_NS</name> 13219 <description>3.0ns</description> 13220 <value>7</value> 13221 </enumeratedValue> 13222 </enumeratedValues> 13223 </field> 13224 </fields> 13225 </register> 13226 </registers> 13227 </peripheral> 13228<!--SPIXFM SPIXF Master--> 13229 <peripheral> 13230 <name>SPI</name> 13231 <description>SPI peripheral.</description> 13232 <baseAddress>0x40046000</baseAddress> 13233 <addressBlock> 13234 <offset>0x00</offset> 13235 <size>0x1000</size> 13236 <usage>registers</usage> 13237 </addressBlock> 13238 <interrupt> 13239 <name>SPI0</name> 13240 <value>16</value> 13241 </interrupt> 13242 <registers> 13243 <register> 13244 <name>FIFO32</name> 13245 <description>Register for reading and writing the FIFO.</description> 13246 <addressOffset>0x00</addressOffset> 13247 <size>32</size> 13248 <access>read-write</access> 13249 <fields> 13250 <field> 13251 <name>DATA</name> 13252 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 13253 <bitOffset>0</bitOffset> 13254 <bitWidth>32</bitWidth> 13255 </field> 13256 </fields> 13257 </register> 13258 <register> 13259 <dim>2</dim> 13260 <dimIncrement>2</dimIncrement> 13261 <name>FIFO16[%s]</name> 13262 <description>Register for reading and writing the FIFO.</description> 13263 <alternateRegister>FIFO32</alternateRegister> 13264 <addressOffset>0x00</addressOffset> 13265 <size>16</size> 13266 <access>read-write</access> 13267 <fields> 13268 <field> 13269 <name>DATA</name> 13270 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 13271 <bitOffset>0</bitOffset> 13272 <bitWidth>16</bitWidth> 13273 </field> 13274 </fields> 13275 </register> 13276 <register> 13277 <dim>4</dim> 13278 <dimIncrement>1</dimIncrement> 13279 <name>FIFO8[%s]</name> 13280 <description>Register for reading and writing the FIFO.</description> 13281 <alternateRegister>FIFO32</alternateRegister> 13282 <addressOffset>0x00</addressOffset> 13283 <size>8</size> 13284 <access>read-write</access> 13285 <fields> 13286 <field> 13287 <name>DATA</name> 13288 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 13289 <bitOffset>0</bitOffset> 13290 <bitWidth>8</bitWidth> 13291 </field> 13292 </fields> 13293 </register> 13294 <register> 13295 <name>CTRL0</name> 13296 <description>Register for controlling SPI peripheral.</description> 13297 <addressOffset>0x04</addressOffset> 13298 <access>read-write</access> 13299 <fields> 13300 <field> 13301 <name>EN</name> 13302 <description>SPI Enable.</description> 13303 <bitOffset>0</bitOffset> 13304 <bitWidth>1</bitWidth> 13305 <enumeratedValues> 13306 <enumeratedValue> 13307 <name>dis</name> 13308 <description>SPI is disabled.</description> 13309 <value>0</value> 13310 </enumeratedValue> 13311 <enumeratedValue> 13312 <name>en</name> 13313 <description>SPI is enabled.</description> 13314 <value>1</value> 13315 </enumeratedValue> 13316 </enumeratedValues> 13317 </field> 13318 <field> 13319 <name>MST_MODE</name> 13320 <description>Master Mode Enable.</description> 13321 <bitOffset>1</bitOffset> 13322 <bitWidth>1</bitWidth> 13323 <enumeratedValues> 13324 <enumeratedValue> 13325 <name>dis</name> 13326 <description>SPI is Slave mode.</description> 13327 <value>0</value> 13328 </enumeratedValue> 13329 <enumeratedValue> 13330 <name>en</name> 13331 <description>SPI is Master mode.</description> 13332 <value>1</value> 13333 </enumeratedValue> 13334 </enumeratedValues> 13335 </field> 13336 <field> 13337 <name>SS_IO</name> 13338 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 13339 <bitOffset>4</bitOffset> 13340 <bitWidth>1</bitWidth> 13341 <enumeratedValues> 13342 <enumeratedValue> 13343 <name>output</name> 13344 <description>Slave select 0 is output.</description> 13345 <value>0</value> 13346 </enumeratedValue> 13347 <enumeratedValue> 13348 <name>input</name> 13349 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 13350 <value>1</value> 13351 </enumeratedValue> 13352 </enumeratedValues> 13353 </field> 13354 <field> 13355 <name>START</name> 13356 <description>Start Transmit.</description> 13357 <bitOffset>5</bitOffset> 13358 <bitWidth>1</bitWidth> 13359 <enumeratedValues> 13360 <enumeratedValue> 13361 <name>start</name> 13362 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 13363 <value>1</value> 13364 </enumeratedValue> 13365 </enumeratedValues> 13366 </field> 13367 <field> 13368 <name>SS_CTRL</name> 13369 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 13370 <bitOffset>8</bitOffset> 13371 <bitWidth>1</bitWidth> 13372 <enumeratedValues> 13373 <enumeratedValue> 13374 <name>DEASSERT</name> 13375 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 13376 <value>0</value> 13377 </enumeratedValue> 13378 <enumeratedValue> 13379 <name>ASSERT</name> 13380 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 13381 <value>1</value> 13382 </enumeratedValue> 13383 </enumeratedValues> 13384 </field> 13385 <field> 13386 <name>SS_ACTIVE</name> 13387 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 13388 <bitOffset>16</bitOffset> 13389 <bitWidth>4</bitWidth> 13390 <enumeratedValues> 13391 <enumeratedValue> 13392 <name>SS0</name> 13393 <description>SS0 is selected.</description> 13394 <value>0x1</value> 13395 </enumeratedValue> 13396 <enumeratedValue> 13397 <name>SS1</name> 13398 <description>SS1 is selected.</description> 13399 <value>0x2</value> 13400 </enumeratedValue> 13401 <enumeratedValue> 13402 <name>SS2</name> 13403 <description>SS2 is selected.</description> 13404 <value>0x4</value> 13405 </enumeratedValue> 13406 <enumeratedValue> 13407 <name>SS3</name> 13408 <description>SS3 is selected.</description> 13409 <value>0x8</value> 13410 </enumeratedValue> 13411 </enumeratedValues> 13412 </field> 13413 </fields> 13414 </register> 13415 <register> 13416 <name>CTRL1</name> 13417 <description>Register for controlling SPI peripheral.</description> 13418 <addressOffset>0x08</addressOffset> 13419 <access>read-write</access> 13420 <fields> 13421 <field> 13422 <name>TX_NUM_CHAR</name> 13423 <description>Nubmer of Characters to transmit.</description> 13424 <bitOffset>0</bitOffset> 13425 <bitWidth>16</bitWidth> 13426 </field> 13427 <field> 13428 <name>RX_NUM_CHAR</name> 13429 <description>Nubmer of Characters to receive.</description> 13430 <bitOffset>16</bitOffset> 13431 <bitWidth>16</bitWidth> 13432 </field> 13433 </fields> 13434 </register> 13435 <register> 13436 <name>CTRL2</name> 13437 <description>Register for controlling SPI peripheral.</description> 13438 <addressOffset>0x0C</addressOffset> 13439 <access>read-write</access> 13440 <fields> 13441 <field> 13442 <name>CLKPHA</name> 13443 <description>Clock Phase.</description> 13444 <bitOffset>0</bitOffset> 13445 <bitWidth>1</bitWidth> 13446 <enumeratedValues> 13447 <enumeratedValue> 13448 <name>Rising_Edge</name> 13449 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 13450 <value>0</value> 13451 </enumeratedValue> 13452 <enumeratedValue> 13453 <name>Falling_Edge</name> 13454 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 13455 <value>1</value> 13456 </enumeratedValue> 13457 </enumeratedValues> 13458 </field> 13459 <field> 13460 <name>CLKPOL</name> 13461 <description>Clock Polarity.</description> 13462 <bitOffset>1</bitOffset> 13463 <bitWidth>1</bitWidth> 13464 <enumeratedValues> 13465 <enumeratedValue> 13466 <name>Normal</name> 13467 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 13468 <value>0</value> 13469 </enumeratedValue> 13470 <enumeratedValue> 13471 <name>Inverted</name> 13472 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 13473 <value>1</value> 13474 </enumeratedValue> 13475 </enumeratedValues> 13476 </field> 13477 <field> 13478 <name>SCLK_FB_INV</name> 13479 <description>Clock Polarity.</description> 13480 <bitOffset>4</bitOffset> 13481 <bitWidth>1</bitWidth> 13482 <enumeratedValues> 13483 <enumeratedValue> 13484 <name>Normal</name> 13485 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 13486 <value>0</value> 13487 </enumeratedValue> 13488 <enumeratedValue> 13489 <name>Inverted</name> 13490 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 13491 <value>1</value> 13492 </enumeratedValue> 13493 </enumeratedValues> 13494 </field> 13495 <field> 13496 <name>NUMBITS</name> 13497 <description>Number of Bits per character.</description> 13498 <bitOffset>8</bitOffset> 13499 <bitWidth>4</bitWidth> 13500 <enumeratedValues> 13501 <enumeratedValue> 13502 <name>16</name> 13503 <description>16 bits per character.</description> 13504 <value>0</value> 13505 </enumeratedValue> 13506 <enumeratedValue> 13507 <name>1</name> 13508 <description>1 bits per character.</description> 13509 <value>1</value> 13510 </enumeratedValue> 13511 <enumeratedValue> 13512 <name>2</name> 13513 <description>2 bits per character.</description> 13514 <value>2</value> 13515 </enumeratedValue> 13516 <enumeratedValue> 13517 <name>3</name> 13518 <description>3 bits per character.</description> 13519 <value>3</value> 13520 </enumeratedValue> 13521 <enumeratedValue> 13522 <name>4</name> 13523 <description>4 bits per character.</description> 13524 <value>4</value> 13525 </enumeratedValue> 13526 <enumeratedValue> 13527 <name>5</name> 13528 <description>5 bits per character.</description> 13529 <value>5</value> 13530 </enumeratedValue> 13531 <enumeratedValue> 13532 <name>6</name> 13533 <description>6 bits per character.</description> 13534 <value>6</value> 13535 </enumeratedValue> 13536 <enumeratedValue> 13537 <name>7</name> 13538 <description>7 bits per character.</description> 13539 <value>7</value> 13540 </enumeratedValue> 13541 <enumeratedValue> 13542 <name>8</name> 13543 <description>8 bits per character.</description> 13544 <value>8</value> 13545 </enumeratedValue> 13546 <enumeratedValue> 13547 <name>9</name> 13548 <description>9 bits per character.</description> 13549 <value>9</value> 13550 </enumeratedValue> 13551 <enumeratedValue> 13552 <name>10</name> 13553 <description>10 bits per character.</description> 13554 <value>10</value> 13555 </enumeratedValue> 13556 <enumeratedValue> 13557 <name>11</name> 13558 <description>11 bits per character.</description> 13559 <value>11</value> 13560 </enumeratedValue> 13561 <enumeratedValue> 13562 <name>12</name> 13563 <description>12 bits per character.</description> 13564 <value>12</value> 13565 </enumeratedValue> 13566 <enumeratedValue> 13567 <name>13</name> 13568 <description>13 bits per character.</description> 13569 <value>13</value> 13570 </enumeratedValue> 13571 <enumeratedValue> 13572 <name>14</name> 13573 <description>14 bits per character.</description> 13574 <value>14</value> 13575 </enumeratedValue> 13576 <enumeratedValue> 13577 <name>15</name> 13578 <description>15 bits per character.</description> 13579 <value>15</value> 13580 </enumeratedValue> 13581 </enumeratedValues> 13582 </field> 13583 <field> 13584 <name>DATA_WIDTH</name> 13585 <description>SPI Data width.</description> 13586 <bitOffset>12</bitOffset> 13587 <bitWidth>2</bitWidth> 13588 <enumeratedValues> 13589 <enumeratedValue> 13590 <name>Mono</name> 13591 <description>1 data pin.</description> 13592 <value>0</value> 13593 </enumeratedValue> 13594 <enumeratedValue> 13595 <name>Dual</name> 13596 <description>2 data pins.</description> 13597 <value>1</value> 13598 </enumeratedValue> 13599 <enumeratedValue> 13600 <name>Quad</name> 13601 <description>4 data pins.</description> 13602 <value>2</value> 13603 </enumeratedValue> 13604 </enumeratedValues> 13605 </field> 13606 <field> 13607 <name>THREE_WIRE</name> 13608 <description>Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.</description> 13609 <bitOffset>15</bitOffset> 13610 <bitWidth>1</bitWidth> 13611 <enumeratedValues> 13612 <enumeratedValue> 13613 <name>dis</name> 13614 <description>Use four wire mode (Mono only).</description> 13615 <value>0</value> 13616 </enumeratedValue> 13617 <enumeratedValue> 13618 <name>en</name> 13619 <description>Use three wire mode.</description> 13620 <value>1</value> 13621 </enumeratedValue> 13622 </enumeratedValues> 13623 </field> 13624 <field> 13625 <name>SSPOL</name> 13626 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 13627 <bitOffset>16</bitOffset> 13628 <bitWidth>4</bitWidth> 13629 <enumeratedValues> 13630 <enumeratedValue> 13631 <name>SS0_high</name> 13632 <description>SS0 active high.</description> 13633 <value>0x1</value> 13634 </enumeratedValue> 13635 <enumeratedValue> 13636 <name>SS1_high</name> 13637 <description>SS1 active high.</description> 13638 <value>0x2</value> 13639 </enumeratedValue> 13640 <enumeratedValue> 13641 <name>SS2_high</name> 13642 <description>SS2 active high.</description> 13643 <value>0x4</value> 13644 </enumeratedValue> 13645 <enumeratedValue> 13646 <name>SS3_high</name> 13647 <description>SS3 active high.</description> 13648 <value>0x8</value> 13649 </enumeratedValue> 13650 </enumeratedValues> 13651 </field> 13652 </fields> 13653 </register> 13654 <register> 13655 <name>SSTIME</name> 13656 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 13657 <addressOffset>0x10</addressOffset> 13658 <access>read-write</access> 13659 <fields> 13660 <field> 13661 <name>PRE</name> 13662 <description>Slave Select Pre delay 1.</description> 13663 <bitOffset>0</bitOffset> 13664 <bitWidth>8</bitWidth> 13665 <enumeratedValues> 13666 <enumeratedValue> 13667 <name>256</name> 13668 <description>256 system clocks between SS active and first serial clock edge.</description> 13669 <value>0</value> 13670 </enumeratedValue> 13671 </enumeratedValues> 13672 </field> 13673 <field> 13674 <name>POST</name> 13675 <description>Slave Select Post delay 2.</description> 13676 <bitOffset>8</bitOffset> 13677 <bitWidth>8</bitWidth> 13678 <enumeratedValues> 13679 <enumeratedValue> 13680 <name>256</name> 13681 <description>256 system clocks between last serial clock edge and SS inactive.</description> 13682 <value>0</value> 13683 </enumeratedValue> 13684 </enumeratedValues> 13685 </field> 13686 <field> 13687 <name>INACT</name> 13688 <description>Slave Select Inactive delay.</description> 13689 <bitOffset>16</bitOffset> 13690 <bitWidth>8</bitWidth> 13691 <enumeratedValues> 13692 <enumeratedValue> 13693 <name>256</name> 13694 <description>256 system clocks between transactions.</description> 13695 <value>0</value> 13696 </enumeratedValue> 13697 </enumeratedValues> 13698 </field> 13699 </fields> 13700 </register> 13701 <register> 13702 <name>CLKCTRL</name> 13703 <description>Register for controlling SPI clock rate.</description> 13704 <addressOffset>0x14</addressOffset> 13705 <access>read-write</access> 13706 <fields> 13707 <field> 13708 <name>LO</name> 13709 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 13710 <bitOffset>0</bitOffset> 13711 <bitWidth>8</bitWidth> 13712 <enumeratedValues> 13713 <enumeratedValue> 13714 <name>Dis</name> 13715 <description>Duty cycle control of serial clock generation is disabled.</description> 13716 <value>0</value> 13717 </enumeratedValue> 13718 </enumeratedValues> 13719 </field> 13720 <field> 13721 <name>HI</name> 13722 <description>High duty cycle control. In timer mode, reload[15:8].</description> 13723 <bitOffset>8</bitOffset> 13724 <bitWidth>8</bitWidth> 13725 <enumeratedValues> 13726 <enumeratedValue> 13727 <name>Dis</name> 13728 <description>Duty cycle control of serial clock generation is disabled.</description> 13729 <value>0</value> 13730 </enumeratedValue> 13731 </enumeratedValues> 13732 </field> 13733 <field> 13734 <name>CLKDIV</name> 13735 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 13736 <bitOffset>16</bitOffset> 13737 <bitWidth>4</bitWidth> 13738 </field> 13739 </fields> 13740 </register> 13741 <register> 13742 <name>DMA</name> 13743 <description>Register for controlling DMA.</description> 13744 <addressOffset>0x1C</addressOffset> 13745 <access>read-write</access> 13746 <fields> 13747 <field> 13748 <name>TX_THD_VAL</name> 13749 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 13750 <bitOffset>0</bitOffset> 13751 <bitWidth>5</bitWidth> 13752 </field> 13753 <field> 13754 <name>TX_FIFO_EN</name> 13755 <description>Transmit FIFO enabled for SPI transactions.</description> 13756 <bitOffset>6</bitOffset> 13757 <bitWidth>1</bitWidth> 13758 <enumeratedValues> 13759 <enumeratedValue> 13760 <name>dis</name> 13761 <description>Transmit FIFO is not enabled.</description> 13762 <value>0</value> 13763 </enumeratedValue> 13764 <enumeratedValue> 13765 <name>en</name> 13766 <description>Transmit FIFO is enabled.</description> 13767 <value>1</value> 13768 </enumeratedValue> 13769 </enumeratedValues> 13770 </field> 13771 <field> 13772 <name>TX_FLUSH</name> 13773 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 13774 pointers. This should be done when FIFO is not being accessed on the SPI side. 13775 .</description> 13776 <bitOffset>7</bitOffset> 13777 <bitWidth>1</bitWidth> 13778 <enumeratedValues> 13779 <enumeratedValue> 13780 <name>CLEAR</name> 13781 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 13782 <value>1</value> 13783 </enumeratedValue> 13784 </enumeratedValues> 13785 </field> 13786 <field> 13787 <name>TX_LVL</name> 13788 <description>Count of entries in TX FIFO.</description> 13789 <bitOffset>8</bitOffset> 13790 <bitWidth>6</bitWidth> 13791 <access>read-only</access> 13792 </field> 13793 <field> 13794 <name>TX_EN</name> 13795 <description>TX DMA Enable.</description> 13796 <bitOffset>15</bitOffset> 13797 <bitWidth>1</bitWidth> 13798 <enumeratedValues> 13799 <enumeratedValue> 13800 <name>DIS</name> 13801 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 13802 <value>0</value> 13803 </enumeratedValue> 13804 <enumeratedValue> 13805 <name>en</name> 13806 <description>TX DMA requests are enabled.</description> 13807 <value>1</value> 13808 </enumeratedValue> 13809 </enumeratedValues> 13810 </field> 13811 <field> 13812 <name>RX_THD_VAL</name> 13813 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 13814 <bitOffset>16</bitOffset> 13815 <bitWidth>5</bitWidth> 13816 </field> 13817 <field> 13818 <name>RX_FIFO_EN</name> 13819 <description>Receive FIFO enabled for SPI transactions.</description> 13820 <bitOffset>22</bitOffset> 13821 <bitWidth>1</bitWidth> 13822 <enumeratedValues> 13823 <enumeratedValue> 13824 <name>DIS</name> 13825 <description>Receive FIFO is not enabled.</description> 13826 <value>0</value> 13827 </enumeratedValue> 13828 <enumeratedValue> 13829 <name>en</name> 13830 <description>Receive FIFO is enabled.</description> 13831 <value>1</value> 13832 </enumeratedValue> 13833 </enumeratedValues> 13834 </field> 13835 <field> 13836 <name>RX_FLUSH</name> 13837 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 13838 <bitOffset>23</bitOffset> 13839 <bitWidth>1</bitWidth> 13840 <enumeratedValues> 13841 <enumeratedValue> 13842 <name>CLEAR</name> 13843 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 13844 <value>1</value> 13845 </enumeratedValue> 13846 </enumeratedValues> 13847 </field> 13848 <field> 13849 <name>RX_LVL</name> 13850 <description>Count of entries in RX FIFO.</description> 13851 <bitOffset>24</bitOffset> 13852 <bitWidth>6</bitWidth> 13853 <access>read-only</access> 13854 </field> 13855 <field> 13856 <name>RX_EN</name> 13857 <description>RX DMA Enable.</description> 13858 <bitOffset>31</bitOffset> 13859 <bitWidth>1</bitWidth> 13860 <enumeratedValues> 13861 <enumeratedValue> 13862 <name>dis</name> 13863 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 13864 <value>0</value> 13865 </enumeratedValue> 13866 <enumeratedValue> 13867 <name>en</name> 13868 <description>RX DMA requests are enabled.</description> 13869 <value>1</value> 13870 </enumeratedValue> 13871 </enumeratedValues> 13872 </field> 13873 </fields> 13874 </register> 13875 <register> 13876 <name>INTFL</name> 13877 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 13878 <addressOffset>0x20</addressOffset> 13879 <access>read-write</access> 13880 <fields> 13881 <field> 13882 <name>TX_THD</name> 13883 <description>TX FIFO Threshold Crossed.</description> 13884 <bitOffset>0</bitOffset> 13885 <bitWidth>1</bitWidth> 13886 <enumeratedValues> 13887 <enumeratedValue> 13888 <name>clear</name> 13889 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 13890 <value>1</value> 13891 </enumeratedValue> 13892 </enumeratedValues> 13893 </field> 13894 <field> 13895 <name>TX_EM</name> 13896 <description>TX FIFO Empty.</description> 13897 <bitOffset>1</bitOffset> 13898 <bitWidth>1</bitWidth> 13899 <enumeratedValues> 13900 <enumeratedValue> 13901 <name>clear</name> 13902 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 13903 <value>1</value> 13904 </enumeratedValue> 13905 </enumeratedValues> 13906 </field> 13907 <field> 13908 <name>RX_THD</name> 13909 <description>RX FIFO Threshold Crossed.</description> 13910 <bitOffset>2</bitOffset> 13911 <bitWidth>1</bitWidth> 13912 <enumeratedValues> 13913 <enumeratedValue> 13914 <name>clear</name> 13915 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 13916 <value>1</value> 13917 </enumeratedValue> 13918 </enumeratedValues> 13919 </field> 13920 <field> 13921 <name>RX_FULL</name> 13922 <description>RX FIFO FULL.</description> 13923 <bitOffset>3</bitOffset> 13924 <bitWidth>1</bitWidth> 13925 <enumeratedValues> 13926 <enumeratedValue> 13927 <name>clear</name> 13928 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 13929 <value>1</value> 13930 </enumeratedValue> 13931 </enumeratedValues> 13932 </field> 13933 <field> 13934 <name>SSA</name> 13935 <description>Slave Select Asserted.</description> 13936 <bitOffset>4</bitOffset> 13937 <bitWidth>1</bitWidth> 13938 <enumeratedValues> 13939 <enumeratedValue> 13940 <name>clear</name> 13941 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 13942 <value>1</value> 13943 </enumeratedValue> 13944 </enumeratedValues> 13945 </field> 13946 <field> 13947 <name>SSD</name> 13948 <description>Slave Select Deasserted.</description> 13949 <bitOffset>5</bitOffset> 13950 <bitWidth>1</bitWidth> 13951 <enumeratedValues> 13952 <enumeratedValue> 13953 <name>clear</name> 13954 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 13955 <value>1</value> 13956 </enumeratedValue> 13957 </enumeratedValues> 13958 </field> 13959 <field> 13960 <name>FAULT</name> 13961 <description>Multi-Master Mode Fault.</description> 13962 <bitOffset>8</bitOffset> 13963 <bitWidth>1</bitWidth> 13964 <enumeratedValues> 13965 <enumeratedValue> 13966 <name>clear</name> 13967 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 13968 <value>1</value> 13969 </enumeratedValue> 13970 </enumeratedValues> 13971 </field> 13972 <field> 13973 <name>ABORT</name> 13974 <description>Slave Abort Detected.</description> 13975 <bitOffset>9</bitOffset> 13976 <bitWidth>1</bitWidth> 13977 <enumeratedValues> 13978 <enumeratedValue> 13979 <name>clear</name> 13980 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 13981 <value>1</value> 13982 </enumeratedValue> 13983 </enumeratedValues> 13984 </field> 13985 <field> 13986 <name>MST_DONE</name> 13987 <description>Master Done, set when SPI Master has completed any transactions.</description> 13988 <bitOffset>11</bitOffset> 13989 <bitWidth>1</bitWidth> 13990 <enumeratedValues> 13991 <enumeratedValue> 13992 <name>clear</name> 13993 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 13994 <value>1</value> 13995 </enumeratedValue> 13996 </enumeratedValues> 13997 </field> 13998 <field> 13999 <name>TX_OV</name> 14000 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 14001 <bitOffset>12</bitOffset> 14002 <bitWidth>1</bitWidth> 14003 <enumeratedValues> 14004 <enumeratedValue> 14005 <name>clear</name> 14006 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 14007 <value>1</value> 14008 </enumeratedValue> 14009 </enumeratedValues> 14010 </field> 14011 <field> 14012 <name>TX_UN</name> 14013 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 14014 <bitOffset>13</bitOffset> 14015 <bitWidth>1</bitWidth> 14016 <enumeratedValues> 14017 <enumeratedValue> 14018 <name>clear</name> 14019 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 14020 <value>1</value> 14021 </enumeratedValue> 14022 </enumeratedValues> 14023 </field> 14024 <field> 14025 <name>RX_OV</name> 14026 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 14027 <bitOffset>14</bitOffset> 14028 <bitWidth>1</bitWidth> 14029 <enumeratedValues> 14030 <enumeratedValue> 14031 <name>clear</name> 14032 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 14033 <value>1</value> 14034 </enumeratedValue> 14035 </enumeratedValues> 14036 </field> 14037 <field> 14038 <name>RX_UN</name> 14039 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 14040 <bitOffset>15</bitOffset> 14041 <bitWidth>1</bitWidth> 14042 <enumeratedValues> 14043 <enumeratedValue> 14044 <name>clear</name> 14045 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 14046 <value>1</value> 14047 </enumeratedValue> 14048 </enumeratedValues> 14049 </field> 14050 </fields> 14051 </register> 14052 <register> 14053 <name>INTEN</name> 14054 <description>Register for enabling interrupts.</description> 14055 <addressOffset>0x24</addressOffset> 14056 <access>read-write</access> 14057 <fields> 14058 <field> 14059 <name>TX_THD</name> 14060 <description>TX FIFO Threshold interrupt enable.</description> 14061 <bitOffset>0</bitOffset> 14062 <bitWidth>1</bitWidth> 14063 <enumeratedValues> 14064 <enumeratedValue> 14065 <name>dis</name> 14066 <description>Interrupt is disabled.</description> 14067 <value>0</value> 14068 </enumeratedValue> 14069 <enumeratedValue> 14070 <name>en</name> 14071 <description>Interrupt is enabled.</description> 14072 <value>1</value> 14073 </enumeratedValue> 14074 </enumeratedValues> 14075 </field> 14076 <field> 14077 <name>TX_EM</name> 14078 <description>TX FIFO Empty interrupt enable.</description> 14079 <bitOffset>1</bitOffset> 14080 <bitWidth>1</bitWidth> 14081 <enumeratedValues> 14082 <enumeratedValue> 14083 <name>dis</name> 14084 <description>Interrupt is disabled.</description> 14085 <value>0</value> 14086 </enumeratedValue> 14087 <enumeratedValue> 14088 <name>en</name> 14089 <description>Interrupt is enabled.</description> 14090 <value>1</value> 14091 </enumeratedValue> 14092 </enumeratedValues> 14093 </field> 14094 <field> 14095 <name>RX_THD</name> 14096 <description>RX FIFO Threshold Crossed interrupt enable.</description> 14097 <bitOffset>2</bitOffset> 14098 <bitWidth>1</bitWidth> 14099 <enumeratedValues> 14100 <enumeratedValue> 14101 <name>dis</name> 14102 <description>Interrupt is disabled.</description> 14103 <value>0</value> 14104 </enumeratedValue> 14105 <enumeratedValue> 14106 <name>en</name> 14107 <description>Interrupt is enabled.</description> 14108 <value>1</value> 14109 </enumeratedValue> 14110 </enumeratedValues> 14111 </field> 14112 <field> 14113 <name>RX_FULL</name> 14114 <description>RX FIFO FULL interrupt enable.</description> 14115 <bitOffset>3</bitOffset> 14116 <bitWidth>1</bitWidth> 14117 <enumeratedValues> 14118 <enumeratedValue> 14119 <name>dis</name> 14120 <description>Interrupt is disabled.</description> 14121 <value>0</value> 14122 </enumeratedValue> 14123 <enumeratedValue> 14124 <name>en</name> 14125 <description>Interrupt is enabled.</description> 14126 <value>1</value> 14127 </enumeratedValue> 14128 </enumeratedValues> 14129 </field> 14130 <field> 14131 <name>SSA</name> 14132 <description>Slave Select Asserted interrupt enable.</description> 14133 <bitOffset>4</bitOffset> 14134 <bitWidth>1</bitWidth> 14135 <enumeratedValues> 14136 <enumeratedValue> 14137 <name>dis</name> 14138 <description>Interrupt is disabled.</description> 14139 <value>0</value> 14140 </enumeratedValue> 14141 <enumeratedValue> 14142 <name>en</name> 14143 <description>Interrupt is enabled.</description> 14144 <value>1</value> 14145 </enumeratedValue> 14146 </enumeratedValues> 14147 </field> 14148 <field> 14149 <name>SSD</name> 14150 <description>Slave Select Deasserted interrupt enable.</description> 14151 <bitOffset>5</bitOffset> 14152 <bitWidth>1</bitWidth> 14153 <enumeratedValues> 14154 <enumeratedValue> 14155 <name>dis</name> 14156 <description>Interrupt is disabled.</description> 14157 <value>0</value> 14158 </enumeratedValue> 14159 <enumeratedValue> 14160 <name>en</name> 14161 <description>Interrupt is enabled.</description> 14162 <value>1</value> 14163 </enumeratedValue> 14164 </enumeratedValues> 14165 </field> 14166 <field> 14167 <name>FAULT</name> 14168 <description>Multi-Master Mode Fault interrupt enable.</description> 14169 <bitOffset>8</bitOffset> 14170 <bitWidth>1</bitWidth> 14171 <enumeratedValues> 14172 <enumeratedValue> 14173 <name>dis</name> 14174 <description>Interrupt is disabled.</description> 14175 <value>0</value> 14176 </enumeratedValue> 14177 <enumeratedValue> 14178 <name>en</name> 14179 <description>Interrupt is enabled.</description> 14180 <value>1</value> 14181 </enumeratedValue> 14182 </enumeratedValues> 14183 </field> 14184 <field> 14185 <name>ABORT</name> 14186 <description>Slave Abort Detected interrupt enable.</description> 14187 <bitOffset>9</bitOffset> 14188 <bitWidth>1</bitWidth> 14189 <enumeratedValues> 14190 <enumeratedValue> 14191 <name>dis</name> 14192 <description>Interrupt is disabled.</description> 14193 <value>0</value> 14194 </enumeratedValue> 14195 <enumeratedValue> 14196 <name>en</name> 14197 <description>Interrupt is enabled.</description> 14198 <value>1</value> 14199 </enumeratedValue> 14200 </enumeratedValues> 14201 </field> 14202 <field> 14203 <name>MST_DONE</name> 14204 <description>Master Done interrupt enable.</description> 14205 <bitOffset>11</bitOffset> 14206 <bitWidth>1</bitWidth> 14207 <enumeratedValues> 14208 <enumeratedValue> 14209 <name>dis</name> 14210 <description>Interrupt is disabled.</description> 14211 <value>0</value> 14212 </enumeratedValue> 14213 <enumeratedValue> 14214 <name>en</name> 14215 <description>Interrupt is enabled.</description> 14216 <value>1</value> 14217 </enumeratedValue> 14218 </enumeratedValues> 14219 </field> 14220 <field> 14221 <name>TX_OV</name> 14222 <description>Transmit FIFO Overrun interrupt enable.</description> 14223 <bitOffset>12</bitOffset> 14224 <bitWidth>1</bitWidth> 14225 <enumeratedValues> 14226 <enumeratedValue> 14227 <name>dis</name> 14228 <description>Interrupt is disabled.</description> 14229 <value>0</value> 14230 </enumeratedValue> 14231 <enumeratedValue> 14232 <name>en</name> 14233 <description>Interrupt is enabled.</description> 14234 <value>1</value> 14235 </enumeratedValue> 14236 </enumeratedValues> 14237 </field> 14238 <field> 14239 <name>TX_UN</name> 14240 <description>Transmit FIFO Underrun interrupt enable.</description> 14241 <bitOffset>13</bitOffset> 14242 <bitWidth>1</bitWidth> 14243 <enumeratedValues> 14244 <enumeratedValue> 14245 <name>dis</name> 14246 <description>Interrupt is disabled.</description> 14247 <value>0</value> 14248 </enumeratedValue> 14249 <enumeratedValue> 14250 <name>en</name> 14251 <description>Interrupt is enabled.</description> 14252 <value>1</value> 14253 </enumeratedValue> 14254 </enumeratedValues> 14255 </field> 14256 <field> 14257 <name>RX_OV</name> 14258 <description>Receive FIFO Overrun interrupt enable.</description> 14259 <bitOffset>14</bitOffset> 14260 <bitWidth>1</bitWidth> 14261 <enumeratedValues> 14262 <enumeratedValue> 14263 <name>dis</name> 14264 <description>Interrupt is disabled.</description> 14265 <value>0</value> 14266 </enumeratedValue> 14267 <enumeratedValue> 14268 <name>en</name> 14269 <description>Interrupt is enabled.</description> 14270 <value>1</value> 14271 </enumeratedValue> 14272 </enumeratedValues> 14273 </field> 14274 <field> 14275 <name>RX_UN</name> 14276 <description>Receive FIFO Underrun interrupt enable.</description> 14277 <bitOffset>15</bitOffset> 14278 <bitWidth>1</bitWidth> 14279 <enumeratedValues> 14280 <enumeratedValue> 14281 <name>dis</name> 14282 <description>Interrupt is disabled.</description> 14283 <value>0</value> 14284 </enumeratedValue> 14285 <enumeratedValue> 14286 <name>en</name> 14287 <description>Interrupt is enabled.</description> 14288 <value>1</value> 14289 </enumeratedValue> 14290 </enumeratedValues> 14291 </field> 14292 </fields> 14293 </register> 14294 <register> 14295 <name>WKFL</name> 14296 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 14297 <addressOffset>0x28</addressOffset> 14298 <access>read-write</access> 14299 <fields> 14300 <field> 14301 <name>TX_THD</name> 14302 <description>Wake on TX FIFO Threshold Crossed.</description> 14303 <bitOffset>0</bitOffset> 14304 <bitWidth>1</bitWidth> 14305 <enumeratedValues> 14306 <enumeratedValue> 14307 <name>clear</name> 14308 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 14309 <value>1</value> 14310 </enumeratedValue> 14311 </enumeratedValues> 14312 </field> 14313 <field> 14314 <name>TX_EM</name> 14315 <description>Wake on TX FIFO Empty.</description> 14316 <bitOffset>1</bitOffset> 14317 <bitWidth>1</bitWidth> 14318 <enumeratedValues> 14319 <enumeratedValue> 14320 <name>clear</name> 14321 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 14322 <value>1</value> 14323 </enumeratedValue> 14324 </enumeratedValues> 14325 </field> 14326 <field> 14327 <name>RX_THD</name> 14328 <description>Wake on RX FIFO Threshold Crossed.</description> 14329 <bitOffset>2</bitOffset> 14330 <bitWidth>1</bitWidth> 14331 <enumeratedValues> 14332 <enumeratedValue> 14333 <name>clear</name> 14334 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 14335 <value>1</value> 14336 </enumeratedValue> 14337 </enumeratedValues> 14338 </field> 14339 <field> 14340 <name>RX_FULL</name> 14341 <description>Wake on RX FIFO Full.</description> 14342 <bitOffset>3</bitOffset> 14343 <bitWidth>1</bitWidth> 14344 <enumeratedValues> 14345 <enumeratedValue> 14346 <name>clear</name> 14347 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 14348 <value>1</value> 14349 </enumeratedValue> 14350 </enumeratedValues> 14351 </field> 14352 </fields> 14353 </register> 14354 <register> 14355 <name>WKEN</name> 14356 <description>Register for wake up enable.</description> 14357 <addressOffset>0x2C</addressOffset> 14358 <access>read-write</access> 14359 <fields> 14360 <field> 14361 <name>TX_THD</name> 14362 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 14363 <bitOffset>0</bitOffset> 14364 <bitWidth>1</bitWidth> 14365 <enumeratedValues> 14366 <enumeratedValue> 14367 <name>dis</name> 14368 <description>Wakeup source disabled.</description> 14369 <value>0</value> 14370 </enumeratedValue> 14371 <enumeratedValue> 14372 <name>en</name> 14373 <description>Wakeup source enabled.</description> 14374 <value>1</value> 14375 </enumeratedValue> 14376 </enumeratedValues> 14377 </field> 14378 <field> 14379 <name>TX_EM</name> 14380 <description>Wake on TX FIFO Empty Enable.</description> 14381 <bitOffset>1</bitOffset> 14382 <bitWidth>1</bitWidth> 14383 <enumeratedValues> 14384 <enumeratedValue> 14385 <name>dis</name> 14386 <description>Wakeup source disabled.</description> 14387 <value>0</value> 14388 </enumeratedValue> 14389 <enumeratedValue> 14390 <name>en</name> 14391 <description>Wakeup source enabled.</description> 14392 <value>1</value> 14393 </enumeratedValue> 14394 </enumeratedValues> 14395 </field> 14396 <field> 14397 <name>RX_THD</name> 14398 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 14399 <bitOffset>2</bitOffset> 14400 <bitWidth>1</bitWidth> 14401 <enumeratedValues> 14402 <enumeratedValue> 14403 <name>dis</name> 14404 <description>Wakeup source disabled.</description> 14405 <value>0</value> 14406 </enumeratedValue> 14407 <enumeratedValue> 14408 <name>en</name> 14409 <description>Wakeup source enabled.</description> 14410 <value>1</value> 14411 </enumeratedValue> 14412 </enumeratedValues> 14413 </field> 14414 <field> 14415 <name>RX_FULL</name> 14416 <description>Wake on RX FIFO Full Enable.</description> 14417 <bitOffset>3</bitOffset> 14418 <bitWidth>1</bitWidth> 14419 <enumeratedValues> 14420 <enumeratedValue> 14421 <name>dis</name> 14422 <description>Wakeup source disabled.</description> 14423 <value>0</value> 14424 </enumeratedValue> 14425 <enumeratedValue> 14426 <name>en</name> 14427 <description>Wakeup source enabled.</description> 14428 <value>1</value> 14429 </enumeratedValue> 14430 </enumeratedValues> 14431 </field> 14432 </fields> 14433 </register> 14434 <register> 14435 <name>STATUS</name> 14436 <description>SPI Status register.</description> 14437 <addressOffset>0x30</addressOffset> 14438 <access>read-only</access> 14439 <fields> 14440 <field> 14441 <name>BUSY</name> 14442 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 14443 <bitOffset>0</bitOffset> 14444 <bitWidth>1</bitWidth> 14445 <enumeratedValues> 14446 <enumeratedValue> 14447 <name>not</name> 14448 <description>SPI not active.</description> 14449 <value>0</value> 14450 </enumeratedValue> 14451 <enumeratedValue> 14452 <name>active</name> 14453 <description>SPI active.</description> 14454 <value>1</value> 14455 </enumeratedValue> 14456 </enumeratedValues> 14457 </field> 14458 </fields> 14459 </register> 14460 </registers> 14461 </peripheral> 14462<!--SPI SPI peripheral.--> 14463 <peripheral derivedFrom="SPI"> 14464 <name>SPI1</name> 14465 <description>SPI peripheral. 1</description> 14466 <baseAddress>0x40047000</baseAddress> 14467 <interrupt> 14468 <name>SPI1</name> 14469 <description>SPI1 IRQ</description> 14470 <value>17</value> 14471 </interrupt> 14472 </peripheral> 14473<!--SPI1 SPI peripheral. 1--> 14474 <peripheral derivedFrom="SPI"> 14475 <name>SPI2</name> 14476 <description>SPI peripheral. 2</description> 14477 <baseAddress>0x400BE000</baseAddress> 14478 <interrupt> 14479 <name>SPI2</name> 14480 <description>SPI2 IRQ</description> 14481 <value>56</value> 14482 </interrupt> 14483 </peripheral> 14484<!--SPI2 SPI peripheral. 2--> 14485 <peripheral> 14486 <name>TMR0</name> 14487 <description>32-bit reloadable timer that can be used for timing and event counting.</description> 14488 <groupName>Timers</groupName> 14489 <baseAddress>0x40010000</baseAddress> 14490 <addressBlock> 14491 <offset>0x00</offset> 14492 <size>0x1000</size> 14493 <usage>registers</usage> 14494 </addressBlock> 14495 <interrupt> 14496 <name>TMR0</name> 14497 <description>TMR0 IRQ</description> 14498 <value>5</value> 14499 </interrupt> 14500 <registers> 14501 <register> 14502 <name>CNT</name> 14503 <description>Count. This register stores the current timer count.</description> 14504 <addressOffset>0x00</addressOffset> 14505 <resetValue>0x00000001</resetValue> 14506 <fields> 14507 <field> 14508 <name>COUNT</name> 14509 <description>Count.</description> 14510 <bitOffset>0</bitOffset> 14511 <bitWidth>32</bitWidth> 14512 </field> 14513 </fields> 14514 </register> 14515 <register> 14516 <name>CMP</name> 14517 <description>Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.</description> 14518 <addressOffset>0x04</addressOffset> 14519 <resetValue>0x0000FFFF</resetValue> 14520 <fields> 14521 <field> 14522 <name>COMPARE</name> 14523 <description>Compare.</description> 14524 <bitOffset>0</bitOffset> 14525 <bitWidth>32</bitWidth> 14526 </field> 14527 </fields> 14528 </register> 14529 <register> 14530 <name>PWM</name> 14531 <description>PWM. This register stores the value that is compared to the current timer count.</description> 14532 <addressOffset>0x08</addressOffset> 14533 <fields> 14534 <field> 14535 <name>PWM</name> 14536 <description>PWM</description> 14537 <bitOffset>0</bitOffset> 14538 <bitWidth>32</bitWidth> 14539 </field> 14540 </fields> 14541 </register> 14542 <register> 14543 <name>INTFL</name> 14544 <description>Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.</description> 14545 <addressOffset>0x0C</addressOffset> 14546 <modifiedWriteValues>oneToClear</modifiedWriteValues> 14547 <fields> 14548 <field> 14549 <name>IRQ</name> 14550 <description>Clear Interrupt.</description> 14551 <bitOffset>0</bitOffset> 14552 <bitWidth>1</bitWidth> 14553 </field> 14554 </fields> 14555 </register> 14556 <register> 14557 <name>CTRL</name> 14558 <description>Timer Control Register.</description> 14559 <addressOffset>0x10</addressOffset> 14560 <fields> 14561 <field> 14562 <name>MODE</name> 14563 <description>Timer Mode.</description> 14564 <bitOffset>0</bitOffset> 14565 <bitWidth>3</bitWidth> 14566 <enumeratedValues> 14567 <enumeratedValue> 14568 <name>oneShot</name> 14569 <description>One Shot Mode.</description> 14570 <value>0</value> 14571 </enumeratedValue> 14572 <enumeratedValue> 14573 <name>continuous</name> 14574 <description>Continuous Mode.</description> 14575 <value>1</value> 14576 </enumeratedValue> 14577 <enumeratedValue> 14578 <name>counter</name> 14579 <description>Counter Mode.</description> 14580 <value>2</value> 14581 </enumeratedValue> 14582 <enumeratedValue> 14583 <name>pwm</name> 14584 <description>PWM Mode.</description> 14585 <value>3</value> 14586 </enumeratedValue> 14587 <enumeratedValue> 14588 <name>capture</name> 14589 <description>Capture Mode.</description> 14590 <value>4</value> 14591 </enumeratedValue> 14592 <enumeratedValue> 14593 <name>compare</name> 14594 <description>Compare Mode.</description> 14595 <value>5</value> 14596 </enumeratedValue> 14597 <enumeratedValue> 14598 <name>gated</name> 14599 <description>Gated Mode.</description> 14600 <value>6</value> 14601 </enumeratedValue> 14602 <enumeratedValue> 14603 <name>captureCompare</name> 14604 <description>Capture/Compare Mode.</description> 14605 <value>7</value> 14606 </enumeratedValue> 14607 </enumeratedValues> 14608 </field> 14609 <field> 14610 <name>CLKDIV</name> 14611 <description>Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].</description> 14612 <bitOffset>3</bitOffset> 14613 <bitWidth>3</bitWidth> 14614 <enumeratedValues> 14615 <enumeratedValue> 14616 <name>div1</name> 14617 <description>Divide by 1.</description> 14618 <value>0</value> 14619 </enumeratedValue> 14620 <enumeratedValue> 14621 <name>div2</name> 14622 <description>Divide by 2.</description> 14623 <value>1</value> 14624 </enumeratedValue> 14625 <enumeratedValue> 14626 <name>div4</name> 14627 <description>Divide by 4.</description> 14628 <value>2</value> 14629 </enumeratedValue> 14630 <enumeratedValue> 14631 <name>div8</name> 14632 <description>Divide by 8.</description> 14633 <value>3</value> 14634 </enumeratedValue> 14635 <enumeratedValue> 14636 <name>div16</name> 14637 <description>Divide by 16.</description> 14638 <value>4</value> 14639 </enumeratedValue> 14640 <enumeratedValue> 14641 <name>div32</name> 14642 <description>Divide by 32.</description> 14643 <value>5</value> 14644 </enumeratedValue> 14645 <enumeratedValue> 14646 <name>div64</name> 14647 <description>Divide by 64.</description> 14648 <value>6</value> 14649 </enumeratedValue> 14650 <enumeratedValue> 14651 <name>div128</name> 14652 <description>Divide by 128.</description> 14653 <value>7</value> 14654 </enumeratedValue> 14655 </enumeratedValues> 14656 </field> 14657 <field> 14658 <name>POL</name> 14659 <description>Timer input/output polarity bit.</description> 14660 <bitOffset>6</bitOffset> 14661 <bitWidth>1</bitWidth> 14662 <enumeratedValues> 14663 <enumeratedValue> 14664 <name>activeHi</name> 14665 <description>Active High.</description> 14666 <value>0</value> 14667 </enumeratedValue> 14668 <enumeratedValue> 14669 <name>activeLo</name> 14670 <description>Active Low.</description> 14671 <value>1</value> 14672 </enumeratedValue> 14673 </enumeratedValues> 14674 </field> 14675 <field> 14676 <name>EN</name> 14677 <description>Timer Enable.</description> 14678 <bitOffset>7</bitOffset> 14679 <bitWidth>1</bitWidth> 14680 <enumeratedValues> 14681 <enumeratedValue> 14682 <name>dis</name> 14683 <description>Disable.</description> 14684 <value>0</value> 14685 </enumeratedValue> 14686 <enumeratedValue> 14687 <name>en</name> 14688 <description>Enable.</description> 14689 <value>1</value> 14690 </enumeratedValue> 14691 </enumeratedValues> 14692 </field> 14693 <field> 14694 <name>CLKDIV3</name> 14695 <description>MSB of prescaler value.</description> 14696 <bitOffset>8</bitOffset> 14697 <bitWidth>1</bitWidth> 14698 </field> 14699 <field> 14700 <name>PWMSYNC</name> 14701 <description>Timer PWM Synchronization Mode Enable.</description> 14702 <bitOffset>9</bitOffset> 14703 <bitWidth>1</bitWidth> 14704 <enumeratedValues> 14705 <enumeratedValue> 14706 <name>dis</name> 14707 <description>Disable.</description> 14708 <value>0</value> 14709 </enumeratedValue> 14710 <enumeratedValue> 14711 <name>en</name> 14712 <description>Enable.</description> 14713 <value>1</value> 14714 </enumeratedValue> 14715 </enumeratedValues> 14716 </field> 14717 <field> 14718 <name>NOLHPOL</name> 14719 <description>Timer PWM output 0A polarity bit.</description> 14720 <bitOffset>10</bitOffset> 14721 <bitWidth>1</bitWidth> 14722 <enumeratedValues> 14723 <enumeratedValue> 14724 <name>dis</name> 14725 <description>Disable.</description> 14726 <value>0</value> 14727 </enumeratedValue> 14728 <enumeratedValue> 14729 <name>en</name> 14730 <description>Enable.</description> 14731 <value>1</value> 14732 </enumeratedValue> 14733 </enumeratedValues> 14734 </field> 14735 <field> 14736 <name>NOLLPOL</name> 14737 <description>Timer PWM output 0A' polarity bit.</description> 14738 <bitOffset>11</bitOffset> 14739 <bitWidth>1</bitWidth> 14740 <enumeratedValues> 14741 <enumeratedValue> 14742 <name>dis</name> 14743 <description>Disable.</description> 14744 <value>0</value> 14745 </enumeratedValue> 14746 <enumeratedValue> 14747 <name>en</name> 14748 <description>Enable.</description> 14749 <value>1</value> 14750 </enumeratedValue> 14751 </enumeratedValues> 14752 </field> 14753 <field> 14754 <name>PWMCKBD</name> 14755 <description>Timer PWM output 0A Mode Disable.</description> 14756 <bitOffset>12</bitOffset> 14757 <bitWidth>1</bitWidth> 14758 <enumeratedValues> 14759 <enumeratedValue> 14760 <name>dis</name> 14761 <description>Disable.</description> 14762 <value>1</value> 14763 </enumeratedValue> 14764 <enumeratedValue> 14765 <name>en</name> 14766 <description>Enable.</description> 14767 <value>0</value> 14768 </enumeratedValue> 14769 </enumeratedValues> 14770 </field> 14771 </fields> 14772 </register> 14773 <register> 14774 <name>NOLCMP</name> 14775 <description>Timer Non-Overlapping Compare Register.</description> 14776 <addressOffset>0x14</addressOffset> 14777 <fields> 14778 <field> 14779 <name>LO</name> 14780 <description>Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.</description> 14781 <bitOffset>0</bitOffset> 14782 <bitWidth>8</bitWidth> 14783 </field> 14784 <field> 14785 <name>HI</name> 14786 <description>Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.</description> 14787 <bitOffset>8</bitOffset> 14788 <bitWidth>8</bitWidth> 14789 </field> 14790 </fields> 14791 </register> 14792 </registers> 14793 </peripheral> 14794<!--TMR0 32-bit reloadable timer that can be used for timing and event counting.--> 14795 <peripheral derivedFrom="TMR0"> 14796 <name>TMR1</name> 14797 <description>32-bit reloadable timer that can be used for timing and event counting. 1</description> 14798 <baseAddress>0x40011000</baseAddress> 14799 <interrupt> 14800 <name>TMR1</name> 14801 <description>TMR1 IRQ</description> 14802 <value>6</value> 14803 </interrupt> 14804 </peripheral> 14805<!--TMR1 32-bit reloadable timer that can be used for timing and event counting. 1--> 14806 <peripheral derivedFrom="TMR0"> 14807 <name>TMR2</name> 14808 <description>32-bit reloadable timer that can be used for timing and event counting. 2</description> 14809 <baseAddress>0x40012000</baseAddress> 14810 <interrupt> 14811 <name>TMR2</name> 14812 <description>TMR2 IRQ</description> 14813 <value>7</value> 14814 </interrupt> 14815 </peripheral> 14816<!--TMR2 32-bit reloadable timer that can be used for timing and event counting. 2--> 14817 <peripheral derivedFrom="TMR0"> 14818 <name>TMR3</name> 14819 <description>32-bit reloadable timer that can be used for timing and event counting. 3</description> 14820 <baseAddress>0x40013000</baseAddress> 14821 <interrupt> 14822 <name>TMR3</name> 14823 <description>TMR3 IRQ</description> 14824 <value>8</value> 14825 </interrupt> 14826 </peripheral> 14827<!--TMR3 32-bit reloadable timer that can be used for timing and event counting. 3--> 14828 <peripheral derivedFrom="TMR0"> 14829 <name>TMR4</name> 14830 <description>32-bit reloadable timer that can be used for timing and event counting. 4</description> 14831 <baseAddress>0x40014000</baseAddress> 14832 <interrupt> 14833 <name>TMR4</name> 14834 <description>TMR4 IRQ</description> 14835 <value>9</value> 14836 </interrupt> 14837 </peripheral> 14838<!--TMR4 32-bit reloadable timer that can be used for timing and event counting. 4--> 14839 <peripheral derivedFrom="TMR0"> 14840 <name>TMR5</name> 14841 <description>32-bit reloadable timer that can be used for timing and event counting. 5</description> 14842 <baseAddress>0x40015000</baseAddress> 14843 <interrupt> 14844 <name>TMR5</name> 14845 <description>TMR5 IRQ</description> 14846 <value>10</value> 14847 </interrupt> 14848 </peripheral> 14849<!--TMR5 32-bit reloadable timer that can be used for timing and event counting. 5--> 14850 <peripheral> 14851 <name>TRNG</name> 14852 <description>Random Number Generator.</description> 14853 <baseAddress>0x4004D000</baseAddress> 14854 <addressBlock> 14855 <offset>0x00</offset> 14856 <size>0x1000</size> 14857 <usage>registers</usage> 14858 </addressBlock> 14859 <interrupt> 14860 <name>TRNG</name> 14861 <description>TRNG interrupt.</description> 14862 <value>4</value> 14863 </interrupt> 14864 <registers> 14865 <register> 14866 <name>CTRL</name> 14867 <description>TRNG Control Register.</description> 14868 <addressOffset>0x00</addressOffset> 14869 <resetValue>0x00000003</resetValue> 14870 <fields> 14871 <field> 14872 <name>OD_HEALTH</name> 14873 <description>Start On-Demand health test.</description> 14874 <bitOffset>0</bitOffset> 14875 <bitWidth>1</bitWidth> 14876 </field> 14877 <field> 14878 <name>RND_IE</name> 14879 <description>To enable IRQ generation when a new 32-bit Random number is ready.</description> 14880 <bitOffset>1</bitOffset> 14881 <bitWidth>1</bitWidth> 14882 <enumeratedValues> 14883 <enumeratedValue> 14884 <name>disable</name> 14885 <description>Disable</description> 14886 <value>0</value> 14887 </enumeratedValue> 14888 <enumeratedValue> 14889 <name>enable</name> 14890 <description>Enable</description> 14891 <value>1</value> 14892 </enumeratedValue> 14893 </enumeratedValues> 14894 </field> 14895 <field> 14896 <name>HEALTH_IE</name> 14897 <description>Enable IRQ generation when a health test fails.</description> 14898 <bitOffset>2</bitOffset> 14899 <bitWidth>1</bitWidth> 14900 </field> 14901 <field> 14902 <name>MEU_KEYGEN</name> 14903 <description>If set to 1, the TRNG generates the 256-bit AES MEU keys.</description> 14904 <bitOffset>3</bitOffset> 14905 <bitWidth>1</bitWidth> 14906 </field> 14907 <field> 14908 <name>XIP_KEYGEN</name> 14909 <description>If set to 1, the TRNG generates the 128-bit QSPI (XIP) keys.</description> 14910 <bitOffset>4</bitOffset> 14911 <bitWidth>1</bitWidth> 14912 </field> 14913 <field> 14914 <name>OD_ROMON</name> 14915 <description>Start ring oscillator monitor on demand test.</description> 14916 <bitOffset>6</bitOffset> 14917 <bitWidth>1</bitWidth> 14918 </field> 14919 <field> 14920 <name>OD_EE</name> 14921 <description>Start entropy estimator on demand test.</description> 14922 <bitOffset>7</bitOffset> 14923 <bitWidth>1</bitWidth> 14924 </field> 14925 <field> 14926 <name>ROMON_EE_FOE</name> 14927 <description>Ring Oscillator Monitors and Entropy Estimator Freeze on Error.</description> 14928 <bitOffset>8</bitOffset> 14929 <bitWidth>1</bitWidth> 14930 </field> 14931 <field> 14932 <name>ROMON_EE_FOD</name> 14933 <description>Ring Oscillator Monitors and Entropy Estimator Freeze on Done.</description> 14934 <bitOffset>9</bitOffset> 14935 <bitWidth>1</bitWidth> 14936 </field> 14937 <field> 14938 <name>EBLS</name> 14939 <description>Entropy Bit Load Select.</description> 14940 <bitOffset>10</bitOffset> 14941 <bitWidth>1</bitWidth> 14942 </field> 14943 <field> 14944 <name>KEYWIPE</name> 14945 <description>To wipe the Battery Backed key.</description> 14946 <bitOffset>15</bitOffset> 14947 <bitWidth>1</bitWidth> 14948 </field> 14949 <field> 14950 <name>GET_TERO_CNT</name> 14951 <description>Get Tero Count.</description> 14952 <bitOffset>16</bitOffset> 14953 <bitWidth>1</bitWidth> 14954 </field> 14955 <field> 14956 <name>EE_DONE_IE</name> 14957 <description>Entropy Estimator Done Interrupt Enable.</description> 14958 <bitOffset>23</bitOffset> 14959 <bitWidth>1</bitWidth> 14960 </field> 14961 <field> 14962 <name>ROMON_DIS</name> 14963 <description>Ring Oscillator Disable.</description> 14964 <bitOffset>24</bitOffset> 14965 <bitWidth>3</bitWidth> 14966 <enumeratedValues> 14967 <enumeratedValue> 14968 <name>RO_0</name> 14969 <description>Ring Oscillator 0.</description> 14970 <value>1</value> 14971 </enumeratedValue> 14972 <enumeratedValue> 14973 <name>RO_1</name> 14974 <description>Ring Oscillator 1.</description> 14975 <value>2</value> 14976 </enumeratedValue> 14977 <enumeratedValue> 14978 <name>RO_2</name> 14979 <description>Ring Oscillator 2.</description> 14980 <value>4</value> 14981 </enumeratedValue> 14982 </enumeratedValues> 14983 </field> 14984 </fields> 14985 </register> 14986 <register> 14987 <name>STATUS</name> 14988 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 14989 <addressOffset>0x04</addressOffset> 14990 <fields> 14991 <field> 14992 <name>RDY</name> 14993 <description>32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1.</description> 14994 <bitOffset>0</bitOffset> 14995 <bitWidth>1</bitWidth> 14996 <enumeratedValues> 14997 <enumeratedValue> 14998 <name>Busy</name> 14999 <description>TRNG Busy</description> 15000 <value>0</value> 15001 </enumeratedValue> 15002 <enumeratedValue> 15003 <name>Ready</name> 15004 <description>32 bit random data is ready</description> 15005 <value>1</value> 15006 </enumeratedValue> 15007 </enumeratedValues> 15008 </field> 15009 <field> 15010 <name>OD_HEALTH</name> 15011 <description>On-Demand health test status.</description> 15012 <bitOffset>1</bitOffset> 15013 <bitWidth>1</bitWidth> 15014 </field> 15015 <field> 15016 <name>HEALTH</name> 15017 <description>Health test status.</description> 15018 <bitOffset>2</bitOffset> 15019 <bitWidth>1</bitWidth> 15020 </field> 15021 <field> 15022 <name>SRCFAIL</name> 15023 <description>Entropy source has failed.</description> 15024 <bitOffset>3</bitOffset> 15025 <bitWidth>1</bitWidth> 15026 </field> 15027 <field> 15028 <name>AES_KEYGEN</name> 15029 <description>AESKGD.</description> 15030 <bitOffset>4</bitOffset> 15031 <bitWidth>1</bitWidth> 15032 </field> 15033 <field> 15034 <name>OD_ROMON</name> 15035 <description>On demand ring oscillator test status.</description> 15036 <bitOffset>6</bitOffset> 15037 <bitWidth>1</bitWidth> 15038 </field> 15039 <field> 15040 <name>OD_EE</name> 15041 <description>On demand entropy estimator status.</description> 15042 <bitOffset>7</bitOffset> 15043 <bitWidth>1</bitWidth> 15044 </field> 15045 <field> 15046 <name>PP_ERR</name> 15047 <description>Post process error.</description> 15048 <bitOffset>8</bitOffset> 15049 <bitWidth>1</bitWidth> 15050 </field> 15051 <field> 15052 <name>ROMON_0_ERR</name> 15053 <description>Ring Oscillator 0 Monitor Error.</description> 15054 <bitOffset>9</bitOffset> 15055 <bitWidth>1</bitWidth> 15056 </field> 15057 <field> 15058 <name>ROMON_1_ERR</name> 15059 <description>Ring Oscillator 1 Monitor Error.</description> 15060 <bitOffset>10</bitOffset> 15061 <bitWidth>1</bitWidth> 15062 </field> 15063 <field> 15064 <name>ROMON_2_ERR</name> 15065 <description>Ring Oscillator 2 Monitor Error.</description> 15066 <bitOffset>11</bitOffset> 15067 <bitWidth>1</bitWidth> 15068 </field> 15069 <field> 15070 <name>EE_ERR_THR</name> 15071 <description>Entropy Estimator Threshold Error.</description> 15072 <bitOffset>12</bitOffset> 15073 <bitWidth>1</bitWidth> 15074 </field> 15075 <field> 15076 <name>EE_ERR_OOB</name> 15077 <description>Entropy Estimator Out of Bounds Error..</description> 15078 <bitOffset>13</bitOffset> 15079 <bitWidth>1</bitWidth> 15080 </field> 15081 <field> 15082 <name>EE_ERR_LOCK</name> 15083 <description>Entropy Estimator Lock Error.</description> 15084 <bitOffset>14</bitOffset> 15085 <bitWidth>1</bitWidth> 15086 </field> 15087 <field> 15088 <name>TERO_CNT_RDY</name> 15089 <description>TERO Count Ready.</description> 15090 <bitOffset>16</bitOffset> 15091 <bitWidth>1</bitWidth> 15092 </field> 15093 <field> 15094 <name>RC_ERR</name> 15095 <description>Repetition Count Error.</description> 15096 <bitOffset>17</bitOffset> 15097 <bitWidth>1</bitWidth> 15098 </field> 15099 <field> 15100 <name>AP_ERR</name> 15101 <description>Adaptive Proportion Error.</description> 15102 <bitOffset>18</bitOffset> 15103 <bitWidth>1</bitWidth> 15104 </field> 15105 <field> 15106 <name>DATA_DONE</name> 15107 <description>Data register has been loaded with at least 32 new entropy bits.</description> 15108 <bitOffset>19</bitOffset> 15109 <bitWidth>1</bitWidth> 15110 </field> 15111 <field> 15112 <name>DATA_NIST_DONE</name> 15113 <description>Data NIST register has been loaded with at least 32 new entropy bits.</description> 15114 <bitOffset>20</bitOffset> 15115 <bitWidth>1</bitWidth> 15116 </field> 15117 <field> 15118 <name>HEALTH_DONE</name> 15119 <description>Health Test Done.</description> 15120 <bitOffset>21</bitOffset> 15121 <bitWidth>1</bitWidth> 15122 </field> 15123 <field> 15124 <name>ROMON_DONE</name> 15125 <description>Ring Oscillator Monitor Test Done.</description> 15126 <bitOffset>22</bitOffset> 15127 <bitWidth>1</bitWidth> 15128 </field> 15129 <field> 15130 <name>EE_DONE</name> 15131 <description>Entropy Estimator Test Done.</description> 15132 <bitOffset>23</bitOffset> 15133 <bitWidth>1</bitWidth> 15134 </field> 15135 </fields> 15136 </register> 15137 <register> 15138 <name>DATA</name> 15139 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 15140 <addressOffset>0x08</addressOffset> 15141 <access>read-only</access> 15142 <fields> 15143 <field> 15144 <name>DATA</name> 15145 <description>Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000.</description> 15146 <bitOffset>0</bitOffset> 15147 <bitWidth>32</bitWidth> 15148 </field> 15149 </fields> 15150 </register> 15151 <register> 15152 <name>DATA_NIST</name> 15153 <description>Data NIST Register.</description> 15154 <addressOffset>0x38</addressOffset> 15155 <fields> 15156 <field> 15157 <name>DATA</name> 15158 <description>Ring Oscillator 1 Monitor Last Ring Oscillator Count.</description> 15159 <bitOffset>0</bitOffset> 15160 <bitWidth>32</bitWidth> 15161 </field> 15162 </fields> 15163 </register> 15164 </registers> 15165 </peripheral> 15166<!--TRNG Random Number Generator.--> 15167 <peripheral> 15168 <name>UART</name> 15169 <description>UART Low Power Registers</description> 15170 <baseAddress>0x40042000</baseAddress> 15171 <addressBlock> 15172 <offset>0x00</offset> 15173 <size>0x1000</size> 15174 <usage>registers</usage> 15175 </addressBlock> 15176 <registers> 15177 <register> 15178 <name>CTRL</name> 15179 <description>Control register</description> 15180 <addressOffset>0x0000</addressOffset> 15181 <fields> 15182 <field> 15183 <name>RX_THD_VAL</name> 15184 <description>This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) </description> 15185 <bitOffset>0</bitOffset> 15186 <bitWidth>4</bitWidth> 15187 </field> 15188 <field> 15189 <name>PAR_EN</name> 15190 <description>Parity Enable</description> 15191 <bitOffset>4</bitOffset> 15192 <bitWidth>1</bitWidth> 15193 </field> 15194 <field> 15195 <name>PAR_EO</name> 15196 <description>when PAREN=1 selects odd or even parity odd is 1 even is 0</description> 15197 <bitOffset>5</bitOffset> 15198 <bitWidth>1</bitWidth> 15199 </field> 15200 <field> 15201 <name>PAR_MD</name> 15202 <description>Selects parity based on 1s or 0s count (when PAREN=1) </description> 15203 <bitOffset>6</bitOffset> 15204 <bitWidth>1</bitWidth> 15205 </field> 15206 <field> 15207 <name>CTS_DIS</name> 15208 <description>CTS Sampling Disable </description> 15209 <bitOffset>7</bitOffset> 15210 <bitWidth>1</bitWidth> 15211 </field> 15212 <field> 15213 <name>TX_FLUSH</name> 15214 <description>Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description> 15215 <bitOffset>8</bitOffset> 15216 <bitWidth>1</bitWidth> 15217 </field> 15218 <field> 15219 <name>RX_FLUSH</name> 15220 <description>Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description> 15221 <bitOffset>9</bitOffset> 15222 <bitWidth>1</bitWidth> 15223 </field> 15224 <field> 15225 <name>CHAR_SIZE</name> 15226 <description>Selects UART character size</description> 15227 <bitOffset>10</bitOffset> 15228 <bitWidth>2</bitWidth> 15229 <enumeratedValues> 15230 <enumeratedValue> 15231 <name>5bits</name> 15232 <description>5 bits</description> 15233 <value>0</value> 15234 </enumeratedValue> 15235 <enumeratedValue> 15236 <name>6bits</name> 15237 <description>6 bits</description> 15238 <value>1</value> 15239 </enumeratedValue> 15240 <enumeratedValue> 15241 <name>7bits</name> 15242 <description>7 bits</description> 15243 <value>2</value> 15244 </enumeratedValue> 15245 <enumeratedValue> 15246 <name>8bits</name> 15247 <description>8 bits</description> 15248 <value>3</value> 15249 </enumeratedValue> 15250 </enumeratedValues> 15251 </field> 15252 <field> 15253 <name>STOPBITS</name> 15254 <description>Selects the number of stop bits that will be generated</description> 15255 <bitOffset>12</bitOffset> 15256 <bitWidth>1</bitWidth> 15257 </field> 15258 <field> 15259 <name>HFC_EN</name> 15260 <description>Enables/disables hardware flow control</description> 15261 <bitOffset>13</bitOffset> 15262 <bitWidth>1</bitWidth> 15263 </field> 15264 <field> 15265 <name>RTSDC</name> 15266 <description>Hardware Flow Control RTS Mode</description> 15267 <bitOffset>14</bitOffset> 15268 <bitWidth>1</bitWidth> 15269 </field> 15270 <field> 15271 <name>BCLKEN</name> 15272 <description>Baud clock enable</description> 15273 <bitOffset>15</bitOffset> 15274 <bitWidth>1</bitWidth> 15275 </field> 15276 <field> 15277 <name>BCLKSRC</name> 15278 <description>To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock.</description> 15279 <bitOffset>16</bitOffset> 15280 <bitWidth>2</bitWidth> 15281 <enumeratedValues> 15282 <enumeratedValue> 15283 <name>Peripheral_Clock</name> 15284 <description>apb clock</description> 15285 <value>0</value> 15286 </enumeratedValue> 15287 <enumeratedValue> 15288 <name>External_Clock</name> 15289 <description>Clock 1</description> 15290 <value>1</value> 15291 </enumeratedValue> 15292 <enumeratedValue> 15293 <name>CLK2</name> 15294 <description>Clock 2</description> 15295 <value>2</value> 15296 </enumeratedValue> 15297 <enumeratedValue> 15298 <name>CLK3</name> 15299 <description>Clock 3</description> 15300 <value>3</value> 15301 </enumeratedValue> 15302 </enumeratedValues> 15303 </field> 15304 <field> 15305 <name>DPFE_EN</name> 15306 <description>Data/Parity bit frame error detection enable</description> 15307 <bitOffset>18</bitOffset> 15308 <bitWidth>1</bitWidth> 15309 </field> 15310 <field> 15311 <name>BCLKRDY</name> 15312 <description>Baud clock Ready read only bit</description> 15313 <bitOffset>19</bitOffset> 15314 <bitWidth>1</bitWidth> 15315 </field> 15316 <field> 15317 <name>UCAGM</name> 15318 <description>UART Clock Auto Gating mode</description> 15319 <bitOffset>20</bitOffset> 15320 <bitWidth>1</bitWidth> 15321 </field> 15322 <field> 15323 <name>FDM</name> 15324 <description>Fractional Division Mode</description> 15325 <bitOffset>21</bitOffset> 15326 <bitWidth>1</bitWidth> 15327 </field> 15328 <field> 15329 <name>DESM</name> 15330 <description>RX Dual Edge Sampling Mode</description> 15331 <bitOffset>22</bitOffset> 15332 <bitWidth>1</bitWidth> 15333 </field> 15334 </fields> 15335 </register> 15336 <register> 15337 <name>STATUS</name> 15338 <description>Status register</description> 15339 <addressOffset>0x0004</addressOffset> 15340 <access>read-only</access> 15341 <fields> 15342 <field> 15343 <name>TX_BUSY</name> 15344 <description>Read-only flag indicating the UART transmit status</description> 15345 <bitOffset>0</bitOffset> 15346 <bitWidth>1</bitWidth> 15347 </field> 15348 <field> 15349 <name>RX_BUSY</name> 15350 <description>Read-only flag indicating the UART receiver status</description> 15351 <bitOffset>1</bitOffset> 15352 <bitWidth>1</bitWidth> 15353 </field> 15354 <field> 15355 <name>RX_EM</name> 15356 <description>Read-only flag indicating the RX FIFO state</description> 15357 <bitOffset>4</bitOffset> 15358 <bitWidth>1</bitWidth> 15359 </field> 15360 <field> 15361 <name>RX_FULL</name> 15362 <description>Read-only flag indicating the RX FIFO state</description> 15363 <bitOffset>5</bitOffset> 15364 <bitWidth>1</bitWidth> 15365 </field> 15366 <field> 15367 <name>TX_EM</name> 15368 <description>Read-only flag indicating the TX FIFO state</description> 15369 <bitOffset>6</bitOffset> 15370 <bitWidth>1</bitWidth> 15371 </field> 15372 <field> 15373 <name>TX_FULL</name> 15374 <description>Read-only flag indicating the TX FIFO state</description> 15375 <bitOffset>7</bitOffset> 15376 <bitWidth>1</bitWidth> 15377 </field> 15378 <field> 15379 <name>RX_LVL</name> 15380 <description>Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) </description> 15381 <bitOffset>8</bitOffset> 15382 <bitWidth>4</bitWidth> 15383 </field> 15384 <field> 15385 <name>TX_LVL</name> 15386 <description>Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) </description> 15387 <bitOffset>12</bitOffset> 15388 <bitWidth>4</bitWidth> 15389 </field> 15390 </fields> 15391 </register> 15392 <register> 15393 <name>INTEN</name> 15394 <description>Interrupt Enable control register</description> 15395 <addressOffset>0x0008</addressOffset> 15396 <fields> 15397 <field> 15398 <name>RX_FERR</name> 15399 <description>Enable Interrupt For RX Frame Error</description> 15400 <bitOffset>0</bitOffset> 15401 <bitWidth>1</bitWidth> 15402 </field> 15403 <field> 15404 <name>RX_PAR</name> 15405 <description>Enable Interrupt For RX Parity Error</description> 15406 <bitOffset>1</bitOffset> 15407 <bitWidth>1</bitWidth> 15408 </field> 15409 <field> 15410 <name>CTS_EV</name> 15411 <description>Enable Interrupt For CTS signal change Error</description> 15412 <bitOffset>2</bitOffset> 15413 <bitWidth>1</bitWidth> 15414 </field> 15415 <field> 15416 <name>RX_OV</name> 15417 <description>Enable Interrupt For RX FIFO Overrun Error</description> 15418 <bitOffset>3</bitOffset> 15419 <bitWidth>1</bitWidth> 15420 </field> 15421 <field> 15422 <name>RX_THD</name> 15423 <description>Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD</description> 15424 <bitOffset>4</bitOffset> 15425 <bitWidth>1</bitWidth> 15426 </field> 15427 <field> 15428 <name>TX_OB</name> 15429 <description>Enable Interrupt For TX FIFO has only one byte remaining.</description> 15430 <bitOffset>5</bitOffset> 15431 <bitWidth>1</bitWidth> 15432 </field> 15433 <field> 15434 <name>TX_HE</name> 15435 <description>Enable Interrupt For TX FIFO has half empty</description> 15436 <bitOffset>6</bitOffset> 15437 <bitWidth>1</bitWidth> 15438 </field> 15439 </fields> 15440 </register> 15441 <register> 15442 <name>INTFL</name> 15443 <description>Interrupt status flags Control register</description> 15444 <addressOffset>0x000C</addressOffset> 15445 <fields> 15446 <field> 15447 <name>RX_FERR</name> 15448 <description>Flag for RX Frame Error Interrupt.</description> 15449 <bitOffset>0</bitOffset> 15450 <bitWidth>1</bitWidth> 15451 </field> 15452 <field> 15453 <name>RX_PAR</name> 15454 <description>Flag for RX Parity Error interrupt</description> 15455 <bitOffset>1</bitOffset> 15456 <bitWidth>1</bitWidth> 15457 </field> 15458 <field> 15459 <name>CTS_EV</name> 15460 <description>Flag for CTS signal change interrupt (hardware flow control disabled) </description> 15461 <bitOffset>2</bitOffset> 15462 <bitWidth>1</bitWidth> 15463 </field> 15464 <field> 15465 <name>RX_OV</name> 15466 <description>Flag for RX FIFO Overrun interrupt</description> 15467 <bitOffset>3</bitOffset> 15468 <bitWidth>1</bitWidth> 15469 </field> 15470 <field> 15471 <name>RX_THD</name> 15472 <description>Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field</description> 15473 <bitOffset>4</bitOffset> 15474 <bitWidth>1</bitWidth> 15475 </field> 15476 <field> 15477 <name>TX_OB</name> 15478 <description>Flag for interrupt when TX FIFO has only one byte remaining.</description> 15479 <bitOffset>5</bitOffset> 15480 <bitWidth>1</bitWidth> 15481 </field> 15482 <field> 15483 <name>TX_HE</name> 15484 <description>Flag for interrupt when TX FIFO is half empty</description> 15485 <bitOffset>6</bitOffset> 15486 <bitWidth>1</bitWidth> 15487 </field> 15488 </fields> 15489 </register> 15490 <register> 15491 <name>CLKDIV</name> 15492 <description>Clock Divider register</description> 15493 <addressOffset>0x0010</addressOffset> 15494 <fields> 15495 <field> 15496 <name>CLKDIV</name> 15497 <description>Baud rate divisor value</description> 15498 <bitOffset>0</bitOffset> 15499 <bitWidth>20</bitWidth> 15500 </field> 15501 </fields> 15502 </register> 15503 <register> 15504 <name>OSR</name> 15505 <description>Over Sampling Rate register</description> 15506 <addressOffset>0x0014</addressOffset> 15507 <fields> 15508 <field> 15509 <name>OSR</name> 15510 <description>OSR</description> 15511 <bitOffset>0</bitOffset> 15512 <bitWidth>3</bitWidth> 15513 </field> 15514 </fields> 15515 </register> 15516 <register> 15517 <name>TXPEEK</name> 15518 <description>TX FIFO Output Peek register</description> 15519 <addressOffset>0x0018</addressOffset> 15520 <fields> 15521 <field> 15522 <name>DATA</name> 15523 <description>Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field.</description> 15524 <bitOffset>0</bitOffset> 15525 <bitWidth>8</bitWidth> 15526 </field> 15527 </fields> 15528 </register> 15529 <register> 15530 <name>PNR</name> 15531 <description> Pin register</description> 15532 <addressOffset>0x001C</addressOffset> 15533 <fields> 15534 <field> 15535 <name>CTS</name> 15536 <description>Current sampled value of CTS IO</description> 15537 <bitOffset>0</bitOffset> 15538 <bitWidth>1</bitWidth> 15539 <access>read-only</access> 15540 </field> 15541 <field> 15542 <name>RTS</name> 15543 <description>This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level.</description> 15544 <bitOffset>1</bitOffset> 15545 <bitWidth>1</bitWidth> 15546 </field> 15547 </fields> 15548 </register> 15549 <register> 15550 <name>FIFO</name> 15551 <description>FIFO Read/Write register</description> 15552 <addressOffset>0x0020</addressOffset> 15553 <fields> 15554 <field> 15555 <name>DATA</name> 15556 <description>Load/unload location for TX and RX FIFO buffers.</description> 15557 <bitOffset>0</bitOffset> 15558 <bitWidth>8</bitWidth> 15559 </field> 15560 <field> 15561 <name>RX_PAR</name> 15562 <description>Parity error flag for next byte to be read from FIFO.</description> 15563 <bitOffset>8</bitOffset> 15564 <bitWidth>1</bitWidth> 15565 </field> 15566 </fields> 15567 </register> 15568 <register> 15569 <name>DMA</name> 15570 <description>DMA Configuration register</description> 15571 <addressOffset>0x0030</addressOffset> 15572 <fields> 15573 <field> 15574 <name>TX_THD_VAL</name> 15575 <description>TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory.</description> 15576 <bitOffset>0</bitOffset> 15577 <bitWidth>4</bitWidth> 15578 </field> 15579 <field> 15580 <name>TX_EN</name> 15581 <description>TX DMA channel enable</description> 15582 <bitOffset>4</bitOffset> 15583 <bitWidth>1</bitWidth> 15584 </field> 15585 <field> 15586 <name>RX_THD_VAL</name> 15587 <description>Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory.</description> 15588 <bitOffset>5</bitOffset> 15589 <bitWidth>4</bitWidth> 15590 </field> 15591 <field> 15592 <name>RX_EN</name> 15593 <description>RX DMA channel enable</description> 15594 <bitOffset>9</bitOffset> 15595 <bitWidth>1</bitWidth> 15596 </field> 15597 </fields> 15598 </register> 15599 <register> 15600 <name>WKEN</name> 15601 <description>Wake up enable Control register</description> 15602 <addressOffset>0x0034</addressOffset> 15603 <fields> 15604 <field> 15605 <name>RX_NE</name> 15606 <description>Wake-Up Enable for RX FIFO Not Empty</description> 15607 <bitOffset>0</bitOffset> 15608 <bitWidth>1</bitWidth> 15609 </field> 15610 <field> 15611 <name>RX_FULL</name> 15612 <description>Wake-Up Enable for RX FIFO Full</description> 15613 <bitOffset>1</bitOffset> 15614 <bitWidth>1</bitWidth> 15615 </field> 15616 <field> 15617 <name>RX_THD</name> 15618 <description>Wake-Up Enable for RX FIFO Threshold Met</description> 15619 <bitOffset>2</bitOffset> 15620 <bitWidth>1</bitWidth> 15621 </field> 15622 </fields> 15623 </register> 15624 <register> 15625 <name>WKFL</name> 15626 <description>Wake up Flags register</description> 15627 <addressOffset>0x0038</addressOffset> 15628 <fields> 15629 <field> 15630 <name>RX_NE</name> 15631 <description>Wake-Up Flag for RX FIFO Not Empty</description> 15632 <bitOffset>0</bitOffset> 15633 <bitWidth>1</bitWidth> 15634 </field> 15635 <field> 15636 <name>RX_FULL</name> 15637 <description>Wake-Up Flag for RX FIFO Full</description> 15638 <bitOffset>1</bitOffset> 15639 <bitWidth>1</bitWidth> 15640 </field> 15641 <field> 15642 <name>RX_THD</name> 15643 <description>Wake-Up Flag for RX FIFO Threshold Met</description> 15644 <bitOffset>2</bitOffset> 15645 <bitWidth>1</bitWidth> 15646 </field> 15647 </fields> 15648 </register> 15649 </registers> 15650 </peripheral> 15651<!--UART UART Low Power Registers--> 15652 <peripheral derivedFrom="UART"> 15653 <name>UART1</name> 15654 <description>UART Low Power Registers 1</description> 15655 <baseAddress>0x40043000</baseAddress> 15656 </peripheral> 15657<!--UART1 UART Low Power Registers 1--> 15658 <peripheral derivedFrom="UART"> 15659 <name>UART2</name> 15660 <description>UART Low Power Registers 2</description> 15661 <baseAddress>0x40044000</baseAddress> 15662 </peripheral> 15663<!--UART2 UART Low Power Registers 2--> 15664 <peripheral derivedFrom="UART"> 15665 <name>UART3</name> 15666 <description>UART Low Power Registers 3</description> 15667 <baseAddress>0x40045000</baseAddress> 15668 </peripheral> 15669<!--UART3 UART Low Power Registers 3--> 15670 <peripheral> 15671 <name>USBHS</name> 15672 <description>USB 2.0 High-speed Controller.</description> 15673 <baseAddress>0x400B1000</baseAddress> 15674 <addressBlock> 15675 <offset>0</offset> 15676 <size>0x1000</size> 15677 <usage>registers</usage> 15678 </addressBlock> 15679 <interrupt> 15680 <name>USB</name> 15681 <value>2</value> 15682 </interrupt> 15683 <registers> 15684 <register> 15685 <name>FADDR</name> 15686 <description>Function address register.</description> 15687 <addressOffset>0x00</addressOffset> 15688 <size>8</size> 15689 <resetMask>0x00</resetMask> 15690 <fields> 15691 <field> 15692 <name>ADDR</name> 15693 <description>Function address for this controller.</description> 15694 <bitOffset>0</bitOffset> 15695 <bitWidth>7</bitWidth> 15696 <access>read-write</access> 15697 </field> 15698 <field> 15699 <name>UPDATE</name> 15700 <description>Set when ADDR is written, cleared when new address takes effect.</description> 15701 <bitOffset>7</bitOffset> 15702 <bitWidth>1</bitWidth> 15703 <access>read-only</access> 15704 </field> 15705 </fields> 15706 </register> 15707 <register> 15708 <name>POWER</name> 15709 <description>Power management register.</description> 15710 <addressOffset>0x01</addressOffset> 15711 <size>8</size> 15712 <fields> 15713 <field> 15714 <name>EN_SUSPENDM</name> 15715 <description>Enable SUSPENDM signal.</description> 15716 <bitOffset>0</bitOffset> 15717 <bitWidth>1</bitWidth> 15718 <access>read-write</access> 15719 </field> 15720 <field> 15721 <name>SUSPEND</name> 15722 <description>Suspend mode detected.</description> 15723 <bitOffset>1</bitOffset> 15724 <bitWidth>1</bitWidth> 15725 <access>read-only</access> 15726 </field> 15727 <field> 15728 <name>RESUME</name> 15729 <description>Generate resume signaling.</description> 15730 <bitOffset>2</bitOffset> 15731 <bitWidth>1</bitWidth> 15732 <access>read-write</access> 15733 </field> 15734 <field> 15735 <name>RESET</name> 15736 <description>Bus reset detected.</description> 15737 <bitOffset>3</bitOffset> 15738 <bitWidth>1</bitWidth> 15739 <access>read-only</access> 15740 </field> 15741 <field> 15742 <name>HS_MODE</name> 15743 <description>High-speed mode detected.</description> 15744 <bitOffset>4</bitOffset> 15745 <bitWidth>1</bitWidth> 15746 <access>read-only</access> 15747 </field> 15748 <field> 15749 <name>HS_ENABLE</name> 15750 <description>High-speed mode enable.</description> 15751 <bitOffset>5</bitOffset> 15752 <bitWidth>1</bitWidth> 15753 <access>read-write</access> 15754 </field> 15755 <field> 15756 <name>SOFTCONN</name> 15757 <description>Softconn.</description> 15758 <bitOffset>6</bitOffset> 15759 <bitWidth>1</bitWidth> 15760 <access>read-write</access> 15761 </field> 15762 <field> 15763 <name>ISO_UPDATE</name> 15764 <description>Wait for SOF during Isochronous xfers.</description> 15765 <bitOffset>7</bitOffset> 15766 <bitWidth>1</bitWidth> 15767 <access>read-write</access> 15768 </field> 15769 </fields> 15770 </register> 15771 <register> 15772 <name>INTRIN</name> 15773 <description>Interrupt register for EP0 and IN EP1-15.</description> 15774 <addressOffset>0x02</addressOffset> 15775 <size>16</size> 15776 <fields> 15777 <field> 15778 <name>EP15_IN_INT</name> 15779 <description>Endpoint 15 interrupt.</description> 15780 <bitOffset>15</bitOffset> 15781 <bitWidth>1</bitWidth> 15782 <access>read-only</access> 15783 </field> 15784 <field> 15785 <name>EP14_IN_INT</name> 15786 <description>Endpoint 14 interrupt.</description> 15787 <bitOffset>14</bitOffset> 15788 <bitWidth>1</bitWidth> 15789 <access>read-only</access> 15790 </field> 15791 <field> 15792 <name>EP13_IN_INT</name> 15793 <description>Endpoint 13 interrupt.</description> 15794 <bitOffset>13</bitOffset> 15795 <bitWidth>1</bitWidth> 15796 <access>read-only</access> 15797 </field> 15798 <field> 15799 <name>EP12_IN_INT</name> 15800 <description>Endpoint 12 interrupt.</description> 15801 <bitOffset>12</bitOffset> 15802 <bitWidth>1</bitWidth> 15803 <access>read-only</access> 15804 </field> 15805 <field> 15806 <name>EP11_IN_INT</name> 15807 <description>Endpoint 11 interrupt.</description> 15808 <bitOffset>11</bitOffset> 15809 <bitWidth>1</bitWidth> 15810 <access>read-only</access> 15811 </field> 15812 <field> 15813 <name>EP10_IN_INT</name> 15814 <description>Endpoint 10 interrupt.</description> 15815 <bitOffset>10</bitOffset> 15816 <bitWidth>1</bitWidth> 15817 <access>read-only</access> 15818 </field> 15819 <field> 15820 <name>EP9_IN_INT</name> 15821 <description>Endpoint 9 interrupt.</description> 15822 <bitOffset>9</bitOffset> 15823 <bitWidth>1</bitWidth> 15824 <access>read-only</access> 15825 </field> 15826 <field> 15827 <name>EP8_IN_INT</name> 15828 <description>Endpoint 8 interrupt.</description> 15829 <bitOffset>8</bitOffset> 15830 <bitWidth>1</bitWidth> 15831 <access>read-only</access> 15832 </field> 15833 <field> 15834 <name>EP7_IN_INT</name> 15835 <description>Endpoint 7 interrupt.</description> 15836 <bitOffset>7</bitOffset> 15837 <bitWidth>1</bitWidth> 15838 <access>read-only</access> 15839 </field> 15840 <field> 15841 <name>EP6_IN_INT</name> 15842 <description>Endpoint 6 interrupt.</description> 15843 <bitOffset>6</bitOffset> 15844 <bitWidth>1</bitWidth> 15845 <access>read-only</access> 15846 </field> 15847 <field> 15848 <name>EP5_IN_INT</name> 15849 <description>Endpoint 5 interrupt.</description> 15850 <bitOffset>5</bitOffset> 15851 <bitWidth>1</bitWidth> 15852 <access>read-only</access> 15853 </field> 15854 <field> 15855 <name>EP4_IN_INT</name> 15856 <description>Endpoint 4 interrupt.</description> 15857 <bitOffset>4</bitOffset> 15858 <bitWidth>1</bitWidth> 15859 <access>read-only</access> 15860 </field> 15861 <field> 15862 <name>EP3_IN_INT</name> 15863 <description>Endpoint 3 interrupt.</description> 15864 <bitOffset>3</bitOffset> 15865 <bitWidth>1</bitWidth> 15866 <access>read-only</access> 15867 </field> 15868 <field> 15869 <name>EP2_IN_INT</name> 15870 <description>Endpoint 2 interrupt.</description> 15871 <bitOffset>2</bitOffset> 15872 <bitWidth>1</bitWidth> 15873 <access>read-only</access> 15874 </field> 15875 <field> 15876 <name>EP1_IN_INT</name> 15877 <description>Endpoint 1 interrupt.</description> 15878 <bitOffset>1</bitOffset> 15879 <bitWidth>1</bitWidth> 15880 <access>read-only</access> 15881 </field> 15882 <field> 15883 <name>EP0_IN_INT</name> 15884 <description>Endpoint 0 interrupt.</description> 15885 <bitOffset>0</bitOffset> 15886 <bitWidth>1</bitWidth> 15887 <access>read-only</access> 15888 </field> 15889 </fields> 15890 </register> 15891 <register> 15892 <name>INTROUT</name> 15893 <description>Interrupt register for OUT EP 1-15.</description> 15894 <addressOffset>0x04</addressOffset> 15895 <size>16</size> 15896 <fields> 15897 <field> 15898 <name>EP15_OUT_INT</name> 15899 <description>Endpoint 15 interrupt.</description> 15900 <bitOffset>15</bitOffset> 15901 <bitWidth>1</bitWidth> 15902 <access>read-only</access> 15903 </field> 15904 <field> 15905 <name>EP14_OUT_INT</name> 15906 <description>Endpoint 14 interrupt.</description> 15907 <bitOffset>14</bitOffset> 15908 <bitWidth>1</bitWidth> 15909 <access>read-only</access> 15910 </field> 15911 <field> 15912 <name>EP13_OUT_INT</name> 15913 <description>Endpoint 13 interrupt.</description> 15914 <bitOffset>13</bitOffset> 15915 <bitWidth>1</bitWidth> 15916 <access>read-only</access> 15917 </field> 15918 <field> 15919 <name>EP12_OUT_INT</name> 15920 <description>Endpoint 12 interrupt.</description> 15921 <bitOffset>12</bitOffset> 15922 <bitWidth>1</bitWidth> 15923 <access>read-only</access> 15924 </field> 15925 <field> 15926 <name>EP11_OUT_INT</name> 15927 <description>Endpoint 11 interrupt.</description> 15928 <bitOffset>11</bitOffset> 15929 <bitWidth>1</bitWidth> 15930 <access>read-only</access> 15931 </field> 15932 <field> 15933 <name>EP10_OUT_INT</name> 15934 <description>Endpoint 10 interrupt.</description> 15935 <bitOffset>10</bitOffset> 15936 <bitWidth>1</bitWidth> 15937 <access>read-only</access> 15938 </field> 15939 <field> 15940 <name>EP9_OUT_INT</name> 15941 <description>Endpoint 9 interrupt.</description> 15942 <bitOffset>9</bitOffset> 15943 <bitWidth>1</bitWidth> 15944 <access>read-only</access> 15945 </field> 15946 <field> 15947 <name>EP8_OUT_INT</name> 15948 <description>Endpoint 8 interrupt.</description> 15949 <bitOffset>8</bitOffset> 15950 <bitWidth>1</bitWidth> 15951 <access>read-only</access> 15952 </field> 15953 <field> 15954 <name>EP7_OUT_INT</name> 15955 <description>Endpoint 7 interrupt.</description> 15956 <bitOffset>7</bitOffset> 15957 <bitWidth>1</bitWidth> 15958 <access>read-only</access> 15959 </field> 15960 <field> 15961 <name>EP6_OUT_INT</name> 15962 <description>Endpoint 6 interrupt.</description> 15963 <bitOffset>6</bitOffset> 15964 <bitWidth>1</bitWidth> 15965 <access>read-only</access> 15966 </field> 15967 <field> 15968 <name>EP5_OUT_INT</name> 15969 <description>Endpoint 5 interrupt.</description> 15970 <bitOffset>5</bitOffset> 15971 <bitWidth>1</bitWidth> 15972 <access>read-only</access> 15973 </field> 15974 <field> 15975 <name>EP4_OUT_INT</name> 15976 <description>Endpoint 4 interrupt.</description> 15977 <bitOffset>4</bitOffset> 15978 <bitWidth>1</bitWidth> 15979 <access>read-only</access> 15980 </field> 15981 <field> 15982 <name>EP3_OUT_INT</name> 15983 <description>Endpoint 3 interrupt.</description> 15984 <bitOffset>3</bitOffset> 15985 <bitWidth>1</bitWidth> 15986 <access>read-only</access> 15987 </field> 15988 <field> 15989 <name>EP2_OUT_INT</name> 15990 <description>Endpoint 2 interrupt.</description> 15991 <bitOffset>2</bitOffset> 15992 <bitWidth>1</bitWidth> 15993 <access>read-only</access> 15994 </field> 15995 <field> 15996 <name>EP1_OUT_INT</name> 15997 <description>Endpoint 1 interrupt.</description> 15998 <bitOffset>1</bitOffset> 15999 <bitWidth>1</bitWidth> 16000 <access>read-only</access> 16001 </field> 16002 </fields> 16003 </register> 16004 <register> 16005 <name>INTRINEN</name> 16006 <description>Interrupt enable for EP 0 and IN EP 1-15.</description> 16007 <addressOffset>0x06</addressOffset> 16008 <size>16</size> 16009 <fields> 16010 <field> 16011 <name>EP15_IN_INT_EN</name> 16012 <description>Endpoint 15 interrupt enable.</description> 16013 <bitOffset>15</bitOffset> 16014 <bitWidth>1</bitWidth> 16015 <access>read-write</access> 16016 </field> 16017 <field> 16018 <name>EP14_IN_INT_EN</name> 16019 <description>Endpoint 14 interrupt enable.</description> 16020 <bitOffset>14</bitOffset> 16021 <bitWidth>1</bitWidth> 16022 <access>read-write</access> 16023 </field> 16024 <field> 16025 <name>EP13_IN_INT_EN</name> 16026 <description>Endpoint 13 interrupt enable.</description> 16027 <bitOffset>13</bitOffset> 16028 <bitWidth>1</bitWidth> 16029 <access>read-write</access> 16030 </field> 16031 <field> 16032 <name>EP12_IN_INT_EN</name> 16033 <description>Endpoint 12 interrupt enable.</description> 16034 <bitOffset>12</bitOffset> 16035 <bitWidth>1</bitWidth> 16036 <access>read-write</access> 16037 </field> 16038 <field> 16039 <name>EP11_IN_INT_EN</name> 16040 <description>Endpoint 11 interrupt enable.</description> 16041 <bitOffset>11</bitOffset> 16042 <bitWidth>1</bitWidth> 16043 <access>read-write</access> 16044 </field> 16045 <field> 16046 <name>EP10_IN_INT_EN</name> 16047 <description>Endpoint 10 interrupt enable.</description> 16048 <bitOffset>10</bitOffset> 16049 <bitWidth>1</bitWidth> 16050 <access>read-write</access> 16051 </field> 16052 <field> 16053 <name>EP9_IN_INT_EN</name> 16054 <description>Endpoint 9 interrupt enable.</description> 16055 <bitOffset>9</bitOffset> 16056 <bitWidth>1</bitWidth> 16057 <access>read-write</access> 16058 </field> 16059 <field> 16060 <name>EP8_IN_INT_EN</name> 16061 <description>Endpoint 8 interrupt enable.</description> 16062 <bitOffset>8</bitOffset> 16063 <bitWidth>1</bitWidth> 16064 <access>read-write</access> 16065 </field> 16066 <field> 16067 <name>EP7_IN_INT_EN</name> 16068 <description>Endpoint 7 interrupt enable.</description> 16069 <bitOffset>7</bitOffset> 16070 <bitWidth>1</bitWidth> 16071 <access>read-write</access> 16072 </field> 16073 <field> 16074 <name>EP6_IN_INT_EN</name> 16075 <description>Endpoint 6 interrupt enable.</description> 16076 <bitOffset>6</bitOffset> 16077 <bitWidth>1</bitWidth> 16078 <access>read-write</access> 16079 </field> 16080 <field> 16081 <name>EP5_IN_INT_EN</name> 16082 <description>Endpoint 5 interrupt enable.</description> 16083 <bitOffset>5</bitOffset> 16084 <bitWidth>1</bitWidth> 16085 <access>read-write</access> 16086 </field> 16087 <field> 16088 <name>EP4_IN_INT_EN</name> 16089 <description>Endpoint 4 interrupt enable.</description> 16090 <bitOffset>4</bitOffset> 16091 <bitWidth>1</bitWidth> 16092 <access>read-write</access> 16093 </field> 16094 <field> 16095 <name>EP3_IN_INT_EN</name> 16096 <description>Endpoint 3 interrupt enable.</description> 16097 <bitOffset>3</bitOffset> 16098 <bitWidth>1</bitWidth> 16099 <access>read-write</access> 16100 </field> 16101 <field> 16102 <name>EP2_IN_INT_EN</name> 16103 <description>Endpoint 2 interrupt enable.</description> 16104 <bitOffset>2</bitOffset> 16105 <bitWidth>1</bitWidth> 16106 <access>read-write</access> 16107 </field> 16108 <field> 16109 <name>EP1_IN_INT_EN</name> 16110 <description>Endpoint 1 interrupt enable.</description> 16111 <bitOffset>1</bitOffset> 16112 <bitWidth>1</bitWidth> 16113 <access>read-write</access> 16114 </field> 16115 <field> 16116 <name>EP0_INT_EN</name> 16117 <description>Endpoint 0 interrupt enable.</description> 16118 <bitOffset>0</bitOffset> 16119 <bitWidth>1</bitWidth> 16120 <access>read-write</access> 16121 </field> 16122 </fields> 16123 </register> 16124 <register> 16125 <name>INTROUTEN</name> 16126 <description>Interrupt enable for OUT EP 1-15.</description> 16127 <addressOffset>0x08</addressOffset> 16128 <size>16</size> 16129 <fields> 16130 <field> 16131 <name>EP15_OUT_INT_EN</name> 16132 <description>Endpoint 15 interrupt.</description> 16133 <bitOffset>15</bitOffset> 16134 <bitWidth>1</bitWidth> 16135 <access>read-write</access> 16136 </field> 16137 <field> 16138 <name>EP14_OUT_INT_EN</name> 16139 <description>Endpoint 14 interrupt.</description> 16140 <bitOffset>14</bitOffset> 16141 <bitWidth>1</bitWidth> 16142 <access>read-write</access> 16143 </field> 16144 <field> 16145 <name>EP13_OUT_INT_EN</name> 16146 <description>Endpoint 13 interrupt.</description> 16147 <bitOffset>13</bitOffset> 16148 <bitWidth>1</bitWidth> 16149 <access>read-write</access> 16150 </field> 16151 <field> 16152 <name>EP12_OUT_INT_EN</name> 16153 <description>Endpoint 12 interrupt.</description> 16154 <bitOffset>12</bitOffset> 16155 <bitWidth>1</bitWidth> 16156 <access>read-write</access> 16157 </field> 16158 <field> 16159 <name>EP11_OUT_INT_EN</name> 16160 <description>Endpoint 11 interrupt.</description> 16161 <bitOffset>11</bitOffset> 16162 <bitWidth>1</bitWidth> 16163 <access>read-write</access> 16164 </field> 16165 <field> 16166 <name>EP10_OUT_INT_EN</name> 16167 <description>Endpoint 10 interrupt.</description> 16168 <bitOffset>10</bitOffset> 16169 <bitWidth>1</bitWidth> 16170 <access>read-write</access> 16171 </field> 16172 <field> 16173 <name>EP9_OUT_INT_EN</name> 16174 <description>Endpoint 9 interrupt.</description> 16175 <bitOffset>9</bitOffset> 16176 <bitWidth>1</bitWidth> 16177 <access>read-write</access> 16178 </field> 16179 <field> 16180 <name>EP8_OUT_INT_EN</name> 16181 <description>Endpoint 8 interrupt.</description> 16182 <bitOffset>8</bitOffset> 16183 <bitWidth>1</bitWidth> 16184 <access>read-write</access> 16185 </field> 16186 <field> 16187 <name>EP7_OUT_INT_EN</name> 16188 <description>Endpoint 7 interrupt.</description> 16189 <bitOffset>7</bitOffset> 16190 <bitWidth>1</bitWidth> 16191 <access>read-write</access> 16192 </field> 16193 <field> 16194 <name>EP6_OUT_INT_EN</name> 16195 <description>Endpoint 6 interrupt.</description> 16196 <bitOffset>6</bitOffset> 16197 <bitWidth>1</bitWidth> 16198 <access>read-write</access> 16199 </field> 16200 <field> 16201 <name>EP5_OUT_INT_EN</name> 16202 <description>Endpoint 5 interrupt.</description> 16203 <bitOffset>5</bitOffset> 16204 <bitWidth>1</bitWidth> 16205 <access>read-write</access> 16206 </field> 16207 <field> 16208 <name>EP4_OUT_INT_EN</name> 16209 <description>Endpoint 4 interrupt.</description> 16210 <bitOffset>4</bitOffset> 16211 <bitWidth>1</bitWidth> 16212 <access>read-write</access> 16213 </field> 16214 <field> 16215 <name>EP3_OUT_INT_EN</name> 16216 <description>Endpoint 3 interrupt.</description> 16217 <bitOffset>3</bitOffset> 16218 <bitWidth>1</bitWidth> 16219 <access>read-write</access> 16220 </field> 16221 <field> 16222 <name>EP2_OUT_INT_EN</name> 16223 <description>Endpoint 2 interrupt.</description> 16224 <bitOffset>2</bitOffset> 16225 <bitWidth>1</bitWidth> 16226 <access>read-write</access> 16227 </field> 16228 <field> 16229 <name>EP1_OUT_INT_EN</name> 16230 <description>Endpoint 1 interrupt.</description> 16231 <bitOffset>1</bitOffset> 16232 <bitWidth>1</bitWidth> 16233 <access>read-write</access> 16234 </field> 16235 </fields> 16236 </register> 16237 <register> 16238 <name>INTRUSB</name> 16239 <description>Interrupt register for common USB interrupts.</description> 16240 <addressOffset>0x0A</addressOffset> 16241 <size>8</size> 16242 <fields> 16243 <field> 16244 <name>SOF_INT</name> 16245 <description>Start of Frame.</description> 16246 <bitOffset>3</bitOffset> 16247 <bitWidth>1</bitWidth> 16248 <access>read-only</access> 16249 </field> 16250 <field> 16251 <name>RESET_INT</name> 16252 <description>Bus reset detected.</description> 16253 <bitOffset>2</bitOffset> 16254 <bitWidth>1</bitWidth> 16255 <access>read-only</access> 16256 </field> 16257 <field> 16258 <name>RESUME_INT</name> 16259 <description>Resume detected.</description> 16260 <bitOffset>1</bitOffset> 16261 <bitWidth>1</bitWidth> 16262 <access>read-only</access> 16263 </field> 16264 <field> 16265 <name>SUSPEND_INT</name> 16266 <description>Suspend detected.</description> 16267 <bitOffset>0</bitOffset> 16268 <bitWidth>1</bitWidth> 16269 <access>read-only</access> 16270 </field> 16271 </fields> 16272 </register> 16273 <register> 16274 <name>INTRUSBEN</name> 16275 <description>Interrupt enable for common USB interrupts.</description> 16276 <addressOffset>0x0B</addressOffset> 16277 <size>8</size> 16278 <fields> 16279 <field> 16280 <name>SOF_INT_EN</name> 16281 <description>Start of Frame.</description> 16282 <bitOffset>3</bitOffset> 16283 <bitWidth>1</bitWidth> 16284 <access>read-write</access> 16285 </field> 16286 <field> 16287 <name>RESET_INT_EN</name> 16288 <description>Bus reset detected.</description> 16289 <bitOffset>2</bitOffset> 16290 <bitWidth>1</bitWidth> 16291 <access>read-write</access> 16292 </field> 16293 <field> 16294 <name>RESUME_INT_EN</name> 16295 <description>Resume detected.</description> 16296 <bitOffset>1</bitOffset> 16297 <bitWidth>1</bitWidth> 16298 <access>read-write</access> 16299 </field> 16300 <field> 16301 <name>SUSPEND_INT_EN</name> 16302 <description>Suspend detected.</description> 16303 <bitOffset>0</bitOffset> 16304 <bitWidth>1</bitWidth> 16305 <access>read-write</access> 16306 </field> 16307 </fields> 16308 </register> 16309 <register> 16310 <name>FRAME</name> 16311 <description>Frame number.</description> 16312 <addressOffset>0x0C</addressOffset> 16313 <size>16</size> 16314 <fields> 16315 <field> 16316 <name>FRAMENUM</name> 16317 <description>Read the last received frame number, that is the 11-bit frame number received in the SOF packet.</description> 16318 <bitOffset>0</bitOffset> 16319 <bitWidth>11</bitWidth> 16320 <access>read-only</access> 16321 </field> 16322 </fields> 16323 </register> 16324 <register> 16325 <name>INDEX</name> 16326 <description>Index for banked registers.</description> 16327 <addressOffset>0x0E</addressOffset> 16328 <size>8</size> 16329 <fields> 16330 <field> 16331 <name>INDEX</name> 16332 <description>Index Register Access Selector. </description> 16333 <bitOffset>0</bitOffset> 16334 <bitWidth>4</bitWidth> 16335 <access>read-write</access> 16336 </field> 16337 </fields> 16338 </register> 16339 <register> 16340 <name>TESTMODE</name> 16341 <description>USB 2.0 test mode enable register.</description> 16342 <addressOffset>0x0F</addressOffset> 16343 <size>8</size> 16344 <fields> 16345 <field> 16346 <name>FORCE_FS</name> 16347 <description>Force USB to Full-speed after reset.</description> 16348 <bitOffset>5</bitOffset> 16349 <bitWidth>1</bitWidth> 16350 <access>read-write</access> 16351 </field> 16352 <field> 16353 <name>FORCE_HS</name> 16354 <description>Force USB to High-speed after reset.</description> 16355 <bitOffset>4</bitOffset> 16356 <bitWidth>1</bitWidth> 16357 <access>read-write</access> 16358 </field> 16359 <field> 16360 <name>TEST_PKT</name> 16361 <description>Transmit fixed test packet.</description> 16362 <bitOffset>3</bitOffset> 16363 <bitWidth>1</bitWidth> 16364 <access>read-write</access> 16365 </field> 16366 <field> 16367 <name>TEST_K</name> 16368 <description>Force USB to continuous K state.</description> 16369 <bitOffset>2</bitOffset> 16370 <bitWidth>1</bitWidth> 16371 <access>read-write</access> 16372 </field> 16373 <field> 16374 <name>TEST_J</name> 16375 <description>Force USB to continuous J state.</description> 16376 <bitOffset>1</bitOffset> 16377 <bitWidth>1</bitWidth> 16378 <access>read-write</access> 16379 </field> 16380 <field> 16381 <name>TEST_SE0_NAK</name> 16382 <description>Respond to any valid IN token with NAK.</description> 16383 <bitOffset>0</bitOffset> 16384 <bitWidth>1</bitWidth> 16385 <access>read-write</access> 16386 </field> 16387 </fields> 16388 </register> 16389 <register> 16390 <name>INMAXP</name> 16391 <description>Maximum packet size for INx endpoint (x == INDEX).</description> 16392 <addressOffset>0x10</addressOffset> 16393 <size>16</size> 16394 <fields> 16395 <field> 16396 <name>MAXPACKETSIZE</name> 16397 <description>Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9</description> 16398 <bitOffset>0</bitOffset> 16399 <bitWidth>11</bitWidth> 16400 </field> 16401 <field> 16402 <name>NUMPACKMINUS1</name> 16403 <description>Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases. </description> 16404 <bitOffset>11</bitOffset> 16405 <bitWidth>5</bitWidth> 16406 </field> 16407 </fields> 16408 </register> 16409 <register> 16410 <name>CSR0</name> 16411 <description>Control status register for EP 0 (when INDEX == 0).</description> 16412 <addressOffset>0x12</addressOffset> 16413 <size>8</size> 16414 <fields> 16415 <field> 16416 <name>SERV_SETUP_END</name> 16417 <description>Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set </description> 16418 <bitOffset>7</bitOffset> 16419 <bitWidth>1</bitWidth> 16420 <access>read-write</access> 16421 </field> 16422 <field> 16423 <name>SERV_OUTPKTRDY</name> 16424 <description>Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set.</description> 16425 <bitOffset>6</bitOffset> 16426 <bitWidth>1</bitWidth> 16427 <access>read-write</access> 16428 </field> 16429 <field> 16430 <name>SEND_STALL</name> 16431 <description>Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set. </description> 16432 <bitOffset>5</bitOffset> 16433 <bitWidth>1</bitWidth> 16434 <access>read-write</access> 16435 </field> 16436 <field> 16437 <name>SETUP_END</name> 16438 <description>Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear.</description> 16439 <bitOffset>4</bitOffset> 16440 <bitWidth>1</bitWidth> 16441 <access>read-only</access> 16442 </field> 16443 <field> 16444 <name>DATA_END</name> 16445 <description>Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet. </description> 16446 <bitOffset>3</bitOffset> 16447 <bitWidth>1</bitWidth> 16448 <access>read-write</access> 16449 </field> 16450 <field> 16451 <name>SENT_STALL</name> 16452 <description> Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear. </description> 16453 <bitOffset>2</bitOffset> 16454 <bitWidth>1</bitWidth> 16455 <access>read-write</access> 16456 </field> 16457 <field> 16458 <name>INPKTRDY</name> 16459 <description>EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared. </description> 16460 <bitOffset>1</bitOffset> 16461 <bitWidth>1</bitWidth> 16462 <access>read-write</access> 16463 </field> 16464 <field> 16465 <name>OUTPKTRDY</name> 16466 <description>EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO. </description> 16467 <bitOffset>0</bitOffset> 16468 <bitWidth>1</bitWidth> 16469 <access>read-only</access> 16470 </field> 16471 </fields> 16472 </register> 16473 <register> 16474 <name>INCSRL</name> 16475 <description>Control status lower register for INx endpoint (x == INDEX).</description> 16476 <alternateRegister>CSR0</alternateRegister> 16477 <addressOffset>0x12</addressOffset> 16478 <size>8</size> 16479 <fields> 16480 <field> 16481 <name>INCOMPTX</name> 16482 <description>Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear.</description> 16483 <bitOffset>7</bitOffset> 16484 <bitWidth>1</bitWidth> 16485 <access>read-write</access> 16486 </field> 16487 <field> 16488 <name>CLRDATATOG</name> 16489 <description>Write 1 to clear IN endpoint data-toggle to 0.</description> 16490 <bitOffset>6</bitOffset> 16491 <bitWidth>1</bitWidth> 16492 <access>read-write</access> 16493 </field> 16494 <field> 16495 <name>SENTSTALL</name> 16496 <description>Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear.</description> 16497 <bitOffset>5</bitOffset> 16498 <bitWidth>1</bitWidth> 16499 <access>read-write</access> 16500 </field> 16501 <field> 16502 <name>SENDSTALL</name> 16503 <description>Send STALL Handshake.</description> 16504 <bitOffset>4</bitOffset> 16505 <bitWidth>1</bitWidth> 16506 <access>read-only</access> 16507 <enumeratedValues> 16508 <enumeratedValue> 16509 <name>terminate</name> 16510 <description>Terminate STALL handhsake</description> 16511 <value>0</value> 16512 </enumeratedValue> 16513 <enumeratedValue> 16514 <name>respond</name> 16515 <description>Respond to an IN token with a STALL handshake</description> 16516 <value>1</value> 16517 </enumeratedValue> 16518 </enumeratedValues> 16519 </field> 16520 <field> 16521 <name>FLUSHFIFO</name> 16522 <description>Flush Next Packet from IN FIFO. Write 1 to clear</description> 16523 <bitOffset>3</bitOffset> 16524 <bitWidth>1</bitWidth> 16525 <access>read-write</access> 16526 </field> 16527 <field> 16528 <name>UNDERRUN</name> 16529 <description>Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear</description> 16530 <bitOffset>2</bitOffset> 16531 <bitWidth>1</bitWidth> 16532 <access>read-write</access> 16533 </field> 16534 <field> 16535 <name>FIFONOTEMPTY</name> 16536 <description>Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear. </description> 16537 <bitOffset>1</bitOffset> 16538 <bitWidth>1</bitWidth> 16539 <access>read-write</access> 16540 </field> 16541 <field> 16542 <name>INPKTRDY</name> 16543 <description>IN Packet Ready. Write a 1 to clear </description> 16544 <bitOffset>0</bitOffset> 16545 <bitWidth>1</bitWidth> 16546 <access>read-only</access> 16547 </field> 16548 </fields> 16549 </register> 16550 <register> 16551 <name>INCSRU</name> 16552 <description>Control status upper register for INx endpoint (x == INDEX).</description> 16553 <addressOffset>0x13</addressOffset> 16554 <size>8</size> 16555 <fields> 16556 <field> 16557 <name>AUTOSET</name> 16558 <description>Auto Set inpktrdy. </description> 16559 <bitOffset>7</bitOffset> 16560 <bitWidth>1</bitWidth> 16561 <access>read-write</access> 16562 <enumeratedValues> 16563 <enumeratedValue> 16564 <name>set</name> 16565 <description>USBHS_INCSRL_inpktrdy must be set by firmware.</description> 16566 <value>0</value> 16567 </enumeratedValue> 16568 <enumeratedValue> 16569 <name>auto</name> 16570 <description>USBHS_INCSRL_inpktrdy is automatically set. </description> 16571 <value>1</value> 16572 </enumeratedValue> 16573 </enumeratedValues> 16574 </field> 16575 <field> 16576 <name>ISO</name> 16577 <description>Isochronous Transfer Enable</description> 16578 <bitOffset>6</bitOffset> 16579 <bitWidth>1</bitWidth> 16580 <access>read-write</access> 16581 <enumeratedValues> 16582 <enumeratedValue> 16583 <name>interrupt</name> 16584 <description>Enable IN Bulk and IN interrupt transfers.</description> 16585 <value>0</value> 16586 </enumeratedValue> 16587 <enumeratedValue> 16588 <name>isochronous</name> 16589 <description>Enable IN Isochronous transfers. </description> 16590 <value>1</value> 16591 </enumeratedValue> 16592 </enumeratedValues> 16593 </field> 16594 <field> 16595 <name>MODE</name> 16596 <description> Endpoint Direction Mode.</description> 16597 <bitOffset>5</bitOffset> 16598 <bitWidth>1</bitWidth> 16599 <access>read-write</access> 16600 <enumeratedValues> 16601 <enumeratedValue> 16602 <name>out</name> 16603 <description>Endpoint direction is OUT.</description> 16604 <value>0</value> 16605 </enumeratedValue> 16606 <enumeratedValue> 16607 <name>in</name> 16608 <description>Endpoint direction is IN. </description> 16609 <value>1</value> 16610 </enumeratedValue> 16611 </enumeratedValues> 16612 </field> 16613 <field> 16614 <name>FRCDATATOG</name> 16615 <description> Force In Data - Toggle</description> 16616 <bitOffset>3</bitOffset> 16617 <bitWidth>1</bitWidth> 16618 <access>read-write</access> 16619 <enumeratedValues> 16620 <enumeratedValue> 16621 <name>received</name> 16622 <description>Toggle data-toglge only when an ACK is received.</description> 16623 <value>0</value> 16624 </enumeratedValue> 16625 <enumeratedValue> 16626 <name>dontcare</name> 16627 <description>Toggle data-toggle regardless of ACK. </description> 16628 <value>1</value> 16629 </enumeratedValue> 16630 </enumeratedValues> 16631 </field> 16632 <field> 16633 <name>DPKTBUFDIS</name> 16634 <description> Double Packet Buffering Disable </description> 16635 <bitOffset>1</bitOffset> 16636 <bitWidth>1</bitWidth> 16637 <access>read-write</access> 16638 <enumeratedValues> 16639 <enumeratedValue> 16640 <name>en</name> 16641 <description>Enable Double packet buffering.</description> 16642 <value>0</value> 16643 </enumeratedValue> 16644 <enumeratedValue> 16645 <name>dis</name> 16646 <description>Disable Double Packet Buffering.</description> 16647 <value>1</value> 16648 </enumeratedValue> 16649 </enumeratedValues> 16650 </field> 16651 </fields> 16652 </register> 16653 <register> 16654 <name>OUTMAXP</name> 16655 <description>Maximum packet size for OUTx endpoint (x == INDEX).</description> 16656 <addressOffset>0x14</addressOffset> 16657 <size>16</size> 16658 <fields> 16659 <field> 16660 <name>NUMPACKMINUS1</name> 16661 <description>Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize. </description> 16662 <bitOffset>11</bitOffset> 16663 <bitWidth>5</bitWidth> 16664 </field> 16665 <field> 16666 <name>MAXPACKETSIZE</name> 16667 <description>Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9.</description> 16668 <bitOffset>0</bitOffset> 16669 <bitWidth>11</bitWidth> 16670 </field> 16671 </fields> 16672 </register> 16673 <register> 16674 <name>OUTCSRL</name> 16675 <description>Control status lower register for OUTx endpoint (x == INDEX).</description> 16676 <addressOffset>0x16</addressOffset> 16677 <size>8</size> 16678 <fields> 16679 <field> 16680 <name>CLRDATATOG</name> 16681 <bitOffset>7</bitOffset> 16682 <bitWidth>1</bitWidth> 16683 <access>read-write</access> 16684 </field> 16685 <field> 16686 <name>SENTSTALL</name> 16687 <bitOffset>6</bitOffset> 16688 <bitWidth>1</bitWidth> 16689 <access>read-write</access> 16690 </field> 16691 <field> 16692 <name>SENDSTALL</name> 16693 <bitOffset>5</bitOffset> 16694 <bitWidth>1</bitWidth> 16695 <access>read-write</access> 16696 </field> 16697 <field> 16698 <name>FLUSHFIFO</name> 16699 <bitOffset>4</bitOffset> 16700 <bitWidth>1</bitWidth> 16701 <access>read-write</access> 16702 </field> 16703 <field> 16704 <name>DATAERROR</name> 16705 <bitOffset>3</bitOffset> 16706 <bitWidth>1</bitWidth> 16707 <access>read-only</access> 16708 </field> 16709 <field> 16710 <name>OVERRUN</name> 16711 <bitOffset>2</bitOffset> 16712 <bitWidth>1</bitWidth> 16713 <access>read-write</access> 16714 </field> 16715 <field> 16716 <name>FIFOFULL</name> 16717 <bitOffset>1</bitOffset> 16718 <bitWidth>1</bitWidth> 16719 <access>read-only</access> 16720 </field> 16721 <field> 16722 <name>OUTPKTRDY</name> 16723 <bitOffset>0</bitOffset> 16724 <bitWidth>1</bitWidth> 16725 <access>read-write</access> 16726 </field> 16727 </fields> 16728 </register> 16729 <register> 16730 <name>OUTCSRU</name> 16731 <description>Control status upper register for OUTx endpoint (x == INDEX).</description> 16732 <addressOffset>0x17</addressOffset> 16733 <size>8</size> 16734 <fields> 16735 <field> 16736 <name>AUTOCLEAR</name> 16737 <bitOffset>7</bitOffset> 16738 <bitWidth>1</bitWidth> 16739 <access>read-write</access> 16740 </field> 16741 <field> 16742 <name>ISO</name> 16743 <bitOffset>6</bitOffset> 16744 <bitWidth>1</bitWidth> 16745 <access>read-write</access> 16746 </field> 16747 <field> 16748 <name>DISNYET</name> 16749 <bitOffset>4</bitOffset> 16750 <bitWidth>1</bitWidth> 16751 <access>read-write</access> 16752 </field> 16753 <field> 16754 <name>DPKTBUFDIS</name> 16755 <bitOffset>1</bitOffset> 16756 <bitWidth>1</bitWidth> 16757 <access>read-write</access> 16758 </field> 16759 <field> 16760 <name>INCOMPRX</name> 16761 <bitOffset>0</bitOffset> 16762 <bitWidth>1</bitWidth> 16763 <access>read-only</access> 16764 </field> 16765 </fields> 16766 </register> 16767 <register> 16768 <name>COUNT0</name> 16769 <description>Number of received bytes in EP 0 FIFO (INDEX == 0).</description> 16770 <addressOffset>0x18</addressOffset> 16771 <size>16</size> 16772 <fields> 16773 <field> 16774 <name>COUNT0</name> 16775 <description>Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1 </description> 16776 <bitOffset>0</bitOffset> 16777 <bitWidth>7</bitWidth> 16778 <access>read-only</access> 16779 </field> 16780 </fields> 16781 </register> 16782 <register> 16783 <name>OUTCOUNT</name> 16784 <description>Number of received bytes in OUT EPx FIFO (x == INDEX).</description> 16785 <alternateRegister>COUNT0</alternateRegister> 16786 <addressOffset>0x18</addressOffset> 16787 <size>16</size> 16788 <fields> 16789 <field> 16790 <name>OUTCOUNT</name> 16791 <description>Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO. </description> 16792 <bitOffset>0</bitOffset> 16793 <bitWidth>13</bitWidth> 16794 <access>read-only</access> 16795 </field> 16796 </fields> 16797 </register> 16798 <register> 16799 <name>FIFO0</name> 16800 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16801 <addressOffset>0x20</addressOffset> 16802 <fields> 16803 <field> 16804 <name>USBHS_FIFO0</name> 16805 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16806 <bitOffset>0</bitOffset> 16807 <bitWidth>32</bitWidth> 16808 </field> 16809 </fields> 16810 </register> 16811 <register> 16812 <name>FIFO1</name> 16813 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16814 <addressOffset>0x24</addressOffset> 16815 <fields> 16816 <field> 16817 <name>USBHS_FIFO1</name> 16818 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16819 <bitOffset>0</bitOffset> 16820 <bitWidth>32</bitWidth> 16821 </field> 16822 </fields> 16823 </register> 16824 <register> 16825 <name>FIFO2</name> 16826 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16827 <addressOffset>0x28</addressOffset> 16828 <fields> 16829 <field> 16830 <name>USBHS_FIFO2</name> 16831 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16832 <bitOffset>0</bitOffset> 16833 <bitWidth>32</bitWidth> 16834 </field> 16835 </fields> 16836 </register> 16837 <register> 16838 <name>FIFO3</name> 16839 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16840 <addressOffset>0x2c</addressOffset> 16841 <fields> 16842 <field> 16843 <name>USBHS_FIFO3</name> 16844 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16845 <bitOffset>0</bitOffset> 16846 <bitWidth>32</bitWidth> 16847 </field> 16848 </fields> 16849 </register> 16850 <register> 16851 <name>FIFO4</name> 16852 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16853 <addressOffset>0x30</addressOffset> 16854 <fields> 16855 <field> 16856 <name>USBHS_FIFO4</name> 16857 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16858 <bitOffset>0</bitOffset> 16859 <bitWidth>32</bitWidth> 16860 </field> 16861 </fields> 16862 </register> 16863 <register> 16864 <name>FIFO5</name> 16865 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16866 <addressOffset>0x34</addressOffset> 16867 <fields> 16868 <field> 16869 <name>USBHS_FIFO5</name> 16870 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16871 <bitOffset>0</bitOffset> 16872 <bitWidth>32</bitWidth> 16873 </field> 16874 </fields> 16875 </register> 16876 <register> 16877 <name>FIFO6</name> 16878 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16879 <addressOffset>0x38</addressOffset> 16880 <fields> 16881 <field> 16882 <name>USBHS_FIFO6</name> 16883 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16884 <bitOffset>0</bitOffset> 16885 <bitWidth>32</bitWidth> 16886 </field> 16887 </fields> 16888 </register> 16889 <register> 16890 <name>FIFO7</name> 16891 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16892 <addressOffset>0x3c</addressOffset> 16893 <fields> 16894 <field> 16895 <name>USBHS_FIFO7</name> 16896 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16897 <bitOffset>0</bitOffset> 16898 <bitWidth>32</bitWidth> 16899 </field> 16900 </fields> 16901 </register> 16902 <register> 16903 <name>FIFO8</name> 16904 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16905 <addressOffset>0x40</addressOffset> 16906 <fields> 16907 <field> 16908 <name>USBHS_FIFO8</name> 16909 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16910 <bitOffset>0</bitOffset> 16911 <bitWidth>32</bitWidth> 16912 </field> 16913 </fields> 16914 </register> 16915 <register> 16916 <name>FIFO9</name> 16917 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16918 <addressOffset>0x44</addressOffset> 16919 <fields> 16920 <field> 16921 <name>USBHS_FIFO9</name> 16922 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16923 <bitOffset>0</bitOffset> 16924 <bitWidth>32</bitWidth> 16925 </field> 16926 </fields> 16927 </register> 16928 <register> 16929 <name>FIFO10</name> 16930 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16931 <addressOffset>0x48</addressOffset> 16932 <fields> 16933 <field> 16934 <name>USBHS_FIFO10</name> 16935 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16936 <bitOffset>0</bitOffset> 16937 <bitWidth>32</bitWidth> 16938 </field> 16939 </fields> 16940 </register> 16941 <register> 16942 <name>FIFO11</name> 16943 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16944 <addressOffset>0x4c</addressOffset> 16945 <fields> 16946 <field> 16947 <name>USBHS_FIFO11</name> 16948 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16949 <bitOffset>0</bitOffset> 16950 <bitWidth>32</bitWidth> 16951 </field> 16952 </fields> 16953 </register> 16954 <register> 16955 <name>FIFO12</name> 16956 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16957 <addressOffset>0x50</addressOffset> 16958 <fields> 16959 <field> 16960 <name>USBHS_FIFO12</name> 16961 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16962 <bitOffset>0</bitOffset> 16963 <bitWidth>32</bitWidth> 16964 </field> 16965 </fields> 16966 </register> 16967 <register> 16968 <name>FIFO13</name> 16969 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16970 <addressOffset>0x54</addressOffset> 16971 <fields> 16972 <field> 16973 <name>USBHS_FIFO13</name> 16974 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16975 <bitOffset>0</bitOffset> 16976 <bitWidth>32</bitWidth> 16977 </field> 16978 </fields> 16979 </register> 16980 <register> 16981 <name>FIFO14</name> 16982 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16983 <addressOffset>0x58</addressOffset> 16984 <fields> 16985 <field> 16986 <name>USBHS_FIFO14</name> 16987 <description>USBHS Endpoint FIFO Read/Write Register.</description> 16988 <bitOffset>0</bitOffset> 16989 <bitWidth>32</bitWidth> 16990 </field> 16991 </fields> 16992 </register> 16993 <register> 16994 <name>FIFO15</name> 16995 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 16996 <addressOffset>0x5c</addressOffset> 16997 <fields> 16998 <field> 16999 <name>USBHS_FIFO15</name> 17000 <description>USBHS Endpoint FIFO Read/Write Register.</description> 17001 <bitOffset>0</bitOffset> 17002 <bitWidth>32</bitWidth> 17003 </field> 17004 </fields> 17005 </register> 17006 <register> 17007 <name>HWVERS</name> 17008 <description>HWVERS</description> 17009 <addressOffset>0x6c</addressOffset> 17010 <size>16</size> 17011 <fields> 17012 <field> 17013 <name>USBHS_HWVERS</name> 17014 <description>USBHS Register.</description> 17015 <bitOffset>0</bitOffset> 17016 <bitWidth>16</bitWidth> 17017 </field> 17018 </fields> 17019 </register> 17020 <register> 17021 <name>EPINFO</name> 17022 <description>Endpoint hardware information.</description> 17023 <addressOffset>0x78</addressOffset> 17024 <size>8</size> 17025 <fields> 17026 <field> 17027 <name>OUTENDPOINTS</name> 17028 <bitOffset>4</bitOffset> 17029 <bitWidth>4</bitWidth> 17030 <access>read-only</access> 17031 </field> 17032 <field> 17033 <name>INTENDPOINTS</name> 17034 <bitOffset>0</bitOffset> 17035 <bitWidth>4</bitWidth> 17036 <access>read-only</access> 17037 </field> 17038 </fields> 17039 </register> 17040 <register> 17041 <name>RAMINFO</name> 17042 <description>RAM width information.</description> 17043 <addressOffset>0x79</addressOffset> 17044 <size>8</size> 17045 <fields> 17046 <field> 17047 <name>RAMBITS</name> 17048 <bitOffset>0</bitOffset> 17049 <bitWidth>4</bitWidth> 17050 <access>read-only</access> 17051 </field> 17052 </fields> 17053 </register> 17054 <register> 17055 <name>SOFTRESET</name> 17056 <description>Software reset register.</description> 17057 <addressOffset>0x7A</addressOffset> 17058 <size>8</size> 17059 <fields> 17060 <field> 17061 <name>RSTXS</name> 17062 <bitOffset>1</bitOffset> 17063 <bitWidth>1</bitWidth> 17064 <access>read-write</access> 17065 </field> 17066 <field> 17067 <name>RSTS</name> 17068 <bitOffset>0</bitOffset> 17069 <bitWidth>1</bitWidth> 17070 <access>read-write</access> 17071 </field> 17072 </fields> 17073 </register> 17074 <register> 17075 <name>CTUCH</name> 17076 <description>Chirp timeout timer setting.</description> 17077 <addressOffset>0x80</addressOffset> 17078 <size>16</size> 17079 <fields> 17080 <field> 17081 <name>C_T_UCH</name> 17082 <description>HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host. </description> 17083 <bitOffset>0</bitOffset> 17084 <bitWidth>16</bitWidth> 17085 </field> 17086 </fields> 17087 </register> 17088 <register> 17089 <name>CTHSRTN</name> 17090 <description>Sets delay between HS resume to UTM normal operating mode.</description> 17091 <addressOffset>0x82</addressOffset> 17092 <size>16</size> 17093 <fields> 17094 <field> 17095 <name>C_T_HSTRN</name> 17096 <description>High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation.</description> 17097 <bitOffset>0</bitOffset> 17098 <bitWidth>16</bitWidth> 17099 </field> 17100 </fields> 17101 </register> 17102 <register> 17103 <name>MXM_USB_REG_00</name> 17104 <description>MXM_USB_REG_00</description> 17105 <addressOffset>0x400</addressOffset> 17106 </register> 17107 <register> 17108 <name>M31_PHY_UTMI_RESET</name> 17109 <description>M31_PHY_UTMI_RESET</description> 17110 <addressOffset>0x404</addressOffset> 17111 </register> 17112 <register> 17113 <name>M31_PHY_UTMI_VCONTROL</name> 17114 <description>M31_PHY_UTMI_VCONTROL</description> 17115 <addressOffset>0x408</addressOffset> 17116 </register> 17117 <register> 17118 <name>M31_PHY_CLK_EN</name> 17119 <description>M31_PHY_CLK_EN</description> 17120 <addressOffset>0x40C</addressOffset> 17121 </register> 17122 <register> 17123 <name>M31_PHY_PONRST</name> 17124 <description>M31_PHY_PONRST</description> 17125 <addressOffset>0x410</addressOffset> 17126 </register> 17127 <register> 17128 <name>M31_PHY_NONCRY_RSTB</name> 17129 <description>M31_PHY_NONCRY_RSTB</description> 17130 <addressOffset>0x414</addressOffset> 17131 </register> 17132 <register> 17133 <name>M31_PHY_NONCRY_EN</name> 17134 <description>M31_PHY_NONCRY_EN</description> 17135 <addressOffset>0x418</addressOffset> 17136 </register> 17137 <register> 17138 <name>M31_PHY_U2_COMPLIANCE_EN</name> 17139 <description>M31_PHY_U2_COMPLIANCE_EN</description> 17140 <addressOffset>0x420</addressOffset> 17141 </register> 17142 <register> 17143 <name>M31_PHY_U2_COMPLIANCE_DAC_ADJ</name> 17144 <description>M31_PHY_U2_COMPLIANCE_DAC_ADJ</description> 17145 <addressOffset>0x424</addressOffset> 17146 </register> 17147 <register> 17148 <name>M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN</name> 17149 <description>M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN</description> 17150 <addressOffset>0x428</addressOffset> 17151 </register> 17152 <register> 17153 <name>M31_PHY_CLK_RDY</name> 17154 <description>M31_PHY_CLK_RDY</description> 17155 <addressOffset>0x42C</addressOffset> 17156 </register> 17157 <register> 17158 <name>M31_PHY_PLL_EN</name> 17159 <description>M31_PHY_PLL_EN</description> 17160 <addressOffset>0x430</addressOffset> 17161 </register> 17162 <register> 17163 <name>M31_PHY_BIST_OK</name> 17164 <description>M31_PHY_BIST_OK</description> 17165 <addressOffset>0x434</addressOffset> 17166 </register> 17167 <register> 17168 <name>M31_PHY_DATA_OE</name> 17169 <description>M31_PHY_DATA_OE</description> 17170 <addressOffset>0x438</addressOffset> 17171 </register> 17172 <register> 17173 <name>M31_PHY_OSCOUTEN</name> 17174 <description>M31_PHY_OSCOUTEN</description> 17175 <addressOffset>0x43C</addressOffset> 17176 </register> 17177 <register> 17178 <name>M31_PHY_LPM_ALIVE</name> 17179 <description>M31_PHY_LPM_ALIVE</description> 17180 <addressOffset>0x440</addressOffset> 17181 </register> 17182 <register> 17183 <name>M31_PHY_HS_BIST_MODE</name> 17184 <description>M31_PHY_HS_BIST_MODE</description> 17185 <addressOffset>0x444</addressOffset> 17186 </register> 17187 <register> 17188 <name>M31_PHY_CORECLKIN</name> 17189 <description>M31_PHY_CORECLKIN</description> 17190 <addressOffset>0x448</addressOffset> 17191 </register> 17192 <register> 17193 <name>M31_PHY_XTLSEL</name> 17194 <description>M31_PHY_XTLSEL</description> 17195 <addressOffset>0x44C</addressOffset> 17196 </register> 17197 <register> 17198 <name>M31_PHY_LS_EN</name> 17199 <description>M31_PHY_LS_EN</description> 17200 <addressOffset>0x450</addressOffset> 17201 </register> 17202 <register> 17203 <name>M31_PHY_DEBUG_SEL</name> 17204 <description>M31_PHY_DEBUG_SEL</description> 17205 <addressOffset>0x454</addressOffset> 17206 </register> 17207 <register> 17208 <name>M31_PHY_DEBUG_OUT</name> 17209 <description>M31_PHY_DEBUG_OUT</description> 17210 <addressOffset>0x458</addressOffset> 17211 </register> 17212 <register> 17213 <name>M31_PHY_OUTCLKSEL</name> 17214 <description>M31_PHY_OUTCLKSEL</description> 17215 <addressOffset>0x45C</addressOffset> 17216 </register> 17217 <register> 17218 <name>M31_PHY_XCFGI_31_0</name> 17219 <description>M31_PHY_XCFGI_31_0</description> 17220 <addressOffset>0x460</addressOffset> 17221 </register> 17222 <register> 17223 <name>M31_PHY_XCFGI_63_32</name> 17224 <description>M31_PHY_XCFGI_63_32</description> 17225 <addressOffset>0x464</addressOffset> 17226 </register> 17227 <register> 17228 <name>M31_PHY_XCFGI_95_64</name> 17229 <description>M31_PHY_XCFGI_95_64</description> 17230 <addressOffset>0x468</addressOffset> 17231 </register> 17232 <register> 17233 <name>M31_PHY_XCFGI_127_96</name> 17234 <description>M31_PHY_XCFGI_127_96</description> 17235 <addressOffset>0x46C</addressOffset> 17236 </register> 17237 <register> 17238 <name>M31_PHY_XCFGI_137_128</name> 17239 <description>M31_PHY_XCFGI_137_128</description> 17240 <addressOffset>0x470</addressOffset> 17241 </register> 17242 <register> 17243 <name>M31_PHY_XCFG_HS_COARSE_TUNE_NUM</name> 17244 <description>M31_PHY_XCFG_HS_COARSE_TUNE_NUM</description> 17245 <addressOffset>0x474</addressOffset> 17246 </register> 17247 <register> 17248 <name>M31_PHY_XCFG_HS_FINE_TUNE_NUM</name> 17249 <description>M31_PHY_XCFG_HS_FINE_TUNE_NUM</description> 17250 <addressOffset>0x478</addressOffset> 17251 </register> 17252 <register> 17253 <name>M31_PHY_XCFG_FS_COARSE_TUNE_NUM</name> 17254 <description>M31_PHY_XCFG_FS_COARSE_TUNE_NUM</description> 17255 <addressOffset>0x47C</addressOffset> 17256 </register> 17257 <register> 17258 <name>M31_PHY_XCFG_FS_FINE_TUNE_NUM</name> 17259 <description>M31_PHY_XCFG_FS_FINE_TUNE_NUM</description> 17260 <addressOffset>0x480</addressOffset> 17261 </register> 17262 <register> 17263 <name>M31_PHY_XCFG_LOCK_RANGE_MAX</name> 17264 <description>M31_PHY_XCFG_LOCK_RANGE_MAX</description> 17265 <addressOffset>0x484</addressOffset> 17266 </register> 17267 <register> 17268 <name>M31_PHY_XCFGI_LOCK_RANGE_MIN</name> 17269 <description>M31_PHY_XCFGI_LOCK_RANGE_MIN</description> 17270 <addressOffset>0x488</addressOffset> 17271 </register> 17272 <register> 17273 <name>M31_PHY_XCFG_OB_RSEL</name> 17274 <description>M31_PHY_XCFG_OB_RSEL</description> 17275 <addressOffset>0x48C</addressOffset> 17276 </register> 17277 <register> 17278 <name>M31_PHY_XCFG_OC_RSEL</name> 17279 <description>M31_PHY_XCFG_OC_RSEL</description> 17280 <addressOffset>0x490</addressOffset> 17281 </register> 17282 <register> 17283 <name>M31_PHY_XCFGO</name> 17284 <description>M31_PHY_XCFGO</description> 17285 <addressOffset>0x494</addressOffset> 17286 </register> 17287 <register> 17288 <name>MXM_INT</name> 17289 <description>USB Added Maxim Interrupt Flag Register.</description> 17290 <addressOffset>0x498</addressOffset> 17291 <fields> 17292 <field> 17293 <name>VBUS</name> 17294 <description>VBUS</description> 17295 <bitOffset>0</bitOffset> 17296 <bitWidth>1</bitWidth> 17297 </field> 17298 <field> 17299 <name>NOVBUS</name> 17300 <description>NOVBUS</description> 17301 <bitOffset>1</bitOffset> 17302 <bitWidth>1</bitWidth> 17303 </field> 17304 </fields> 17305 </register> 17306 <register> 17307 <name>MXM_INT_EN</name> 17308 <description>USB Added Maxim Interrupt Enable Register.</description> 17309 <addressOffset>0x49C</addressOffset> 17310 <fields> 17311 <field> 17312 <name>VBUS</name> 17313 <description>VBUS</description> 17314 <bitOffset>0</bitOffset> 17315 <bitWidth>1</bitWidth> 17316 </field> 17317 <field> 17318 <name>NOVBUS</name> 17319 <description>NOVBUS</description> 17320 <bitOffset>1</bitOffset> 17321 <bitWidth>1</bitWidth> 17322 </field> 17323 </fields> 17324 </register> 17325 <register> 17326 <name>MXM_SUSPEND</name> 17327 <description>USB Added Maxim Suspend Register.</description> 17328 <addressOffset>0x4A0</addressOffset> 17329 <fields> 17330 <field> 17331 <name>SEL</name> 17332 <description>Suspend register</description> 17333 <bitOffset>0</bitOffset> 17334 <bitWidth>1</bitWidth> 17335 </field> 17336 </fields> 17337 </register> 17338 <register> 17339 <name>MXM_REG_A4</name> 17340 <description>USB Added Maxim Power Status Register</description> 17341 <addressOffset>0x4A4</addressOffset> 17342 <fields> 17343 <field> 17344 <name>VRST_VDDB_N_A</name> 17345 <description>VRST_VDDB_N_A</description> 17346 <bitOffset>0</bitOffset> 17347 <bitWidth>1</bitWidth> 17348 </field> 17349 </fields> 17350 </register> 17351 </registers> 17352 </peripheral> 17353<!--USBHS USB 2.0 High-speed Controller.--> 17354 <peripheral> 17355 <name>WDT</name> 17356 <description>Windowed Watchdog Timer</description> 17357 <baseAddress>0x40003000</baseAddress> 17358 <addressBlock> 17359 <offset>0x00</offset> 17360 <size>0x0400</size> 17361 <usage>registers</usage> 17362 </addressBlock> 17363 <interrupt> 17364 <name>WWDT</name> 17365 <value>1</value> 17366 </interrupt> 17367 <registers> 17368 <register> 17369 <name>CTRL</name> 17370 <description>Watchdog Timer Control Register.</description> 17371 <addressOffset>0x00</addressOffset> 17372 <access>read-write</access> 17373 <fields> 17374 <field> 17375 <name>INT_LATE_VAL</name> 17376 <description>Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 17377 <bitOffset>0</bitOffset> 17378 <bitWidth>4</bitWidth> 17379 <enumeratedValues> 17380 <enumeratedValue> 17381 <name>wdt2pow31</name> 17382 <description>2**31 clock cycles.</description> 17383 <value>0</value> 17384 </enumeratedValue> 17385 <enumeratedValue> 17386 <name>wdt2pow30</name> 17387 <description>2**30 clock cycles.</description> 17388 <value>1</value> 17389 </enumeratedValue> 17390 <enumeratedValue> 17391 <name>wdt2pow29</name> 17392 <description>2**29 clock cycles.</description> 17393 <value>2</value> 17394 </enumeratedValue> 17395 <enumeratedValue> 17396 <name>wdt2pow28</name> 17397 <description>2**28 clock cycles.</description> 17398 <value>3</value> 17399 </enumeratedValue> 17400 <enumeratedValue> 17401 <name>wdt2pow27</name> 17402 <description>2^27 clock cycles.</description> 17403 <value>4</value> 17404 </enumeratedValue> 17405 <enumeratedValue> 17406 <name>wdt2pow26</name> 17407 <description>2**26 clock cycles.</description> 17408 <value>5</value> 17409 </enumeratedValue> 17410 <enumeratedValue> 17411 <name>wdt2pow25</name> 17412 <description>2**25 clock cycles.</description> 17413 <value>6</value> 17414 </enumeratedValue> 17415 <enumeratedValue> 17416 <name>wdt2pow24</name> 17417 <description>2**24 clock cycles.</description> 17418 <value>7</value> 17419 </enumeratedValue> 17420 <enumeratedValue> 17421 <name>wdt2pow23</name> 17422 <description>2**23 clock cycles.</description> 17423 <value>8</value> 17424 </enumeratedValue> 17425 <enumeratedValue> 17426 <name>wdt2pow22</name> 17427 <description>2**22 clock cycles.</description> 17428 <value>9</value> 17429 </enumeratedValue> 17430 <enumeratedValue> 17431 <name>wdt2pow21</name> 17432 <description>2**21 clock cycles.</description> 17433 <value>10</value> 17434 </enumeratedValue> 17435 <enumeratedValue> 17436 <name>wdt2pow20</name> 17437 <description>2**20 clock cycles.</description> 17438 <value>11</value> 17439 </enumeratedValue> 17440 <enumeratedValue> 17441 <name>wdt2pow19</name> 17442 <description>2**19 clock cycles.</description> 17443 <value>12</value> 17444 </enumeratedValue> 17445 <enumeratedValue> 17446 <name>wdt2pow18</name> 17447 <description>2**18 clock cycles.</description> 17448 <value>13</value> 17449 </enumeratedValue> 17450 <enumeratedValue> 17451 <name>wdt2pow17</name> 17452 <description>2**17 clock cycles.</description> 17453 <value>14</value> 17454 </enumeratedValue> 17455 <enumeratedValue> 17456 <name>wdt2pow16</name> 17457 <description>2**16 clock cycles.</description> 17458 <value>15</value> 17459 </enumeratedValue> 17460 </enumeratedValues> 17461 </field> 17462 <field> 17463 <name>RST_LATE_VAL</name> 17464 <description>Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 17465 <bitOffset>4</bitOffset> 17466 <bitWidth>4</bitWidth> 17467 <enumeratedValues> 17468 <enumeratedValue> 17469 <name>wdt2pow31</name> 17470 <description>2**31 clock cycles.</description> 17471 <value>0</value> 17472 </enumeratedValue> 17473 <enumeratedValue> 17474 <name>wdt2pow30</name> 17475 <description>2**30 clock cycles.</description> 17476 <value>1</value> 17477 </enumeratedValue> 17478 <enumeratedValue> 17479 <name>wdt2pow29</name> 17480 <description>2**29 clock cycles.</description> 17481 <value>2</value> 17482 </enumeratedValue> 17483 <enumeratedValue> 17484 <name>wdt2pow28</name> 17485 <description>2**28 clock cycles.</description> 17486 <value>3</value> 17487 </enumeratedValue> 17488 <enumeratedValue> 17489 <name>wdt2pow27</name> 17490 <description>2^27 clock cycles.</description> 17491 <value>4</value> 17492 </enumeratedValue> 17493 <enumeratedValue> 17494 <name>wdt2pow26</name> 17495 <description>2**26 clock cycles.</description> 17496 <value>5</value> 17497 </enumeratedValue> 17498 <enumeratedValue> 17499 <name>wdt2pow25</name> 17500 <description>2**25 clock cycles.</description> 17501 <value>6</value> 17502 </enumeratedValue> 17503 <enumeratedValue> 17504 <name>wdt2pow24</name> 17505 <description>2**24 clock cycles.</description> 17506 <value>7</value> 17507 </enumeratedValue> 17508 <enumeratedValue> 17509 <name>wdt2pow23</name> 17510 <description>2**23 clock cycles.</description> 17511 <value>8</value> 17512 </enumeratedValue> 17513 <enumeratedValue> 17514 <name>wdt2pow22</name> 17515 <description>2**22 clock cycles.</description> 17516 <value>9</value> 17517 </enumeratedValue> 17518 <enumeratedValue> 17519 <name>wdt2pow21</name> 17520 <description>2**21 clock cycles.</description> 17521 <value>10</value> 17522 </enumeratedValue> 17523 <enumeratedValue> 17524 <name>wdt2pow20</name> 17525 <description>2**20 clock cycles.</description> 17526 <value>11</value> 17527 </enumeratedValue> 17528 <enumeratedValue> 17529 <name>wdt2pow19</name> 17530 <description>2**19 clock cycles.</description> 17531 <value>12</value> 17532 </enumeratedValue> 17533 <enumeratedValue> 17534 <name>wdt2pow18</name> 17535 <description>2**18 clock cycles.</description> 17536 <value>13</value> 17537 </enumeratedValue> 17538 <enumeratedValue> 17539 <name>wdt2pow17</name> 17540 <description>2**17 clock cycles.</description> 17541 <value>14</value> 17542 </enumeratedValue> 17543 <enumeratedValue> 17544 <name>wdt2pow16</name> 17545 <description>2**16 clock cycles.</description> 17546 <value>15</value> 17547 </enumeratedValue> 17548 </enumeratedValues> 17549 </field> 17550 <field> 17551 <name>EN</name> 17552 <description>Windowed Watchdog Timer Enable.</description> 17553 <bitOffset>8</bitOffset> 17554 <bitWidth>1</bitWidth> 17555 <enumeratedValues> 17556 <enumeratedValue> 17557 <name>dis</name> 17558 <description>Disable.</description> 17559 <value>0</value> 17560 </enumeratedValue> 17561 <enumeratedValue> 17562 <name>en</name> 17563 <description>Enable.</description> 17564 <value>1</value> 17565 </enumeratedValue> 17566 </enumeratedValues> 17567 </field> 17568 <field> 17569 <name>INT_LATE</name> 17570 <description>Windowed Watchdog Timer Interrupt Flag Too Late.</description> 17571 <bitOffset>9</bitOffset> 17572 <bitWidth>1</bitWidth> 17573 <enumeratedValues> 17574 <usage>read-write</usage> 17575 <enumeratedValue> 17576 <name>inactive</name> 17577 <description>No interrupt is pending.</description> 17578 <value>0</value> 17579 </enumeratedValue> 17580 <enumeratedValue> 17581 <name>pending</name> 17582 <description>An interrupt is pending.</description> 17583 <value>1</value> 17584 </enumeratedValue> 17585 </enumeratedValues> 17586 </field> 17587 <field> 17588 <name>WDT_INT_EN</name> 17589 <description>Windowed Watchdog Timer Interrupt Enable.</description> 17590 <bitOffset>10</bitOffset> 17591 <bitWidth>1</bitWidth> 17592 <enumeratedValues> 17593 <enumeratedValue> 17594 <name>dis</name> 17595 <description>Disable.</description> 17596 <value>0</value> 17597 </enumeratedValue> 17598 <enumeratedValue> 17599 <name>en</name> 17600 <description>Enable.</description> 17601 <value>1</value> 17602 </enumeratedValue> 17603 </enumeratedValues> 17604 </field> 17605 <field> 17606 <name>WDT_RST_EN</name> 17607 <description>Windowed Watchdog Timer Reset Enable.</description> 17608 <bitOffset>11</bitOffset> 17609 <bitWidth>1</bitWidth> 17610 <enumeratedValues> 17611 <enumeratedValue> 17612 <name>dis</name> 17613 <description>Disable.</description> 17614 <value>0</value> 17615 </enumeratedValue> 17616 <enumeratedValue> 17617 <name>en</name> 17618 <description>Enable.</description> 17619 <value>1</value> 17620 </enumeratedValue> 17621 </enumeratedValues> 17622 </field> 17623 <field> 17624 <name>INT_EARLY</name> 17625 <description>Windowed Watchdog Timer Interrupt Flag Too Soon.</description> 17626 <bitOffset>12</bitOffset> 17627 <bitWidth>1</bitWidth> 17628 <enumeratedValues> 17629 <usage>read-write</usage> 17630 <enumeratedValue> 17631 <name>inactive</name> 17632 <description>No interrupt is pending.</description> 17633 <value>0</value> 17634 </enumeratedValue> 17635 <enumeratedValue> 17636 <name>pending</name> 17637 <description>An interrupt is pending.</description> 17638 <value>1</value> 17639 </enumeratedValue> 17640 </enumeratedValues> 17641 </field> 17642 <field> 17643 <name>INT_EARLY_VAL</name> 17644 <description>Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 17645 <bitOffset>16</bitOffset> 17646 <bitWidth>4</bitWidth> 17647 <enumeratedValues> 17648 <enumeratedValue> 17649 <name>wdt2pow31</name> 17650 <description>2**31 clock cycles.</description> 17651 <value>0</value> 17652 </enumeratedValue> 17653 <enumeratedValue> 17654 <name>wdt2pow30</name> 17655 <description>2**30 clock cycles.</description> 17656 <value>1</value> 17657 </enumeratedValue> 17658 <enumeratedValue> 17659 <name>wdt2pow29</name> 17660 <description>2**29 clock cycles.</description> 17661 <value>2</value> 17662 </enumeratedValue> 17663 <enumeratedValue> 17664 <name>wdt2pow28</name> 17665 <description>2**28 clock cycles.</description> 17666 <value>3</value> 17667 </enumeratedValue> 17668 <enumeratedValue> 17669 <name>wdt2pow27</name> 17670 <description>2^27 clock cycles.</description> 17671 <value>4</value> 17672 </enumeratedValue> 17673 <enumeratedValue> 17674 <name>wdt2pow26</name> 17675 <description>2**26 clock cycles.</description> 17676 <value>5</value> 17677 </enumeratedValue> 17678 <enumeratedValue> 17679 <name>wdt2pow25</name> 17680 <description>2**25 clock cycles.</description> 17681 <value>6</value> 17682 </enumeratedValue> 17683 <enumeratedValue> 17684 <name>wdt2pow24</name> 17685 <description>2**24 clock cycles.</description> 17686 <value>7</value> 17687 </enumeratedValue> 17688 <enumeratedValue> 17689 <name>wdt2pow23</name> 17690 <description>2**23 clock cycles.</description> 17691 <value>8</value> 17692 </enumeratedValue> 17693 <enumeratedValue> 17694 <name>wdt2pow22</name> 17695 <description>2**22 clock cycles.</description> 17696 <value>9</value> 17697 </enumeratedValue> 17698 <enumeratedValue> 17699 <name>wdt2pow21</name> 17700 <description>2**21 clock cycles.</description> 17701 <value>10</value> 17702 </enumeratedValue> 17703 <enumeratedValue> 17704 <name>wdt2pow20</name> 17705 <description>2**20 clock cycles.</description> 17706 <value>11</value> 17707 </enumeratedValue> 17708 <enumeratedValue> 17709 <name>wdt2pow19</name> 17710 <description>2**19 clock cycles.</description> 17711 <value>12</value> 17712 </enumeratedValue> 17713 <enumeratedValue> 17714 <name>wdt2pow18</name> 17715 <description>2**18 clock cycles.</description> 17716 <value>13</value> 17717 </enumeratedValue> 17718 <enumeratedValue> 17719 <name>wdt2pow17</name> 17720 <description>2**17 clock cycles.</description> 17721 <value>14</value> 17722 </enumeratedValue> 17723 <enumeratedValue> 17724 <name>wdt2pow16</name> 17725 <description>2**16 clock cycles.</description> 17726 <value>15</value> 17727 </enumeratedValue> 17728 </enumeratedValues> 17729 </field> 17730 <field> 17731 <name>RST_EARLY_VAL</name> 17732 <description>Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 17733 <bitOffset>20</bitOffset> 17734 <bitWidth>4</bitWidth> 17735 <enumeratedValues> 17736 <enumeratedValue> 17737 <name>wdt2pow31</name> 17738 <description>2**31 clock cycles.</description> 17739 <value>0</value> 17740 </enumeratedValue> 17741 <enumeratedValue> 17742 <name>wdt2pow30</name> 17743 <description>2**30 clock cycles.</description> 17744 <value>1</value> 17745 </enumeratedValue> 17746 <enumeratedValue> 17747 <name>wdt2pow29</name> 17748 <description>2**29 clock cycles.</description> 17749 <value>2</value> 17750 </enumeratedValue> 17751 <enumeratedValue> 17752 <name>wdt2pow28</name> 17753 <description>2**28 clock cycles.</description> 17754 <value>3</value> 17755 </enumeratedValue> 17756 <enumeratedValue> 17757 <name>wdt2pow27</name> 17758 <description>2^27 clock cycles.</description> 17759 <value>4</value> 17760 </enumeratedValue> 17761 <enumeratedValue> 17762 <name>wdt2pow26</name> 17763 <description>2**26 clock cycles.</description> 17764 <value>5</value> 17765 </enumeratedValue> 17766 <enumeratedValue> 17767 <name>wdt2pow25</name> 17768 <description>2**25 clock cycles.</description> 17769 <value>6</value> 17770 </enumeratedValue> 17771 <enumeratedValue> 17772 <name>wdt2pow24</name> 17773 <description>2**24 clock cycles.</description> 17774 <value>7</value> 17775 </enumeratedValue> 17776 <enumeratedValue> 17777 <name>wdt2pow23</name> 17778 <description>2**23 clock cycles.</description> 17779 <value>8</value> 17780 </enumeratedValue> 17781 <enumeratedValue> 17782 <name>wdt2pow22</name> 17783 <description>2**22 clock cycles.</description> 17784 <value>9</value> 17785 </enumeratedValue> 17786 <enumeratedValue> 17787 <name>wdt2pow21</name> 17788 <description>2**21 clock cycles.</description> 17789 <value>10</value> 17790 </enumeratedValue> 17791 <enumeratedValue> 17792 <name>wdt2pow20</name> 17793 <description>2**20 clock cycles.</description> 17794 <value>11</value> 17795 </enumeratedValue> 17796 <enumeratedValue> 17797 <name>wdt2pow19</name> 17798 <description>2**19 clock cycles.</description> 17799 <value>12</value> 17800 </enumeratedValue> 17801 <enumeratedValue> 17802 <name>wdt2pow18</name> 17803 <description>2**18 clock cycles.</description> 17804 <value>13</value> 17805 </enumeratedValue> 17806 <enumeratedValue> 17807 <name>wdt2pow17</name> 17808 <description>2**17 clock cycles.</description> 17809 <value>14</value> 17810 </enumeratedValue> 17811 <enumeratedValue> 17812 <name>wdt2pow16</name> 17813 <description>2**16 clock cycles.</description> 17814 <value>15</value> 17815 </enumeratedValue> 17816 </enumeratedValues> 17817 </field> 17818 <field> 17819 <name>CLKRDY_IE</name> 17820 <description>Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock.</description> 17821 <bitOffset>27</bitOffset> 17822 <bitWidth>1</bitWidth> 17823 </field> 17824 <field> 17825 <name>CLKRDY</name> 17826 <description>Clock Status.</description> 17827 <bitOffset>28</bitOffset> 17828 <bitWidth>1</bitWidth> 17829 </field> 17830 <field> 17831 <name>WIN_EN</name> 17832 <description>Enables the Windowed Watchdog Function.</description> 17833 <bitOffset>29</bitOffset> 17834 <bitWidth>1</bitWidth> 17835 <enumeratedValues> 17836 <enumeratedValue> 17837 <name>dis</name> 17838 <description>Windowed Mode Disabled (i.e. Compatibility Mode).</description> 17839 <value>0</value> 17840 </enumeratedValue> 17841 <enumeratedValue> 17842 <name>en</name> 17843 <description>Windowed Mode Enabled.</description> 17844 <value>1</value> 17845 </enumeratedValue> 17846 </enumeratedValues> 17847 </field> 17848 <field> 17849 <name>RST_EARLY</name> 17850 <description>Windowed Watchdog Timer Reset Flag Too Soon.</description> 17851 <bitOffset>30</bitOffset> 17852 <bitWidth>1</bitWidth> 17853 <enumeratedValues> 17854 <usage>read-write</usage> 17855 <enumeratedValue> 17856 <name>noEvent</name> 17857 <description>The event has not occurred.</description> 17858 <value>0</value> 17859 </enumeratedValue> 17860 <enumeratedValue> 17861 <name>occurred</name> 17862 <description>The event has occurred.</description> 17863 <value>1</value> 17864 </enumeratedValue> 17865 </enumeratedValues> 17866 </field> 17867 <field> 17868 <name>RST_LATE</name> 17869 <description>Windowed Watchdog Timer Reset Flag Too Late.</description> 17870 <bitOffset>31</bitOffset> 17871 <bitWidth>1</bitWidth> 17872 <enumeratedValues> 17873 <usage>read-write</usage> 17874 <enumeratedValue> 17875 <name>noEvent</name> 17876 <description>The event has not occurred.</description> 17877 <value>0</value> 17878 </enumeratedValue> 17879 <enumeratedValue> 17880 <name>occurred</name> 17881 <description>The event has occurred.</description> 17882 <value>1</value> 17883 </enumeratedValue> 17884 </enumeratedValues> 17885 </field> 17886 </fields> 17887 </register> 17888 <register> 17889 <name>RST</name> 17890 <description>Windowed Watchdog Timer Reset Register.</description> 17891 <addressOffset>0x04</addressOffset> 17892 <access>write-only</access> 17893 <fields> 17894 <field> 17895 <name>RESET</name> 17896 <description>Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled.</description> 17897 <bitOffset>0</bitOffset> 17898 <bitWidth>8</bitWidth> 17899 <enumeratedValues> 17900 <enumeratedValue> 17901 <name>seq0</name> 17902 <description>The first value to be written to reset the WDT.</description> 17903 <value>0x000000A5</value> 17904 </enumeratedValue> 17905 <enumeratedValue> 17906 <name>seq1</name> 17907 <description>The second value to be written to reset the WDT.</description> 17908 <value>0x0000005A</value> 17909 </enumeratedValue> 17910 </enumeratedValues> 17911 </field> 17912 </fields> 17913 </register> 17914 <register> 17915 <name>CLKSEL</name> 17916 <description>Windowed Watchdog Timer Clock Select Register.</description> 17917 <addressOffset>0x08</addressOffset> 17918 <access>read-write</access> 17919 <fields> 17920 <field> 17921 <name>SOURCE</name> 17922 <description>WWDT Clock Selection Register.</description> 17923 <bitOffset>0</bitOffset> 17924 <bitWidth>3</bitWidth> 17925 </field> 17926 </fields> 17927 </register> 17928 <register> 17929 <name>CNT</name> 17930 <description>Windowed Watchdog Timer Count Register.</description> 17931 <addressOffset>0x0C</addressOffset> 17932 <access>read-only</access> 17933 <fields> 17934 <field> 17935 <name>COUNT</name> 17936 <description>Current Value of the Windowed Watchdog Timer Counter.</description> 17937 <bitOffset>0</bitOffset> 17938 <bitWidth>32</bitWidth> 17939 </field> 17940 </fields> 17941 </register> 17942 </registers> 17943 </peripheral> 17944<!--WDT Windowed Watchdog Timer--> 17945 <peripheral derivedFrom="WDT"> 17946 <name>WDT1</name> 17947 <description>Windowed Watchdog Timer 1</description> 17948 <baseAddress>0x40003400</baseAddress> 17949 <interrupt> 17950 <name>WDT1</name> 17951 <description>WDT1 IRQ</description> 17952 <value>57</value> 17953 </interrupt> 17954 </peripheral> 17955<!--WDT1 Windowed Watchdog Timer 1--> 17956 <peripheral> 17957 <name>SKBD</name> 17958 <description>Secure Keyboard</description> 17959 <baseAddress>0x40032000</baseAddress> 17960 <addressBlock> 17961 <offset>0x00</offset> 17962 <size>0x1000</size> 17963 <usage>registers</usage> 17964 </addressBlock> 17965 <interrupt> 17966 <name>Secure_Keypad</name> 17967 <description>Secure Keypad interrupt</description> 17968 <value>19</value> 17969 </interrupt> 17970 <registers> 17971 <register> 17972 <name>CTRL0</name> 17973 <description>Input Output Select Bits. Each bit of IOSEL selects the pin direction for the corresponding KBDIO pin. If IOSEL[0] = 1, KBDIO0 is an output.</description> 17974 <addressOffset>0x00</addressOffset> 17975 <fields> 17976 <field> 17977 <name>KBDIO0</name> 17978 <description>Input Output Select for KBDIO0 pin.</description> 17979 <bitOffset>0</bitOffset> 17980 <bitWidth>1</bitWidth> 17981 <enumeratedValues> 17982 <enumeratedValue> 17983 <name>input</name> 17984 <description>Input</description> 17985 <value>0</value> 17986 </enumeratedValue> 17987 <enumeratedValue> 17988 <name>output</name> 17989 <description>Output</description> 17990 <value>1</value> 17991 </enumeratedValue> 17992 </enumeratedValues> 17993 </field> 17994 <field derivedFrom="KBDIO0"> 17995 <name>KBDIO1</name> 17996 <description>Input Output Select for KBDIO1 pin.</description> 17997 <bitOffset>1</bitOffset> 17998 <bitWidth>1</bitWidth> 17999 </field> 18000 <field derivedFrom="KBDIO0"> 18001 <name>KBDIO2</name> 18002 <description>Input Output Select for KBDIO2 pin.</description> 18003 <bitOffset>2</bitOffset> 18004 <bitWidth>1</bitWidth> 18005 </field> 18006 <field derivedFrom="KBDIO0"> 18007 <name>KBDIO3</name> 18008 <description>Input Output Select for KBDIO3 pin.</description> 18009 <bitOffset>3</bitOffset> 18010 <bitWidth>1</bitWidth> 18011 </field> 18012 <field derivedFrom="KBDIO0"> 18013 <name>KBDIO4</name> 18014 <description>Input Output Select for KBDIO4 pin.</description> 18015 <bitOffset>4</bitOffset> 18016 <bitWidth>1</bitWidth> 18017 </field> 18018 <field derivedFrom="KBDIO0"> 18019 <name>KBDIO5</name> 18020 <description>Input Output Select for KBDIO5 pin.</description> 18021 <bitOffset>5</bitOffset> 18022 <bitWidth>1</bitWidth> 18023 </field> 18024 <field derivedFrom="KBDIO0"> 18025 <name>KBDIO6</name> 18026 <description>Input Output Select for KBDIO6 pin.</description> 18027 <bitOffset>6</bitOffset> 18028 <bitWidth>1</bitWidth> 18029 </field> 18030 <field derivedFrom="KBDIO0"> 18031 <name>KBDIO7</name> 18032 <description>Input Output Select for KBDIO7 pin.</description> 18033 <bitOffset>7</bitOffset> 18034 <bitWidth>1</bitWidth> 18035 </field> 18036 <field derivedFrom="KBDIO0"> 18037 <name>KBDIO8</name> 18038 <description>Input Output Select for KBDIO8 pin.</description> 18039 <bitOffset>8</bitOffset> 18040 <bitWidth>1</bitWidth> 18041 </field> 18042 <field derivedFrom="KBDIO0"> 18043 <name>KBDIO9</name> 18044 <description>Input Output Select for KBDIO9 pin.</description> 18045 <bitOffset>9</bitOffset> 18046 <bitWidth>1</bitWidth> 18047 </field> 18048 </fields> 18049 </register> 18050 <register> 18051 <name>CTRL1</name> 18052 <description>Control Register 1</description> 18053 <addressOffset>0x04</addressOffset> 18054 <fields> 18055 <field> 18056 <name>AUTOSCAN_EN</name> 18057 <description>Automatic Keyboard Scan Enable</description> 18058 <bitOffset>0</bitOffset> 18059 <bitWidth>1</bitWidth> 18060 <enumeratedValues> 18061 <enumeratedValue> 18062 <name>disable</name> 18063 <description>Disable</description> 18064 <value>0</value> 18065 </enumeratedValue> 18066 <enumeratedValue> 18067 <name>enable</name> 18068 <description>Enable</description> 18069 <value>1</value> 18070 </enumeratedValue> 18071 </enumeratedValues> 18072 </field> 18073 <field derivedFrom="AUTOSCAN_EN"> 18074 <name>AUTOCLEAR</name> 18075 <description>Auto Clear Bit</description> 18076 <bitOffset>1</bitOffset> 18077 <bitWidth>1</bitWidth> 18078 </field> 18079 <field> 18080 <name>OUTNUM</name> 18081 <description>Output Number. Number of KBDIO pins selected as outputs. NOTE: 18082 Output pins must be allocated contiguously starting with KBDIO0 and continuing through to KBDIO7.</description> 18083 <bitOffset>8</bitOffset> 18084 <bitWidth>4</bitWidth> 18085 </field> 18086 <field> 18087 <name>DBTM</name> 18088 <description>Debounce Time. Number of milliseconds a keypress event must be active before it is considered actual. NOTE: 18089 Debounce time values based on system running from an external 12MHz clock source with PLL0 enabled. Other external crystal values will cause the debounce time to scale linearly.</description> 18090 <bitOffset>13</bitOffset> 18091 <bitWidth>3</bitWidth> 18092 <enumeratedValues> 18093 <enumeratedValue> 18094 <name>time4ms</name> 18095 <description>4.1 ms</description> 18096 <value>0</value> 18097 </enumeratedValue> 18098 <enumeratedValue> 18099 <name>time5ms</name> 18100 <description>5.3 ms</description> 18101 <value>1</value> 18102 </enumeratedValue> 18103 <enumeratedValue> 18104 <name>time6ms</name> 18105 <description>6.5 ms</description> 18106 <value>2</value> 18107 </enumeratedValue> 18108 <enumeratedValue> 18109 <name>time7ms</name> 18110 <description>7.6 ms</description> 18111 <value>3</value> 18112 </enumeratedValue> 18113 <enumeratedValue> 18114 <name>time8ms</name> 18115 <description>8.8 ms</description> 18116 <value>4</value> 18117 </enumeratedValue> 18118 <enumeratedValue> 18119 <name>time10ms</name> 18120 <description>10.0 ms</description> 18121 <value>5</value> 18122 </enumeratedValue> 18123 <enumeratedValue> 18124 <name>time11ms</name> 18125 <description>11.2 ms</description> 18126 <value>6</value> 18127 </enumeratedValue> 18128 <enumeratedValue> 18129 <name>time12ms</name> 18130 <description>12.3 ms</description> 18131 <value>7</value> 18132 </enumeratedValue> 18133 </enumeratedValues> 18134 </field> 18135 </fields> 18136 </register> 18137 <register> 18138 <name>STATUS</name> 18139 <description>Status Register</description> 18140 <addressOffset>0x08</addressOffset> 18141 <access>read-only</access> 18142 <fields> 18143 <field> 18144 <name>BUSY</name> 18145 <description>Busy bit. This bit is set by hardware when the automatic keyboard scan is enabled and running. This bit is clear at all other times.</description> 18146 <bitOffset>0</bitOffset> 18147 <bitWidth>1</bitWidth> 18148 <enumeratedValues> 18149 <enumeratedValue> 18150 <name>idle</name> 18151 <description>Idle</description> 18152 <value>0</value> 18153 </enumeratedValue> 18154 <enumeratedValue> 18155 <name>busy</name> 18156 <description>Busy</description> 18157 <value>1</value> 18158 </enumeratedValue> 18159 </enumeratedValues> 18160 </field> 18161 </fields> 18162 </register> 18163 <register> 18164 <name>INTEN</name> 18165 <description>Interrupt Enable Register</description> 18166 <addressOffset>0x0C</addressOffset> 18167 <fields> 18168 <field> 18169 <name>PUSH</name> 18170 <description>Push Event Enable Bit. When set, this bit enables an interrupt to be generated on a key push event. Automatic keyboard scan must be enabled.</description> 18171 <bitOffset>0</bitOffset> 18172 <bitWidth>1</bitWidth> 18173 <enumeratedValues> 18174 <enumeratedValue> 18175 <name>disable</name> 18176 <description>Disable</description> 18177 <value>0</value> 18178 </enumeratedValue> 18179 <enumeratedValue> 18180 <name>enable</name> 18181 <description>Enable</description> 18182 <value>1</value> 18183 </enumeratedValue> 18184 </enumeratedValues> 18185 </field> 18186 <field derivedFrom="PUSH"> 18187 <name>RELEASE</name> 18188 <description>Release Event Enable Bit. When set, this bit enables an interrupt to be generated on a key release event. Automatic keyboard scan must be enabled.</description> 18189 <bitOffset>1</bitOffset> 18190 <bitWidth>1</bitWidth> 18191 </field> 18192 <field derivedFrom="PUSH"> 18193 <name>OVERRUN</name> 18194 <description>Overrun Event Enable Bit. When set, this bit enables an interrupt to be generated on an overrun event. Automatic keyboard scan must be enabled.</description> 18195 <bitOffset>2</bitOffset> 18196 <bitWidth>1</bitWidth> 18197 </field> 18198 <field> 18199 <name>KBD_PINS</name> 18200 <description>Keyboard Pins Interrupt Enable.</description> 18201 <bitOffset>3</bitOffset> 18202 <bitWidth>1</bitWidth> 18203 </field> 18204 </fields> 18205 </register> 18206 <register> 18207 <name>INTFL</name> 18208 <description>Interrupt Status Register</description> 18209 <addressOffset>0x10</addressOffset> 18210 <fields> 18211 <field> 18212 <name>PUSH</name> 18213 <description>Push Interrupt Flag. This bit is set by hardware when a key has been pushed. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software.</description> 18214 <bitOffset>0</bitOffset> 18215 <bitWidth>1</bitWidth> 18216 <enumeratedValues> 18217 <enumeratedValue> 18218 <name>inactive</name> 18219 <description>No interrupt is pending.</description> 18220 <value>0</value> 18221 </enumeratedValue> 18222 <enumeratedValue> 18223 <name>pending</name> 18224 <description>An interrupt is pending.</description> 18225 <value>1</value> 18226 </enumeratedValue> 18227 </enumeratedValues> 18228 </field> 18229 <field derivedFrom="PUSH"> 18230 <name>RELEASE</name> 18231 <description>Release Interrupt Flag. This bit is set by hardware when a key has been released. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software.</description> 18232 <bitOffset>1</bitOffset> 18233 <bitWidth>1</bitWidth> 18234 </field> 18235 <field derivedFrom="PUSH"> 18236 <name>OVERRUN</name> 18237 <description>Overrun Event Enable Bit. This bit is set by hardware when an overrun event has occurred. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software.</description> 18238 <bitOffset>2</bitOffset> 18239 <bitWidth>1</bitWidth> 18240 </field> 18241 </fields> 18242 </register> 18243 <register> 18244 <dim>4</dim> 18245 <dimIncrement>4</dimIncrement> 18246 <name>EVT[%s]</name> 18247 <description>Key Register</description> 18248 <addressOffset>0x14</addressOffset> 18249 <access>read-only</access> 18250 <resetValue>0x00000C00</resetValue> 18251 <fields> 18252 <field> 18253 <name>IOIN</name> 18254 <description>IO Input. Input pin of key event.</description> 18255 <bitOffset>0</bitOffset> 18256 <bitWidth>3</bitWidth> 18257 </field> 18258 <field> 18259 <name>IOOUT</name> 18260 <description>IO Output. Output pin of key event.</description> 18261 <bitOffset>5</bitOffset> 18262 <bitWidth>3</bitWidth> 18263 </field> 18264 <field> 18265 <name>PUSH</name> 18266 <description>If set to 1 the key has been released. If set to 0 the key has been pushed.</description> 18267 <bitOffset>10</bitOffset> 18268 <bitWidth>1</bitWidth> 18269 <enumeratedValues> 18270 <enumeratedValue> 18271 <name>pushed</name> 18272 <description>Pushed</description> 18273 <value>0</value> 18274 </enumeratedValue> 18275 <enumeratedValue> 18276 <name>released</name> 18277 <description>Released</description> 18278 <value>1</value> 18279 </enumeratedValue> 18280 </enumeratedValues> 18281 </field> 18282 <field> 18283 <name>READ</name> 18284 <description>If set to 1 this register has been read. If set to 0 the key register has not been read since its last change.</description> 18285 <bitOffset>11</bitOffset> 18286 <bitWidth>1</bitWidth> 18287 <enumeratedValues> 18288 <enumeratedValue> 18289 <name>notRead</name> 18290 <description>This register has not been read since its last change.</description> 18291 <value>0</value> 18292 </enumeratedValue> 18293 <enumeratedValue> 18294 <name>read</name> 18295 <description>This register has been read.</description> 18296 <value>1</value> 18297 </enumeratedValue> 18298 </enumeratedValues> 18299 </field> 18300 <field> 18301 <name>NEXT</name> 18302 <description>If set to 1 one of the next key registers (x+1 to 3) contains a key event.</description> 18303 <bitOffset>12</bitOffset> 18304 <bitWidth>1</bitWidth> 18305 <enumeratedValues> 18306 <enumeratedValue> 18307 <name>none</name> 18308 <description>No more key register contain a key event.</description> 18309 <value>0</value> 18310 </enumeratedValue> 18311 <enumeratedValue> 18312 <name>more</name> 18313 <description>Other key registers contain a key event.</description> 18314 <value>1</value> 18315 </enumeratedValue> 18316 </enumeratedValues> 18317 </field> 18318 </fields> 18319 </register> 18320 <register> 18321 <name>GPIO0</name> 18322 <description>General Purpose Register 0.</description> 18323 <addressOffset>0x24</addressOffset> 18324 <fields> 18325 <field> 18326 <name>ALL</name> 18327 <description>Mask of all of the pins on the port.</description> 18328 <bitOffset>0</bitOffset> 18329 <bitWidth>32</bitWidth> 18330 </field> 18331 </fields> 18332 </register> 18333 <register> 18334 <name>GPIO1</name> 18335 <description>General Purpose Register 1.</description> 18336 <addressOffset>0x28</addressOffset> 18337 <fields> 18338 <field> 18339 <name>ALL</name> 18340 <description>Mask of all of the pins on the port.</description> 18341 <bitOffset>0</bitOffset> 18342 <bitWidth>32</bitWidth> 18343 </field> 18344 </fields> 18345 </register> 18346 </registers> 18347 </peripheral> 18348<!--SKBD Secure Keyboard--> 18349 <peripheral> 18350 <name>SEMA</name> 18351 <description>The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. 18352 The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software 18353 architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be 18354 18355 modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.</description> 18356 <baseAddress>0x4003E000</baseAddress> 18357 <addressBlock> 18358 <offset>0x00</offset> 18359 <size>0x1000</size> 18360 <usage>registers</usage> 18361 </addressBlock> 18362 <registers> 18363 <register> 18364 <dim>8</dim> 18365 <dimIncrement>4</dimIncrement> 18366 <name>SEMAPHORES[%s]</name> 18367 <description>Read to test and set, returns prior value. Write 0 to clear semaphore.</description> 18368 <addressOffset>0x00</addressOffset> 18369 <size>32</size> 18370 <fields> 18371 <field> 18372 <name>sema</name> 18373 <bitOffset>0</bitOffset> 18374 <bitWidth>1</bitWidth> 18375 </field> 18376 </fields> 18377 </register> 18378 <register> 18379 <name>irq0</name> 18380 <description>Semaphore IRQ0 register.</description> 18381 <addressOffset>0x40</addressOffset> 18382 <size>32</size> 18383 <fields> 18384 <field> 18385 <name>en</name> 18386 <bitOffset>0</bitOffset> 18387 <bitWidth>1</bitWidth> 18388 </field> 18389 <field> 18390 <name>cm4_irq</name> 18391 <bitOffset>16</bitOffset> 18392 <bitWidth>1</bitWidth> 18393 </field> 18394 </fields> 18395 </register> 18396 <register> 18397 <name>mail0</name> 18398 <description>Semaphore Mailbox 0 register.</description> 18399 <addressOffset>0x44</addressOffset> 18400 <size>32</size> 18401 <fields> 18402 <field> 18403 <name>data</name> 18404 <bitOffset>0</bitOffset> 18405 <bitWidth>32</bitWidth> 18406 </field> 18407 </fields> 18408 </register> 18409 <register> 18410 <name>irq1</name> 18411 <description>Semaphore IRQ1 register.</description> 18412 <addressOffset>0x48</addressOffset> 18413 <size>32</size> 18414 <fields> 18415 <field> 18416 <name>en</name> 18417 <bitOffset>0</bitOffset> 18418 <bitWidth>1</bitWidth> 18419 </field> 18420 <field> 18421 <name>rv32_irq</name> 18422 <bitOffset>16</bitOffset> 18423 <bitWidth>1</bitWidth> 18424 </field> 18425 </fields> 18426 </register> 18427 <register> 18428 <name>mail1</name> 18429 <description>Semaphore Mailbox 1 register.</description> 18430 <addressOffset>0x4C</addressOffset> 18431 <size>32</size> 18432 <fields> 18433 <field> 18434 <name>data</name> 18435 <bitOffset>0</bitOffset> 18436 <bitWidth>32</bitWidth> 18437 </field> 18438 </fields> 18439 </register> 18440 <register> 18441 <name>status</name> 18442 <description>Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken.</description> 18443 <addressOffset>0x100</addressOffset> 18444 <size>32</size> 18445 <fields> 18446 <field> 18447 <name>status0</name> 18448 <bitOffset>0</bitOffset> 18449 <bitWidth>1</bitWidth> 18450 </field> 18451 <field> 18452 <name>status1</name> 18453 <bitOffset>1</bitOffset> 18454 <bitWidth>1</bitWidth> 18455 </field> 18456 <field> 18457 <name>status2</name> 18458 <bitOffset>2</bitOffset> 18459 <bitWidth>1</bitWidth> 18460 </field> 18461 <field> 18462 <name>status3</name> 18463 <bitOffset>3</bitOffset> 18464 <bitWidth>1</bitWidth> 18465 </field> 18466 <field> 18467 <name>status4</name> 18468 <bitOffset>4</bitOffset> 18469 <bitWidth>1</bitWidth> 18470 </field> 18471 <field> 18472 <name>status5</name> 18473 <bitOffset>5</bitOffset> 18474 <bitWidth>1</bitWidth> 18475 </field> 18476 <field> 18477 <name>status6</name> 18478 <bitOffset>6</bitOffset> 18479 <bitWidth>1</bitWidth> 18480 </field> 18481 <field> 18482 <name>status7</name> 18483 <bitOffset>7</bitOffset> 18484 <bitWidth>1</bitWidth> 18485 </field> 18486 </fields> 18487 </register> 18488 </registers> 18489 </peripheral> 18490<!--SEMA The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. 18491 The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software 18492 architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be 18493 18494 modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.--> 18495 <peripheral> 18496 <name>SCN</name> 18497 <description>Smart Card Interface.</description> 18498 <groupName>SCN</groupName> 18499 <baseAddress>0x4002C000</baseAddress> 18500 <addressBlock> 18501 <offset>0x00</offset> 18502 <size>0x1000</size> 18503 <usage>registers</usage> 18504 </addressBlock> 18505 <interrupt> 18506 <name>SC0</name> 18507 <description>SC0 IRQ</description> 18508 <value>11</value> 18509 </interrupt> 18510 <registers> 18511 <register> 18512 <name>CR</name> 18513 <description>Control Register.</description> 18514 <addressOffset>0x00</addressOffset> 18515 <fields> 18516 <field> 18517 <name>CONV</name> 18518 <description>Convention Select Bit.</description> 18519 <bitOffset>0</bitOffset> 18520 <bitWidth>1</bitWidth> 18521 </field> 18522 <field> 18523 <name>CREP</name> 18524 <description>Character Repeat Enable Bit.</description> 18525 <bitOffset>1</bitOffset> 18526 <bitWidth>1</bitWidth> 18527 </field> 18528 <field> 18529 <name>WTEN</name> 18530 <description>Wait Time Counter Enable Bit.</description> 18531 <bitOffset>2</bitOffset> 18532 <bitWidth>1</bitWidth> 18533 </field> 18534 <field> 18535 <name>UART</name> 18536 <description>Smart Card Mode Bit.</description> 18537 <bitOffset>3</bitOffset> 18538 <bitWidth>1</bitWidth> 18539 </field> 18540 <field> 18541 <name>CCEN</name> 18542 <description>Clock Counter Enable Bit.</description> 18543 <bitOffset>4</bitOffset> 18544 <bitWidth>1</bitWidth> 18545 </field> 18546 <field> 18547 <name>RXFLUSH</name> 18548 <description>Receive FIFO Flush.</description> 18549 <bitOffset>5</bitOffset> 18550 <bitWidth>1</bitWidth> 18551 </field> 18552 <field> 18553 <name>TXFLUSH</name> 18554 <description>Transmit FIFO Flush.</description> 18555 <bitOffset>6</bitOffset> 18556 <bitWidth>1</bitWidth> 18557 </field> 18558 <field> 18559 <name>RXTHD</name> 18560 <description>Receive FIFO Depth.</description> 18561 <bitOffset>8</bitOffset> 18562 <bitWidth>4</bitWidth> 18563 </field> 18564 <field> 18565 <name>TXTHD</name> 18566 <description>Transmit FIFO Depth.</description> 18567 <bitOffset>12</bitOffset> 18568 <bitWidth>4</bitWidth> 18569 </field> 18570 <field> 18571 <name>DUAL_MODE</name> 18572 <description>Dual Internal AFE and Bypass Mode.</description> 18573 <bitOffset>23</bitOffset> 18574 <bitWidth>1</bitWidth> 18575 </field> 18576 </fields> 18577 </register> 18578 <register> 18579 <name>SR</name> 18580 <description>Status Register.</description> 18581 <addressOffset>0x04</addressOffset> 18582 <fields> 18583 <field> 18584 <name>PAR</name> 18585 <description>Parity Error Detector Flag.</description> 18586 <bitOffset>0</bitOffset> 18587 <bitWidth>1</bitWidth> 18588 </field> 18589 <field> 18590 <name>WTOV</name> 18591 <description>Waiting Time Counter Overflow.</description> 18592 <bitOffset>1</bitOffset> 18593 <bitWidth>1</bitWidth> 18594 </field> 18595 <field> 18596 <name>CCOV</name> 18597 <description>Clock Counter Overflow Flag.</description> 18598 <bitOffset>2</bitOffset> 18599 <bitWidth>1</bitWidth> 18600 </field> 18601 <field> 18602 <name>TXCF</name> 18603 <description>Transmit Complete Flag.</description> 18604 <bitOffset>3</bitOffset> 18605 <bitWidth>1</bitWidth> 18606 </field> 18607 <field> 18608 <name>RXEMPTY</name> 18609 <description>Receive FIFO Empty Flag.</description> 18610 <bitOffset>4</bitOffset> 18611 <bitWidth>1</bitWidth> 18612 </field> 18613 <field> 18614 <name>RXFULL</name> 18615 <description>Receive FIFO Full Flag.</description> 18616 <bitOffset>5</bitOffset> 18617 <bitWidth>1</bitWidth> 18618 </field> 18619 <field> 18620 <name>TXEMPTY</name> 18621 <description>Transmit FIFO Empty Flag.</description> 18622 <bitOffset>6</bitOffset> 18623 <bitWidth>1</bitWidth> 18624 </field> 18625 <field> 18626 <name>TXFULL</name> 18627 <description>Transmit FIFO Full Flag.</description> 18628 <bitOffset>7</bitOffset> 18629 <bitWidth>1</bitWidth> 18630 </field> 18631 <field> 18632 <name>RXELT</name> 18633 <description>Number of Bytes in the Receive FIFO.</description> 18634 <bitOffset>8</bitOffset> 18635 <bitWidth>4</bitWidth> 18636 </field> 18637 <field> 18638 <name>TXELT</name> 18639 <description>Number of Bytes in the Transmit FIFO.</description> 18640 <bitOffset>12</bitOffset> 18641 <bitWidth>4</bitWidth> 18642 </field> 18643 </fields> 18644 </register> 18645 <register> 18646 <name>PN</name> 18647 <description>Pin Register.</description> 18648 <addressOffset>0x08</addressOffset> 18649 <fields> 18650 <field> 18651 <name>CRDRST</name> 18652 <description>Smart Card Reset Pin Control.</description> 18653 <bitOffset>0</bitOffset> 18654 <bitWidth>1</bitWidth> 18655 </field> 18656 <field> 18657 <name>CRDCLK</name> 18658 <description>Smart Card Clock Piin Control.</description> 18659 <bitOffset>1</bitOffset> 18660 <bitWidth>1</bitWidth> 18661 </field> 18662 <field> 18663 <name>CRDIO</name> 18664 <description>Smart Card IO Pin Control.</description> 18665 <bitOffset>2</bitOffset> 18666 <bitWidth>1</bitWidth> 18667 </field> 18668 <field> 18669 <name>CRDC4</name> 18670 <description>Smart Card SCn_C4 Pin Control.</description> 18671 <bitOffset>3</bitOffset> 18672 <bitWidth>1</bitWidth> 18673 </field> 18674 <field> 18675 <name>CRDC8</name> 18676 <description>Smart Card SCn_C8 Pin Control.</description> 18677 <bitOffset>4</bitOffset> 18678 <bitWidth>1</bitWidth> 18679 </field> 18680 <field> 18681 <name>CLKSEL</name> 18682 <description>Smart Card Clock Select.</description> 18683 <bitOffset>5</bitOffset> 18684 <bitWidth>1</bitWidth> 18685 </field> 18686 <field> 18687 <name>IO_C48_EN</name> 18688 <description>Pin Enable.</description> 18689 <bitOffset>16</bitOffset> 18690 <bitWidth>1</bitWidth> 18691 </field> 18692 </fields> 18693 </register> 18694 <register> 18695 <name>ETUR</name> 18696 <description>ETU Register.</description> 18697 <addressOffset>0x0C</addressOffset> 18698 <fields> 18699 <field> 18700 <name>ETU</name> 18701 <description>Elemental Time Unit Value.</description> 18702 <bitOffset>0</bitOffset> 18703 <bitWidth>15</bitWidth> 18704 </field> 18705 <field> 18706 <name>COMP</name> 18707 <description>Compensation Mode Enable Bit.</description> 18708 <bitOffset>15</bitOffset> 18709 <bitWidth>1</bitWidth> 18710 </field> 18711 <field> 18712 <name>HALF</name> 18713 <description>Half ETU Count Selection Bit.</description> 18714 <bitOffset>16</bitOffset> 18715 <bitWidth>1</bitWidth> 18716 </field> 18717 </fields> 18718 </register> 18719 <register> 18720 <name>GTR</name> 18721 <description>Guard Time Register.</description> 18722 <addressOffset>0x10</addressOffset> 18723 <fields> 18724 <field> 18725 <name>GT</name> 18726 <description>Guard Time.</description> 18727 <bitOffset>0</bitOffset> 18728 <bitWidth>16</bitWidth> 18729 </field> 18730 </fields> 18731 </register> 18732 <register> 18733 <name>WT0R</name> 18734 <description>Waiting Time 0 Register.</description> 18735 <addressOffset>0x14</addressOffset> 18736 <fields> 18737 <field> 18738 <name>WT</name> 18739 <description>Wait Time.</description> 18740 <bitOffset>0</bitOffset> 18741 <bitWidth>32</bitWidth> 18742 </field> 18743 </fields> 18744 </register> 18745 <register> 18746 <name>WT1R</name> 18747 <description>Waiting Time 1 Register.</description> 18748 <addressOffset>0x18</addressOffset> 18749 <fields> 18750 <field> 18751 <name>WT</name> 18752 <description>Wait Time.</description> 18753 <bitOffset>0</bitOffset> 18754 <bitWidth>8</bitWidth> 18755 </field> 18756 </fields> 18757 </register> 18758 <register> 18759 <name>IER</name> 18760 <description>Interrupt Enable Register.</description> 18761 <addressOffset>0x1C</addressOffset> 18762 <fields> 18763 <field> 18764 <name>PARIE</name> 18765 <description>Parity Error Interrupt Enable.</description> 18766 <bitOffset>0</bitOffset> 18767 <bitWidth>1</bitWidth> 18768 </field> 18769 <field> 18770 <name>WTIE</name> 18771 <description>Waiting Time Overflow Interrupt Enable.</description> 18772 <bitOffset>1</bitOffset> 18773 <bitWidth>1</bitWidth> 18774 </field> 18775 <field> 18776 <name>CTIE</name> 18777 <description>Clock Counter Overflow Interrupt Enable.</description> 18778 <bitOffset>2</bitOffset> 18779 <bitWidth>1</bitWidth> 18780 </field> 18781 <field> 18782 <name>TCIE</name> 18783 <description>Character Transmission Completion Interrupt Enable.</description> 18784 <bitOffset>3</bitOffset> 18785 <bitWidth>1</bitWidth> 18786 </field> 18787 <field> 18788 <name>RXEIE</name> 18789 <description>Receive FIFO Empty Interrupt Enable.</description> 18790 <bitOffset>4</bitOffset> 18791 <bitWidth>1</bitWidth> 18792 </field> 18793 <field> 18794 <name>RXTIE</name> 18795 <description>Receive FIFO Threshold Reached Interrupt Enable.</description> 18796 <bitOffset>5</bitOffset> 18797 <bitWidth>1</bitWidth> 18798 </field> 18799 <field> 18800 <name>RXFIE</name> 18801 <description>Receive FIFO Full Interrupt Enable.</description> 18802 <bitOffset>6</bitOffset> 18803 <bitWidth>1</bitWidth> 18804 </field> 18805 <field> 18806 <name>TXEIE</name> 18807 <description>Transmit FIFO Empty Interrupt Enable.</description> 18808 <bitOffset>7</bitOffset> 18809 <bitWidth>1</bitWidth> 18810 </field> 18811 <field> 18812 <name>TXTIE</name> 18813 <description>Transmit FIFO Threshold Reached Interrupt Enable.</description> 18814 <bitOffset>8</bitOffset> 18815 <bitWidth>1</bitWidth> 18816 </field> 18817 </fields> 18818 </register> 18819 <register> 18820 <name>ISR</name> 18821 <description>Interrupt Status Register.</description> 18822 <addressOffset>0x20</addressOffset> 18823 <fields> 18824 <field> 18825 <name>PARIS</name> 18826 <description>Parity Error Interrupt Status Flag.</description> 18827 <bitOffset>0</bitOffset> 18828 <bitWidth>1</bitWidth> 18829 </field> 18830 <field> 18831 <name>WTIS</name> 18832 <description>Waiting Time Overflow Interrupt Status Flag.</description> 18833 <bitOffset>1</bitOffset> 18834 <bitWidth>1</bitWidth> 18835 </field> 18836 <field> 18837 <name>CTIS</name> 18838 <description>Clock Counter Overflow Interrupt Status Flag.</description> 18839 <bitOffset>2</bitOffset> 18840 <bitWidth>1</bitWidth> 18841 </field> 18842 <field> 18843 <name>TCIS</name> 18844 <description>Character Transmission Completion Interrupt Status Flag.</description> 18845 <bitOffset>3</bitOffset> 18846 <bitWidth>1</bitWidth> 18847 </field> 18848 <field> 18849 <name>RXEIS</name> 18850 <description>Receive FIFO Empty Interrupt Status Flag.</description> 18851 <bitOffset>4</bitOffset> 18852 <bitWidth>1</bitWidth> 18853 </field> 18854 <field> 18855 <name>RXTIS</name> 18856 <description>Receive FIFO Threshold Reached Interrupt Status Flag.</description> 18857 <bitOffset>5</bitOffset> 18858 <bitWidth>1</bitWidth> 18859 </field> 18860 <field> 18861 <name>RXFIS</name> 18862 <description>Receive FIFO Full Interrupt Status Flag.</description> 18863 <bitOffset>6</bitOffset> 18864 <bitWidth>1</bitWidth> 18865 </field> 18866 <field> 18867 <name>TXEIS</name> 18868 <description>Transmit FIFO Empty Interrupt Status Flag.</description> 18869 <bitOffset>7</bitOffset> 18870 <bitWidth>1</bitWidth> 18871 </field> 18872 <field> 18873 <name>TXTIS</name> 18874 <description>Transmit FIFO Threshold Reached Interrupt Status Flag.</description> 18875 <bitOffset>8</bitOffset> 18876 <bitWidth>1</bitWidth> 18877 </field> 18878 </fields> 18879 </register> 18880 <register> 18881 <name>TXR</name> 18882 <description>Transmit Register.</description> 18883 <addressOffset>0x24</addressOffset> 18884 <fields> 18885 <field> 18886 <name>DATA</name> 18887 <description>Transmit Data.</description> 18888 <bitOffset>0</bitOffset> 18889 <bitWidth>8</bitWidth> 18890 </field> 18891 </fields> 18892 </register> 18893 <register> 18894 <name>RXR</name> 18895 <description>Receive Register.</description> 18896 <addressOffset>0x28</addressOffset> 18897 <fields> 18898 <field> 18899 <name>DATA</name> 18900 <description>Receive Data.</description> 18901 <bitOffset>0</bitOffset> 18902 <bitWidth>8</bitWidth> 18903 </field> 18904 <field> 18905 <name>PARER</name> 18906 <description>Parity Error Detect Bit.</description> 18907 <bitOffset>8</bitOffset> 18908 <bitWidth>1</bitWidth> 18909 </field> 18910 </fields> 18911 </register> 18912 <register> 18913 <name>CCR</name> 18914 <description>Clock Counter Register.</description> 18915 <addressOffset>0x2C</addressOffset> 18916 <fields> 18917 <field> 18918 <name>CCYC</name> 18919 <description>Number of Clock Cycles to Count.</description> 18920 <bitOffset>0</bitOffset> 18921 <bitWidth>24</bitWidth> 18922 </field> 18923 <field> 18924 <name>MAN</name> 18925 <description>Manual Mode.</description> 18926 <bitOffset>31</bitOffset> 18927 <bitWidth>1</bitWidth> 18928 </field> 18929 </fields> 18930 </register> 18931 </registers> 18932 </peripheral> 18933<!--SCN Smart Card Interface.--> 18934 </peripherals> 18935</device> 18936
