Maxim-Integrated Maxim max32572 ARMCM4 1.0 MAX32572 32-bit ARM Cortex-M4 microcontroller, 1024KB of flash, 760KB of system RAM, 128KB of Boot ROM. CM4 r2p1 little true true 3 false 8 32 0x20 read-write 0x00000000 0xFFFFFFFF ADC 10-bit Analog to Digital Converter 0x40034000 32 read-write 0 0x1000 registers ADC ADC IRQ 20 CTRL ADC Control 0x0000 read-write START Start ADC Conversion [0:0] read-write PWR ADC Power Up [1:1] read-write REBUF_PWR ADC Reference Buffer Power Up [3:3] read-write CHGPUMP_PWR ADC Charge Pump Power Up [4:4] read-write REF_SCALE ADC Reference Scale [8:8] read-write SCALE ADC Scale [9:9] read-write CLK_EN ADC Clock Enable [11:11] read-write CH_SEL ADC Channel Select [16:12] read-write AIN0 0 AIN1 1 AIN2 2 AIN3 3 AIN4 4 AIN5 5 AIN6 6 AIN7 7 VcoreA 8 VcoreB 9 Vrxout 10 Vtxout 11 VddA 12 VddB VddB/4 13 Vddio Vddio/4 14 Vddioh Vddioh/4 15 VregI VregI/4 16 DIVSEL Scales the external inputs, all inputs are scaled the same [18:17] read-write DIV1 0 DIV2 1 DIV3 2 DIV4 3 DATA_ALIGN ADC Data Alignment Select [20:20] read-write STATUS ADC Status 0x0004 read-write ACTIVE ADC Conversion In Progress [0:0] read-only AFE_PWR_UP_ACTIVE AFE Power Up Delay Active [2:2] read-only OVERFLOW ADC Overflow [3:3] read-only DATA ADC Output Data 0x0008 read-write DATA ADC Converted Sample Data Output [15:0] read-only INTR ADC Interrupt Control Register 0x000C read-write DONE_IE ADC Done Interrupt Enable [0:0] read-write REF_READY_IE ADC Reference Ready Interrupt Enable [1:1] read-write HI_LIMIT_IE ADC Hi Limit Monitor Interrupt Enable [2:2] read-write LO_LIMIT_IE ADC Lo Limit Monitor Interrupt Enable [3:3] read-write OVERFLOW_IE ADC Overflow Interrupt Enable [4:4] read-write DONE_IF ADC Done Interrupt Flag [16:16] read-write oneToClear REF_READY_IF ADC Reference Ready Interrupt Flag [17:17] read-write oneToClear HI_LIMIT_IF ADC Hi Limit Monitor Interrupt Flag [18:18] read-write oneToClear LO_LIMIT_IF ADC Lo Limit Monitor Interrupt Flag [19:19] read-write oneToClear OVERFLOW_IF ADC Overflow Interrupt Flag [20:20] read-write oneToClear PENDING ADC Interrupt Pending Status [22:22] read-only 4 4 LIMIT[%s] ADC Limit 0x0010 read-write CH_LO_LIMIT Low Limit Threshold [9:0] read-write CH_HI_LIMIT High Limit Threshold [21:12] read-write CH_SEL ADC Channel Select [27:24] read-write CH_LO_LIMIT_EN Low Limit Monitoring Enable [28:28] read-write CH_HI_LIMIT_EN High Limit Monitoring Enable [29:29] read-write DECCNT ADC Decimation Count. 0x0020 read-write DELAY Delay. [31:0] read-write AESKEYS AES Key Registers. 0x40005000 0x00 0x400 registers 8 4 MEU[%s] AES-256 SRAM Encryption Key (MEU). 0x00 32 read-write 4 4 XIP[%s] AES-128 QSPI Code Key (MEMPROT XIP). 0x20 32 read-write MSRADC Magnetic Strip Reader - 9 bit ADC 0x4002B000 32 read-write 0 0x1000 registers ADC9 ADC IRQ 22 CTRL ADC Control 0x0000 read-write CLKDIV ADC Clock Divider. [7:0] read-write ACHSEL A Channel ADC Input Pin Selection. [10:8] read-write invalid 0 CH1_IN 1 CH2_IN 2 CH3_IN 3 BCHSEL B Channel ADC Input Pin Selection. [13:11] read-write CCHSEL C Channel ADC Input Pin Selection. [16:14] read-write DCHSEL D Channel ADC Input Pin Selection. [19:17] read-write ECHSEL E Channel ADC Input Pin Selection. [22:20] read-write FCHSEL F Channel ADC Input Pin Selection. [25:23] read-write GCHSEL G Channel ADC Input Pin Selection. [28:26] read-write HCHSEL H Channel ADC Input Pin Selection. [31:29] read-write CMD MSRADC Command 0x0004 read-write RST ADC Reset. [0:0] read-write SNGLSMPL Single Sample Mode. [1:1] read-write CONTSMPL Continuous Sample Mode Enable. [2:2] read-write ROTLIMIT Rotation Limit. [6:4] read-write 1_channel 0 2_channels 1 3_channels 2 4_channels 3 5_channels 4 6_channels 5 7_channels 6 8_channels 7 CLKSEL Clock Select. [10:8] read-write 3_samples 0 5_samples 1 4_samples 2 8_samples 3 16_samples 4 32_samples 5 64_samples 6 128_samples 7 FIFO ADC FIFO 0x0008 read-write SAMPLE ADC Converted Sample Data Output [8:0] read-only INPUT ADC Sample Pin [11:9] read-only invalid 0 CH1_IN 1 CH2_IN 2 CH3_IN 3 CH4_IN 4 CH5_IN 5 CH6_IN 6 CH7_IN 7 INCOMPLETE ADC Incomplete. [12:12] read-only INTEN ADC Interrupt Enable Register 0x000C read-write SET_FIFOLVL Set FIFO Interrupt Level. [4:0] read-write at_least_1 0 at_least_2 1 at_least_3 2 at_least_4 3 at_least_5 4 at_least_6 5 at_least_7 6 at_least_8 7 at_least_9 8 at_least_10 9 at_least_11 10 at_least_12 11 at_least_13 12 at_least_14 13 at_least_15 14 at_least_16 15 DMAREQ DMA Request Enable. [5:5] read-write FIFO_OV FIFO Overflow Interrupt Enable. [6:6] read-write FIFO_UN FIFO Underflow Interrupt Enable. [7:7] read-write FIFO_LVL FIFO Level Interrupt Enable. [8:8] read-write GLOBAL ADC Global Interrupt Enable. [9:9] read-write INTFL ADC Interrupt Flag Register. read-write 0x0010 FIFOCNT FIFO Count. [5:0] read-only FIFO_FULL_ST FIFO Full Status. [6:6] read-only FIFO_EM_ST FIFO Empty Status. [7:7] read-only FIFO_OV FIFO Overflow Status. [8:8] read-only FIFO_UN FIFO Underflow Status. [9:9] read-only FIFO_LVL FIFO Level Status. [10:10] read-only GLOBAL ADC Global Interrupt Flag. [11:11] read-only FCR Function Control Register. 0x40000800 0x00 0x400 registers FCTRL0 Register 0. 0x00 read-write USBCLKSEL USB External Core Clock Select. 16 1 sys Generated clock from system clock. 0 dig Digital clock from a GPIO. 1 I2C0DGEN0 I2C0 SDA Glitch Filter Enable. 20 1 dis Filter disabled. 0 en Filter enabled. 1 I2C0DGEN1 I2C0 SCL Glitch Filter Enable. 21 1 dis Filter disabled. 0 en Filter enabled. 1 I2C1DGEN0 I2C1 SDA Glitch Filter Enable. 22 1 dis Filter disabled. 0 en Filter enabled. 1 I2C1DGEN1 I2C1 SCL Glitch Filter Enable. 23 1 dis Filter disabled. 0 en Filter enabled. 1 FCTRL1 Register 1. 0x04 read-write AC_EN Auto-calibration Enable. 0 1 dis Disabled. 0 en Enabled. 1 AC_RUN Autocalibration Run. 1 1 not Not Running. 0 run Running. 1 LOAD Load Trim. 2 1 INV_GAIN Invert Gain. 3 1 not Not Running. 0 run Running. 1 ATOMIC Atomic mode. 4 1 not Not Running. 0 run Running. 1 MU MU value. 8 12 AC_TRIM 150MHz HFIO Auto Calibration Trim 23 9 FCTRL3 Register 3. 0x0C read-write DONECNT Auto-calibration Done Counter Setting. 0 8 URVBOOTADDR Register 4. 0x10 read-write BOOTADDR RISCV Boot Address. 0 32 URVCTRL Register 5. 0x14 read-write SLEEP_REQ Sleep Request to RISCV. 0 1 SLEEP_ACK Acknowledgement of Sleep Request for RISCV. 1 1 GP General Purpose Register. 0x1C read-write GP General Purpose. 0 32 TRIMCTRL MSR ADC Trim Register. 0x20 read-write MSR_R1 MSR R1 0 2 0K 0kOhm 0 1P2K 1.2kOhm 1 2P4K 2.4kOhm 2 4P8K 4.8kOhm 3 MSR_R2 MSR R2 2 3 OPEN Open drain. 0 3K 3kOhm 4 6K 6kOhm 5 12K 12kOhm 6 24K 24kOhm 7 ERFOKS ERFO Kick Start Register. 0x24 read-write CTRL Kick Start Control. 0 16 TRIMSIR Trim System Initilazation Registers 0x40005400 0x00 0x400 registers BBSIR2 System Init. Configuration Register 2. 0x08 read-only BBSIR3 System Init. Configuration Register 3. 0x0C read-only MCR Misc Control. 0x40006C00 0x00 0x400 registers PDOWN PDOWN Drive Strength 0x08 PDOWNDS PDOWN Drive Strength 0 2 PDOWNVS PDOWN Voltage Select 2 1 CTRL Misc Power State Control Register 0x10 VDDCSW Controls switching of VCORE 1 2 USBSWEN_N USB Switch Control 3 1 off USB SW off in LP modes 1 on USB SW On 0 P1M Enable the Reset Pad Pull Up Resistors 9 1 1m 1MOhm Pullup 0 25k 25kOhm Pullup. 1 rstn_voltage_sel Error! Description not Found! 10 1 CLKCTRL Clock Control Register. 0x14 ERTCO_PD 32kHz Crystal Oscillator Power Down. 16 1 ERTCO_EN 32kHz Crystal Oscillator Enable. 17 1 RST Reset Register. 0x18 RTC Real Time Cock Reset. 0 1 RTCTRIM RTC Trim Register. 0x1C TRIM_X1 RTC Trim X1 0 5 TRIM_X2 RTC TRIM X2 8 5 LDOCTRL LDO Control Register. 0x60 0P9V_EN LDO 0.9V Enable. 0 1 PWRMONST Power Monitor Statuses Register. 0x64 PORZ_VLOSS Sticky bit indicating power on status of core power domains. 0 1 PORZ_VBAT Sticky bit indicating power on status of the battery. 1 1 PORZ_VRTC Sticky bit indicating power on status of the RTC. 2 1 PORZ_VDDC Sticky bit indicating power on status of VCORE. 5 1 PORZ_VDDA Sticky bit indicating power on status of VDDA. 6 1 PORZ_VDDB Sticky bit indicating power on status of VDDB. 7 1 RSTZ_VDDC Sticky bit indicating reset condition on VCORE. 9 1 RSTZ_VDDA Sticky bit indicating reset condition on VDDA. 10 1 RSTZ_VDDB Sticky bit indicating reset condition on VDDB. 11 1 RSTZ_VDDIO Sticky bit indicating reset condition on VDDIO. 12 1 RSTZ_VDDIOH Sticky bit indicating reset condition on VDDIOH. 13 1 RSTZ_VRTC Sticky bit indicating reset condition on RTC. 14 1 RSTZ_LDO_0P9V Non-sticky bit indicating reset condition on 0.9V USB supply. 16 1 RSTZ_VDDCA Non-sticky bit indicating reset condition on VCORE in Analog supply. 17 1 RSTZ_VCOREHV Non-sticky bit indicating high voltage reset condition on VCORE supply. 18 1 RSTZ_VDDIOHV Non-sticky bit indicating high voltage reset condition on VDDIO supply. 19 1 RSTZ_VDDIOHHV Non-sticky bit indicating high voltage reset condition on VDDIOH supply. 20 1 CTB The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. 0x40001000 0x00 0x1000 registers Crypto_Engine Crypto Engine interrupt. 27 CTRL Crypto Control Register. 0x00 0xC0000000 RST Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle. 0 1 reset_write write reset Starts reset operation. 1 reset_read read reset_done Reset complete. 0 busy Reset in progress. 1 INTR Interrupt Enable. Generates an interrupt when done or error set. 1 1 dis Disable 0 en Enable 1 SRC Source Select. This bit selects the hash function and CRC generator input source. 2 1 inputFIFO Input FIFO 0 outputFIFO Output FIFO 1 BSO Byte Swap Output. Note. No byte swap will occur if there is not a full word. 4 1 BSI Byte Swap Input. Note. No byte swap will occur if there is not a full word. 5 1 WAIT_EN Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready. 6 1 WAIT_POL Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state. 7 1 activeLo Active Low. 0 activeHi Active High. 1 WRSRC Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled. 8 2 none None. 0 cipherOutput Cipher Output. 1 readFIFO Read FIFO. 2 RDSRC Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator. 10 2 dmaDisabled DMA Disable. 0 dmaOrApb DMA Or APB. 1 rng RNG. 2 FLAG_MODE Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs. 14 1 unres_wr Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags. 0 res_wr Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect. 1 DMADNEMSK DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA. 15 1 not_used DMA_DONE not used in setting CRYPTO_CTRL.DONE bit. 0 used DMA_DONE used in setting CRYPTO_CTRL.DONE bit. 1 DMA_DONE DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation. 24 1 notDone Not Done. 0 done Done. 1 GLS_DONE Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator. 25 1 HSH_DONE Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation. 26 1 CPH_DONE Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation. 27 1 ERR AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block. 29 1 read-only noError No Error. 0 error Error. 1 RDY Ready. Crypto block ready for more data. 30 1 read-only busy Busy. 0 ready Ready. 1 DONE Done. One or more cryptographic calculations complete (logical OR of done flags). 31 1 read-only CIPHER_CTRL Cipher Control Register. 0x04 ENC Encrypt. Select encryption or decryption of input data. 0 1 encrypt Encrypt. 0 decrypt Decrypt. 1 KEY Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag. 1 1 complete No operation/complete. 0 start Start operation. 1 SRC Source of Random key. 2 2 cipherKey User cipher key (0x4000_1060). 0 regFile Key from battery-backed register file (0x4000_5000 to 0x4000_501F). 2 qspiKey_regFile Key from battery-backed register file (0x4000_5020 to 0x4000_502F). 3 CIPHER Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation. 4 3 dis Disabled. 0 aes128 AES 128. 1 aes192 AES 192. 2 aes256 AES 256. 3 des DES. 4 tdes Triple DES. 5 MODE Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes. 8 3 ECB ECB Mode. 0 CBC CBC Mode. 1 CFB CFB (AES only). 2 OFB OFB (AES only). 3 CTR CTR (AES only). 4 HVC H Vector Computation. 11 1 read-only DTYPE GCM/CCM data type. 12 1 read-only CCMM CCM M Parameter. 13 3 read-only CCML CCM L Parameter. 16 3 read-only HASH_CTRL HASH Control Register. 0x08 INIT Initialize. Initializes hash registers with standard constants. 0 1 nop No operation/complete. 0 start Start operation. 1 XOR XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad. 1 1 dis Disable. 0 en Enable. 1 HASH Hash function selection. 2 3 dis Disabled. 0 sha1 SHA-1. 1 sha224 SHA 224. 2 sha256 SHA 256. 3 sha384 SHA 384. 4 sha512 SHA 512. 5 LAST Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash. 5 1 noEffect No Effect. 0 lastMsgData Last Message Data. 1 CRC_CTRL CRC Control Register. 0x0C CRC Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled. 0 1 dis Disable. 0 en Enable. 1 MSB MSB select. This bit selects the order of calculating CRC on data. 1 1 lsbFirst LSB First. 0 msbFirst MSB First. 1 PRNG Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle. 2 1 ENT Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source. 3 1 HAM Hamming Code Enable. Enable hamming code calculation. 4 1 HRST Hamming Reset. Reset Hamming code ECC generator for next block. 5 1 write-only write reset Starts reset operation. 1 DMA_SRC Crypto DMA Source Address. 0x10 ADDR DMA Source Address. 0 32 DMA_DEST Crypto DMA Destination Address. 0x14 ADDR DMA Destination Address. 0 32 DMA_CNT Crypto DMA Byte Count. 0x18 ADDR DMA Byte Address. 0 32 MAA_CTRL MAA Control Register. 0x1C 4 4 DIN[%s] Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register. 0x20 write-only DATA Crypto Data Input. Input can be written to this register instead of using DMA. 0 32 4 4 DOUT[%s] Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits. 0x30 read-only DATA Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm. 0 32 CRC_POLY CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. 0x40 0xEDB88320 POLY CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. 0 32 CRC_VAL CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit. 0x44 0xFFFFFFFF VAL CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit. 0 32 CRC_PRNG CRC PRNG Register. 0x48 PRNG PRNG 0 32 HAM_ECC Hamming ECC Register. 0x4C ECC Hamming ECC Value. These bits are the even parity of their corresponding bit groups. 0 16 PAR Parity. This is the parity of the entire array. 16 1 even Even. 0 odd Odd. 1 4 4 CIPHER_INIT[%s] Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. 0x50 IVEC Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. 0 32 8 4 CIPHER_KEY[%s] Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits. 0x60 write-only KEY Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits. 0 32 16 4 HASH_DIGEST[%s] This register holds the calculated hash value. This register is affected by the endian swap bits. 0x80 HASH This register holds the calculated hash value. This register is affected by the endian swap bits. 0 32 4 4 HASH_MSG_SZ[%s] Message Size. This register holds the lowest 32-bit of message size in bytes. 0xC0 MSGSZ Message Size. This register holds the lowest 32-bit of message size in bytes. 0 32 2 4 AAD_LENGTH[%s] AAD Length Registers. 0xD0 0x0 LENGTH AAD length in bytes for AES GCM and CCM operations. 0 32 2 4 PLD_LENGTH[%s] PLD Length Registers. 0xD8 0x0 LENGTH PLD length in bytes for AES GCM and CCM operations. 0 32 4 4 TAGMIC[%s] TAG/MIC Registers. 0xE0 LENGTH TAG/MIC output for AES GCM and CCM operations. 0 32 MAA_MAWS MAA Word Size Register. 0xF0 0x0 SIZE MAA Word Size. 0 32 SCA_CTRL0 SCA Control 0 Register. 0x700 STC Start Calculation. 0 1 SCAIE SCA Interrupt Enable. 1 1 disable Disable 0 enable Enable 1 ABORT Abort Operation. 2 1 AFFJAC Select Affine or Jacobi Coordinates. 3 1 ERMEM Erase Cryptographic Memory. 4 1 MANPARAM ECC Parameter Source. 5 1 HWKEY Hardware Key Select. 6 1 OPCODE SCA Opcode. 8 5 MODADDR MODULO Address Offset. 16 5 ECCSIZE ECC Size. 24 2 SCA_CTRL1 SCA Advanced Control Register. 0x704 MAN SCA Mode. 0 1 auto Auto Mode 0 manual Manual Mode 1 AUTOCARRY Automatically propagate the carry for the next operation. 1 1 PLUSONE Enable Carry propagation for the next operation. 2 1 RESSELECT ALU Selection. 3 2 NRNG Enable NIST RNG. 5 1 CARRYPOS To set Carry location. 8 10 CM_EN Enable Countermeasure. 20 12 SCA_STAT SCA Status Register. 0x708 BUSY SCA Busy. 0 1 SCAIF SCA Interrupt Flag. 1 1 PVF1 Point 1 Verification Failed. 2 1 PVF2 Point 2 Verification Failed. 3 1 FSMERR FSM Transition Error. 4 1 COMPERR EC Computation Error. 5 1 MEMERR SCA Memory Access Error. 6 1 CARRY Carry on ongoing operation. 8 1 GTE2I2 Modulo 2x Result. 9 1 ALUNEG1 ALU 2 SubSign of the subtraction result for ALU_2. 10 1 ALUNEG2 ALU 2 SubSign of the subtraction result for ALU_2. 11 1 SCA_PPX_ADDR PPX Coordinate Data Pointer Register. 0x70C 0x0 ADDR Point P Coordinate Data Pointer. 0 32 SCA_PPY_ADDR PPY Coordinate Data Pointer Register. 0x710 0x0 ADDR Point P Coordinate Data Pointer. 0 32 SCA_PPZ_ADDR PPZ Coordinate Data Pointer Register. 0x714 0x0 ADDR Point P Coordinate Data Pointer. 0 32 SCA_PQX_ADDR PQX Coordinate Data Pointer Register. 0x718 0x0 ADDR Point Q Coordinate Data Pointer. 0 32 SCA_PQY_ADDR PQY Coordinate Data Pointer Register. 0x71C 0x0 ADDR Point Q Coordinate Data Pointer. 0 32 SCA_PQZ_ADDR PQZ Coordinate Data Pointer Register. 0x720 0x0 ADDR Point Q Coordinate Data Pointer. 0 32 SCA_RDSA_ADDR SCA RDSA Address Register. 0x724 0x0 ADDR The starting address of the R portion for R, S ECDSA signature. 0 32 SCA_RES_ADDR SCA Result Address Register. 0x728 0x0 ADDR Starting address of result storage. 0 32 SCA_OP_BUFF_ADDR SCA Operation Buffer Address Register. 0x72C 0x0 ADDR Starting address of operation buffer. 0 32 SCA_MODDATA SCA Modulo Data Input Register. 0x730 0x0 DATA Used to load the SCA modulo for modular operations. 0 32 SCA_NRNG SCA NIST RNG Address Register. 0x734 0x0 ADDR Starting SRAM address where up to 32 words of NIST washed RNG data is stored. 0 32 SCA_WASH SCA Wash Register. 0x738 0x0 ADDR Starting SRAM address where up to 1 word of random is stored for SRAM washing. 0 32 DMA DMA Controller Fully programmable, chaining capable DMA channels. 0x40028000 32 0x00 0x1000 registers DMA0 28 DMA1 29 DMA2 30 DMA3 31 DMA4 68 DMA5 69 DMA6 70 DMA7 71 DMA8 72 DMA9 73 DMA10 74 DMA11 75 DMA12 76 DMA13 77 DMA14 78 DMA15 79 INTEN DMA Interrupt Enable Register. 0x000 CH0 Channel 0 Interrupt Enable. 0 1 dis Disable. 0 en Enable. 1 CH1 Channel 1 Interrupt Enable. 1 1 CH2 Channel 2 Interrupt Enable. 2 1 CH3 Channel 3 Interrupt Enable. 3 1 CH4 Channel 4 Interrupt Enable. 4 1 CH5 Channel 5 Interrupt Enable. 5 1 CH6 Channel 6 Interrupt Enable. 6 1 CH7 Channel 7 Interrupt Enable. 7 1 CH8 Channel 8 Interrupt Enable. 8 1 CH9 Channel 9 Interrupt Enable. 9 1 CH10 Channel 10 Interrupt Enable. 10 1 CH11 Channel 11 Interrupt Enable. 11 1 CH12 Channel 12 Interrupt Enable. 12 1 CH13 Channel 13 Interrupt Enable. 13 1 CH14 Channel 14 Interrupt Enable. 14 1 CH15 Channel 15 Interrupt Enable. 15 1 INTFL DMA Interrupt Flag Register. 0x004 read-only CH0 Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CH1 1 1 CH2 2 1 CH3 3 1 CH4 4 1 CH5 5 1 CH6 6 1 CH7 7 1 CH8 8 1 CH9 9 1 CH10 10 1 CH11 11 1 CH12 12 1 CH13 13 1 CH14 14 1 CH15 15 1 16 0x20 CH[%s] DMA Channel registers. dma_ch 0x100 read-write CTRL DMA Channel Control Register. 0x000 EN Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 RLDEN Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. 1 1 dis Disable. 0 en Enable. 1 PRI DMA Priority. 2 2 high Highest Priority. 0 medHigh Medium High Priority. 1 medLow Medium Low Priority. 2 low Lowest Priority. 3 REQUEST Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. 4 6 MEMTOMEM Memory To Memory 0x00 SPI0RX SPI0 RX 0x01 SPI1RX SPI1 RX 0x02 UART0RX UART0 RX 0x04 UART1RX UART1 RX 0x05 SC0RX SC0 RX 0x06 I2C0RX I2C0 RX 0x07 I2C1RX I2C1 RX 0x08 ADC Analog-to-Digital Converter Channel 0x09 MSRADC MSR 9 bit ADC. 0x0B UART2RX UART2 RX 0x0E SPI3RX SPI3 RX 0x0F USBRXEP1 USB Endpoint 1 RX 0x11 USBRXEP2 USB Endpoint 2 RX 0x12 USBRXEP3 USB Endpoint 3 RX 0x13 USBRXEP4 USB Endpoint 4 RX 0x14 USBRXEP5 USB Endpoint 5 RX 0x15 USBRXEP6 USB Endpoint 6 RX 0x16 USBRXEP7 USB Endpoint 7 RX 0x17 USBRXEP8 USB Endpoint 8 RX 0x18 USBRXEP9 USB Endpoint 9 RX 0x19 USBRXEP10 USB Endpoint 10 RX 0x1A USBRXEP11 USB Endpoint 11 RX 0x1B UART3RX UART3 RX 0x1C SPI0TX SPI0 TX 0x21 SPI1TX SPI1 TX 0x22 UART0TX UART0 TX 0x24 UART1TX UART1 TX 0x25 SC0TX SC0 TX 0x26 I2C0TX I2C0 TX 0x27 I2C1TX I2C1 TX 0x28 UART2TX UART2 TX 0x2E SPI3TX SPI3 TX 0x2F USBTXEP1 USB Endpoint 1 TX 0x31 USBTXEP2 USB Endpoint 2 TX 0x32 USBTXEP3 USB Endpoint 3 TX 0x33 USBTXEP4 USB Endpoint 4 TX 0x34 USBTXEP5 USB Endpoint 5 TX 0x35 USBTXEP6 USB Endpoint 6 TX 0x36 USBTXEP7 USB Endpoint 7 TX 0x37 USBTXEP8 USB Endpoint 8 TX 0x38 USBTXEP9 USB Endpoint 9 TX 0x39 USBTXEP10 USB Endpoint 10 TX 0x3A USBTXEP11 USB Endpoint 11 TX 0x3B UART3TX UART3 TX 0x3C TO_WAIT Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. 10 1 dis Disable. 0 en Enable. 1 TO_PER Timeout Period Select. 11 3 to4 Timeout of 3 to 4 prescale clocks. 0 to8 Timeout of 7 to 8 prescale clocks. 1 to16 Timeout of 15 to 16 prescale clocks. 2 to32 Timeout of 31 to 32 prescale clocks. 3 to64 Timeout of 63 to 64 prescale clocks. 4 to128 Timeout of 127 to 128 prescale clocks. 5 to256 Timeout of 255 to 256 prescale clocks. 6 to512 Timeout of 511 to 512 prescale clocks. 7 TO_CLKDIV Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. 14 2 dis Disable timer. 0 div256 hclk / 256. 1 div64k hclk / 64k. 2 div16M hclk / 16M. 3 SRCWD Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. 16 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 SRCINC Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. 18 1 dis Disable. 0 en Enable. 1 DSTWD Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). 20 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 DSTINC Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. 22 1 dis Disable. 0 en Enable. 1 BURST_SIZE Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. 24 5 DIS_IE Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. 30 1 dis Disable. 0 en Enable. 1 CTZ_IE Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. 31 1 dis Disable. 0 en Enable. 1 STATUS DMA Channel Status Register. 0x004 STATUS Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). 0 1 read-only dis Disable. 0 en Enable. 1 IPEND Channel Interrupt. 1 1 read-only inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CTZ_IF Count-to-Zero (CTZ) Event Interrupt Flag 2 1 oneToClear RLD_IF Reload Event Interrupt Flag. 3 1 oneToClear BUS_ERR Bus Error. Indicates that an AHB abort was received and the channel has been disabled. 4 1 oneToClear TO_IF Time-Out Event Interrupt Flag. 6 1 oneToClear SRC Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. 0x008 ADDR 0 32 DST Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. 0x00C ADDR 0 32 CNT DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. 0x010 CNT DMA Counter. 0 24 SRCRLD Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. 0x014 ADDR Source Address Reload Value. 0 31 DSTRLD Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. 0x018 ADDR Destination Address Reload Value. 0 31 CNTRLD DMA Channel Count Reload Register. 0x01C CNT Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. 0 24 EN Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. 31 1 dis Disable. 0 en Enable. 1 GCR Global Control Registers. 0x40000000 0 0x400 registers SYSCTRL System Control. 0x00 0xFFFFFFFE BSTAPEN Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE. 0 1 dis Boundary Scan TAP port disabled. 0 en Boundary Scan TAP port enabled. 1 SBUSARB System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. 1 2 fix Fixed Burst abritration. 0 round Round-robin scheme. 1 FPU_DIS Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. 5 1 SFCC_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 CHKRES1 Result of CPU1 ROM1 Checksum. 11 1 CCHK1 Compute CPU1 ROM1 Checksum 12 1 CCHK0 Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 SWD_DIS Serial Wire Debug Disable. 14 1 CHKRES0 ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 RST0 Reset. 0x04 DMA DMA Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT0 Watchdog Timer 0 Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 TMR0 Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TMR1 Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TMR2 Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TMR3 Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 TMR4 Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. 9 1 TMR5 Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. 10 1 UART0 UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI0 SPI 0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 SPI1 SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 14 1 I2C0 I2C 0 Reset. 16 1 CRYPTO Crypto Reset. 18 1 USB USB Reset. 23 1 TRNG TRNG Reset. 24 1 ADC ADC Reset. 26 1 UART2 UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. 28 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCTRL Clock Control. 0x08 0x00000008 PCLK_DIV PCLK Divider. 3 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSCLK_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 ISO The internal 60 MHz oscillator is used for the system clock. 0 ERFO The external 32 MHz input is used for the system clock. 2 INRO 8 kHz LIRC is used for the system clock. 3 IPO The internal 100 MHz oscillator is used for the system clock. 4 IBRO The internal 7.3725 MHz oscillator is used for the system clock. 5 ERTCO External 32 kHz input is used for the system clock. 6 CRYPTOCLK_DIV Cryptographic clock divider 12 1 non_div The cryptographic accelerator clock is running in non-divided mode. 0 div The cryptographic accelerator clock is running in divided mode. 1 SYSCLK_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 IPO_DIV IPO Divider. 14 2 DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 DIV8 Divide by 8. 3 ERFO_EN 27 MHz Crystal Oscillator Enable. 16 1 dis Is Disabled. 0 en Is Enabled. 1 ISO_EN 60 MHz Internal Oscillator Enable. 18 1 IPO_EN 100 MHz Clock Enable. 19 1 IBRO_EN 7.3725 MHz Clock Enable. 20 1 IBRO_VS 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO. 21 1 Vcor VCore Supply 0 1V Dedicated 1V regulated supply. 1 ERFO_RDY 32 MHz Oscillator Ready 24 1 read-only not Is not Ready. 0 ready Is Ready. 1 ERTCO_RDY 32 kHz Crystal Oscillator Ready 25 1 ISO_RDY 60 MHz Oscillator Ready. 26 1 IPO_RDY 100 MHz Clock Ready. 27 1 IBRO_RDY 7.3725 MHz HIRC Ready. 28 1 INRO_RDY 8 kHz Low Frequency Reference Clock Ready. 29 1 PM Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 sleep Sleep Mode. 1 deepsleep DeepSleep Mode. 2 shutdown ShutDown Mode. 3 backup Backup Mode. 4 GPIO_WE GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTC_WE RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 USB_WE USB Wake Up Enable. This bit enables USB IRQ as wakeup source 6 1 ERFO_PD 27 MHz power down. This bit selects the 27 MHz clock power state in DEEPSLEEP mode. 12 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 ISO_PD 60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode. 15 1 IPO_PD 100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. 16 1 IBRO_PD 7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. 17 1 ERFO_BP 27MHz Oscillator Bypass. 20 1 PCLKDIV Peripheral Clock Divider. 0x18 0x00000001 SKBDFRQ GCR Frequency Indicator for Secure Keyboard. 0 3 ADCFRQ ADC clock Frequency. These bits define the ADC clock frequency. fADC = fPCLK / (ADCFRQ) 10 4 AONCLKDIV AON Clock Divider. These bits define the AON Domain Clock Divider. 14 2 div4 0 div8 1 div16 2 div32 3 PCLKDIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Clock Disable. 1 1 USB USB Clock Disable. 3 1 DMA DMA Clock Disable. 5 1 SPI0 SPI 0 Clock Disable. 6 1 SPI1 SPI 1 Clock Disable. 7 1 UART0 UART 0 Clock Disable. 9 1 UART1 UART 1 Clock Disable. 10 1 I2C0 I2C 0 Clock Disable. 13 1 CRYPTO Crypto Clock Disable. 14 1 TMR0 Timer 0 Clock Disable. 15 1 TMR1 Timer 1 Clock Disable. 16 1 TMR2 Timer 2 Clock Disable. 17 1 TMR3 Timer 3 Clock Disable. 18 1 TMR4 Timer 4 Clock Disable. 19 1 TMR5 Timer 5 Clock Disable. 20 1 SKBD Secure Keypad Clock Disable. 22 1 ADC ADC Clock Disable. 23 1 HTMR0 High Speed Timer 0 Clock Disable. 26 1 HTMR1 High Speed Timer 1 Clock Disable. 27 1 I2C1 I2C 1 Clock Disable. 28 1 PT Pluse Train Clock Disable. 29 1 SPIXIP SPI XIP Clock Disable. 30 1 SPIXIPC SPI XIPC Clock Disable. 31 1 MEMCTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 RAM4_WS System RAM4 WS Select. 4 1 RAM5_WS System RAM5 WS Select. 5 1 RAM6_WS System RAM6 WS Select. 6 1 ROM1_WS ROM1 WS Select. 7 1 RAM0LS_EN System RAM 0 Light Sleep Mode. 16 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 RAM1LS_EN System RAM 1 Light Sleep Mode. 17 1 RAM2LS_EN System RAM 2 Light Sleep Mode. 18 1 RAM3LS_EN System RAM 3 Light Sleep Mode. 19 1 RAM4LS_EN System RAM 4 Light Sleep Mode. 20 1 RAM5LS_EN System RAM 5 Light Sleep Mode. 21 1 RAM6LS_EN System RAM 6 Light Sleep Mode. 22 1 ICCXIPLS_EN ICACHE-XIP RAM Light Sleep Mode. 25 1 CRYPTOLS_EN MEU RAM Light Sleep Mode. 27 1 USBLS_EN USB FIFO Light Sleep Mode. 28 1 ROM0LS_EN ROM0 Light Sleep Mode. 29 1 ROM1LS_EN ROM1 Light Sleep Mode. 30 1 MAALS_EN MAA Light Sleep Mode. 31 1 MEMZ Memory Zeroize Control. 0x2C RAM0 System RAM Block 0 Zeroization. 0 1 nop No operation/complete. 0 start Start operation. 1 RAM1 System RAM Block 1 Zeroization. 1 1 RAM2 System RAM Block 2 Zeroization. 2 1 RAM3 System RAM Block 3 Zeroization. 3 1 RAM4 System RAM Block 4 Zeroization. 4 1 RAM5 System RAM Block 5 Zeroization. 5 1 RAM6 System RAM Block 6 Zeroization. 6 1 ICCXIP Internal ICC XIP Data and Tag RAM Zeroization. 9 1 CRYPTO MEU Memory Zeroization. 12 1 USBFIFO USB FIFO Zeroization. 13 1 SCCLKCTRL Smart Card Clock Control. 0x34 0x00000000 SC0CLK_DIV Smart Card0 Clock Divider 0 6 SC1CLK_DIV Smart Card1 Clock Divider 8 6 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 CODEINTERR Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. 1 1 norm Normal Operating Condition. 0 code Code Integrity Error. 1 SCMEMF System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. 5 1 norm Normal Operating Condition. 0 memory Memory Fault. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset_read read reset_done Reset complete. 0 busy Starts reset or indicates reset in progress. 1 PT PT Reset. 1 1 SPIXIP SPI XIPF Reset. 3 1 SPIXIPM SPI XIP Master Reset. 4 1 WDT1 WDT1 Reset. 8 1 SPI3 SPI3 Reset. 9 1 AC Auto-Cal Reset. 14 1 SEMA Semaphore Reset. 16 1 UART3 UART3 Reset. 18 1 SKBD SKBD Reset. 21 1 MSRADC MSRADC Reset. 22 1 SC0 SC0 Reset. 23 1 SC1 SC1 Reset. 24 1 HTMR0 HTIMER0 Reset. 28 1 HTMR1 HTIMER1 Reset. 29 1 CPU1 CPU1 Reset. 31 1 PCLKDIS1 Peripheral Clock Disable. 0x48 UART2 UART2 Clock Disable. 1 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 TRNG TRNG Clock Disable. 2 1 OTP OTP Clock Disable. 3 1 WDT0 Watchdog 0 Clock Disable. 4 1 WDT1 Watchdog 1 Clock Disable. 5 1 SEMA Semaphore Disable. 9 1 SPI3 SPI3 Clock Disable. 14 1 UART3 UART3 Clock Disable. 22 1 MSRADC MSRADC Clock Disable. 25 1 SC0 SC0 Clock Disable. 26 1 SC1 SC1 Clock Disable. 27 1 CPU1 CPU1 Clock Disable. 31 1 EVENTEN Event Enable Register. 0x4C DMA Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 RX Enable RXEV pin event. When this bit is set, RXEV event from the CPU is output to GPIO1.9. 1 1 TX Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9. 2 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSIE System Status Interrupt Enable Register. 0x54 ICEUNLOCK ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 CIE Code Integrity Error Interrupt Enable. 1 1 SCMF System Cache Memory Fault Interrupt Enable. 5 1 IPOCNT IPO Warmup Count Register. 0x58 WMUPCNT TBD 0 10 GPIO0 Individual I/O for each GPIO GPIO 0x40008000 0x00 0x1000 registers GPIO0 GPIO0 interrupt. 24 EN0 GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. 0x00 ALL Mask of all of the pins on the port. 0 32 ALTERNATE Alternate function enabled. 0 GPIO GPIO function is enabled. 1 EN0_SET GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. 0x04 ALL Mask of all of the pins on the port. 0 32 EN0_CLR GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. 0x08 ALL Mask of all of the pins on the port. 0 32 OUTEN GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. 0x0C ALL Mask of all of the pins on the port. 0 32 dis GPIO Output Disable 0 en GPIO Output Enable 1 OUTEN_SET GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. 0x10 ALL Mask of all of the pins on the port. 0 32 OUTEN_CLR GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. 0x14 ALL Mask of all of the pins on the port. 0 32 OUT GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. 0x18 ALL Mask of all of the pins on the port. 0 32 low Drive Logic 0 (low) on GPIO output. 0 high Drive logic 1 (high) on GPIO output. 1 OUT_SET GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. 0x1C write-only ALL Mask of all of the pins on the port. 0 32 no No Effect. 0 set Set GPIO_OUT bit in this position to '1' 1 OUT_CLR GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. 0x20 write-only ALL Mask of all of the pins on the port. 0 32 IN GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. 0x24 read-only ALL Mask of all of the pins on the port. 0 32 INTMODE GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. 0x28 ALL Mask of all of the pins on the port. 0 32 level Interrupts for this pin are level triggered. 0 edge Interrupts for this pin are edge triggered. 1 INTPOL GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. 0x2C ALL Mask of all of the pins on the port. 0 32 falling Interrupts are latched on a falling edge or low level condition for this pin. 0 rising Interrupts are latched on a rising edge or high condition for this pin. 1 INEN GPIO Input Enable 0x30 INTEN GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. 0x34 ALL Mask of all of the pins on the port. 0 32 dis Interrupts are disabled for this GPIO pin. 0 en Interrupts are enabled for this GPIO pin. 1 INTEN_SET GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. 0x38 ALL Mask of all of the pins on the port. 0 32 no No effect. 0 set Set GPIO_INT_EN bit in this position to '1' 1 INTEN_CLR GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. 0x3C ALL Mask of all of the pins on the port. 0 32 no No Effect. 0 clear Clear GPIO_INT_EN bit in this position to '0' 1 INTFL GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. 0x40 read-only ALL Mask of all of the pins on the port. 0 32 no No Interrupt is pending on this GPIO pin. 0 pending An Interrupt is pending on this GPIO pin. 1 INTFL_CLR GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. 0x48 ALL Mask of all of the pins on the port. 0 32 WKEN GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. 0x4C ALL Mask of all of the pins on the port. 0 32 dis PMU wakeup for this GPIO is disabled. 0 en PMU wakeup for this GPIO is enabled. 1 WKEN_SET GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. 0x50 ALL Mask of all of the pins on the port. 0 32 WKEN_CLR GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. 0x54 ALL Mask of all of the pins on the port. 0 32 DUALEDGE GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. 0x5C ALL Mask of all of the pins on the port. 0 32 no No Effect. 0 en Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. 1 PADCTRL0 GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x60 ALL The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Weak pull-up mode. 1 pd weak pull-down mode. 2 PADCTRL1 GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x64 ALL The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Weak pull-up mode. 1 pd weak pull-down mode. 2 EN1 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x68 ALL Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 EN1_SET GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. 0x6C ALL Mask of all of the pins on the port. 0 32 EN1_CLR GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. 0x70 ALL Mask of all of the pins on the port. 0 32 EN2 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x74 ALL Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 EN2_SET GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. 0x78 ALL Mask of all of the pins on the port. 0 32 EN2_CLR GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. 0x7C ALL Mask of all of the pins on the port. 0 32 HYSEN GPIO Input Hysteresis Enable. 0xA8 ALL Mask of all of the pins on the port. 0 32 SRSEL GPIO Slew Rate Enable Register. 0xAC ALL Mask of all of the pins on the port. 0 32 FAST Fast Slew Rate selected. 0 SLOW Slow Slew Rate selected. 1 DS0 GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. 0xB0 ALL Mask of all of the pins on the port. 0 32 ld GPIO port pin is in low-drive mode. 0 hd GPIO port pin is in high-drive mode. 1 DS1 GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. 0xB4 ALL Mask of all of the pins on the port. 0 32 PSSEL GPIO Pull Select Mode. 0xB8 ALL Mask of all of the pins on the port. 0 32 VSSEL GPIO Voltage Select. 0xC0 ALL Mask of all of the pins on the port. 0 32 GPIO1 Individual I/O for each GPIO 1 0x40009000 GPIO1 GPIO1 IRQ 25 HTMR High Speed Timer Module. 0x4001B000 0x00 0xFFF registers HTimer HTimer interrupt. 93 LNICNT HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter. 0x00 0x00000000 CNT HTimer Long Interval Counter. 0 32 SHICNT HTimer Short Interval Counter. This counter ticks every t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 CNT HTimer Short Interval Counter. 0 8 LNIALM HTimer Long Interval Alarm Value Register. 0x08 0x00000000 ALM HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0] 0 20 SHIALM HTimer Short Interval Alarm Value Register. 0x0C 0x00000000 ALM This register contains the reload value for the short interval alarm. 0 32 CTRL HTimer Control Register. 0x10 0x00000008 0xFFFFFF38 EN HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 LONG_ALM_IE Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 SHORT_ALM_IE Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 RDY HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register. 4 1 busy Register has not updated. 0 ready Ready. 1 RDY_IE HTimer Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 LONG_ALM_IF Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active. 0 pending Active. 1 SHORT_ALM_IF Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active. 0 Pending Active. 1 WR_EN Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits. 15 1 dis Not active. 0 en . 1 TRIM HTimer Trim Register. 0x14 0x00000000 TRIM HTimer Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. 0 8 VBAT_TMR VBAT Timer Value. When HTimer is running off of VBAT, this field is incremented every 32 seconds. 8 24 OSCCTRL HTimer Oscillator Control Register. 0x18 0x00000000 FILTER_EN Enable Filter. 0 1 IBIAS_SEL IBIAS Select. 1 1 2x 2x 0 4x 4x 1 HYST_EN HTimer Hysteresis Enable. 2 1 IBIAS_EN HTimer IBIAS Enable. 3 1 BYPASS HTimer Crystal Bypass 4 1 dis Disable. 0 en Enable. 1 SQW_32K HTimer 32kHz Square Wave Output 5 1 dis Disable. 0 en Enable. 1 HTMR1 High Speed Timer Module. 1 0x4001C000 HTMR1 HTMR1 IRQ 94 I2C0 Inter-Integrated Circuit. I2C 0x4001D000 32 0x00 0x1000 registers I2C0 I2C0 IRQ 13 CTRL Control Register0. 0x00 EN I2C Enable. [0:0] read-write dis Disable I2C. 0 en enable I2C. 1 MST_MODE Master Mode Enable. [1:1] read-write slave_mode Slave Mode. 0 master_mode Master Mode. 1 GC_ADDR_EN General Call Address Enable. [2:2] read-write dis Ignore Gneral Call Address. 0 en Acknowledge general call address. 1 IRXM_EN Interactive Receive Mode. [3:3] read-write dis Disable Interactive Receive Mode. 0 en Enable Interactive Receive Mode. 1 IRXM_ACK Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. [4:4] read-write ack return ACK (pulling SDA LOW). 0 nack return NACK (leaving SDA HIGH). 1 SCL_OUT SCL Output. This bits control SCL output when SWOE =1. [6:6] read-write drive_scl_low Drive SCL low. 0 release_scl Release SCL. 1 SDA_OUT SDA Output. This bits control SDA output when SWOE = 1. [7:7] read-write drive_sda_low Drive SDA low. 0 release_sda Release SDA. 1 SCL SCL status. This bit reflects the logic gate of SCL signal. [8:8] read-only SDA SDA status. THis bit reflects the logic gate of SDA signal. [9:9] read-only BB_EN Software Output Enable. [10:10] read-write outputs_disable I2C Outputs SCLO and SDAO disabled. 0 outputs_enable I2C Outputs SCLO and SDAO enabled. 1 READ Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. [11:11] read-only write Write. 0 read Read. 1 CLKSTR_DIS This bit will disable slave clock stretching when set. [12:12] read-write en Slave clock stretching enabled. 0 dis Slave clock stretching disabled. 1 ONE_MST_MODE SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. [13:13] read-write dis Standard open-drain operation: drive low for 0, Hi-Z for 1 0 en Non-standard push-pull operation: drive low for 0, drive high for 1 1 HS_EN High speed mode enable [15:15] read-write STATUS Status Register. 0x04 BUSY Bus Status. [0:0] read-only idle I2C Bus Idle. 0 busy I2C Bus Busy. 1 RX_EM RX empty. [1:1] read-only not_empty Not Empty. 0 empty Empty. 1 RX_FULL RX Full. [2:2] read-only not_full Not Full. 0 full Full. 1 TX_EM TX Empty. [3:3] not_empty Not Empty. 0 empty Empty. 1 TX_FULL TX Full. [4:4] not_empty Not Empty. 0 empty Empty. 1 MST_BUSY Clock Mode. [5:5] read-only not_actively_driving_scl_clock Device not actively driving SCL clock cycles. 0 actively_driving_scl_clock Device operating as master and actively driving SCL clock cycles. 1 INTFL0 Interrupt Status Register. 0x08 DONE Transfer Done Interrupt. [0:0] INT_FL0_Done inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 IRXM Interactive Receive Interrupt. [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 GC_ADDR_MATCH Slave General Call Address Match Interrupt. [2:2] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADDR_MATCH Slave Address Match Interrupt. [3:3] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 RX_THD Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. [4:4] inactive No interrupt is pending. 0 pending An interrupt is pending. RX_FIFO equal or more bytes than the threshold. 1 TX_THD Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. [5:5] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 STOP STOP Interrupt. [6:6] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 ADDR_ACK Address Acknowledge Interrupt. [7:7] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ARB_ERR Arbritation error Interrupt. [8:8] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TO_ERR timeout Error Interrupt. [9:9] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADDR_NACK_ERR Address NACK Error Interrupt. [10:10] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DATA_ERR Data NACK Error Interrupt. [11:11] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DNR_ERR Do Not Respond Error Interrupt. [12:12] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 START_ERR Start Error Interrupt. [13:13] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 STOP_ERR Stop Error Interrupt. [14:14] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TX_LOCKOUT Transmit Lock Out Interrupt. [15:15] MAMI Multiple Address Match Interrupt [21:16] RD_ADDR_MATCH Slave Read Address Match Interrupt [22:22] WR_ADDR_MATCH Slave Write Address Match Interrupt [23:23] INTEN0 Interrupt Enable Register. 0x0C read-write DONE Transfer Done Interrupt Enable. [0:0] read-write dis Interrupt disabled. 0 en Interrupt enabled when DONE = 1. 1 IRXM Description not available. [1:1] read-write dis Interrupt disabled. 0 en Interrupt enabled when RX_MODE = 1. 1 GC_ADDR_MATCH Slave mode general call address match received input enable. [2:2] read-write dis Interrupt disabled. 0 en Interrupt enabled when GEN_CTRL_ADDR = 1. 1 ADDR_MATCH Slave mode incoming address match interrupt. [3:3] read-write dis Interrupt disabled. 0 en Interrupt enabled when ADDR_MATCH = 1. 1 RX_THD RX FIFO Above Treshold Level Interrupt Enable. [4:4] read-write dis Interrupt disabled. 0 en Interrupt enabled. 1 TX_THD TX FIFO Below Treshold Level Interrupt Enable. [5:5] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOP Stop Interrupt Enable [6:6] read-write dis Interrupt disabled. 0 en Interrupt enabled when STOP = 1. 1 ADDR_ACK Received Address ACK from Slave Interrupt. [7:7] dis Interrupt disabled. 0 en Interrupt enabled. 1 ARB_ERR Master Mode Arbitration Lost Interrupt. [8:8] dis Interrupt disabled. 0 en Interrupt enabled. 1 TO_ERR Timeout Error Interrupt Enable. [9:9] dis Interrupt disabled. 0 en Interrupt enabled. 1 ADDR_NACK_ERR Master Mode Address NACK Received Interrupt. [10:10] dis Interrupt disabled. 0 en Interrupt enabled. 1 DATA_ERR Master Mode Data NACK Received Interrupt. [11:11] dis Interrupt disabled. 0 en Interrupt enabled. 1 DNR_ERR Slave Mode Do Not Respond Interrupt. [12:12] dis Interrupt disabled. 0 en Interrupt enabled. 1 START_ERR Out of Sequence START condition detected interrupt. [13:13] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOP_ERR Out of Sequence STOP condition detected interrupt. [14:14] dis Interrupt disabled. 0 en Interrupt enabled. 1 TX_LOCKOUT TX FIFO Locked Out Interrupt. [15:15] MAMI Multiple Address Match Interrupt [21:16] RD_ADDR_MATCH Slave Read Address Match Interrupt [22:22] WR_ADDR_MATCH Slave Write Address Match Interrupt [23:23] INTFL1 Interrupt Status Register 1. 0x10 RX_OV Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. [0:0] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TX_UN Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 START START Condition Status Flag. [2:2] INTEN1 Interrupt Staus Register 1. 0x14 read-write RX_OV Receiver Overflow Interrupt Enable. [0:0] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 TX_UN Transmit Underflow Interrupt Enable. [1:1] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 START START Condition Interrupt Enable. [2:2] FIFOLEN FIFO Configuration Register. 0x18 RX_DEPTH Receive FIFO Length. [7:0] read-only TX_DEPTH Transmit FIFO Length. [15:8] read-only RXCTRL0 Receive Control Register 0. 0x1C DNR Do Not Respond. [0:0] respond Always respond to address match. 0 not_respond_rx_fifo_empty Do not respond to address match when RX_FIFO is not empty. 1 FLUSH Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. [7:7] not_flushed FIFO not flushed. 0 flush Flush RX_FIFO. 1 THD_LVL Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. [11:8] RXCTRL1 Receive Control Register 1. 0x20 CNT Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. [7:0] LVL Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. [11:8] read-only TXCTRL0 Transmit Control Register 0. 0x24 PRELOAD_MODE Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. [0:0] TX_READY_MODE Transmit FIFO Ready Manual Mode. [1:1] en HW control of I2CTXRDY enabled. 0 dis HW control of I2CTXRDY disabled. 1 GC_ADDR_FLUSH_DIS TX FIFO General Call Address Match Auto Flush Disable. [2:2] en Enabled. 0 dis Disabled. 1 WR_ADDR_FLUSH_DIS TX FIFO Slave Address Match Write Auto Flush Disable. [3:3] en Enabled. 0 dis Disabled. 1 RD_ADDR_FLUSH_DIS TX FIFO Slave Address Match Read Auto Flush Disable. [4:4] en Enabled. 0 dis Disabled. 1 NACK_FLUSH_DIS TX FIFO received NACK Auto Flush Disable. [5:5] en Enabled. 0 dis Disabled. 1 FLUSH Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. [7:7] not_flushed FIFO not flushed. 0 flush Flush TX_FIFO. 1 THD_VAL Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. [11:8] TXCTRL1 Transmit Control Register 1. 0x28 PRELOAD_RDY Transmit FIFO Preload Ready. [0:0] LAST Transmit Last. [1:1] LVL Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. [11:8] read-only FIFO Data Register. 0x2C DATA Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. 0 8 MSTCTRL Master Control Register. 0x30 START Setting this bit to 1 will start a master transfer. [0:0] RESTART Setting this bit to 1 will generate a repeated START. [1:1] STOP Setting this bit to 1 will generate a STOP condition. [2:2] EX_ADDR_EN Slave Extend Address Select. [7:7] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 CODE Master Code. [10:8] IGN_ACK Master Ignore Acknowledge. [12:12] CLKLO Clock Low Register. 0x34 LO Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. [8:0] CLKHI Clock high Register. 0x38 HI Clock High. In master mode, these bits define the SCL high period. [8:0] HSCLK Clock high Register. 0x3C LO Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. [7:0] HI Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA [15:8] TIMEOUT Timeout Register 0x40 SCL_TO_VAL Timeout [15:0] DMA DMA Register. 0x48 TX_EN TX channel enable. [0:0] dis Disable. 0 en Enable. 1 RX_EN RX channel enable. [1:1] dis Disable. 0 en Enable. 1 4 4 SLAVE_MULTI[%s] Slave Address Register. SLAVE0 0x4C 32 read-write ADDR Slave Address. [9:0] DIS Slave Disable. [10:10] EXT_ADDR_EN Extended Address Select. [15:15] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 SLAVE0 Slave Address Register. 0x4C SLAVE1 Slave Address Register. 0x50 SLAVE2 Slave Address Register. 0x54 SLAVE3 Slave Address Register. 0x58 I2C1 Inter-Integrated Circuit. 1 0x4001E000 I2C1 I2C1 IRQ 36 I2C2 Inter-Integrated Circuit. 2 0x4001F000 I2C2 I2C2 IRQ 62 SFCC SPIXF Cache Controller Registers 0x4002F000 0x00 0x1000 registers INFO Cache ID Register. 0x0000 read-only RELNUM Release Number. Identifies the RTL release version. 0 6 PARTNUM Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. 6 4 ID Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. 10 6 SZ Memory Configuration Register. 0x0004 read-only 0x00080008 CCH Cache Size. Indicates total size in Kbytes of cache. 0 16 MEM Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. 16 16 CTRL Cache Control and Status Register. 0x0100 EN Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. 0 1 dis Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. 0 en Cache Enabled. 1 RDY Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. 16 1 read-only notReady Not Ready. 0 ready Ready. 1 INVALIDATE Invalidate All Registers. 0x0700 read-write INVALID Invalidate. 0 32 OTP One-Time Programmable (OTP) Memory Controller. OTP 0x40041000 0x00 0x1000 registers CTRL OTP Control Register. 0x00 ADDR Address of the OTP 32 bit value. 0 16 READ Read Operation. Setting this bit starts a read operation from the OTP. 24 1 no_op No operation. 0 start Initiate program operation. 1 WRITE Program Operation. Setting this bit starts a write operation from the OTP location specified in the ADDR field. 25 1 CLKDIV OTP Clock Divide Register. 0x04 PCLKDIV Clock Divider. The input clock, PCLK, is divided for generating OTP timing signals. 0 6 DIV2 Divide by 2 1 DIV4 Divide by 4 3 DIV8 Divide by 8 7 DIV16 Divide by 16 15 DIV32 Divide by 32 31 SPWE Smart PWE. If programmed value is 1, don't assert PWE. 8 1 PD Power Down OTP. OTP controller will generate power up and down signals for control pins. 9 1 HCLKDIV Clock Divider. The input clock, HCLK, is divided for generating OTP pwr on and down timing signals. 16 6 RDATA GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. 0x08 DATA OTP Read Data. 0 32 STATUS OTP Status Register. 0x0C BUSY OTP Busy Flag. This bit indicates whether the OTP controller is working a read or write operation. 0 1 FAIL OTP Failed Flag. This bit indicates whether OTP programming has failed. OTP programming fails if the controller accesses a 32 bit location that has not been previously programmed. 1 1 UNLOCK1 Unlock1 Flag. This bit indicates that 1st password was entered, and the user block is enabled for OTP programming. 8 1 UNLOCK3 Unlock3 Flag. This bit indicates that 3 words unlock process is complete. 9 1 PWR_RDY OTP Power On Status. 16 1 WDATA OTP Write Data Register. 0x30 DATA Write Data. 0 32 ACTRL0 Access Control for user block. 0x3C ADATA User Block Access Control. 0 32 ACTRL1 Access Control for sys and user block. 0x40 ADATA System Info Block Access Data. 0 32 PT Pulse Train Pulse_Train 0x4003C020 32 read-write 0 0x0010 registers RATE_LENGTH Pulse Train Configuration 0x0000 read-write rate_control Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train. 0 27 read-write mode Pulse Train Output Mode/Train Length 27 5 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 2_BIT Pulse train, 2 bit pattern. 2 3_BIT Pulse train, 3 bit pattern. 3 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 TRAIN Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length. 0x0004 read-write LOOP Pulse Train Loop Count 0x0008 read-write count Number of loops for this pulse train to repeat. 0 16 read-write delay Delay between loops of the Pulse Train in PT Peripheral Clock cycles 16 12 read-write RESTART Pulse Train Auto-Restart Configuration. 0x000C read-write pt_x_select Auto-Restart PT X Select 0 5 read-write on_pt_x_loop_exit Enable Auto-Restart on PT X Loop Exit 7 1 read-write pt_y_select Auto-Restart PT Y Select 8 5 read-write on_pt_y_loop_exit Enable Auto-Restart on PT Y Loop Exit 15 1 read-write PT1 Pulse Train 1 0x4003C030 PT2 Pulse Train 2 0x4003C040 PT3 Pulse Train 3 0x4003C050 PT4 Pulse Train 4 0x4003C060 PT5 Pulse Train 5 0x4003C070 PT6 Pulse Train 6 0x4003C080 PT7 Pulse Train 7 0x4003C090 PT8 Pulse Train 8 PTG Pulse Train Generation Pulse_Train 0x4003C000 32 read-write 0 0x0020 registers PT Pulse Train IRQ 59 ENABLE Global Enable/Disable Controls for All Pulse Trains 0x0000 read-write pt0 Enable/Disable control for PT0 0 1 read-write pt1 Enable/Disable control for PT1 1 1 read-write pt2 Enable/Disable control for PT2 2 1 read-write pt3 Enable/Disable control for PT3 3 1 read-write pt4 Enable/Disable control for PT4 4 1 read-write pt5 Enable/Disable control for PT5 5 1 read-write pt6 Enable/Disable control for PT6 6 1 read-write pt7 Enable/Disable control for PT7 7 1 read-write RESYNC Global Resync (All Pulse Trains) Control 0x0004 read-write pt0 Resync control for PT0 0 1 read-write pt1 Resync control for PT1 1 1 read-write pt2 Resync control for PT2 2 1 read-write pt3 Resync control for PT3 3 1 read-write pt4 Resync control for PT4 4 1 read-write pt5 Resync control for PT5 5 1 read-write pt6 Resync control for PT6 6 1 read-write pt7 Resync control for PT7 7 1 read-write STOP_INTFL Pulse Train Stop Interrupt Flags 0x0008 read-write pt0 Pulse Train 0 Stopped Interrupt Flag 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Flag 1 1 read-write pt2 Pulse Train 2 Stopped Interrupt Flag 2 1 read-write pt3 Pulse Train 3 Stopped Interrupt Flag 3 1 read-write pt4 Pulse Train 4 Stopped Interrupt Flag 4 1 read-write pt5 Pulse Train 5 Stopped Interrupt Flag 5 1 read-write pt6 Pulse Train 6 Stopped Interrupt Flag 6 1 read-write pt7 Pulse Train 7 Stopped Interrupt Flag 7 1 read-write STOP_INTEN Pulse Train Stop Interrupt Enable/Disable 0x000C read-write pt0 Pulse Train 0 Stopped Interrupt Enable/Disable 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Enable/Disable 1 1 read-write pt2 Pulse Train 2 Stopped Interrupt Enable/Disable 2 1 read-write pt3 Pulse Train 3 Stopped Interrupt Enable/Disable 3 1 read-write pt4 Pulse Train 4 Stopped Interrupt Enable/Disable 4 1 read-write pt5 Pulse Train 5 Stopped Interrupt Enable/Disable 5 1 read-write pt6 Pulse Train 6 Stopped Interrupt Enable/Disable 6 1 read-write pt7 Pulse Train 7 Stopped Interrupt Enable/Disable 7 1 read-write SAFE_EN Pulse Train Global Safe Enable. 0x0010 write-only PT0 0 1 write-only PT1 1 1 write-only PT2 2 1 write-only PT3 3 1 write-only PT4 4 1 write-only PT5 5 1 write-only PT6 6 1 write-only PT7 7 1 write-only SAFE_DIS Pulse Train Global Safe Disable. 0x0014 write-only PT0 0 1 write-only PT1 1 1 write-only PT2 2 1 write-only PT3 3 1 write-only PT4 4 1 write-only PT5 5 1 write-only PT6 6 1 write-only PT7 7 1 write-only READY_INTFL Pulse Train Ready Interrupt Flags 0x0018 read-write pt0 Pulse Train 0 Ready Interrupt Flag 0 1 read-write pt1 Pulse Train 1 Ready Interrupt Flag 1 1 read-write pt2 Pulse Train 2 Ready Interrupt Flag 2 1 read-write pt3 Pulse Train 3 Ready Interrupt Flag 3 1 read-write pt4 Pulse Train 4 Ready Interrupt Flag 4 1 read-write pt5 Pulse Train 5 Ready Interrupt Flag 5 1 read-write pt6 Pulse Train 6 Ready Interrupt Flag 6 1 read-write pt7 Pulse Train 7 Ready Interrupt Flag 7 1 read-write READY_INTEN Pulse Train Ready Interrupt Enable/Disable 0x001C read-write pt0 Pulse Train 0 Ready Interrupt Enable/Disable 0 1 read-write pt1 Pulse Train 1 Ready Interrupt Enable/Disable 1 1 read-write pt2 Pulse Train 2 Ready Interrupt Enable/Disable 2 1 read-write pt3 Pulse Train 3 Ready Interrupt Enable/Disable 3 1 read-write pt4 Pulse Train 4 Ready Interrupt Enable/Disable 4 1 read-write pt5 Pulse Train 5 Ready Interrupt Enable/Disable 5 1 read-write pt6 Pulse Train 6 Ready Interrupt Enable/Disable 6 1 read-write pt7 Pulse Train 7 Ready Interrupt Enable/Disable 7 1 read-write PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers LPCTRL Low Power Control Register. 0x00 RAMRET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 4 OVR Operating Voltage Range 4 2 1_1V 1.1V 2 RETREG_EN Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. 8 1 dis Disabled. 0 en Enabled. 1 FASTWK_EN Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). 10 1 dis Disabled. 0 en Enabled. 1 BGOFF Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode (default). 1 VCOREPOR_DIS VCore Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. 12 1 dis Disabled. 0 en Enabled. 1 VDDIOHHVMON_DIS VDDIOH High Voltage Monitor Disable. 17 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VDDIOHVMON_DIS VDDIO High Voltage Monitor Disable. 18 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VCOREHVMON_DIS VCORE High Voltage Monitor Disable. 19 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VCOREMON_DIS Vcore Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. 20 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VRTCMON_DIS VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. 21 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VDDAMON_DIS VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 22 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VDDIOMON_DIS VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 23 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VDDIOHMON_DIS VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 24 1 en Enable if Bandgap is ON (default) 0 dis Disabled. 1 VDDBMON_DIS VDDB Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. 27 1 dis Disabled. 0 en Enabled. 1 DEEPSLEEP_PDOUT_DIS PDOWN out enable in DEEPSLEEP mode. 30 1 LPWKFL0 Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 1 LPWKEN0 Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 LPWKFL1 Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C LPWKEN1 Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 LPWKFL2 Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2. 0x14 LPWKEN2 Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2. 0x18 LPWKFL3 Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3. 0x1C LPWKEN3 Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3. 0x20 LPPWKFL Low Power Peripheral Wakeup Status Register. 0x30 USBLS USB UTMI Linestate Detect Wakeup Flag (write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. 0 2 USBVBUS USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. 2 1 CPU1 CPU1 Detect Wakeup Flag (wite one to clear). This bit will be set when the SDMA IRQ transitions from low to high, or high to low. 3 1 BACKUP Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode. 16 1 RESET Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup 17 1 DRS_EVT Tamper Detext Status. Can only be cleared with a system reset. 19 1 LPPWKEN Low Power Peripheral Wakeup Enable Register. 0x34 USBLS USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal (s) on transition (s) from low to high or high to low when PM.USBWKEN is set. 0 2 USBVBUS USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. 2 1 CPU1 CPU1 Wakeup Enable. 3 1 LPMEMSD Low Power Memory Shutdown Control. 0x40 RAM0 System RAM block 0 Shut Down. 0 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM1 System RAM block 1 Shut Down. 1 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM2 System RAM block 2 Shut Down. 2 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM3 System RAM block 3 Shut Down. 3 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM4 System RAM block 4 Shut Down. 4 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM5 System RAM block 5 Shut Down. 5 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM6 System RAM block 6 Shut Down. 6 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ICCXIP XiP Instruction Cache RAM Shut Down. 8 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 CRYPTO MAA memory Shut Down. 10 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 USBFIFO USB FIFO Shut Down. 11 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ROM0 ROM0 Shut Down. 12 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 MEUMEM MEU memory Shut Down. 13 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ROM1 ROM1 Shut Down. 15 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 LPVDDPD Low Power VDD Domain Power Down Control. 0x44 GP0 General Purpose Register 0 0x48 GP1 General Purpose Register 1 0x4C RTC Real Time Clock and Alarm. 0x40006000 0x00 0x400 registers RTC RTC interrupt. 3 SEC RTC Second Counter. This register contains the 32-bit second counter. 0x00 0x00000000 SEC Seconds Counter. 0 32 SSEC RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 SSEC Sub-Seconds Counter (12-bit). 0 12 TODA Time-of-day Alarm. 0x08 0x00000000 TOD_ALARM Time-of-day Alarm. 0 20 SSECA RTC sub-second alarm. This register contains the reload value for the sub-second alarm. 0x0C 0x00000000 SSEC_ALARM This register contains the reload value for the sub-second alarm. 0 32 CTRL RTC Control Register. 0x10 0x00000008 0xFFFFFF38 EN Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 TOD_ALARM_IE Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 SSEC_ALARM_IE Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 RDY RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 4 1 busy Register has not updated. 0 ready Ready. 1 RDY_IE RTC Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 TOD_ALARM_IF Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active. 0 pending Active. 1 SSEC_ALARM_IF Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active. 0 pending Active. 1 SQW_EN Square Wave Output Enable. 8 1 dis Disable. 0 en Enable. 1 SQW_SEL Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 9 2 freq1Hz 1 Hz (Compensated). 0 freq512Hz 512 Hz (Compensated). 1 freq4KHz 4 KHz. 2 clkDiv8 RTC Input Clock / 8. 3 RD_EN Asynchronous Counter Read Enable. 14 1 sync Synchronous. 0 async Asynchronous. 1 WR_EN Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 15 1 ignore Ignored. 0 allow Allowed. 1 TRIM RTC Trim Register. 0x14 0x00000000 TRIM RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. 0 8 VBAT_TMR VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. 8 24 OSCCTRL RTC Oscillator Control Register. 0x18 0x00000000 FILTER_EN Enable Filter. 0 1 IBIAS_SEL IBIAS Select. 1 1 2x 2x 0 4x 4x 1 HYST_EN RTC Hysteresis Enable. 2 1 IBIAS_EN RTC IBIAS Enable. 3 1 BYPASS RTC Crystal Bypass 4 1 dis Disable. 0 en Enable. 1 SQW_32K RTC 32kHz Square Wave Output 5 1 dis Disable. 0 en Enable. 1 SIR System Initialization Registers. 0x40000400 read-only 0x00 0x400 registers SISTAT System Initialization Status Register. 0x00 read-only MAGIC Magic Word Validation. This bit is set by the system initialization block following power-up. 0 1 read-only read magicNotSet Magic word was not set (OTP has not been initialized properly). 0 magicSet Magic word was set (OTP contains valid settings). 1 CRCERR CRC Error Status. This bit is set by the system initialization block following power-up. 1 1 read-only read noError No CRC errors occurred during the read of the OTP memory block. 0 error A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. 1 SIADDR Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x04 read-only ERRADDR 0 32 FSTAT funcstat register. 0x100 read-only FPU FPU Function. 0 1 no 0 yes 1 USB USB Device. 1 1 no 0 yes 1 ADC 10-bit Sigma Delta ADC. 2 1 no 0 yes 1 SPIXIP SPIXIPffunction. 3 1 no 0 yes 1 ADC9 ADC9 function. 9 1 no 0 yes 1 SC SC function. 10 1 no 0 yes 1 NMI NMI function. 12 1 no 0 yes 1 SFSTAT Security Function 0x104 read-only SECBOOT Secure Boot Disable. 0 1 no 0 yes 1 SERLOAD Serial Load Disable function. 1 1 no 0 yes 1 TRNG TRNG function. 2 1 no 0 yes 1 AES AES function. 3 1 no 0 yes 1 SHA SHA function. 4 1 no 0 yes 1 SECMODE Security Mode Disable. 7 1 no 0 yes 1 SMON The Security Monitor block used to monitor system threat conditions. 0x40004000 0x00 0x400 registers EXTSCTRL External Sensor Control Register. 0x00 0x3800FFC0 EXTS_EN0 External Sensor Enable for input/output pair 0. 0 1 dis Disable. 0 en Enable. 1 EXTS_EN1 External Sensor Enable for input/output pair 1. 1 1 dis Disable. 0 en Enable. 1 EXTS_EN2 External Sensor Enable for input/output pair 2. 2 1 dis Disable. 0 en Enable. 1 EXTS_EN3 External Sensor Enable for input/output pair 3. 3 1 dis Disable. 0 en Enable. 1 EXTS_EN4 External Sensor Enable for input/output pair 4. 4 1 dis Disable. 0 en Enable. 1 EXTS_EN5 External Sensor Enable for input/output pair 5. 5 1 dis Disable. 0 en Enable. 1 EXTCNT External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered. 16 5 EXTFRQ External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair. 21 3 freq2000Hz Div 4 (2000Hz). 0 freq1000Hz Div 8 (1000Hz). 1 freq500Hz Div 16 (500Hz). 2 freq250Hz Div 32 (250Hz). 3 freq125Hz Div 64 (125Hz). 4 freq63Hz Div 128 (63Hz). 5 freq31Hz Div 256 (31Hz). 6 RFU Reserved. Do not use. 7 CLKDIV Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor. 24 3 div1 Divide by 1 (8000 Hz). 0 div2 Divide by 2 (4000 Hz). 1 div4 Divide by 4 (2000 Hz). 2 div8 Divide by 8 (1000 Hz). 3 div16 Divide by 16 (500 Hz). 4 div32 Divide by 32 (250 Hz). 5 div64 Divide by 64 (125 Hz). 6 BUSY Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain. 30 1 read-only idle Idle. 0 busy Update in Progress. 1 LOCK Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. 31 1 unlocked Unlocked. 0 locked Locked. 1 INTSCTRL Internal Sensor Control Register. 0x04 0x7F00FFF7 SHIELD_EN Die Shield Enable. 0 1 dis Disable. 0 en Enable. 1 TEMP_EN Temperature Sensor Enable. 1 1 dis Disable. 0 en Enable. 1 VBAT_EN Battery Monitor Enable. 2 1 dis Disable. 0 en Enable. 1 DFD_EN Digital Fault Dector Enable 3 1 DFD_NMI_EN Digital Fault NMI Enable 4 1 TAMPOUT_EN Tamper Output Enable. 7 1 LOTEMP_SEL Low Temperature Detection Select. 16 1 neg50C -50 degrees C. 0 neg30C -30 degrees C. 1 HITEMP_SEL High Temperature Detection Select. 17 1 VCORELO_EN VCORE Undervoltage Detect Enable. 18 1 dis Disable. 0 en Enable. 1 VCOREHI_EN VCORE Overvoltage Detect Enable. 19 1 dis Disable. 0 en Enable. 1 VDDLO_EN VDD Undervoltage Detect Enable. 20 1 dis Disable. 0 en Enable. 1 VDDHI_EN VDD Overvoltage Detect Enable. 21 1 dis Disable. 0 en Enable. 1 VGL_EN Voltage Glitch Detection Enable. 22 1 dis Disable. 0 en Enable. 1 LOCK Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. 31 1 unlocked Unlocked. 0 locked Locked. 1 SECALM Security Alarm Register. 0x08 0x00000000 0x00000000 DRS Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware. 0 1 complete No operation/complete. 0 start Start operation. 1 KEYWIPE Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped. 1 1 complete No operation/complete. 0 start Start operation. 1 SHIELD_FL Die Shield Flag. 2 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 LOTEMP_FL Low Temperature Detect. 3 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 HITEMP_FL High Temperature Detect. 4 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATLO_FL Battery Undervoltage Detect. 5 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATHI_FL Battery Overvoltage Detect. 6 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTS_FL External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. 7 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 DFD_FL Digital Fault Detector. 8 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VMAINPF_FL VMAIN Power Fail Flag. 9 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VCOREHI_FL VCORE Overvoltage Detect Flag. 10 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VDDHI_FL VDD Overvoltage Flag. 11 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VGL_FL Voltage Glitch Detection Flag. 12 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT0_FL External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 16 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT1_FL External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 17 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT2_FL External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 18 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT3_FL External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 19 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT4_FL External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 20 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT5_FL External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 21 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN0_FL External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 24 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN1_FL External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 25 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN2_FL External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 26 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN3_FL External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 27 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN4_FL External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 28 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN5_FL External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 29 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 SECDIAG Security Diagnostic Register. 0x0C read-write 0x00000001 0xFFC0FE02 POR_FL Power-On-Reset Flag. This bit is set once the power supply is conneted. 0 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 SHIELD_FL Die Shield Flag. 2 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 LOTEMP_FL Low Temperature Detect. 3 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 HITEMP_FL High Temperature Detect. 4 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATLO_FL Battery Undervoltage Detect. 5 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATHI_FL Battery Overvoltage Detect. 6 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 DYNS_FL Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. 7 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 AESKT_MEU AES Key Transfer. This bit is set to 1 when the NVSRAM 256 bit AES key is generated by the TRNG and loaded to the AES KEY NVSRAM Encryption registers. This bit is reset by a POR or DRS. 8 1 incomplete Key has not been transferred. 0 complete Key has been transferred. 1 AESKT_MEMPROT_XIP AES Key Transfer. This bit is set to 1 when AES MDU Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR. 9 1 incomplete Key has not been transferred. 0 complete Key has been transferred. 1 KEY0_ZERO Key0 Cleared. 10 1 incomplete Key has not been transferred. 0 complete Key has been transferred. 1 KEY1_ZERO Key1 Cleared. 11 1 incomplete Key has not been transferred. 0 complete Key has been transferred. 1 DFD_FL Digital Fault Detector Flag. 15 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTS0_FL External Sensor 0 Detect. 16 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTS1_FL External Sensor 1 Detect. 17 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTS2_FL External Sensor 2 Detect. 18 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTS3_FL External Sensor 3 Detect. 19 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTS4_FL External Sensor 4 Detect. 20 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTS5_FL External Sensor 5 Detect. 21 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 DLRTC DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred. 0x10 read-only 0x00000000 DLRTC DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured. 0 32 MEUCTRL MEU Configuration 0x24 0x00000000 ENC_EN Configuration plain/encrypted area of the backed NVSRAM. 0 7 LOCK Lock. 31 1 SECST Security Monitor Status Register. 0x34 read-only EXTSCTRL External Sensor Control Register Status. 0 1 allowed Access authorized. 0 notAllowed Access not authorized. 1 INTSCTRL Internal Sensor Control Register Status. 1 1 allowed Access authorized. 0 notAllowed Access not authorized. 1 SECALM Security Alarm Register Status. 2 1 allowed Access authorized. 0 notAllowed Access not authorized. 1 MEUCTRL Security Alarm Register Status. 7 1 allowed Access authorized. 0 notAllowed Access not authorized. 1 SDBE Security Monitor Self Destruct Byte. 0x38 SDBYTE Self Destruct Byte 0 8 SDBYTE_EN Self-Destruct Byte Enable. 31 1 SPIXFC SPI XiP Flash Configuration Controller 0x40027000 0 0x1000 registers SPIXFC SPIXFC IRQ 38 CTRL0 Control Register. 0x00 SSEL Slaves Select. 0 3 Slave_0 Slave 0 is selected. 0 Slave_1 Slave 1 is selected. 1 THREE_WIRE Three Wire Mode. 3 1 MODE Defines SPI Mode, Only valid values are 0 and 3. 4 2 SPI_Mode_0 SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0. 0 SPI_Mode_3 SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1. 3 PGSZ Page Size. 6 2 4_bytes 4 bytes. 0 8_bytes 8 bytes. 1 16_bytes 16 bytes. 2 32_bytes 32 bytes. 3 HICLK SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high. 8 4 16_SCLK 16 system clocks. 0 LOCLK SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low. 12 4 16_SCLK 16 system clocks. 0 SSACT Slaves Select Activate Timing. 16 2 0_CLKS 0 sytem clocks. 0 2_CLKS 2 sytem clocks. 1 4_CLKS 4 sytem clocks. 2 8_CLKS 8 sytem clocks. 3 SSINACT Slaves Select Inactive Timing. 18 2 4_CLKS 4 sytem clocks. 0 6_CLKS 6 sytem clocks. 1 8_CLKS 8 sytem clocks. 2 12_CLKS 12 sytem clocks. 3 IOSMPL Sample Delay 20 4 SSPOL SPIX Controller Slave Select Polarity Register. 0x04 SSPOL Slave Select Polarity. 0 1 lo Active Low. 0 hi Active High. 1 FCPOL FC Polarity. 8 1 lo Active Low. 0 hi Active High. 1 CTRL1 SPIX Controller General Controller Register. 0x08 EN SPI Master enable. 0 1 dis Disable SPI Master, putting a reset state. 0 en Enable SPI Master for processing transactions. 1 TX_FIFO_EN Transaction FIFO Enable. 1 1 dis_txfifo Disable Transaction FIFO. 0 en_txfifo Enable Transaction FIFO. 1 RX_FIFO_EN Result FIFO Enable. 2 1 DIS_RXFIFO Disable Result FIFO. 0 EN_RXFIFO Enable Result FIFO. 1 BB_EN Bit-Bang Mode. 3 1 dis Disable Bit-Bang Mode. 0 en Enable Bit-Bang Mode. 1 SSDR This bits reflects the state of the currently selected slave select. 4 1 output0 Selected Slave select output = 0. 0 output1 Selected Slave select output = 1. 1 FCDR This bits reflects the state of the selected FC. 5 1 SCLKDR SCLK Drive and State. 6 1 SCLK_0 SCLK is 0. 0 SCLK_1 SCLK is 1. 1 SDIO_DATA_IN SDIO Input Data Value. 8 4 SDIO0 SDIO[0] 0 SDIO1 SDIO[1] 1 SDIO2 SDIO[2] 2 SDIO3 SDIO[3] 3 BB_DATA_OUT Bit Bang SDIO Output. 12 4 SDIO0 SDIO[0] 0 SDIO1 SDIO[1] 1 SDIO2 SDIO[2] 2 SDIO3 SDIO[3] 3 BB_DATA_OUT_EN Bit Bang SDIO Output Enable. 16 4 SDIO0 SDIO[0] 0 SDIO1 SDIO[1] 1 SDIO2 SDIO[2] 2 SDIO3 SDIO[3] 3 SIMPLE_EN Simple Mode Enable. 20 1 SIMPLE_RX Simple Receive Enable. 21 1 SIMPLE_SS Simple Mode Slave Select. 22 1 SCLK_FB Enable SCLK Feedback Mode. 24 1 Dis 0 En 1 SCLK_FB_INV SCK Invert. 25 1 CTRL2 SPIX Controller FIFO Control and Status Register. 0x0C TX_AE_LVL Transaction FIFO Almost Empty Level. 0 4 TX_CNT Transaction FIFO Used. 8 5 RX_AF_LVL Results FIFO Almost Full Level. 16 5 RX_CNT Result FIFO Used. 24 6 CTRL3 SPIX Controller Special Control Register. 0x10 SAMPLE Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the next slave select assertion. 0 1 MISO_FC_EN MISO FC Enable. 1 1 SDIO_OUT_VAL SDIO Output Value Sample Mode 4 4 SDIO_OUT_EN SDIO Output Enable Sample Mode 8 4 SCLKINH3 SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams. 16 1 EN Allow trailing SCLK low pulse prior to Slave Select de-assertion. 0 DIS Inhibit trailing SCLK low pulse prior to Slave Select de-assertion. 1 INTFL SPIX Controller Interrupt Status Register. 0x14 TX_STALLED Transaction Stalled Interrupt Flag. 0 1 CLR Normal FIFO Transaction. 0 SET Stalled FIFO Transaction. 1 RX_STALLED Results Stalled Interrupt Flag. 1 1 CLR Normal FIFO Operation. 0 SET Stalled FIFO. 1 TX_RDY Transaction Ready Interrupt Status. 2 1 CLR FIFO Transaction not ready. 0 SET FIFO Transaction ready. 1 RX_DONE Results Done Interrupt Status. 3 1 CLR Results FIFO ready. 0 SET Results FIFO Not ready. 1 TX_AE Transaction FIFO Almost Empty Flag. 4 1 CLR Transaction FIFO not Almost Empty. 0 SET Transaction FIFO Almost Empty. 1 RX_AF Results FIFO Almost Full Flag. 5 1 CLR Results FIFO level below the Almost Full level. 0 SET Results FIFO level at Almost Full level. 1 INTEN SPIX Controller Interrupt Enable Register. 0x18 TX_STALLED Transaction Stalled Interrupt Enable. 0 1 EN Disable Transaction Stalled Interrupt. 0 DIS Enable Transaction Stalled Interrupt. 1 RX_STALLED Results Stalled Interrupt Enable. 1 1 EN Disable Results Stalled Interrupt. 0 DIS Enable Results Stalled Interrupt. 1 TX_RDY Transaction Ready Interrupt Enable. 2 1 EN Disable FIFO Transaction Ready Interrupt. 0 DIS Enable FIFO Transaction Ready Interrupt. 1 RX_DONE Results Done Interrupt Enable. 3 1 EN Disable Results Done Interrupt. 0 DIS Enable Results Done Interrupt. 1 TX_AE Transaction FIFO Almost Empty Interrupt Enable. 4 1 EN Disable Transaction FIFO Almost Empty Interrupt. 0 DIS Enable Transaction FIFO Almost Empty Interrupt. 1 RX_AF Results FIFO Almost Full Interrupt Enable. 5 1 EN Disable Results FIFO Almost Full Interrupt. 0 DIS Enable Results FIFO Almost Full Interrupt. 1 HEADER Simple Header 0x1C TX_BIDIR TX Bdirectional Header. 0 14 RX_ONLY RX Only Header. 16 14 AUTOCTRL Auto Control Register. 0x20 AUTOCMD Auto Command Register. 0x24 SPIXFC_FIFO SPI XiP Master Controller FIFO. 0x400BC000 0 0x1000 registers TX_8 SPI TX FIFO 8-Bit Write 0x00 8 uint8_t TX_16 SPI TX FIFO 16-Bit Write TX_8 0x00 16 uint16_t TX_32 SPI TX FIFO 32-Bit Write TX_8 0x00 32 uint32_t RX_8 SPI RX FIFO 8-Bit Access 0x04 8 uint8_t RX_16 SPI RX FIFO 16-Bit Access RX_8 0x04 16 uint16_t RX_32 SPI RX FIFO 32-Bit Access RX_8 0x04 32 uint32_t SPIXFM SPIXF Master 0x40026000 0x00 0x1000 registers CTRL SPIX Control Register. 0x00 MODE Defines SPI Mode, Only valid values are 0 and 3. 0 2 SCLK_HI_SAMPLE_RISING Description not available. 0 SCLK_LO_SAMPLE_FAILLING Description not available. 3 SSPOL Slave Select Polarity. 2 1 ACTIVE_HIGH Slave Select is Active High. 0 ACTIVE_LOW Slave Select is Active Low. 1 SSEL Slave Select. Only valid value is zero. 4 3 LOCLK Number of system clocks that SCLK will be low when SCLK pulses are generated. 8 4 HICLK Number of system clocks that SCLK will be high when SCLK pulses are generated. 12 4 SSACT Slave Select Active Timing. 16 2 off 0 system clocks. 0 for_2_mod_clk 2 System clocks. 1 for_4_mod_clk 4 System clocks. 2 for_8_mod_clk 8 System clocks. 3 SSINACT Slave Select Inactive Timing. 18 2 for_1_mod_clk 1 system clocks. 0 for_3_mod_clk 3 System clocks. 1 for_5_mod_clk 5 System clocks. 2 for_9_mod_clk 9 System clocks. 3 FETCHCTRL SPIX Fetch Control Register. 0x04 CMD_VAL Command Value sent to target to initiate fetching from SPI flash. 0 8 CMD_WDTH Command Width. Number of data I/O used to send commands. 8 2 Single Single SDIO. 0 Dual_IO Dual SDIO. 1 Quad_IO Quad SDIO. 2 Invalid Invalid. 3 ADDR_WDTH Address Width. Number of data I/O used to send address, and mode/dummy clocks. 10 2 Single Single SDIO. 0 Dual_IO Dual SDIO. 1 Quad_IO Quad SDIO. 2 Invalid Invalid. 3 DATA_WDTH Data Width. Number of data I/O used to receive data. 12 2 Single Single SDIO. 0 Dual_IO Dual SDIO. 1 Quad_IO Quad SDIO. 2 Invalid Invalid. 3 4BADDR Four Byte Address Mode. Enables 4-byte Flash Address Mode. 16 1 3 3 Byte Address Mode. 0 4 4 Byte Address Mode. 1 MODECTRL SPIX Mode Control Register. 0x08 MDCLK Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch. 0 4 NOCMD No Command Mode. 8 1 always Send read command every time SPI transaction is initiated. 0 once Send read command only once. NO read command in subsequent SPI transactions. 1 EXIT_NOCMD Mode Send. 9 1 MODEDATA SPIX Mode Data Register. 0x0C DATA Mode Data. Specifies the data to send with the Dummy/Mode clocks. 0 16 OUT_EN Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA. 16 16 FBCTRL SPIX Feedback Control Register. 0x10 EN Enable SCLK feedback mode. 0 1 dis Disable SCLK feedback mode. 0 en Enable SCLK feedback mode. 1 INVERT Invert SCLK in feedback mode. 1 1 dis Disable Invert SCLK feedback mode. 0 en Enable Invert SCLK feedback mode. 1 IOCTRL SPIX IO Control Register. 0x1C SCLK_DS SCLK drive Strength. This bit controls the drive strength on the SCLK pin. 0 1 Low Low drive strength. 0 High High drive strength. 1 SS_DS Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin. 1 1 Low Low drive strength. 0 High High drive strength. 1 SDIO_DS SDIO Drive Strength. This bit controls the drive strength of all SDIO pins. 2 1 Low Low drive strength. 0 High High drive strength. 1 PADCTRL IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins. 3 2 tri_state Tristate. 0 Pull_Up Pull-Up. 1 Pull_down Pull-Down. 2 MEMSECCTRL SPIX Memory Security Control Register. 0x20 DEC_EN Decryption Enable. 0 1 dis Disable decryption of SPIX data. 0 en Enable decryption of SPIX data. 1 AUTH_DIS Integrity Enable. 1 1 en Integrity checking enabled. 0 dis Integrity checking disabled. 1 CNTOPT_EN Enable counters optimization (when authentication is enabled). 2 1 dis Disable counter optimization. 0 en Enable counter optimization. 1 INTERL_DIS Disable authenticity interleaving (when authentication is enabled) 3 1 dis Disable interleaving of SPIX data. 1 en Enable interleaving of SPIX data. 0 AUTHERR_FL Authentication Error Flag Bit. 4 1 BUSIDLE Bus Idle 0x24 BUSIDLE A 16-bit timer will be triggered for each external access. The timer will be restarted if another access is performed before the timer expires. When the timer expires, slave select will be deactivated. 0 16 AUTHOFFSET Auth Offset 0x28 BYPASS_MODE Bypass Mode Register. 0x2C EN Enable bypass. 0 1 FCLK_DELAY FCLK Delay. 1 3 0_NS 0ns 0 0P5_NS 0.5ns 1 1P0_NS 1.0ns 2 1P5_NS 1.5ns 3 2P0_NS 2.0ns 4 2P5_NS 2.5ns 5 3P0_NS 3.0ns 6 3P5_NS 3.0ns 7 SCLK_DELAY SCLK Delay. 4 3 0_NS 0ns 0 0P5_NS 0.5ns 1 1P0_NS 1.0ns 2 1P5_NS 1.5ns 3 2P0_NS 2.0ns 4 2P5_NS 2.5ns 5 3P0_NS 3.0ns 6 3P5_NS 3.0ns 7 SPI SPI peripheral. 0x40046000 0x00 0x1000 registers SPI0 16 FIFO32 Register for reading and writing the FIFO. 0x00 32 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 32 2 2 FIFO16[%s] Register for reading and writing the FIFO. FIFO32 0x00 16 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 16 4 1 FIFO8[%s] Register for reading and writing the FIFO. FIFO32 0x00 8 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 8 CTRL0 Register for controlling SPI peripheral. 0x04 read-write EN SPI Enable. 0 1 dis SPI is disabled. 0 en SPI is enabled. 1 MST_MODE Master Mode Enable. 1 1 dis SPI is Slave mode. 0 en SPI is Master mode. 1 SS_IO Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 4 1 output Slave select 0 is output. 0 input Slave Select 0 is input, only valid if MMEN=1. 1 START Start Transmit. 5 1 start Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. 1 SS_CTRL Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. 8 1 DEASSERT SPI De-asserts Slave Select at the end of a transaction. 0 ASSERT SPI leaves Slave Select asserted at the end of a transaction. 1 SS_ACTIVE Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 16 4 SS0 SS0 is selected. 0x1 SS1 SS1 is selected. 0x2 SS2 SS2 is selected. 0x4 SS3 SS3 is selected. 0x8 CTRL1 Register for controlling SPI peripheral. 0x08 read-write TX_NUM_CHAR Nubmer of Characters to transmit. 0 16 RX_NUM_CHAR Nubmer of Characters to receive. 16 16 CTRL2 Register for controlling SPI peripheral. 0x0C read-write CLKPHA Clock Phase. 0 1 Rising_Edge Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 0 Falling_Edge Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 1 CLKPOL Clock Polarity. 1 1 Normal Normal Clock. Use when in SPI Mode 0 and Mode 1 0 Inverted Inverted Clock. Use when in SPI Mode 2 and Mode 3 1 SCLK_FB_INV Clock Polarity. 4 1 Normal Normal Clock. Use when in SPI Mode 0 and Mode 1 0 Inverted Inverted Clock. Use when in SPI Mode 2 and Mode 3 1 NUMBITS Number of Bits per character. 8 4 16 16 bits per character. 0 1 1 bits per character. 1 2 2 bits per character. 2 3 3 bits per character. 3 4 4 bits per character. 4 5 5 bits per character. 5 6 6 bits per character. 6 7 7 bits per character. 7 8 8 bits per character. 8 9 9 bits per character. 9 10 10 bits per character. 10 11 11 bits per character. 11 12 12 bits per character. 12 13 13 bits per character. 13 14 14 bits per character. 14 15 15 bits per character. 15 DATA_WIDTH SPI Data width. 12 2 Mono 1 data pin. 0 Dual 2 data pins. 1 Quad 4 data pins. 2 THREE_WIRE Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. 15 1 dis Use four wire mode (Mono only). 0 en Use three wire mode. 1 SSPOL Slave Select Polarity, each Slave Select can have unique polarity. 16 4 SS0_high SS0 active high. 0x1 SS1_high SS1 active high. 0x2 SS2_high SS2 active high. 0x4 SS3_high SS3 active high. 0x8 SSTIME Register for controlling SPI peripheral/Slave Select Timing. 0x10 read-write PRE Slave Select Pre delay 1. 0 8 256 256 system clocks between SS active and first serial clock edge. 0 POST Slave Select Post delay 2. 8 8 256 256 system clocks between last serial clock edge and SS inactive. 0 INACT Slave Select Inactive delay. 16 8 256 256 system clocks between transactions. 0 CLKCTRL Register for controlling SPI clock rate. 0x14 read-write LO Low duty cycle control. In timer mode, reload[7:0]. 0 8 Dis Duty cycle control of serial clock generation is disabled. 0 HI High duty cycle control. In timer mode, reload[15:8]. 8 8 Dis Duty cycle control of serial clock generation is disabled. 0 CLKDIV System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. 16 4 DMA Register for controlling DMA. 0x1C read-write TX_THD_VAL Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. 0 5 TX_FIFO_EN Transmit FIFO enabled for SPI transactions. 6 1 dis Transmit FIFO is not enabled. 0 en Transmit FIFO is enabled. 1 TX_FLUSH Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. . 7 1 CLEAR Clear the Transmit FIFO, clears any pending TX FIFO status. 1 TX_LVL Count of entries in TX FIFO. 8 6 read-only TX_EN TX DMA Enable. 15 1 DIS TX DMA requests are disabled, andy pending DMA requests are cleared. 0 en TX DMA requests are enabled. 1 RX_THD_VAL Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. 16 5 RX_FIFO_EN Receive FIFO enabled for SPI transactions. 22 1 DIS Receive FIFO is not enabled. 0 en Receive FIFO is enabled. 1 RX_FLUSH Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 23 1 CLEAR Clear the Receive FIFO, clears any pending RX FIFO status. 1 RX_LVL Count of entries in RX FIFO. 24 6 read-only RX_EN RX DMA Enable. 31 1 dis RX DMA requests are disabled, any pending DMA requests are cleared. 0 en RX DMA requests are enabled. 1 INTFL Register for reading and clearing interrupt flags. All bits are write 1 to clear. 0x20 read-write TX_THD TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL RX FIFO FULL. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSA Slave Select Asserted. 4 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSD Slave Select Deasserted. 5 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 FAULT Multi-Master Mode Fault. 8 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 ABORT Slave Abort Detected. 9 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 MST_DONE Master Done, set when SPI Master has completed any transactions. 11 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_OV Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 12 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_UN Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. 13 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_OV Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. 14 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_UN Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. 15 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 INTEN Register for enabling interrupts. 0x24 read-write TX_THD TX FIFO Threshold interrupt enable. 0 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_EM TX FIFO Empty interrupt enable. 1 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_THD RX FIFO Threshold Crossed interrupt enable. 2 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_FULL RX FIFO FULL interrupt enable. 3 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSA Slave Select Asserted interrupt enable. 4 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSD Slave Select Deasserted interrupt enable. 5 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 FAULT Multi-Master Mode Fault interrupt enable. 8 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 ABORT Slave Abort Detected interrupt enable. 9 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 MST_DONE Master Done interrupt enable. 11 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_OV Transmit FIFO Overrun interrupt enable. 12 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_UN Transmit FIFO Underrun interrupt enable. 13 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_OV Receive FIFO Overrun interrupt enable. 14 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_UN Receive FIFO Underrun interrupt enable. 15 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 WKFL Register for wake up flags. All bits in this register are write 1 to clear. 0x28 read-write TX_THD Wake on TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM Wake on TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD Wake on RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL Wake on RX FIFO Full. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 WKEN Register for wake up enable. 0x2C read-write TX_THD Wake on TX FIFO Threshold Crossed Enable. 0 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 TX_EM Wake on TX FIFO Empty Enable. 1 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_THD Wake on RX FIFO Threshold Crossed Enable. 2 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_FULL Wake on RX FIFO Full Enable. 3 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 STATUS SPI Status register. 0x30 read-only BUSY SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 0 1 not SPI not active. 0 active SPI active. 1 SPI1 SPI peripheral. 1 0x40047000 SPI1 SPI1 IRQ 17 SPI2 SPI peripheral. 2 0x400BE000 SPI2 SPI2 IRQ 56 TMR0 32-bit reloadable timer that can be used for timing and event counting. Timers 0x40010000 0x00 0x1000 registers TMR0 TMR0 IRQ 5 CNT Count. This register stores the current timer count. 0x00 0x00000001 COUNT Count. 0 32 CMP Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. 0x04 0x0000FFFF COMPARE Compare. 0 32 PWM PWM. This register stores the value that is compared to the current timer count. 0x08 PWM PWM 0 32 INTFL Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. 0x0C oneToClear IRQ Clear Interrupt. 0 1 CTRL Timer Control Register. 0x10 MODE Timer Mode. 0 3 oneShot One Shot Mode. 0 continuous Continuous Mode. 1 counter Counter Mode. 2 pwm PWM Mode. 3 capture Capture Mode. 4 compare Compare Mode. 5 gated Gated Mode. 6 captureCompare Capture/Compare Mode. 7 CLKDIV Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. 3 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 POL Timer input/output polarity bit. 6 1 activeHi Active High. 0 activeLo Active Low. 1 EN Timer Enable. 7 1 dis Disable. 0 en Enable. 1 CLKDIV3 MSB of prescaler value. 8 1 PWMSYNC Timer PWM Synchronization Mode Enable. 9 1 dis Disable. 0 en Enable. 1 NOLHPOL Timer PWM output 0A polarity bit. 10 1 dis Disable. 0 en Enable. 1 NOLLPOL Timer PWM output 0A' polarity bit. 11 1 dis Disable. 0 en Enable. 1 PWMCKBD Timer PWM output 0A Mode Disable. 12 1 dis Disable. 1 en Enable. 0 NOLCMP Timer Non-Overlapping Compare Register. 0x14 LO Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. 0 8 HI Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. 8 8 TMR1 32-bit reloadable timer that can be used for timing and event counting. 1 0x40011000 TMR1 TMR1 IRQ 6 TMR2 32-bit reloadable timer that can be used for timing and event counting. 2 0x40012000 TMR2 TMR2 IRQ 7 TMR3 32-bit reloadable timer that can be used for timing and event counting. 3 0x40013000 TMR3 TMR3 IRQ 8 TMR4 32-bit reloadable timer that can be used for timing and event counting. 4 0x40014000 TMR4 TMR4 IRQ 9 TMR5 32-bit reloadable timer that can be used for timing and event counting. 5 0x40015000 TMR5 TMR5 IRQ 10 TRNG Random Number Generator. 0x4004D000 0x00 0x1000 registers TRNG TRNG interrupt. 4 CTRL TRNG Control Register. 0x00 0x00000003 OD_HEALTH Start On-Demand health test. 0 1 RND_IE To enable IRQ generation when a new 32-bit Random number is ready. 1 1 disable Disable 0 enable Enable 1 HEALTH_IE Enable IRQ generation when a health test fails. 2 1 MEU_KEYGEN If set to 1, the TRNG generates the 256-bit AES MEU keys. 3 1 XIP_KEYGEN If set to 1, the TRNG generates the 128-bit QSPI (XIP) keys. 4 1 OD_ROMON Start ring oscillator monitor on demand test. 6 1 OD_EE Start entropy estimator on demand test. 7 1 ROMON_EE_FOE Ring Oscillator Monitors and Entropy Estimator Freeze on Error. 8 1 ROMON_EE_FOD Ring Oscillator Monitors and Entropy Estimator Freeze on Done. 9 1 EBLS Entropy Bit Load Select. 10 1 KEYWIPE To wipe the Battery Backed key. 15 1 GET_TERO_CNT Get Tero Count. 16 1 EE_DONE_IE Entropy Estimator Done Interrupt Enable. 23 1 ROMON_DIS Ring Oscillator Disable. 24 3 RO_0 Ring Oscillator 0. 1 RO_1 Ring Oscillator 1. 2 RO_2 Ring Oscillator 2. 4 STATUS Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x04 RDY 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. 0 1 Busy TRNG Busy 0 Ready 32 bit random data is ready 1 OD_HEALTH On-Demand health test status. 1 1 HEALTH Health test status. 2 1 SRCFAIL Entropy source has failed. 3 1 AES_KEYGEN AESKGD. 4 1 OD_ROMON On demand ring oscillator test status. 6 1 OD_EE On demand entropy estimator status. 7 1 PP_ERR Post process error. 8 1 ROMON_0_ERR Ring Oscillator 0 Monitor Error. 9 1 ROMON_1_ERR Ring Oscillator 1 Monitor Error. 10 1 ROMON_2_ERR Ring Oscillator 2 Monitor Error. 11 1 EE_ERR_THR Entropy Estimator Threshold Error. 12 1 EE_ERR_OOB Entropy Estimator Out of Bounds Error.. 13 1 EE_ERR_LOCK Entropy Estimator Lock Error. 14 1 TERO_CNT_RDY TERO Count Ready. 16 1 RC_ERR Repetition Count Error. 17 1 AP_ERR Adaptive Proportion Error. 18 1 DATA_DONE Data register has been loaded with at least 32 new entropy bits. 19 1 DATA_NIST_DONE Data NIST register has been loaded with at least 32 new entropy bits. 20 1 HEALTH_DONE Health Test Done. 21 1 ROMON_DONE Ring Oscillator Monitor Test Done. 22 1 EE_DONE Entropy Estimator Test Done. 23 1 DATA Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x08 read-only DATA Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. 0 32 DATA_NIST Data NIST Register. 0x38 DATA Ring Oscillator 1 Monitor Last Ring Oscillator Count. 0 32 UART UART Low Power Registers 0x40042000 0x00 0x1000 registers CTRL Control register 0x0000 RX_THD_VAL This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) 0 4 PAR_EN Parity Enable 4 1 PAR_EO when PAREN=1 selects odd or even parity odd is 1 even is 0 5 1 PAR_MD Selects parity based on 1s or 0s count (when PAREN=1) 6 1 CTS_DIS CTS Sampling Disable 7 1 TX_FLUSH Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. 8 1 RX_FLUSH Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. 9 1 CHAR_SIZE Selects UART character size 10 2 5bits 5 bits 0 6bits 6 bits 1 7bits 7 bits 2 8bits 8 bits 3 STOPBITS Selects the number of stop bits that will be generated 12 1 HFC_EN Enables/disables hardware flow control 13 1 RTSDC Hardware Flow Control RTS Mode 14 1 BCLKEN Baud clock enable 15 1 BCLKSRC To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. 16 2 Peripheral_Clock apb clock 0 External_Clock Clock 1 1 CLK2 Clock 2 2 CLK3 Clock 3 3 DPFE_EN Data/Parity bit frame error detection enable 18 1 BCLKRDY Baud clock Ready read only bit 19 1 UCAGM UART Clock Auto Gating mode 20 1 FDM Fractional Division Mode 21 1 DESM RX Dual Edge Sampling Mode 22 1 STATUS Status register 0x0004 read-only TX_BUSY Read-only flag indicating the UART transmit status 0 1 RX_BUSY Read-only flag indicating the UART receiver status 1 1 RX_EM Read-only flag indicating the RX FIFO state 4 1 RX_FULL Read-only flag indicating the RX FIFO state 5 1 TX_EM Read-only flag indicating the TX FIFO state 6 1 TX_FULL Read-only flag indicating the TX FIFO state 7 1 RX_LVL Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) 8 4 TX_LVL Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) 12 4 INTEN Interrupt Enable control register 0x0008 RX_FERR Enable Interrupt For RX Frame Error 0 1 RX_PAR Enable Interrupt For RX Parity Error 1 1 CTS_EV Enable Interrupt For CTS signal change Error 2 1 RX_OV Enable Interrupt For RX FIFO Overrun Error 3 1 RX_THD Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD 4 1 TX_OB Enable Interrupt For TX FIFO has only one byte remaining. 5 1 TX_HE Enable Interrupt For TX FIFO has half empty 6 1 INTFL Interrupt status flags Control register 0x000C RX_FERR Flag for RX Frame Error Interrupt. 0 1 RX_PAR Flag for RX Parity Error interrupt 1 1 CTS_EV Flag for CTS signal change interrupt (hardware flow control disabled) 2 1 RX_OV Flag for RX FIFO Overrun interrupt 3 1 RX_THD Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field 4 1 TX_OB Flag for interrupt when TX FIFO has only one byte remaining. 5 1 TX_HE Flag for interrupt when TX FIFO is half empty 6 1 CLKDIV Clock Divider register 0x0010 CLKDIV Baud rate divisor value 0 20 OSR Over Sampling Rate register 0x0014 OSR OSR 0 3 TXPEEK TX FIFO Output Peek register 0x0018 DATA Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field. 0 8 PNR Pin register 0x001C CTS Current sampled value of CTS IO 0 1 read-only RTS This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level. 1 1 FIFO FIFO Read/Write register 0x0020 DATA Load/unload location for TX and RX FIFO buffers. 0 8 RX_PAR Parity error flag for next byte to be read from FIFO. 8 1 DMA DMA Configuration register 0x0030 TX_THD_VAL TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory. 0 4 TX_EN TX DMA channel enable 4 1 RX_THD_VAL Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory. 5 4 RX_EN RX DMA channel enable 9 1 WKEN Wake up enable Control register 0x0034 RX_NE Wake-Up Enable for RX FIFO Not Empty 0 1 RX_FULL Wake-Up Enable for RX FIFO Full 1 1 RX_THD Wake-Up Enable for RX FIFO Threshold Met 2 1 WKFL Wake up Flags register 0x0038 RX_NE Wake-Up Flag for RX FIFO Not Empty 0 1 RX_FULL Wake-Up Flag for RX FIFO Full 1 1 RX_THD Wake-Up Flag for RX FIFO Threshold Met 2 1 UART1 UART Low Power Registers 1 0x40043000 UART2 UART Low Power Registers 2 0x40044000 UART3 UART Low Power Registers 3 0x40045000 USBHS USB 2.0 High-speed Controller. 0x400B1000 0 0x1000 registers USB 2 FADDR Function address register. 0x00 8 0x00 ADDR Function address for this controller. 0 7 read-write UPDATE Set when ADDR is written, cleared when new address takes effect. 7 1 read-only POWER Power management register. 0x01 8 EN_SUSPENDM Enable SUSPENDM signal. 0 1 read-write SUSPEND Suspend mode detected. 1 1 read-only RESUME Generate resume signaling. 2 1 read-write RESET Bus reset detected. 3 1 read-only HS_MODE High-speed mode detected. 4 1 read-only HS_ENABLE High-speed mode enable. 5 1 read-write SOFTCONN Softconn. 6 1 read-write ISO_UPDATE Wait for SOF during Isochronous xfers. 7 1 read-write INTRIN Interrupt register for EP0 and IN EP1-15. 0x02 16 EP15_IN_INT Endpoint 15 interrupt. 15 1 read-only EP14_IN_INT Endpoint 14 interrupt. 14 1 read-only EP13_IN_INT Endpoint 13 interrupt. 13 1 read-only EP12_IN_INT Endpoint 12 interrupt. 12 1 read-only EP11_IN_INT Endpoint 11 interrupt. 11 1 read-only EP10_IN_INT Endpoint 10 interrupt. 10 1 read-only EP9_IN_INT Endpoint 9 interrupt. 9 1 read-only EP8_IN_INT Endpoint 8 interrupt. 8 1 read-only EP7_IN_INT Endpoint 7 interrupt. 7 1 read-only EP6_IN_INT Endpoint 6 interrupt. 6 1 read-only EP5_IN_INT Endpoint 5 interrupt. 5 1 read-only EP4_IN_INT Endpoint 4 interrupt. 4 1 read-only EP3_IN_INT Endpoint 3 interrupt. 3 1 read-only EP2_IN_INT Endpoint 2 interrupt. 2 1 read-only EP1_IN_INT Endpoint 1 interrupt. 1 1 read-only EP0_IN_INT Endpoint 0 interrupt. 0 1 read-only INTROUT Interrupt register for OUT EP 1-15. 0x04 16 EP15_OUT_INT Endpoint 15 interrupt. 15 1 read-only EP14_OUT_INT Endpoint 14 interrupt. 14 1 read-only EP13_OUT_INT Endpoint 13 interrupt. 13 1 read-only EP12_OUT_INT Endpoint 12 interrupt. 12 1 read-only EP11_OUT_INT Endpoint 11 interrupt. 11 1 read-only EP10_OUT_INT Endpoint 10 interrupt. 10 1 read-only EP9_OUT_INT Endpoint 9 interrupt. 9 1 read-only EP8_OUT_INT Endpoint 8 interrupt. 8 1 read-only EP7_OUT_INT Endpoint 7 interrupt. 7 1 read-only EP6_OUT_INT Endpoint 6 interrupt. 6 1 read-only EP5_OUT_INT Endpoint 5 interrupt. 5 1 read-only EP4_OUT_INT Endpoint 4 interrupt. 4 1 read-only EP3_OUT_INT Endpoint 3 interrupt. 3 1 read-only EP2_OUT_INT Endpoint 2 interrupt. 2 1 read-only EP1_OUT_INT Endpoint 1 interrupt. 1 1 read-only INTRINEN Interrupt enable for EP 0 and IN EP 1-15. 0x06 16 EP15_IN_INT_EN Endpoint 15 interrupt enable. 15 1 read-write EP14_IN_INT_EN Endpoint 14 interrupt enable. 14 1 read-write EP13_IN_INT_EN Endpoint 13 interrupt enable. 13 1 read-write EP12_IN_INT_EN Endpoint 12 interrupt enable. 12 1 read-write EP11_IN_INT_EN Endpoint 11 interrupt enable. 11 1 read-write EP10_IN_INT_EN Endpoint 10 interrupt enable. 10 1 read-write EP9_IN_INT_EN Endpoint 9 interrupt enable. 9 1 read-write EP8_IN_INT_EN Endpoint 8 interrupt enable. 8 1 read-write EP7_IN_INT_EN Endpoint 7 interrupt enable. 7 1 read-write EP6_IN_INT_EN Endpoint 6 interrupt enable. 6 1 read-write EP5_IN_INT_EN Endpoint 5 interrupt enable. 5 1 read-write EP4_IN_INT_EN Endpoint 4 interrupt enable. 4 1 read-write EP3_IN_INT_EN Endpoint 3 interrupt enable. 3 1 read-write EP2_IN_INT_EN Endpoint 2 interrupt enable. 2 1 read-write EP1_IN_INT_EN Endpoint 1 interrupt enable. 1 1 read-write EP0_INT_EN Endpoint 0 interrupt enable. 0 1 read-write INTROUTEN Interrupt enable for OUT EP 1-15. 0x08 16 EP15_OUT_INT_EN Endpoint 15 interrupt. 15 1 read-write EP14_OUT_INT_EN Endpoint 14 interrupt. 14 1 read-write EP13_OUT_INT_EN Endpoint 13 interrupt. 13 1 read-write EP12_OUT_INT_EN Endpoint 12 interrupt. 12 1 read-write EP11_OUT_INT_EN Endpoint 11 interrupt. 11 1 read-write EP10_OUT_INT_EN Endpoint 10 interrupt. 10 1 read-write EP9_OUT_INT_EN Endpoint 9 interrupt. 9 1 read-write EP8_OUT_INT_EN Endpoint 8 interrupt. 8 1 read-write EP7_OUT_INT_EN Endpoint 7 interrupt. 7 1 read-write EP6_OUT_INT_EN Endpoint 6 interrupt. 6 1 read-write EP5_OUT_INT_EN Endpoint 5 interrupt. 5 1 read-write EP4_OUT_INT_EN Endpoint 4 interrupt. 4 1 read-write EP3_OUT_INT_EN Endpoint 3 interrupt. 3 1 read-write EP2_OUT_INT_EN Endpoint 2 interrupt. 2 1 read-write EP1_OUT_INT_EN Endpoint 1 interrupt. 1 1 read-write INTRUSB Interrupt register for common USB interrupts. 0x0A 8 SOF_INT Start of Frame. 3 1 read-only RESET_INT Bus reset detected. 2 1 read-only RESUME_INT Resume detected. 1 1 read-only SUSPEND_INT Suspend detected. 0 1 read-only INTRUSBEN Interrupt enable for common USB interrupts. 0x0B 8 SOF_INT_EN Start of Frame. 3 1 read-write RESET_INT_EN Bus reset detected. 2 1 read-write RESUME_INT_EN Resume detected. 1 1 read-write SUSPEND_INT_EN Suspend detected. 0 1 read-write FRAME Frame number. 0x0C 16 FRAMENUM Read the last received frame number, that is the 11-bit frame number received in the SOF packet. 0 11 read-only INDEX Index for banked registers. 0x0E 8 INDEX Index Register Access Selector. 0 4 read-write TESTMODE USB 2.0 test mode enable register. 0x0F 8 FORCE_FS Force USB to Full-speed after reset. 5 1 read-write FORCE_HS Force USB to High-speed after reset. 4 1 read-write TEST_PKT Transmit fixed test packet. 3 1 read-write TEST_K Force USB to continuous K state. 2 1 read-write TEST_J Force USB to continuous J state. 1 1 read-write TEST_SE0_NAK Respond to any valid IN token with NAK. 0 1 read-write INMAXP Maximum packet size for INx endpoint (x == INDEX). 0x10 16 MAXPACKETSIZE Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9 0 11 NUMPACKMINUS1 Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases. 11 5 CSR0 Control status register for EP 0 (when INDEX == 0). 0x12 8 SERV_SETUP_END Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set 7 1 read-write SERV_OUTPKTRDY Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set. 6 1 read-write SEND_STALL Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set. 5 1 read-write SETUP_END Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear. 4 1 read-only DATA_END Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet. 3 1 read-write SENT_STALL Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear. 2 1 read-write INPKTRDY EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared. 1 1 read-write OUTPKTRDY EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO. 0 1 read-only INCSRL Control status lower register for INx endpoint (x == INDEX). CSR0 0x12 8 INCOMPTX Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear. 7 1 read-write CLRDATATOG Write 1 to clear IN endpoint data-toggle to 0. 6 1 read-write SENTSTALL Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear. 5 1 read-write SENDSTALL Send STALL Handshake. 4 1 read-only terminate Terminate STALL handhsake 0 respond Respond to an IN token with a STALL handshake 1 FLUSHFIFO Flush Next Packet from IN FIFO. Write 1 to clear 3 1 read-write UNDERRUN Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear 2 1 read-write FIFONOTEMPTY Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear. 1 1 read-write INPKTRDY IN Packet Ready. Write a 1 to clear 0 1 read-only INCSRU Control status upper register for INx endpoint (x == INDEX). 0x13 8 AUTOSET Auto Set inpktrdy. 7 1 read-write set USBHS_INCSRL_inpktrdy must be set by firmware. 0 auto USBHS_INCSRL_inpktrdy is automatically set. 1 ISO Isochronous Transfer Enable 6 1 read-write interrupt Enable IN Bulk and IN interrupt transfers. 0 isochronous Enable IN Isochronous transfers. 1 MODE Endpoint Direction Mode. 5 1 read-write out Endpoint direction is OUT. 0 in Endpoint direction is IN. 1 FRCDATATOG Force In Data - Toggle 3 1 read-write received Toggle data-toglge only when an ACK is received. 0 dontcare Toggle data-toggle regardless of ACK. 1 DPKTBUFDIS Double Packet Buffering Disable 1 1 read-write en Enable Double packet buffering. 0 dis Disable Double Packet Buffering. 1 OUTMAXP Maximum packet size for OUTx endpoint (x == INDEX). 0x14 16 NUMPACKMINUS1 Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize. 11 5 MAXPACKETSIZE Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9. 0 11 OUTCSRL Control status lower register for OUTx endpoint (x == INDEX). 0x16 8 CLRDATATOG 7 1 read-write SENTSTALL 6 1 read-write SENDSTALL 5 1 read-write FLUSHFIFO 4 1 read-write DATAERROR 3 1 read-only OVERRUN 2 1 read-write FIFOFULL 1 1 read-only OUTPKTRDY 0 1 read-write OUTCSRU Control status upper register for OUTx endpoint (x == INDEX). 0x17 8 AUTOCLEAR 7 1 read-write ISO 6 1 read-write DISNYET 4 1 read-write DPKTBUFDIS 1 1 read-write INCOMPRX 0 1 read-only COUNT0 Number of received bytes in EP 0 FIFO (INDEX == 0). 0x18 16 COUNT0 Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1 0 7 read-only OUTCOUNT Number of received bytes in OUT EPx FIFO (x == INDEX). COUNT0 0x18 16 OUTCOUNT Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO. 0 13 read-only FIFO0 Read for OUT data FIFO, write for IN data FIFO. 0x20 USBHS_FIFO0 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO1 Read for OUT data FIFO, write for IN data FIFO. 0x24 USBHS_FIFO1 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO2 Read for OUT data FIFO, write for IN data FIFO. 0x28 USBHS_FIFO2 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO3 Read for OUT data FIFO, write for IN data FIFO. 0x2c USBHS_FIFO3 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO4 Read for OUT data FIFO, write for IN data FIFO. 0x30 USBHS_FIFO4 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO5 Read for OUT data FIFO, write for IN data FIFO. 0x34 USBHS_FIFO5 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO6 Read for OUT data FIFO, write for IN data FIFO. 0x38 USBHS_FIFO6 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO7 Read for OUT data FIFO, write for IN data FIFO. 0x3c USBHS_FIFO7 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO8 Read for OUT data FIFO, write for IN data FIFO. 0x40 USBHS_FIFO8 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO9 Read for OUT data FIFO, write for IN data FIFO. 0x44 USBHS_FIFO9 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO10 Read for OUT data FIFO, write for IN data FIFO. 0x48 USBHS_FIFO10 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO11 Read for OUT data FIFO, write for IN data FIFO. 0x4c USBHS_FIFO11 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO12 Read for OUT data FIFO, write for IN data FIFO. 0x50 USBHS_FIFO12 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO13 Read for OUT data FIFO, write for IN data FIFO. 0x54 USBHS_FIFO13 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO14 Read for OUT data FIFO, write for IN data FIFO. 0x58 USBHS_FIFO14 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO15 Read for OUT data FIFO, write for IN data FIFO. 0x5c USBHS_FIFO15 USBHS Endpoint FIFO Read/Write Register. 0 32 HWVERS HWVERS 0x6c 16 USBHS_HWVERS USBHS Register. 0 16 EPINFO Endpoint hardware information. 0x78 8 OUTENDPOINTS 4 4 read-only INTENDPOINTS 0 4 read-only RAMINFO RAM width information. 0x79 8 RAMBITS 0 4 read-only SOFTRESET Software reset register. 0x7A 8 RSTXS 1 1 read-write RSTS 0 1 read-write CTUCH Chirp timeout timer setting. 0x80 16 C_T_UCH HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host. 0 16 CTHSRTN Sets delay between HS resume to UTM normal operating mode. 0x82 16 C_T_HSTRN High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation. 0 16 MXM_USB_REG_00 MXM_USB_REG_00 0x400 M31_PHY_UTMI_RESET M31_PHY_UTMI_RESET 0x404 M31_PHY_UTMI_VCONTROL M31_PHY_UTMI_VCONTROL 0x408 M31_PHY_CLK_EN M31_PHY_CLK_EN 0x40C M31_PHY_PONRST M31_PHY_PONRST 0x410 M31_PHY_NONCRY_RSTB M31_PHY_NONCRY_RSTB 0x414 M31_PHY_NONCRY_EN M31_PHY_NONCRY_EN 0x418 M31_PHY_U2_COMPLIANCE_EN M31_PHY_U2_COMPLIANCE_EN 0x420 M31_PHY_U2_COMPLIANCE_DAC_ADJ M31_PHY_U2_COMPLIANCE_DAC_ADJ 0x424 M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN 0x428 M31_PHY_CLK_RDY M31_PHY_CLK_RDY 0x42C M31_PHY_PLL_EN M31_PHY_PLL_EN 0x430 M31_PHY_BIST_OK M31_PHY_BIST_OK 0x434 M31_PHY_DATA_OE M31_PHY_DATA_OE 0x438 M31_PHY_OSCOUTEN M31_PHY_OSCOUTEN 0x43C M31_PHY_LPM_ALIVE M31_PHY_LPM_ALIVE 0x440 M31_PHY_HS_BIST_MODE M31_PHY_HS_BIST_MODE 0x444 M31_PHY_CORECLKIN M31_PHY_CORECLKIN 0x448 M31_PHY_XTLSEL M31_PHY_XTLSEL 0x44C M31_PHY_LS_EN M31_PHY_LS_EN 0x450 M31_PHY_DEBUG_SEL M31_PHY_DEBUG_SEL 0x454 M31_PHY_DEBUG_OUT M31_PHY_DEBUG_OUT 0x458 M31_PHY_OUTCLKSEL M31_PHY_OUTCLKSEL 0x45C M31_PHY_XCFGI_31_0 M31_PHY_XCFGI_31_0 0x460 M31_PHY_XCFGI_63_32 M31_PHY_XCFGI_63_32 0x464 M31_PHY_XCFGI_95_64 M31_PHY_XCFGI_95_64 0x468 M31_PHY_XCFGI_127_96 M31_PHY_XCFGI_127_96 0x46C M31_PHY_XCFGI_137_128 M31_PHY_XCFGI_137_128 0x470 M31_PHY_XCFG_HS_COARSE_TUNE_NUM M31_PHY_XCFG_HS_COARSE_TUNE_NUM 0x474 M31_PHY_XCFG_HS_FINE_TUNE_NUM M31_PHY_XCFG_HS_FINE_TUNE_NUM 0x478 M31_PHY_XCFG_FS_COARSE_TUNE_NUM M31_PHY_XCFG_FS_COARSE_TUNE_NUM 0x47C M31_PHY_XCFG_FS_FINE_TUNE_NUM M31_PHY_XCFG_FS_FINE_TUNE_NUM 0x480 M31_PHY_XCFG_LOCK_RANGE_MAX M31_PHY_XCFG_LOCK_RANGE_MAX 0x484 M31_PHY_XCFGI_LOCK_RANGE_MIN M31_PHY_XCFGI_LOCK_RANGE_MIN 0x488 M31_PHY_XCFG_OB_RSEL M31_PHY_XCFG_OB_RSEL 0x48C M31_PHY_XCFG_OC_RSEL M31_PHY_XCFG_OC_RSEL 0x490 M31_PHY_XCFGO M31_PHY_XCFGO 0x494 MXM_INT USB Added Maxim Interrupt Flag Register. 0x498 VBUS VBUS 0 1 NOVBUS NOVBUS 1 1 MXM_INT_EN USB Added Maxim Interrupt Enable Register. 0x49C VBUS VBUS 0 1 NOVBUS NOVBUS 1 1 MXM_SUSPEND USB Added Maxim Suspend Register. 0x4A0 SEL Suspend register 0 1 MXM_REG_A4 USB Added Maxim Power Status Register 0x4A4 VRST_VDDB_N_A VRST_VDDB_N_A 0 1 WDT Windowed Watchdog Timer 0x40003000 0x00 0x0400 registers WWDT 1 CTRL Watchdog Timer Control Register. 0x00 read-write INT_LATE_VAL Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_LATE_VAL Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 4 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 EN Windowed Watchdog Timer Enable. 8 1 dis Disable. 0 en Enable. 1 INT_LATE Windowed Watchdog Timer Interrupt Flag Too Late. 9 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 WDT_INT_EN Windowed Watchdog Timer Interrupt Enable. 10 1 dis Disable. 0 en Enable. 1 WDT_RST_EN Windowed Watchdog Timer Reset Enable. 11 1 dis Disable. 0 en Enable. 1 INT_EARLY Windowed Watchdog Timer Interrupt Flag Too Soon. 12 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 INT_EARLY_VAL Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 16 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_EARLY_VAL Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 20 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 CLKRDY_IE Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock. 27 1 CLKRDY Clock Status. 28 1 WIN_EN Enables the Windowed Watchdog Function. 29 1 dis Windowed Mode Disabled (i.e. Compatibility Mode). 0 en Windowed Mode Enabled. 1 RST_EARLY Windowed Watchdog Timer Reset Flag Too Soon. 30 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST_LATE Windowed Watchdog Timer Reset Flag Too Late. 31 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST Windowed Watchdog Timer Reset Register. 0x04 write-only RESET Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled. 0 8 seq0 The first value to be written to reset the WDT. 0x000000A5 seq1 The second value to be written to reset the WDT. 0x0000005A CLKSEL Windowed Watchdog Timer Clock Select Register. 0x08 read-write SOURCE WWDT Clock Selection Register. 0 3 CNT Windowed Watchdog Timer Count Register. 0x0C read-only COUNT Current Value of the Windowed Watchdog Timer Counter. 0 32 WDT1 Windowed Watchdog Timer 1 0x40003400 WDT1 WDT1 IRQ 57 SKBD Secure Keyboard 0x40032000 0x00 0x1000 registers Secure_Keypad Secure Keypad interrupt 19 CTRL0 Input Output Select Bits. Each bit of IOSEL selects the pin direction for the corresponding KBDIO pin. If IOSEL[0] = 1, KBDIO0 is an output. 0x00 KBDIO0 Input Output Select for KBDIO0 pin. 0 1 input Input 0 output Output 1 KBDIO1 Input Output Select for KBDIO1 pin. 1 1 KBDIO2 Input Output Select for KBDIO2 pin. 2 1 KBDIO3 Input Output Select for KBDIO3 pin. 3 1 KBDIO4 Input Output Select for KBDIO4 pin. 4 1 KBDIO5 Input Output Select for KBDIO5 pin. 5 1 KBDIO6 Input Output Select for KBDIO6 pin. 6 1 KBDIO7 Input Output Select for KBDIO7 pin. 7 1 KBDIO8 Input Output Select for KBDIO8 pin. 8 1 KBDIO9 Input Output Select for KBDIO9 pin. 9 1 CTRL1 Control Register 1 0x04 AUTOSCAN_EN Automatic Keyboard Scan Enable 0 1 disable Disable 0 enable Enable 1 AUTOCLEAR Auto Clear Bit 1 1 OUTNUM Output Number. Number of KBDIO pins selected as outputs. NOTE: Output pins must be allocated contiguously starting with KBDIO0 and continuing through to KBDIO7. 8 4 DBTM Debounce Time. Number of milliseconds a keypress event must be active before it is considered actual. NOTE: Debounce time values based on system running from an external 12MHz clock source with PLL0 enabled. Other external crystal values will cause the debounce time to scale linearly. 13 3 time4ms 4.1 ms 0 time5ms 5.3 ms 1 time6ms 6.5 ms 2 time7ms 7.6 ms 3 time8ms 8.8 ms 4 time10ms 10.0 ms 5 time11ms 11.2 ms 6 time12ms 12.3 ms 7 STATUS Status Register 0x08 read-only BUSY Busy bit. This bit is set by hardware when the automatic keyboard scan is enabled and running. This bit is clear at all other times. 0 1 idle Idle 0 busy Busy 1 INTEN Interrupt Enable Register 0x0C PUSH Push Event Enable Bit. When set, this bit enables an interrupt to be generated on a key push event. Automatic keyboard scan must be enabled. 0 1 disable Disable 0 enable Enable 1 RELEASE Release Event Enable Bit. When set, this bit enables an interrupt to be generated on a key release event. Automatic keyboard scan must be enabled. 1 1 OVERRUN Overrun Event Enable Bit. When set, this bit enables an interrupt to be generated on an overrun event. Automatic keyboard scan must be enabled. 2 1 KBD_PINS Keyboard Pins Interrupt Enable. 3 1 INTFL Interrupt Status Register 0x10 PUSH Push Interrupt Flag. This bit is set by hardware when a key has been pushed. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 RELEASE Release Interrupt Flag. This bit is set by hardware when a key has been released. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software. 1 1 OVERRUN Overrun Event Enable Bit. This bit is set by hardware when an overrun event has occurred. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software. 2 1 4 4 EVT[%s] Key Register 0x14 read-only 0x00000C00 IOIN IO Input. Input pin of key event. 0 3 IOOUT IO Output. Output pin of key event. 5 3 PUSH If set to 1 the key has been released. If set to 0 the key has been pushed. 10 1 pushed Pushed 0 released Released 1 READ If set to 1 this register has been read. If set to 0 the key register has not been read since its last change. 11 1 notRead This register has not been read since its last change. 0 read This register has been read. 1 NEXT If set to 1 one of the next key registers (x+1 to 3) contains a key event. 12 1 none No more key register contain a key event. 0 more Other key registers contain a key event. 1 GPIO0 General Purpose Register 0. 0x24 ALL Mask of all of the pins on the port. 0 32 GPIO1 General Purpose Register 1. 0x28 ALL Mask of all of the pins on the port. 0 32 SEMA The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. 0x4003E000 0x00 0x1000 registers 8 4 SEMAPHORES[%s] Read to test and set, returns prior value. Write 0 to clear semaphore. 0x00 32 sema 0 1 irq0 Semaphore IRQ0 register. 0x40 32 en 0 1 cm4_irq 16 1 mail0 Semaphore Mailbox 0 register. 0x44 32 data 0 32 irq1 Semaphore IRQ1 register. 0x48 32 en 0 1 rv32_irq 16 1 mail1 Semaphore Mailbox 1 register. 0x4C 32 data 0 32 status Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. 0x100 32 status0 0 1 status1 1 1 status2 2 1 status3 3 1 status4 4 1 status5 5 1 status6 6 1 status7 7 1 SCN Smart Card Interface. SCN 0x4002C000 0x00 0x1000 registers SC0 SC0 IRQ 11 CR Control Register. 0x00 CONV Convention Select Bit. 0 1 CREP Character Repeat Enable Bit. 1 1 WTEN Wait Time Counter Enable Bit. 2 1 UART Smart Card Mode Bit. 3 1 CCEN Clock Counter Enable Bit. 4 1 RXFLUSH Receive FIFO Flush. 5 1 TXFLUSH Transmit FIFO Flush. 6 1 RXTHD Receive FIFO Depth. 8 4 TXTHD Transmit FIFO Depth. 12 4 DUAL_MODE Dual Internal AFE and Bypass Mode. 23 1 SR Status Register. 0x04 PAR Parity Error Detector Flag. 0 1 WTOV Waiting Time Counter Overflow. 1 1 CCOV Clock Counter Overflow Flag. 2 1 TXCF Transmit Complete Flag. 3 1 RXEMPTY Receive FIFO Empty Flag. 4 1 RXFULL Receive FIFO Full Flag. 5 1 TXEMPTY Transmit FIFO Empty Flag. 6 1 TXFULL Transmit FIFO Full Flag. 7 1 RXELT Number of Bytes in the Receive FIFO. 8 4 TXELT Number of Bytes in the Transmit FIFO. 12 4 PN Pin Register. 0x08 CRDRST Smart Card Reset Pin Control. 0 1 CRDCLK Smart Card Clock Piin Control. 1 1 CRDIO Smart Card IO Pin Control. 2 1 CRDC4 Smart Card SCn_C4 Pin Control. 3 1 CRDC8 Smart Card SCn_C8 Pin Control. 4 1 CLKSEL Smart Card Clock Select. 5 1 IO_C48_EN Pin Enable. 16 1 ETUR ETU Register. 0x0C ETU Elemental Time Unit Value. 0 15 COMP Compensation Mode Enable Bit. 15 1 HALF Half ETU Count Selection Bit. 16 1 GTR Guard Time Register. 0x10 GT Guard Time. 0 16 WT0R Waiting Time 0 Register. 0x14 WT Wait Time. 0 32 WT1R Waiting Time 1 Register. 0x18 WT Wait Time. 0 8 IER Interrupt Enable Register. 0x1C PARIE Parity Error Interrupt Enable. 0 1 WTIE Waiting Time Overflow Interrupt Enable. 1 1 CTIE Clock Counter Overflow Interrupt Enable. 2 1 TCIE Character Transmission Completion Interrupt Enable. 3 1 RXEIE Receive FIFO Empty Interrupt Enable. 4 1 RXTIE Receive FIFO Threshold Reached Interrupt Enable. 5 1 RXFIE Receive FIFO Full Interrupt Enable. 6 1 TXEIE Transmit FIFO Empty Interrupt Enable. 7 1 TXTIE Transmit FIFO Threshold Reached Interrupt Enable. 8 1 ISR Interrupt Status Register. 0x20 PARIS Parity Error Interrupt Status Flag. 0 1 WTIS Waiting Time Overflow Interrupt Status Flag. 1 1 CTIS Clock Counter Overflow Interrupt Status Flag. 2 1 TCIS Character Transmission Completion Interrupt Status Flag. 3 1 RXEIS Receive FIFO Empty Interrupt Status Flag. 4 1 RXTIS Receive FIFO Threshold Reached Interrupt Status Flag. 5 1 RXFIS Receive FIFO Full Interrupt Status Flag. 6 1 TXEIS Transmit FIFO Empty Interrupt Status Flag. 7 1 TXTIS Transmit FIFO Threshold Reached Interrupt Status Flag. 8 1 TXR Transmit Register. 0x24 DATA Transmit Data. 0 8 RXR Receive Register. 0x28 DATA Receive Data. 0 8 PARER Parity Error Detect Bit. 8 1 CCR Clock Counter Register. 0x2C CCYC Number of Clock Cycles to Count. 0 24 MAN Manual Mode. 31 1