1 /* 2 * Copyright (c) 2024 Antmicro <www.antmicro.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_SOC_ARM_XLNX_ZYNQMP_SOC_PINCTRL_H_ 8 #define ZEPHYR_SOC_ARM_XLNX_ZYNQMP_SOC_PINCTRL_H_ 9 10 #include <zephyr/devicetree.h> 11 #include <zephyr/sys/util.h> 12 #include <zephyr/types.h> 13 14 #define MIO_L0_SEL BIT(1) 15 #define MIO_L1_SEL BIT(2) 16 #define MIO_L2_SEL GENMASK(4, 3) 17 #define MIO_L3_SEL GENMASK(7, 5) 18 19 /* All other selectors should be zeroed and FIELD_PREP does that */ 20 #define UARTX_SEL FIELD_PREP(MIO_L3_SEL, 6) 21 22 /* 23 * Each peripheral PINCTRL mask is defined as such: 24 * [7 ... 0] MIO register number 25 * [15 ... 8] Function, mapped as: 26 * 1 - UART 27 * 28 * The function numbers serve as an enumerator in the pinctrl driver 29 * and the defines controling those are listed in `pinctrl-zynqmp.h`. 30 * Currently, one function for UART is specified and subsequent ones 31 * can be added when the need arises. 32 */ 33 34 typedef struct pinctrl_soc_pin_t { 35 uint32_t pin; 36 uint32_t func; 37 } pinctrl_soc_pin_t; 38 39 40 #define ZYNQMP_GET_PIN(pinctrl) (pinctrl & 0xff) 41 #define ZYNQMP_GET_FUNC(pinctrl) ((pinctrl >> 8) & 0xff) 42 43 #define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ 44 { \ 45 .pin = ZYNQMP_GET_PIN(DT_PROP_BY_IDX(node_id, prop, idx)), \ 46 .func = ZYNQMP_GET_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)), \ 47 }, 48 49 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) { \ 50 DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ 51 DT_FOREACH_PROP_ELEM, pinmux, \ 52 Z_PINCTRL_STATE_PIN_INIT)} 53 54 #endif 55
