1# Copyright 2024-2025 NXP 2# SPDX-License-Identifier: Apache-2.0 3 4if SOC_MIMXRT798S_CM33_CPU0 5 6config ROM_START_OFFSET 7 default 0x4000 if NXP_IMXRT_BOOT_HEADER 8 9config NUM_IRQS 10 default 158 11 12config SYS_CLOCK_HW_CYCLES_PER_SEC 13 default 237500000 if CORTEX_M_SYSTICK 14 default 1000000 if MCUX_OS_TIMER 15 16choice CACHE_TYPE 17 default EXTERNAL_CACHE 18endchoice 19 20endif # SOC_MIMXRT798S_CM33_CPU0 21 22if SOC_MIMXRT798S_CM33_CPU1 23 24config NUM_IRQS 25 default 93 26 27config SYS_CLOCK_HW_CYCLES_PER_SEC 28 default 100000000 if CORTEX_M_SYSTICK 29 default 1000000 if MCUX_OS_TIMER 30 31endif # SOC_MIMXRT798S_CM33_CPU1 32 33config MFD 34 default y 35 depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED 36 37if SOC_MIMXRT798S_HIFI4 38 39config SYS_CLOCK_HW_CYCLES_PER_SEC 40 default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) 41 42config XTENSA_TIMER 43 default y 44 45config XTENSA_CCOUNT_HZ 46 default SYS_CLOCK_HW_CYCLES_PER_SEC 47 48config SYS_CLOCK_TICKS_PER_SEC 49 default 1000 50 51config GEN_IRQ_VECTOR_TABLE 52 default n 53 54config NXP_IMXRT_BOOT_HEADER 55 default n 56 57endif # SOC_MIMXRT798S_HIFI4 58 59if SOC_MIMXRT798S_HIFI1 60 61config SYS_CLOCK_HW_CYCLES_PER_SEC 62 default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) 63 64config XTENSA_TIMER 65 default y 66 67config GEN_IRQ_VECTOR_TABLE 68 default n 69 70config NXP_IMXRT_BOOT_HEADER 71 default n 72 73config XTENSA_CCOUNT_HZ 74 default SYS_CLOCK_HW_CYCLES_PER_SEC 75 76config SYS_CLOCK_TICKS_PER_SEC 77 default 1000 78 79endif # SOC_MIMXRT798S_HIFI1 80
