1/*
2 * Copyright (c) 2023 PSICONTROl nv
3 * Copyright (c) 2023 STMicroelectronics
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <st/u5/stm32u5.dtsi>
9
10
11/ {
12	soc {
13		compatible = "st,stm32u595", "st,stm32u5", "simple-bus";
14
15		pinctrl: pin-controller@42020000 {
16			compatible = "st,stm32-pinctrl";
17			#address-cells = <1>;
18			#size-cells = <1>;
19			reg = <0x42020000 0x2800>;
20
21			gpioj: gpio@42022400 {
22				compatible = "st,stm32-gpio";
23				gpio-controller;
24				#gpio-cells = <2>;
25				reg = <0x42022400 0x400>;
26				clocks = <&rcc STM32_CLOCK(AHB2, 9U)>;
27			};
28		};
29
30		usart6: serial@40006400 {
31			compatible = "st,stm32-usart", "st,stm32-uart";
32			reg = <0x40006400 0x400>;
33			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
34			resets = <&rctl STM32_RESET(APB1L, 25U)>;
35			interrupts = <126 0>;
36			status = "disabled";
37		};
38
39		i2c5: i2c@40009800 {
40			compatible = "st,stm32-i2c-v2";
41			clock-frequency = <I2C_BITRATE_STANDARD>;
42			#address-cells = <1>;
43			#size-cells = <0>;
44			reg = <0x40009800 0x400>;
45			clocks = <&rcc STM32_CLOCK(APB1_2, 6U)>;
46			interrupts = <128 0>, <127 0>;
47			interrupt-names = "event", "error";
48			status = "disabled";
49		};
50
51		i2c6: i2c@40009c00 {
52			compatible = "st,stm32-i2c-v2";
53			clock-frequency = <I2C_BITRATE_STANDARD>;
54			#address-cells = <1>;
55			#size-cells = <0>;
56			reg = <0x40009c00 0x400>;
57			clocks = <&rcc STM32_CLOCK(APB1_2, 7U)>;
58			interrupts = <130 0>, <129 0>;
59			interrupt-names = "event", "error";
60			status = "disabled";
61		};
62
63		/* Available in STM32U59x/5Ax/5Fx/5Gx SoCs */
64		adc2: adc@42028100 {
65			compatible = "st,stm32-adc";
66			reg = <0x42028100 0x400>;
67			clocks = <&rcc STM32_CLOCK(AHB2, 10U)>,
68				 <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>;
69			interrupts = <37 0>;
70			status = "disabled";
71			#io-channel-cells = <1>;
72			resolutions = <STM32_ADC_RES(14, 0x00)
73				       STM32_ADC_RES(12, 0x01)
74				       STM32_ADC_RES(10, 0x02)
75				       STM32_ADC_RES(8, 0x03)>;
76			sampling-times = <5 6 12 20 36 68 391 814>;
77			st,adc-clock-source = "ASYNC";
78			st,adc-sequencer = "FULLY_CONFIGURABLE";
79			st,adc-oversampler = "OVERSAMPLER_EXTENDED";
80		};
81
82		/*
83		 * Available in STM32U59x/5Ax/5Fx/5Gx SoCs
84		 * dual mode: adc1 and adc2 coupled
85		 */
86		adc1_2: adc@42028300 {
87			compatible = "st,stm32-adc";
88			reg = <0x42028300 0x400>;
89			clocks = <&rcc STM32_CLOCK(AHB2, 10U)>;
90			interrupts = <37 0>;
91			status = "disabled";
92			#io-channel-cells = <1>;
93			resolutions = <STM32_ADC_RES(14, 0x00)
94				       STM32_ADC_RES(12, 0x01)
95				       STM32_ADC_RES(10, 0x02)
96				       STM32_ADC_RES(8, 0x03)>;
97			sampling-times = <5 6 12 20 36 68 391 814>;
98			st,adc-clock-source = "ASYNC";
99			st,adc-sequencer = "FULLY_CONFIGURABLE";
100			st,adc-oversampler = "OVERSAMPLER_EXTENDED";
101		};
102
103		usbotg_hs: otghs@42040000 {
104			compatible = "st,stm32-otghs";
105			reg = <0x42040000 0x20000>;
106			interrupts = <73 0>;
107			interrupt-names = "otghs";
108			num-bidir-endpoints = <9>;
109			ram-size = <4096>;
110			maximum-speed = "high-speed";
111			clocks = <&rcc STM32_CLOCK(AHB2, 14U)>;
112			phys = <&otghs_phy>;
113			status = "disabled";
114		};
115	};
116
117	otghs_phy: otghs_phy {
118		compatible = "st,stm32u5-otghs-phy";
119		clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
120			 <&rcc STM32_SRC_HSE OTGHS_SEL(0)>;
121		#phy-cells = <0>;
122	};
123
124	smbus5: smbus5 {
125		compatible = "st,stm32-smbus";
126		#address-cells = <1>;
127		#size-cells = <0>;
128		i2c = <&i2c5>;
129		status = "disabled";
130	};
131
132	smbus6: smbus6 {
133		compatible = "st,stm32-smbus";
134		#address-cells = <1>;
135		#size-cells = <0>;
136		i2c = <&i2c6>;
137		status = "disabled";
138	};
139};
140