1 /*
2 * Copyright (c) 2019 Vestas Wind Systems A/S
3 * Copyright (c) 2020 Innoseis BV
4 * Copyright (c) 2023 Cruise LLC
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8 #include <zephyr/device.h>
9 #include <zephyr/devicetree.h>
10 #include <zephyr/drivers/adc.h>
11 #include <zephyr/drivers/i2c.h>
12 #include <zephyr/kernel.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/sys/byteorder.h>
15 #include <zephyr/sys/util.h>
16
17 #define ADC_CONTEXT_USES_KERNEL_TIMER 1
18 #include "adc_context.h"
19
20 #define DT_DRV_COMPAT ti_ads1112
21
22 LOG_MODULE_REGISTER(ADS1112, CONFIG_ADC_LOG_LEVEL);
23
24 #define ADS1112_CONFIG_GAIN(x) ((x)&BIT_MASK(2))
25 #define ADS1112_CONFIG_DR(x) (((x)&BIT_MASK(2)) << 2)
26 #define ADS1112_CONFIG_CM(x) (((x)&BIT_MASK(1)) << 4)
27 #define ADS1112_CONFIG_MUX(x) (((x)&BIT_MASK(2)) << 5)
28
29 #define ADS1112_CONFIG_MASK_READY BIT(7)
30
31 #define ADS1112_DEFAULT_CONFIG 0x8C
32 #define ADS1112_REF_INTERNAL 2048
33
34 enum ads1112_reg {
35 ADS1112_REG_OUTPUT = 0,
36 ADS1112_REG_CONFIG = 1,
37 };
38
39 enum {
40 ADS1112_CONFIG_MUX_DIFF_0_1 = 0,
41 ADS1112_CONFIG_MUX_BOTH_2_3 = 1,
42 ADS1112_CONFIG_MUX_SINGLE_0_3 = 2,
43 ADS1112_CONFIG_MUX_SINGLE_1_3 = 3,
44 };
45
46 enum {
47 ADS1112_CONFIG_DR_RATE_240_RES_12 = 0,
48 ADS1112_CONFIG_DR_RATE_60_RES_14 = 1,
49 ADS1112_CONFIG_DR_RATE_30_RES_15 = 2,
50 ADS1112_CONFIG_DR_RATE_15_RES_16 = 3,
51 ADS1112_CONFIG_DR_DEFAULT = ADS1112_CONFIG_DR_RATE_15_RES_16,
52 };
53
54 enum {
55 ADS1112_CONFIG_GAIN_1 = 0,
56 ADS1112_CONFIG_GAIN_2 = 1,
57 ADS1112_CONFIG_GAIN_4 = 2,
58 ADS1112_CONFIG_GAIN_8 = 3,
59 };
60
61 enum {
62 ADS1112_CONFIG_CM_SINGLE = 0,
63 ADS1112_CONFIG_CM_CONTINUOUS = 1,
64 };
65
66 struct ads1112_config {
67 const struct i2c_dt_spec bus;
68 };
69
70 struct ads1112_data {
71 struct adc_context ctx;
72 k_timeout_t ready_time;
73 struct k_sem acq_sem;
74 int16_t *buffer;
75 int16_t *buffer_ptr;
76 bool differential;
77 };
78
ads1112_read_reg(const struct device * dev,enum ads1112_reg reg_addr,uint8_t * reg_val)79 static int ads1112_read_reg(const struct device *dev, enum ads1112_reg reg_addr, uint8_t *reg_val)
80 {
81 const struct ads1112_config *config = dev->config;
82 uint8_t buf[3] = {0};
83 int rc = i2c_read_dt(&config->bus, buf, sizeof(buf));
84
85 if (reg_addr == ADS1112_REG_OUTPUT) {
86 reg_val[0] = buf[0];
87 reg_val[1] = buf[1];
88 } else {
89 reg_val[0] = buf[2];
90 }
91
92 return rc;
93 }
94
ads1112_write_reg(const struct device * dev,uint8_t reg)95 static int ads1112_write_reg(const struct device *dev, uint8_t reg)
96 {
97 uint8_t msg[1] = {reg};
98 const struct ads1112_config *config = dev->config;
99
100 /* It's only possible to write the config register, so the ADS1112
101 * assumes all writes are going to that register and omits the register
102 * parameter from write transactions
103 */
104 return i2c_write_dt(&config->bus, msg, sizeof(msg));
105 }
106
ads1112_acq_time_to_dr(const struct device * dev,uint16_t acq_time)107 static inline int ads1112_acq_time_to_dr(const struct device *dev, uint16_t acq_time)
108 {
109 struct ads1112_data *data = dev->data;
110 int odr = -EINVAL;
111 uint16_t acq_value = ADC_ACQ_TIME_VALUE(acq_time);
112 uint32_t ready_time_us = 0;
113
114 if (acq_time == ADC_ACQ_TIME_DEFAULT) {
115 acq_value = ADS1112_CONFIG_DR_DEFAULT;
116 } else if (ADC_ACQ_TIME_UNIT(acq_time) != ADC_ACQ_TIME_TICKS) {
117 return -EINVAL;
118 }
119
120 switch (acq_value) {
121 case ADS1112_CONFIG_DR_RATE_15_RES_16:
122 odr = ADS1112_CONFIG_DR_RATE_15_RES_16;
123 ready_time_us = (1000 * 1000) / 15;
124 break;
125 case ADS1112_CONFIG_DR_RATE_30_RES_15:
126 odr = ADS1112_CONFIG_DR_RATE_30_RES_15;
127 ready_time_us = (1000 * 1000) / 30;
128 break;
129 case ADS1112_CONFIG_DR_RATE_60_RES_14:
130 odr = ADS1112_CONFIG_DR_RATE_60_RES_14;
131 ready_time_us = (1000 * 1000) / 60;
132 break;
133 case ADS1112_CONFIG_DR_RATE_240_RES_12:
134 odr = ADS1112_CONFIG_DR_RATE_240_RES_12;
135 ready_time_us = (1000 * 1000) / 240;
136 break;
137 default:
138 break;
139 }
140
141 /* Add some additional time to ensure that the data is truly ready,
142 * as chips in this family often require some additional time beyond
143 * the listed times
144 */
145 data->ready_time = K_USEC(ready_time_us + 10);
146
147 return odr;
148 }
149
ads1112_wait_data_ready(const struct device * dev)150 static int ads1112_wait_data_ready(const struct device *dev)
151 {
152 int rc;
153 struct ads1112_data *data = dev->data;
154
155 k_sleep(data->ready_time);
156 uint8_t status = 0;
157
158 rc = ads1112_read_reg(dev, ADS1112_REG_CONFIG, &status);
159 if (rc != 0) {
160 return rc;
161 }
162
163 while ((status & ADS1112_CONFIG_MASK_READY) == 0) {
164
165 k_sleep(K_USEC(100));
166 rc = ads1112_read_reg(dev, ADS1112_REG_CONFIG, &status);
167 if (rc != 0) {
168 return rc;
169 }
170 }
171
172 return 0;
173 }
174
ads1112_read_sample(const struct device * dev,uint16_t * buff)175 static int ads1112_read_sample(const struct device *dev, uint16_t *buff)
176 {
177 int res;
178 uint8_t sample[2] = {0};
179
180 res = ads1112_read_reg(dev, ADS1112_REG_OUTPUT, sample);
181 buff[0] = sys_get_be16(sample);
182 return res;
183 }
184
ads1112_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)185 static int ads1112_channel_setup(const struct device *dev,
186 const struct adc_channel_cfg *channel_cfg)
187 {
188 struct ads1112_data *data = dev->data;
189 uint8_t config = 0;
190 int dr = 0;
191
192 if (channel_cfg->channel_id != 0) {
193 return -EINVAL;
194 }
195
196 if (channel_cfg->differential) {
197 if (channel_cfg->input_positive == 0 && channel_cfg->input_negative == 1) {
198 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_DIFF_0_1);
199 } else if (channel_cfg->input_positive == 2 && channel_cfg->input_negative == 3) {
200 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_BOTH_2_3);
201 } else {
202 return -EINVAL;
203 }
204 } else {
205 if (channel_cfg->input_positive == 0) {
206 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_SINGLE_0_3);
207 } else if (channel_cfg->input_positive == 1) {
208 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_SINGLE_1_3);
209 } else if (channel_cfg->input_positive == 2) {
210 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_BOTH_2_3);
211 } else {
212 return -EINVAL;
213 }
214 }
215
216 data->differential = channel_cfg->differential;
217
218 dr = ads1112_acq_time_to_dr(dev, channel_cfg->acquisition_time);
219 if (dr < 0) {
220 return dr;
221 }
222
223 config |= ADS1112_CONFIG_DR(dr);
224
225 switch (channel_cfg->gain) {
226 case ADC_GAIN_1:
227 config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_1);
228 break;
229 case ADC_GAIN_2:
230 config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_2);
231 break;
232 case ADC_GAIN_3:
233 config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_4);
234 break;
235 case ADC_GAIN_4:
236 config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_8);
237 break;
238 default:
239 return -EINVAL;
240 }
241
242 config |= ADS1112_CONFIG_CM(ADS1112_CONFIG_CM_SINGLE); /* Only single shot supported */
243
244 return ads1112_write_reg(dev, config);
245 }
246
ads1112_validate_buffer_size(const struct adc_sequence * sequence)247 static int ads1112_validate_buffer_size(const struct adc_sequence *sequence)
248 {
249 size_t needed = sizeof(int16_t);
250
251 if (sequence->options) {
252 needed *= (1 + sequence->options->extra_samplings);
253 }
254
255 if (sequence->buffer_size < needed) {
256 LOG_ERR("Insufficient buffer %i < %i", sequence->buffer_size, needed);
257 return -ENOMEM;
258 }
259
260 return 0;
261 }
262
ads1112_validate_sequence(const struct device * dev,const struct adc_sequence * sequence)263 static int ads1112_validate_sequence(const struct device *dev, const struct adc_sequence *sequence)
264 {
265 if (sequence->channels != BIT(0)) {
266 LOG_ERR("Invalid Channel 0x%x", sequence->channels);
267 return -EINVAL;
268 }
269
270 if (sequence->oversampling) {
271 LOG_ERR("Oversampling not supported");
272 return -EINVAL;
273 }
274
275 return ads1112_validate_buffer_size(sequence);
276 }
277
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)278 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
279 {
280 struct ads1112_data *data = CONTAINER_OF(ctx, struct ads1112_data, ctx);
281
282 if (repeat_sampling) {
283 data->buffer = data->buffer_ptr;
284 }
285 }
286
adc_context_start_sampling(struct adc_context * ctx)287 static void adc_context_start_sampling(struct adc_context *ctx)
288 {
289 struct ads1112_data *data = CONTAINER_OF(ctx, struct ads1112_data, ctx);
290
291 data->buffer_ptr = data->buffer;
292 k_sem_give(&data->acq_sem);
293 }
294
ads1112_adc_start_read(const struct device * dev,const struct adc_sequence * sequence,bool wait)295 static int ads1112_adc_start_read(const struct device *dev, const struct adc_sequence *sequence,
296 bool wait)
297 {
298 int rc = 0;
299 struct ads1112_data *data = dev->data;
300
301 rc = ads1112_validate_sequence(dev, sequence);
302 if (rc != 0) {
303 return rc;
304 }
305
306 data->buffer = sequence->buffer;
307
308 adc_context_start_read(&data->ctx, sequence);
309
310 if (wait) {
311 rc = adc_context_wait_for_completion(&data->ctx);
312 }
313 return rc;
314 }
315
ads1112_adc_perform_read(const struct device * dev)316 static int ads1112_adc_perform_read(const struct device *dev)
317 {
318 int rc;
319 struct ads1112_data *data = dev->data;
320
321 k_sem_take(&data->acq_sem, K_FOREVER);
322
323 rc = ads1112_wait_data_ready(dev);
324 if (rc != 0) {
325 adc_context_complete(&data->ctx, rc);
326 return rc;
327 }
328
329 rc = ads1112_read_sample(dev, data->buffer);
330 if (rc != 0) {
331 adc_context_complete(&data->ctx, rc);
332 return rc;
333 }
334 data->buffer++;
335
336 adc_context_on_sampling_done(&data->ctx, dev);
337
338 return rc;
339 }
340
ads1112_read(const struct device * dev,const struct adc_sequence * sequence)341 static int ads1112_read(const struct device *dev, const struct adc_sequence *sequence)
342 {
343 int rc;
344 struct ads1112_data *data = dev->data;
345
346 adc_context_lock(&data->ctx, false, NULL);
347 rc = ads1112_adc_start_read(dev, sequence, false);
348
349 while (rc == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
350 rc = ads1112_adc_perform_read(dev);
351 }
352
353 adc_context_release(&data->ctx, rc);
354 return rc;
355 }
356
ads1112_init(const struct device * dev)357 static int ads1112_init(const struct device *dev)
358 {
359 int rc = 0;
360 const struct ads1112_config *config = dev->config;
361 struct ads1112_data *data = dev->data;
362
363 adc_context_init(&data->ctx);
364
365 k_sem_init(&data->acq_sem, 0, 1);
366
367 if (!device_is_ready(config->bus.bus)) {
368 return -ENODEV;
369 }
370
371 rc = ads1112_write_reg(dev, ADS1112_DEFAULT_CONFIG);
372 if (rc) {
373 LOG_ERR("Could not set default config 0x%x", ADS1112_DEFAULT_CONFIG);
374 return rc;
375 }
376
377 adc_context_unlock_unconditionally(&data->ctx);
378
379 return rc;
380 }
381
382 static DEVICE_API(adc, api) = {
383 .channel_setup = ads1112_channel_setup,
384 .read = ads1112_read,
385 .ref_internal = ADS1112_REF_INTERNAL,
386 };
387 #define ADC_ADS1112_INST_DEFINE(n) \
388 static const struct ads1112_config config_##n = {.bus = I2C_DT_SPEC_INST_GET(n)}; \
389 static struct ads1112_data data_##n; \
390 DEVICE_DT_INST_DEFINE(n, ads1112_init, NULL, &data_##n, &config_##n, POST_KERNEL, \
391 CONFIG_ADC_INIT_PRIORITY, &api);
392
393 DT_INST_FOREACH_STATUS_OKAY(ADC_ADS1112_INST_DEFINE);
394
