1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <nxp/s32/S32K344-172MQFP-pinctrl.h>
8
9&pinctrl {
10	eirq0_default: eirq0_default {
11		group1 {
12			pinmux = <PTD15_EIRQ31>, <PTA18_EIRQ0>, <PTA25_EIRQ5>, <PTD5_EIRQ13>;
13			input-enable;
14		};
15	};
16
17	lpuart0_default: lpuart0_default {
18		group1 {
19			pinmux = <PTA3_LPUART0_TX_O>, <PTA1_LPUART0_RTS>;
20			output-enable;
21		};
22		group2 {
23			pinmux = <PTA2_LPUART0_RX>, <PTA0_LPUART0_CTS>;
24			input-enable;
25		};
26	};
27
28	lpuart1_default: lpuart1_default {
29		group1 {
30			pinmux = <PTC7_LPUART1_TX_O>, <PTE6_LPUART1_RTS>;
31			output-enable;
32		};
33		group2 {
34			pinmux = <PTC6_LPUART1_RX>, <PTE2_LPUART1_CTS>;
35			input-enable;
36		};
37	};
38
39	lpuart2_default: lpuart2_default {
40		group1 {
41			pinmux = <PTA9_LPUART2_TX_O>;
42			output-enable;
43		};
44		group2 {
45			pinmux = <PTA8_LPUART2_RX>;
46			input-enable;
47		};
48	};
49
50	lpuart9_default: lpuart9_default {
51		group1 {
52			pinmux = <PTB3_LPUART9_TX_O>;
53			output-enable;
54		};
55		group2 {
56			pinmux = <PTB2_LPUART9_RX>;
57			input-enable;
58		};
59	};
60
61	lpuart10_default: lpuart10_default {
62		group1 {
63			pinmux = <PTC13_LPUART10_TX_O>;
64			output-enable;
65		};
66		group2 {
67			pinmux = <PTC12_LPUART10_RX>;
68			input-enable;
69		};
70	};
71
72	lpuart13_default: lpuart13_default {
73		group1 {
74			pinmux = <PTB18_LPUART13_TX_O>;
75			output-enable;
76		};
77		group2 {
78			pinmux = <PTB19_LPUART13_RX>;
79			input-enable;
80		};
81	};
82
83	lpuart14_default: lpuart14_default {
84		group1 {
85			pinmux = <PTB20_LPUART14_TX_O>;
86			output-enable;
87		};
88		group2 {
89			pinmux = <PTB21_LPUART14_RX>;
90			input-enable;
91		};
92	};
93
94	qspi0_default: qspi0_default {
95		group1 {
96			pinmux = <(PTD11_QUADSPI_IOFA0_O | PTD11_QUADSPI_IOFA0_I)>,
97				<(PTD7_QUADSPI_IOFA1_O | PTD7_QUADSPI_IOFA1_I)>,
98				<(PTD12_QUADSPI_IOFA2_O | PTD12_QUADSPI_IOFA2_I)>,
99				<(PTC2_QUADSPI_IOFA3_O | PTC2_QUADSPI_IOFA3_I)>;
100			output-enable;
101			input-enable;
102		};
103		group2 {
104			pinmux = <PTD10_QUADSPI_SCKFA_O>;
105			output-enable;
106		};
107		group3 {
108			pinmux = <PTC3_QUADSPI_PCSFA>;
109			output-enable;
110			bias-pull-up;
111		};
112	};
113
114	flexcan0_default: flexcan0_default {
115		group1 {
116			pinmux = <PTA6_CAN0_RX>;
117			input-enable;
118		};
119		group2 {
120			pinmux = <PTA7_CAN0_TX>;
121			output-enable;
122		};
123	};
124
125	flexcan1_default: flexcan1_default {
126		group1 {
127			pinmux = <PTC9_CAN1_RX>;
128			input-enable;
129		};
130		group2 {
131			pinmux = <PTC8_CAN1_TX>;
132			output-enable;
133		};
134	};
135
136	flexcan2_default: flexcan2_default {
137		group1 {
138			pinmux = <PTE25_CAN2_RX>;
139			input-enable;
140		};
141		group2 {
142			pinmux = <PTE24_CAN2_TX>;
143			output-enable;
144		};
145	};
146
147	flexcan3_default: flexcan3_default {
148		group1 {
149			pinmux = <PTC29_CAN3_RX>;
150			input-enable;
151		};
152		group2 {
153			pinmux = <PTC28_CAN3_TX>;
154			output-enable;
155		};
156	};
157
158	flexcan4_default: flexcan4_default {
159		group1 {
160			pinmux = <PTC31_CAN4_RX>;
161			input-enable;
162		};
163		group2 {
164			pinmux = <PTC30_CAN4_TX>;
165			output-enable;
166		};
167	};
168
169	flexcan5_default: flexcan5_default {
170		group1 {
171			pinmux = <PTC11_CAN5_RX>;
172			input-enable;
173		};
174		group2 {
175			pinmux = <PTC10_CAN5_TX>;
176			output-enable;
177		};
178	};
179
180	lpi2c0_default: lpi2c0_default {
181		group1 {
182			pinmux = <(PTD13_LPI2C0_SDA_I | PTD13_LPI2C0_SDA_O)>,
183				<(PTD14_LPI2C0_SCL_I | PTD14_LPI2C0_SCL_O)>;
184			input-enable;
185			output-enable;
186		};
187	};
188
189	lpi2c1_default: lpi2c1_default {
190		group1 {
191			pinmux = <(PTD8_LPI2C1_SDA_I | PTD8_LPI2C1_SDA_O)>,
192				<(PTD9_LPI2C1_SCL_I | PTD9_LPI2C1_SCL_O)>;
193			input-enable;
194			output-enable;
195		};
196	};
197
198	lpspi1_default: lpspi1_default {
199		group1 {
200			pinmux = <PTA28_LPSPI1_SCK_O>, <PTA29_LPSPI1_SIN_O>,
201				<PTA21_LPSPI1_PCS0_O>, <PTE4_LPSPI1_PCS1_O>;
202			output-enable;
203		};
204		group2 {
205			pinmux = <PTA30_LPSPI1_SOUT_I>;
206			input-enable;
207		};
208	};
209
210	lpspi2_default: lpspi2_default {
211		group1 {
212			pinmux = <PTB29_LPSPI2_SCK_O>, <PTB28_LPSPI2_SIN_O>,
213				<PTB25_LPSPI2_PCS0_O>, <PTC19_LPSPI2_PCS1_O>;
214			output-enable;
215		};
216		group2 {
217			pinmux = <PTB27_LPSPI2_SOUT_I>;
218			input-enable;
219		};
220	};
221
222	lpspi3_default: lpspi3_default {
223		group1 {
224			pinmux = <PTD1_LPSPI3_SCK_O>, <PTE10_LPSPI3_SIN_O>,
225				<PTD17_LPSPI3_PCS0_O>;
226			output-enable;
227		};
228		group2 {
229			pinmux = <PTD0_LPSPI3_SOUT_I>;
230			input-enable;
231		};
232	};
233
234	lpspi4_default: lpspi4_default {
235		group1 {
236			pinmux = <PTB10_LPSPI4_SCK_O>, <PTB11_LPSPI4_SIN_O>,
237				<PTB8_LPSPI4_PCS0_O>;
238			output-enable;
239		};
240		group2 {
241			pinmux = <PTB9_LPSPI4_SOUT_I>;
242			input-enable;
243		};
244	};
245
246	lpspi5_default: lpspi5_default {
247		group1 {
248			pinmux = <PTD26_LPSPI5_SCK_O>, <PTD28_LPSPI5_SIN_O>;
249			output-enable;
250		};
251		group2 {
252			pinmux = <PTD27_LPSPI5_SOUT_I>;
253			input-enable;
254		};
255	};
256
257	emac0_default: emac0_default {
258		group1 {
259			pinmux = <PTC0_EMAC_MII_RMII_RXD0>,
260				<PTC1_EMAC_MII_RMII_RXD1>,
261				<PTC14_EMAC_MII_RMII_RX_ER>,
262				<PTC15_EMAC_MII_RMII_RX_DV>,
263				<PTD6_EMAC_MII_RMII_TX_CLK>;
264			input-enable;
265		};
266		group2 {
267			pinmux = <PTB5_EMAC_MII_RMII_TXD0>,
268				<PTB4_EMAC_MII_RMII_TXD1>,
269				<PTE9_EMAC_MII_RMII_TX_EN>;
270		};
271	};
272
273	mdio0_default: mdio0_default {
274		group1 {
275			pinmux = <(PTD16_EMAC_MII_RMII_MDIO_O | PTD16_EMAC_MII_RMII_MDIO_I)>;
276			input-enable;
277			output-enable;
278		};
279		group2 {
280			pinmux = <PTE8_EMAC_MII_RMII_MDC>;
281			output-enable;
282		};
283	};
284
285	emios0_default: emios0_default {
286		group1 {
287			pinmux = <PTB12_EMIOS_0_CH0_X_O>, <PTB13_EMIOS_0_CH1_G_O>,
288				<PTB14_EMIOS_0_CH2_G_O>, <PTB15_EMIOS_0_CH3_G_O>,
289				<PTB16_EMIOS_0_CH4_G_O>, <PTB17_EMIOS_0_CH5_G_O>,
290				<PTE14_EMIOS_0_CH19_Y_O>;
291			output-enable;
292		};
293	};
294
295	emios1_default: emios1_default {
296		group1 {
297			pinmux = <PTA27_EMIOS_1_CH10_H_O>,
298					<PTE12_EMIOS_1_CH5_H_O>;
299			output-enable;
300		};
301	};
302
303	flexio0_pwm_default: flexio0_pwm_default {
304		group1 {
305			pinmux = <PTA17_FXIO_D19_O>, <PTE7_FXIO_D11_O>;
306			output-enable;
307		};
308	};
309
310	qdec_s32: qdec_s32 {
311		group1 {
312			pinmux = <PTB2_TRGMUX_IN3>,
313				<PTB3_TRGMUX_IN2>,
314				<TRGMUX_INT_OUT37_EMIOS_0_CH6_G>,
315				<TRGMUX_INT_OUT38_EMIOS_0_CH7_G>;
316			input-enable;
317		};
318	};
319};
320